1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2017 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef IRDMA_H 36 #define IRDMA_H 37 38 #define RDMA_BIT2(type, a) ((u##type) 1UL << a) 39 #define RDMA_MASK3(type, mask, shift) ((u##type) mask << shift) 40 #define MAKEMASK(m, s) ((m) << (s)) 41 42 #define IRDMA_WQEALLOC_WQE_DESC_INDEX_S 20 43 #define IRDMA_WQEALLOC_WQE_DESC_INDEX GENMASK(31, 20) 44 45 #define IRDMA_CQPTAIL_WQTAIL_S 0 46 #define IRDMA_CQPTAIL_WQTAIL GENMASK(10, 0) 47 #define IRDMA_CQPTAIL_CQP_OP_ERR_S 31 48 #define IRDMA_CQPTAIL_CQP_OP_ERR BIT(31) 49 50 #define IRDMA_CQPERRCODES_CQP_MINOR_CODE_S 0 51 #define IRDMA_CQPERRCODES_CQP_MINOR_CODE GENMASK(15, 0) 52 #define IRDMA_CQPERRCODES_CQP_MAJOR_CODE_S 16 53 #define IRDMA_CQPERRCODES_CQP_MAJOR_CODE GENMASK(31, 16) 54 #define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE_S 4 55 #define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE GENMASK(5, 4) 56 #define IRDMA_GLINT_RATE_INTERVAL_S 0 57 #define IRDMA_GLINT_RATE_INTERVAL GENMASK(4, 0) 58 #define IRDMA_GLINT_RATE_INTRL_ENA_S 6 59 #define IRDMA_GLINT_RATE_INTRL_ENA_M BIT(6) 60 #define IRDMA_GLINT_RATE_INTRL_ENA BIT(6) 61 62 #define IRDMA_GLINT_DYN_CTL_INTENA_S 0 63 #define IRDMA_GLINT_DYN_CTL_INTENA BIT(0) 64 #define IRDMA_GLINT_DYN_CTL_CLEARPBA_S 1 65 #define IRDMA_GLINT_DYN_CTL_CLEARPBA BIT(1) 66 #define IRDMA_GLINT_DYN_CTL_ITR_INDX_S 3 67 #define IRDMA_GLINT_DYN_CTL_ITR_INDX GENMASK(4, 3) 68 #define IRDMA_GLINT_DYN_CTL_INTERVAL_S 5 69 #define IRDMA_GLINT_DYN_CTL_INTERVAL GENMASK(16, 5) 70 #define IRDMA_GLINT_CEQCTL_ITR_INDX_S 11 71 #define IRDMA_GLINT_CEQCTL_ITR_INDX GENMASK(12, 11) 72 #define IRDMA_GLINT_CEQCTL_CAUSE_ENA_S 30 73 #define IRDMA_GLINT_CEQCTL_CAUSE_ENA BIT(30) 74 #define IRDMA_GLINT_CEQCTL_MSIX_INDX_S 0 75 #define IRDMA_GLINT_CEQCTL_MSIX_INDX GENMASK(10, 0) 76 #define IRDMA_PFINT_AEQCTL_MSIX_INDX_S 0 77 #define IRDMA_PFINT_AEQCTL_MSIX_INDX GENMASK(10, 0) 78 #define IRDMA_PFINT_AEQCTL_ITR_INDX_S 11 79 #define IRDMA_PFINT_AEQCTL_ITR_INDX GENMASK(12, 11) 80 #define IRDMA_PFINT_AEQCTL_CAUSE_ENA_S 30 81 #define IRDMA_PFINT_AEQCTL_CAUSE_ENA BIT(30) 82 #define IRDMA_PFHMC_PDINV_PMSDIDX_S 0 83 #define IRDMA_PFHMC_PDINV_PMSDIDX GENMASK(11, 0) 84 #define IRDMA_PFHMC_PDINV_PMSDPARTSEL_S 15 85 #define IRDMA_PFHMC_PDINV_PMSDPARTSEL BIT(15) 86 #define IRDMA_PFHMC_PDINV_PMPDIDX_S 16 87 #define IRDMA_PFHMC_PDINV_PMPDIDX GENMASK(24, 16) 88 #define IRDMA_PFHMC_SDDATALOW_PMSDVALID_S 0 89 #define IRDMA_PFHMC_SDDATALOW_PMSDVALID BIT(0) 90 #define IRDMA_PFHMC_SDDATALOW_PMSDTYPE_S 1 91 #define IRDMA_PFHMC_SDDATALOW_PMSDTYPE BIT(1) 92 #define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT_S 2 93 #define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT GENMASK(11, 2) 94 #define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW_S 12 95 #define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW GENMASK(31, 12) 96 #define IRDMA_PFHMC_SDCMD_PMSDWR_S 31 97 #define IRDMA_PFHMC_SDCMD_PMSDWR BIT(31) 98 #define IRDMA_PFHMC_SDCMD_PMSDPARTSEL_S 15 99 #define IRDMA_PFHMC_SDCMD_PMSDPARTSEL BIT(15) 100 101 #define IRDMA_INVALID_CQ_IDX 0xffffffff 102 103 enum irdma_dyn_idx_t { 104 IRDMA_IDX_ITR0 = 0, 105 IRDMA_IDX_ITR1 = 1, 106 IRDMA_IDX_ITR2 = 2, 107 IRDMA_IDX_NOITR = 3, 108 }; 109 110 enum irdma_registers { 111 IRDMA_CQPTAIL, 112 IRDMA_CQPDB, 113 IRDMA_CCQPSTATUS, 114 IRDMA_CCQPHIGH, 115 IRDMA_CCQPLOW, 116 IRDMA_CQARM, 117 IRDMA_CQACK, 118 IRDMA_AEQALLOC, 119 IRDMA_CQPERRCODES, 120 IRDMA_WQEALLOC, 121 IRDMA_GLINT_DYN_CTL, 122 IRDMA_DB_ADDR_OFFSET, 123 IRDMA_GLPCI_LBARCTRL, 124 IRDMA_GLPE_CPUSTATUS0, 125 IRDMA_GLPE_CPUSTATUS1, 126 IRDMA_GLPE_CPUSTATUS2, 127 IRDMA_PFINT_AEQCTL, 128 IRDMA_GLINT_CEQCTL, 129 IRDMA_VSIQF_PE_CTL1, 130 IRDMA_PFHMC_PDINV, 131 IRDMA_GLHMC_VFPDINV, 132 IRDMA_GLPE_CRITERR, 133 IRDMA_GLINT_RATE, 134 IRDMA_MAX_REGS, /* Must be last entry */ 135 }; 136 137 enum irdma_shifts { 138 IRDMA_CCQPSTATUS_CCQP_DONE_S, 139 IRDMA_CCQPSTATUS_CCQP_ERR_S, 140 IRDMA_CQPSQ_STAG_PDID_S, 141 IRDMA_CQPSQ_CQ_CEQID_S, 142 IRDMA_CQPSQ_CQ_CQID_S, 143 IRDMA_COMMIT_FPM_CQCNT_S, 144 IRDMA_CQPSQ_UPESD_HMCFNID_S, 145 IRDMA_MAX_SHIFTS, 146 }; 147 148 enum irdma_masks { 149 IRDMA_CCQPSTATUS_CCQP_DONE_M, 150 IRDMA_CCQPSTATUS_CCQP_ERR_M, 151 IRDMA_CQPSQ_STAG_PDID_M, 152 IRDMA_CQPSQ_CQ_CEQID_M, 153 IRDMA_CQPSQ_CQ_CQID_M, 154 IRDMA_COMMIT_FPM_CQCNT_M, 155 IRDMA_CQPSQ_UPESD_HMCFNID_M, 156 IRDMA_MAX_MASKS, /* Must be last entry */ 157 }; 158 159 #define IRDMA_MAX_MGS_PER_CTX 8 160 161 struct irdma_mcast_grp_ctx_entry_info { 162 u32 qp_id; 163 bool valid_entry; 164 u16 dest_port; 165 u32 use_cnt; 166 }; 167 168 struct irdma_mcast_grp_info { 169 u8 dest_mac_addr[ETHER_ADDR_LEN]; 170 u16 vlan_id; 171 u16 hmc_fcn_id; 172 bool ipv4_valid:1; 173 bool vlan_valid:1; 174 u16 mg_id; 175 u32 no_of_mgs; 176 u32 dest_ip_addr[4]; 177 u16 qs_handle; 178 struct irdma_dma_mem dma_mem_mc; 179 struct irdma_mcast_grp_ctx_entry_info mg_ctx_info[IRDMA_MAX_MGS_PER_CTX]; 180 }; 181 182 enum irdma_vers { 183 IRDMA_GEN_RSVD = 0, 184 IRDMA_GEN_1 = 1, 185 IRDMA_GEN_2 = 2, 186 IRDMA_GEN_MAX = IRDMA_GEN_2, 187 }; 188 189 struct irdma_uk_attrs { 190 u64 feature_flags; 191 u32 max_hw_wq_frags; 192 u32 max_hw_read_sges; 193 u32 max_hw_inline; 194 u32 max_hw_rq_quanta; 195 u32 max_hw_wq_quanta; 196 u32 min_hw_cq_size; 197 u32 max_hw_cq_size; 198 u16 max_hw_sq_chunk; 199 u16 min_hw_wq_size; 200 u8 hw_rev; 201 }; 202 203 struct irdma_hw_attrs { 204 struct irdma_uk_attrs uk_attrs; 205 u64 max_hw_outbound_msg_size; 206 u64 max_hw_inbound_msg_size; 207 u64 max_mr_size; 208 u64 page_size_cap; 209 u32 min_hw_qp_id; 210 u32 min_hw_aeq_size; 211 u32 max_hw_aeq_size; 212 u32 min_hw_ceq_size; 213 u32 max_hw_ceq_size; 214 u32 max_hw_device_pages; 215 u32 max_hw_vf_fpm_id; 216 u32 first_hw_vf_fpm_id; 217 u32 max_hw_ird; 218 u32 max_hw_ord; 219 u32 max_hw_wqes; 220 u32 max_hw_pds; 221 u32 max_hw_ena_vf_count; 222 u32 max_qp_wr; 223 u32 max_pe_ready_count; 224 u32 max_done_count; 225 u32 max_sleep_count; 226 u32 max_cqp_compl_wait_time_ms; 227 u16 max_stat_inst; 228 u16 max_stat_idx; 229 }; 230 231 void icrdma_init_hw(struct irdma_sc_dev *dev); 232 void irdma_check_fc_for_qp(struct irdma_sc_vsi *vsi, struct irdma_sc_qp *sc_qp); 233 #endif /* IRDMA_H*/ 234