1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2017 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef ICRDMA_HW_H 36 #define ICRDMA_HW_H 37 38 #include "irdma.h" 39 40 #define VFPE_CQPTAIL1 0x0000a000 41 #define VFPE_CQPDB1 0x0000bc00 42 #define VFPE_CCQPSTATUS1 0x0000b800 43 #define VFPE_CCQPHIGH1 0x00009800 44 #define VFPE_CCQPLOW1 0x0000ac00 45 #define VFPE_CQARM1 0x0000b400 46 #define VFPE_CQARM1 0x0000b400 47 #define VFPE_CQACK1 0x0000b000 48 #define VFPE_AEQALLOC1 0x0000a400 49 #define VFPE_CQPERRCODES1 0x00009c00 50 #define VFPE_WQEALLOC1 0x0000c000 51 #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */ 52 53 #define PFPE_CQPTAIL 0x00500880 54 #define PFPE_CQPDB 0x00500800 55 #define PFPE_CCQPSTATUS 0x0050a000 56 #define PFPE_CCQPHIGH 0x0050a100 57 #define PFPE_CCQPLOW 0x0050a080 58 #define PFPE_CQARM 0x00502c00 59 #define PFPE_CQACK 0x00502c80 60 #define PFPE_AEQALLOC 0x00502d00 61 #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */ 62 #define GLPCI_LBARCTRL 0x0009de74 63 #define GLPE_CPUSTATUS0 0x0050ba5c 64 #define GLPE_CPUSTATUS1 0x0050ba60 65 #define GLPE_CPUSTATUS2 0x0050ba64 66 #define PFINT_AEQCTL 0x0016cb00 67 #define PFPE_CQPERRCODES 0x0050a200 68 #define PFPE_WQEALLOC 0x00504400 69 #define GLINT_CEQCTL(_INT) (0x0015c000 + ((_INT) * 4)) /* _i=0...2047 */ 70 #define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */ 71 #define PFHMC_PDINV 0x00520300 72 #define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */ 73 #define GLPE_CRITERR 0x00534000 74 #define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ 75 76 #define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_0 0x001e3180 77 #define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_1 0x001e3184 78 #define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_2 0x001e3188 79 #define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_3 0x001e318c 80 81 #define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_0 0x001e31a0 82 #define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_1 0x001e31a4 83 #define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_2 0x001e31a8 84 #define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_3 0x001e31aC 85 86 #define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_0 0x001e34c0 87 #define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_1 0x001e34c4 88 #define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_2 0x001e34c8 89 #define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_3 0x001e34cC 90 91 #define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_0 0x001e35c0 92 #define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_1 0x001e35c4 93 #define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_2 0x001e35c8 94 #define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_3 0x001e35cC 95 96 #define GLDCB_TC2PFC 0x001d2694 97 #define PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001e31c0 98 99 #define ICRDMA_DB_ADDR_OFFSET (8 * 1024 * 1024 - 64 * 1024) 100 101 #define ICRDMA_VF_DB_ADDR_OFFSET (64 * 1024) 102 103 #define ICRDMA_CCQPSTATUS_CCQP_DONE_S 0 104 #define ICRDMA_CCQPSTATUS_CCQP_DONE BIT_ULL(0) 105 #define ICRDMA_CCQPSTATUS_CCQP_ERR_S 31 106 #define ICRDMA_CCQPSTATUS_CCQP_ERR BIT_ULL(31) 107 #define ICRDMA_CQPSQ_STAG_PDID_S 46 108 #define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46) 109 #define ICRDMA_CQPSQ_CQ_CEQID_S 22 110 #define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22) 111 #define ICRDMA_CQPSQ_CQ_CQID_S 0 112 #define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0) 113 #define ICRDMA_COMMIT_FPM_CQCNT_S 0 114 #define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0) 115 #define ICRDMA_CQPSQ_UPESD_HMCFNID_S 0 116 #define ICRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0) 117 118 enum icrdma_device_caps_const { 119 ICRDMA_MAX_WQ_FRAGMENT_COUNT = 13, 120 ICRDMA_MAX_SGE_RD = 13, 121 ICRDMA_MAX_STATS_COUNT = 128, 122 123 ICRDMA_MAX_IRD_SIZE = 32, 124 ICRDMA_MAX_ORD_SIZE = 32, 125 ICRDMA_MIN_WQ_SIZE = 8 /* WQEs */, 126 127 }; 128 129 void icrdma_init_hw(struct irdma_sc_dev *dev); 130 void irdma_init_config_check(struct irdma_config_check *cc, 131 u8 traffic_class, 132 u16 qs_handle); 133 bool irdma_is_config_ok(struct irdma_config_check *cc, struct irdma_sc_vsi *vsi); 134 void irdma_check_fc_for_tc_update(struct irdma_sc_vsi *vsi, 135 struct irdma_l2params *l2params); 136 void irdma_check_fc_for_qp(struct irdma_sc_vsi *vsi, struct irdma_sc_qp *sc_qp); 137 #endif /* ICRDMA_HW_H*/ 138