1 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause 4 * 5 * Copyright (c) 2004-2006 6 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #define IPW_NTBD 128 32 #define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd)) 33 #define IPW_NDATA (IPW_NTBD / 2) 34 #define IPW_NRBD 128 35 #define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd)) 36 #define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status)) 37 38 #define IPW_CSR_INTR 0x0008 39 #define IPW_CSR_INTR_MASK 0x000c 40 #define IPW_CSR_INDIRECT_ADDR 0x0010 41 #define IPW_CSR_INDIRECT_DATA 0x0014 42 #define IPW_CSR_AUTOINC_ADDR 0x0018 43 #define IPW_CSR_AUTOINC_DATA 0x001c 44 #define IPW_CSR_RST 0x0020 45 #define IPW_CSR_CTL 0x0024 46 #define IPW_CSR_IO 0x0030 47 #define IPW_CSR_TX_BASE 0x0200 48 #define IPW_CSR_TX_SIZE 0x0204 49 #define IPW_CSR_RX_BASE 0x0240 50 #define IPW_CSR_STATUS_BASE 0x0244 51 #define IPW_CSR_RX_SIZE 0x0248 52 #define IPW_CSR_TX_READ 0x0280 53 #define IPW_CSR_RX_READ 0x02a0 54 #define IPW_CSR_TABLE1_BASE 0x0380 55 #define IPW_CSR_TABLE2_BASE 0x0384 56 #define IPW_CSR_TX_WRITE 0x0f80 57 #define IPW_CSR_RX_WRITE 0x0fa0 58 59 /* possible flags for register IPW_CSR_INTR */ 60 #define IPW_INTR_TX_TRANSFER 0x00000001 61 #define IPW_INTR_RX_TRANSFER 0x00000002 62 #define IPW_INTR_STATUS_CHANGE 0x00000010 63 #define IPW_INTR_COMMAND_DONE 0x00010000 64 #define IPW_INTR_FW_INIT_DONE 0x01000000 65 #define IPW_INTR_FATAL_ERROR 0x40000000 66 #define IPW_INTR_PARITY_ERROR 0x80000000 67 68 #define IPW_INTR_MASK \ 69 (IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \ 70 IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \ 71 IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \ 72 IPW_INTR_PARITY_ERROR) 73 74 /* possible flags for register IPW_CSR_RST */ 75 #define IPW_RST_PRINCETON_RESET 0x00000001 76 #define IPW_RST_SW_RESET 0x00000080 77 #define IPW_RST_MASTER_DISABLED 0x00000100 78 #define IPW_RST_STOP_MASTER 0x00000200 79 80 /* possible flags for register IPW_CSR_CTL */ 81 #define IPW_CTL_CLOCK_READY 0x00000001 82 #define IPW_CTL_ALLOW_STANDBY 0x00000002 83 #define IPW_CTL_INIT 0x00000004 84 85 /* possible flags for register IPW_CSR_IO */ 86 #define IPW_IO_GPIO1_ENABLE 0x00000008 87 #define IPW_IO_GPIO1_MASK 0x0000000c 88 #define IPW_IO_GPIO3_MASK 0x000000c0 89 #define IPW_IO_LED_OFF 0x00002000 90 #define IPW_IO_RADIO_DISABLED 0x00010000 91 92 /* state codes sent by fw on IPW_STATUS_CODE_NEWSTATE interrupt */ 93 #define IPW_STATE_INITIALIZED 0x0001 94 #define IPW_STATE_CC_FOUND 0x0002 /* 802.11d cc received */ 95 #define IPW_STATE_ASSOCIATED 0x0004 96 #define IPW_STATE_ASSOCIATION_LOST 0x0008 97 #define IPW_STATE_ASSOCIATION_CHANGED 0x0010 /* assoc params changed? */ 98 #define IPW_STATE_SCAN_COMPLETE 0x0020 99 #define IPW_STATE_PS_ENTER 0x0040 /* entered power-save mode */ 100 #define IPW_STATE_PS_EXIT 0x0080 /* exited power-save mode */ 101 #define IPW_STATE_RADIO_DISABLED 0x0100 102 #define IPW_STATE_DISABLED 0x0200 103 #define IPW_STATE_POWER_DOWN 0x0400 /* ??? */ 104 #define IPW_STATE_SCANNING 0x0800 105 106 /* table1 offsets */ 107 #define IPW_INFO_LOCK 480 108 #define IPW_INFO_APS_CNT 604 109 #define IPW_INFO_APS_BASE 608 110 #define IPW_INFO_CARD_DISABLED 628 111 #define IPW_INFO_CURRENT_CHANNEL 756 112 #define IPW_INFO_CURRENT_TX_RATE 768 113 114 /* table2 offsets */ 115 #define IPW_INFO_CURRENT_SSID 48 116 #define IPW_INFO_CURRENT_BSSID 112 117 118 /* supported rates */ 119 #define IPW_RATE_DS1 1 120 #define IPW_RATE_DS2 2 121 #define IPW_RATE_DS5 4 122 #define IPW_RATE_DS11 8 123 124 /* firmware binary image header */ 125 struct ipw_firmware_hdr { 126 uint32_t version; 127 uint32_t mainsz; 128 uint32_t ucodesz; 129 } __packed; 130 131 /* buffer descriptor */ 132 struct ipw_bd { 133 uint32_t physaddr; 134 uint32_t len; 135 uint8_t flags; 136 #define IPW_BD_FLAG_TX_FRAME_802_3 0x00 137 #define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01 138 #define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02 139 #define IPW_BD_FLAG_TX_FRAME_802_11 0x04 140 #define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08 141 uint8_t nfrag; /* number of fragments */ 142 uint8_t reserved[6]; 143 } __packed; 144 145 /* status */ 146 struct ipw_status { 147 uint32_t len; 148 uint16_t code; 149 #define IPW_STATUS_CODE_COMMAND 0 150 #define IPW_STATUS_CODE_NEWSTATE 1 151 #define IPW_STATUS_CODE_DATA_802_11 2 152 #define IPW_STATUS_CODE_DATA_802_3 3 153 #define IPW_STATUS_CODE_NOTIFICATION 4 154 uint8_t flags; 155 #define IPW_STATUS_FLAG_DECRYPTED 0x01 156 #define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02 157 #define IPW_STATUS_FLAG_CRC_ERROR 0x04 158 uint8_t rssi; /* received signal strength indicator */ 159 #define IPW_RSSI_TO_DBM (-98) /* XXX fixed nf to convert dBm */ 160 } __packed; 161 162 /* data header */ 163 struct ipw_hdr { 164 uint32_t type; 165 #define IPW_HDR_TYPE_SEND 33 166 uint32_t subtype; 167 uint8_t encrypted; 168 uint8_t encrypt; 169 uint8_t keyidx; 170 uint8_t keysz; 171 uint8_t key[IEEE80211_KEYBUF_SIZE]; 172 uint8_t reserved[10]; 173 uint8_t src_addr[IEEE80211_ADDR_LEN]; 174 uint8_t dst_addr[IEEE80211_ADDR_LEN]; 175 uint16_t fragmentsz; 176 } __packed; 177 178 /* command */ 179 struct ipw_cmd { 180 uint32_t type; 181 #define IPW_CMD_ENABLE 2 182 #define IPW_CMD_SET_CONFIGURATION 6 183 #define IPW_CMD_SET_ESSID 8 184 #define IPW_CMD_SET_MANDATORY_BSSID 9 185 #define IPW_CMD_SET_MAC_ADDRESS 11 186 #define IPW_CMD_SET_MODE 12 187 #define IPW_CMD_SET_CHANNEL 14 188 #define IPW_CMD_SET_RTS_THRESHOLD 15 189 #define IPW_CMD_SET_FRAG_THRESHOLD 16 190 #define IPW_CMD_SET_POWER_MODE 17 191 #define IPW_CMD_SET_TX_RATES 18 192 #define IPW_CMD_SET_BASIC_TX_RATES 19 193 #define IPW_CMD_SET_WEP_KEY 20 194 #define IPW_CMD_SET_WEP_KEY_INDEX 25 195 #define IPW_CMD_SET_WEP_FLAGS 26 196 #define IPW_CMD_ADD_MULTICAST 27 197 #define IPW_CMD_SET_BEACON_INTERVAL 29 198 #define IPW_CMD_SET_TX_POWER_INDEX 36 199 #define IPW_CMD_BROADCAST_SCAN 43 200 #define IPW_CMD_DISABLE 44 201 #define IPW_CMD_SET_DESIRED_BSSID 45 202 #define IPW_CMD_SET_SCAN_OPTIONS 46 203 #define IPW_CMD_SET_SCAN_DWELL_TIME 47 204 #define IPW_CMD_SET_SHORT_RETRY 51 205 #define IPW_CMD_SET_LONG_RETRY 52 206 #define IPW_CMD_PREPARE_POWER_DOWN 58 207 #define IPW_CMD_DISABLE_PHY 61 208 #define IPW_CMD_SET_MSDU_TX_RATES 62 209 #define IPW_CMD_SET_SECURITY_INFO 67 210 #define IPW_CMD_DISASSOCIATE 68 211 #define IPW_CMD_SET_WPA_IE 69 212 uint32_t subtype; 213 uint32_t seq; 214 uint32_t len; 215 uint8_t data[400]; 216 uint32_t status; 217 uint8_t reserved[68]; 218 } __packed; 219 220 /* possible values for command IPW_CMD_SET_POWER_MODE */ 221 #define IPW_POWER_MODE_CAM 0 222 #define IPW_POWER_MODE_AUTO 6 223 224 /* possible values for command IPW_CMD_SET_MODE */ 225 #define IPW_MODE_BSS 0 226 #define IPW_MODE_IBSS 1 227 #define IPW_MODE_MONITOR 2 228 229 /* possible flags for command IPW_CMD_SET_WEP_FLAGS */ 230 #define IPW_WEPON 0x8 231 232 /* structure for command IPW_CMD_SET_WEP_KEY */ 233 struct ipw_wep_key { 234 uint8_t idx; 235 uint8_t len; 236 uint8_t key[13]; 237 } __packed; 238 239 /* structure for command IPW_CMD_SET_SECURITY_INFORMATION */ 240 struct ipw_security { 241 uint32_t ciphers; 242 #define IPW_CIPHER_NONE 0x00000001 243 #define IPW_CIPHER_WEP40 0x00000002 244 #define IPW_CIPHER_TKIP 0x00000004 245 #define IPW_CIPHER_CCMP 0x00000010 246 #define IPW_CIPHER_WEP104 0x00000020 247 #define IPW_CIPHER_CKIP 0x00000040 248 uint16_t reserved1; 249 uint8_t authmode; 250 #define IPW_AUTH_OPEN 0 251 #define IPW_AUTH_SHARED 1 252 uint16_t reserved2; 253 } __packed; 254 255 /* structure for command IPW_CMD_SET_SCAN_OPTIONS */ 256 struct ipw_scan_options { 257 uint32_t flags; 258 #define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001 259 #define IPW_SCAN_MIXED_CELL 0x00000002 260 #define IPW_SCAN_PASSIVE 0x00000008 261 uint32_t channels; 262 } __packed; 263 264 /* structure for command IPW_CMD_SET_CONFIGURATION */ 265 struct ipw_configuration { 266 uint32_t flags; 267 #define IPW_CFG_PROMISCUOUS 0x00000004 268 #define IPW_CFG_PREAMBLE_AUTO 0x00000010 269 #define IPW_CFG_IBSS_AUTO_START 0x00000020 270 #define IPW_CFG_802_1x_ENABLE 0x00004000 271 #define IPW_CFG_BSS_MASK 0x00008000 272 #define IPW_CFG_IBSS_MASK 0x00010000 273 uint32_t bss_chan; 274 uint32_t ibss_chan; 275 } __packed; 276 277 /* structure for command IPW_CMD_SET_WPA_IE */ 278 struct ipw_wpa_ie { 279 uint16_t mask; 280 uint16_t capinfo; 281 uint16_t lintval; 282 uint8_t bssid[IEEE80211_ADDR_LEN]; 283 uint32_t len; 284 struct ieee80211_ie_wpa ie; 285 } __packed; 286 287 /* element in AP table */ 288 struct ipw_node { 289 uint32_t reserved1[2]; 290 uint8_t bssid[IEEE80211_ADDR_LEN]; 291 uint8_t chan; 292 uint8_t rates; 293 uint16_t reserved2; 294 uint16_t capinfo; 295 uint16_t reserved3; 296 uint16_t intval; 297 uint8_t reserved4[28]; 298 uint8_t essid[IEEE80211_NWID_LEN]; 299 uint16_t reserved5; 300 uint8_t esslen; 301 uint8_t reserved6[7]; 302 uint8_t rssi; 303 } __packed; 304 305 /* EEPROM = Electrically Erasable Programmable Read-Only Memory */ 306 307 #define IPW_MEM_EEPROM_CTL 0x00300040 308 309 #define IPW_EEPROM_RADIO 0x11 310 #define IPW_EEPROM_MAC 0x21 311 #define IPW_EEPROM_CHANNEL_LIST 0x37 312 313 #define IPW_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 314 315 #define IPW_EEPROM_C (1 << 0) /* Serial Clock */ 316 #define IPW_EEPROM_S (1 << 1) /* Chip Select */ 317 #define IPW_EEPROM_D (1 << 2) /* Serial data input */ 318 #define IPW_EEPROM_Q (1 << 4) /* Serial data output */ 319 320 #define IPW_EEPROM_SHIFT_D 2 321 #define IPW_EEPROM_SHIFT_Q 4 322 323 /* 324 * control and status registers access macros 325 */ 326 #define CSR_READ_1(sc, reg) \ 327 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 328 329 #define CSR_READ_2(sc, reg) \ 330 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 331 332 #define CSR_READ_4(sc, reg) \ 333 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 334 335 #define CSR_WRITE_1(sc, reg, val) \ 336 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 337 338 #define CSR_WRITE_2(sc, reg, val) \ 339 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 340 341 #define CSR_WRITE_4(sc, reg, val) \ 342 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 343 344 #define CSR_WRITE_MULTI_1(sc, reg, buf, len) \ 345 bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \ 346 (buf), (len)) 347 348 /* 349 * indirect memory space access macros 350 */ 351 #define MEM_READ_1(sc, addr) \ 352 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \ 353 CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA)) 354 355 #define MEM_READ_4(sc, addr) \ 356 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \ 357 CSR_READ_4((sc), IPW_CSR_INDIRECT_DATA)) 358 359 #define MEM_WRITE_1(sc, addr, val) do { \ 360 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 361 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 362 } while (/* CONSTCOND */0) 363 364 #define MEM_WRITE_2(sc, addr, val) do { \ 365 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 366 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 367 } while (/* CONSTCOND */0) 368 369 #define MEM_WRITE_4(sc, addr, val) do { \ 370 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 371 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 372 } while (/* CONSTCOND */0) 373 374 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 375 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 376 CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \ 377 } while (/* CONSTCOND */0) 378 379 /* 380 * EEPROM access macro 381 */ 382 #define IPW_EEPROM_CTL(sc, val) do { \ 383 MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \ 384 DELAY(IPW_EEPROM_DELAY); \ 385 } while (0) 386