1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2004-2006 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #define IPW_NTBD 128 31 #define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd)) 32 #define IPW_NDATA (IPW_NTBD / 2) 33 #define IPW_NRBD 128 34 #define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd)) 35 #define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status)) 36 37 #define IPW_CSR_INTR 0x0008 38 #define IPW_CSR_INTR_MASK 0x000c 39 #define IPW_CSR_INDIRECT_ADDR 0x0010 40 #define IPW_CSR_INDIRECT_DATA 0x0014 41 #define IPW_CSR_AUTOINC_ADDR 0x0018 42 #define IPW_CSR_AUTOINC_DATA 0x001c 43 #define IPW_CSR_RST 0x0020 44 #define IPW_CSR_CTL 0x0024 45 #define IPW_CSR_IO 0x0030 46 #define IPW_CSR_TX_BASE 0x0200 47 #define IPW_CSR_TX_SIZE 0x0204 48 #define IPW_CSR_RX_BASE 0x0240 49 #define IPW_CSR_STATUS_BASE 0x0244 50 #define IPW_CSR_RX_SIZE 0x0248 51 #define IPW_CSR_TX_READ 0x0280 52 #define IPW_CSR_RX_READ 0x02a0 53 #define IPW_CSR_TABLE1_BASE 0x0380 54 #define IPW_CSR_TABLE2_BASE 0x0384 55 #define IPW_CSR_TX_WRITE 0x0f80 56 #define IPW_CSR_RX_WRITE 0x0fa0 57 58 /* possible flags for register IPW_CSR_INTR */ 59 #define IPW_INTR_TX_TRANSFER 0x00000001 60 #define IPW_INTR_RX_TRANSFER 0x00000002 61 #define IPW_INTR_STATUS_CHANGE 0x00000010 62 #define IPW_INTR_COMMAND_DONE 0x00010000 63 #define IPW_INTR_FW_INIT_DONE 0x01000000 64 #define IPW_INTR_FATAL_ERROR 0x40000000 65 #define IPW_INTR_PARITY_ERROR 0x80000000 66 67 #define IPW_INTR_MASK \ 68 (IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \ 69 IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \ 70 IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \ 71 IPW_INTR_PARITY_ERROR) 72 73 /* possible flags for register IPW_CSR_RST */ 74 #define IPW_RST_PRINCETON_RESET 0x00000001 75 #define IPW_RST_SW_RESET 0x00000080 76 #define IPW_RST_MASTER_DISABLED 0x00000100 77 #define IPW_RST_STOP_MASTER 0x00000200 78 79 /* possible flags for register IPW_CSR_CTL */ 80 #define IPW_CTL_CLOCK_READY 0x00000001 81 #define IPW_CTL_ALLOW_STANDBY 0x00000002 82 #define IPW_CTL_INIT 0x00000004 83 84 /* possible flags for register IPW_CSR_IO */ 85 #define IPW_IO_GPIO1_ENABLE 0x00000008 86 #define IPW_IO_GPIO1_MASK 0x0000000c 87 #define IPW_IO_GPIO3_MASK 0x000000c0 88 #define IPW_IO_LED_OFF 0x00002000 89 #define IPW_IO_RADIO_DISABLED 0x00010000 90 91 /* state codes sent by fw on IPW_STATUS_CODE_NEWSTATE interrupt */ 92 #define IPW_STATE_INITIALIZED 0x0001 93 #define IPW_STATE_CC_FOUND 0x0002 /* 802.11d cc received */ 94 #define IPW_STATE_ASSOCIATED 0x0004 95 #define IPW_STATE_ASSOCIATION_LOST 0x0008 96 #define IPW_STATE_ASSOCIATION_CHANGED 0x0010 /* assoc params changed? */ 97 #define IPW_STATE_SCAN_COMPLETE 0x0020 98 #define IPW_STATE_PS_ENTER 0x0040 /* entered power-save mode */ 99 #define IPW_STATE_PS_EXIT 0x0080 /* exited power-save mode */ 100 #define IPW_STATE_RADIO_DISABLED 0x0100 101 #define IPW_STATE_DISABLED 0x0200 102 #define IPW_STATE_POWER_DOWN 0x0400 /* ??? */ 103 #define IPW_STATE_SCANNING 0x0800 104 105 /* table1 offsets */ 106 #define IPW_INFO_LOCK 480 107 #define IPW_INFO_APS_CNT 604 108 #define IPW_INFO_APS_BASE 608 109 #define IPW_INFO_CARD_DISABLED 628 110 #define IPW_INFO_CURRENT_CHANNEL 756 111 #define IPW_INFO_CURRENT_TX_RATE 768 112 113 /* table2 offsets */ 114 #define IPW_INFO_CURRENT_SSID 48 115 #define IPW_INFO_CURRENT_BSSID 112 116 117 /* supported rates */ 118 #define IPW_RATE_DS1 1 119 #define IPW_RATE_DS2 2 120 #define IPW_RATE_DS5 4 121 #define IPW_RATE_DS11 8 122 123 /* firmware binary image header */ 124 struct ipw_firmware_hdr { 125 uint32_t version; 126 uint32_t mainsz; 127 uint32_t ucodesz; 128 } __packed; 129 130 /* buffer descriptor */ 131 struct ipw_bd { 132 uint32_t physaddr; 133 uint32_t len; 134 uint8_t flags; 135 #define IPW_BD_FLAG_TX_FRAME_802_3 0x00 136 #define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01 137 #define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02 138 #define IPW_BD_FLAG_TX_FRAME_802_11 0x04 139 #define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08 140 uint8_t nfrag; /* number of fragments */ 141 uint8_t reserved[6]; 142 } __packed; 143 144 /* status */ 145 struct ipw_status { 146 uint32_t len; 147 uint16_t code; 148 #define IPW_STATUS_CODE_COMMAND 0 149 #define IPW_STATUS_CODE_NEWSTATE 1 150 #define IPW_STATUS_CODE_DATA_802_11 2 151 #define IPW_STATUS_CODE_DATA_802_3 3 152 #define IPW_STATUS_CODE_NOTIFICATION 4 153 uint8_t flags; 154 #define IPW_STATUS_FLAG_DECRYPTED 0x01 155 #define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02 156 #define IPW_STATUS_FLAG_CRC_ERROR 0x04 157 uint8_t rssi; /* received signal strength indicator */ 158 #define IPW_RSSI_TO_DBM (-98) /* XXX fixed nf to convert dBm */ 159 } __packed; 160 161 /* data header */ 162 struct ipw_hdr { 163 uint32_t type; 164 #define IPW_HDR_TYPE_SEND 33 165 uint32_t subtype; 166 uint8_t encrypted; 167 uint8_t encrypt; 168 uint8_t keyidx; 169 uint8_t keysz; 170 uint8_t key[IEEE80211_KEYBUF_SIZE]; 171 uint8_t reserved[10]; 172 uint8_t src_addr[IEEE80211_ADDR_LEN]; 173 uint8_t dst_addr[IEEE80211_ADDR_LEN]; 174 uint16_t fragmentsz; 175 } __packed; 176 177 /* command */ 178 struct ipw_cmd { 179 uint32_t type; 180 #define IPW_CMD_ENABLE 2 181 #define IPW_CMD_SET_CONFIGURATION 6 182 #define IPW_CMD_SET_ESSID 8 183 #define IPW_CMD_SET_MANDATORY_BSSID 9 184 #define IPW_CMD_SET_MAC_ADDRESS 11 185 #define IPW_CMD_SET_MODE 12 186 #define IPW_CMD_SET_CHANNEL 14 187 #define IPW_CMD_SET_RTS_THRESHOLD 15 188 #define IPW_CMD_SET_FRAG_THRESHOLD 16 189 #define IPW_CMD_SET_POWER_MODE 17 190 #define IPW_CMD_SET_TX_RATES 18 191 #define IPW_CMD_SET_BASIC_TX_RATES 19 192 #define IPW_CMD_SET_WEP_KEY 20 193 #define IPW_CMD_SET_WEP_KEY_INDEX 25 194 #define IPW_CMD_SET_WEP_FLAGS 26 195 #define IPW_CMD_ADD_MULTICAST 27 196 #define IPW_CMD_SET_BEACON_INTERVAL 29 197 #define IPW_CMD_SET_TX_POWER_INDEX 36 198 #define IPW_CMD_BROADCAST_SCAN 43 199 #define IPW_CMD_DISABLE 44 200 #define IPW_CMD_SET_DESIRED_BSSID 45 201 #define IPW_CMD_SET_SCAN_OPTIONS 46 202 #define IPW_CMD_SET_SCAN_DWELL_TIME 47 203 #define IPW_CMD_SET_SHORT_RETRY 51 204 #define IPW_CMD_SET_LONG_RETRY 52 205 #define IPW_CMD_PREPARE_POWER_DOWN 58 206 #define IPW_CMD_DISABLE_PHY 61 207 #define IPW_CMD_SET_MSDU_TX_RATES 62 208 #define IPW_CMD_SET_SECURITY_INFO 67 209 #define IPW_CMD_DISASSOCIATE 68 210 #define IPW_CMD_SET_WPA_IE 69 211 uint32_t subtype; 212 uint32_t seq; 213 uint32_t len; 214 uint8_t data[400]; 215 uint32_t status; 216 uint8_t reserved[68]; 217 } __packed; 218 219 /* possible values for command IPW_CMD_SET_POWER_MODE */ 220 #define IPW_POWER_MODE_CAM 0 221 #define IPW_POWER_MODE_AUTO 6 222 223 /* possible values for command IPW_CMD_SET_MODE */ 224 #define IPW_MODE_BSS 0 225 #define IPW_MODE_IBSS 1 226 #define IPW_MODE_MONITOR 2 227 228 /* possible flags for command IPW_CMD_SET_WEP_FLAGS */ 229 #define IPW_WEPON 0x8 230 231 /* structure for command IPW_CMD_SET_WEP_KEY */ 232 struct ipw_wep_key { 233 uint8_t idx; 234 uint8_t len; 235 uint8_t key[13]; 236 } __packed; 237 238 /* structure for command IPW_CMD_SET_SECURITY_INFORMATION */ 239 struct ipw_security { 240 uint32_t ciphers; 241 #define IPW_CIPHER_NONE 0x00000001 242 #define IPW_CIPHER_WEP40 0x00000002 243 #define IPW_CIPHER_TKIP 0x00000004 244 #define IPW_CIPHER_CCMP 0x00000010 245 #define IPW_CIPHER_WEP104 0x00000020 246 #define IPW_CIPHER_CKIP 0x00000040 247 uint16_t reserved1; 248 uint8_t authmode; 249 #define IPW_AUTH_OPEN 0 250 #define IPW_AUTH_SHARED 1 251 uint16_t reserved2; 252 } __packed; 253 254 /* structure for command IPW_CMD_SET_SCAN_OPTIONS */ 255 struct ipw_scan_options { 256 uint32_t flags; 257 #define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001 258 #define IPW_SCAN_MIXED_CELL 0x00000002 259 #define IPW_SCAN_PASSIVE 0x00000008 260 uint32_t channels; 261 } __packed; 262 263 /* structure for command IPW_CMD_SET_CONFIGURATION */ 264 struct ipw_configuration { 265 uint32_t flags; 266 #define IPW_CFG_PROMISCUOUS 0x00000004 267 #define IPW_CFG_PREAMBLE_AUTO 0x00000010 268 #define IPW_CFG_IBSS_AUTO_START 0x00000020 269 #define IPW_CFG_802_1x_ENABLE 0x00004000 270 #define IPW_CFG_BSS_MASK 0x00008000 271 #define IPW_CFG_IBSS_MASK 0x00010000 272 uint32_t bss_chan; 273 uint32_t ibss_chan; 274 } __packed; 275 276 /* structure for command IPW_CMD_SET_WPA_IE */ 277 struct ipw_wpa_ie { 278 uint16_t mask; 279 uint16_t capinfo; 280 uint16_t lintval; 281 uint8_t bssid[IEEE80211_ADDR_LEN]; 282 uint32_t len; 283 struct ieee80211_ie_wpa ie; 284 } __packed; 285 286 /* element in AP table */ 287 struct ipw_node { 288 uint32_t reserved1[2]; 289 uint8_t bssid[IEEE80211_ADDR_LEN]; 290 uint8_t chan; 291 uint8_t rates; 292 uint16_t reserved2; 293 uint16_t capinfo; 294 uint16_t reserved3; 295 uint16_t intval; 296 uint8_t reserved4[28]; 297 uint8_t essid[IEEE80211_NWID_LEN]; 298 uint16_t reserved5; 299 uint8_t esslen; 300 uint8_t reserved6[7]; 301 uint8_t rssi; 302 } __packed; 303 304 /* EEPROM = Electrically Erasable Programmable Read-Only Memory */ 305 306 #define IPW_MEM_EEPROM_CTL 0x00300040 307 308 #define IPW_EEPROM_RADIO 0x11 309 #define IPW_EEPROM_MAC 0x21 310 #define IPW_EEPROM_CHANNEL_LIST 0x37 311 312 #define IPW_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 313 314 #define IPW_EEPROM_C (1 << 0) /* Serial Clock */ 315 #define IPW_EEPROM_S (1 << 1) /* Chip Select */ 316 #define IPW_EEPROM_D (1 << 2) /* Serial data input */ 317 #define IPW_EEPROM_Q (1 << 4) /* Serial data output */ 318 319 #define IPW_EEPROM_SHIFT_D 2 320 #define IPW_EEPROM_SHIFT_Q 4 321 322 /* 323 * control and status registers access macros 324 */ 325 #define CSR_READ_1(sc, reg) \ 326 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 327 328 #define CSR_READ_2(sc, reg) \ 329 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 330 331 #define CSR_READ_4(sc, reg) \ 332 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 333 334 #define CSR_WRITE_1(sc, reg, val) \ 335 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 336 337 #define CSR_WRITE_2(sc, reg, val) \ 338 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 339 340 #define CSR_WRITE_4(sc, reg, val) \ 341 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 342 343 #define CSR_WRITE_MULTI_1(sc, reg, buf, len) \ 344 bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \ 345 (buf), (len)) 346 347 /* 348 * indirect memory space access macros 349 */ 350 #define MEM_READ_1(sc, addr) \ 351 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \ 352 CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA)) 353 354 #define MEM_READ_4(sc, addr) \ 355 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \ 356 CSR_READ_4((sc), IPW_CSR_INDIRECT_DATA)) 357 358 #define MEM_WRITE_1(sc, addr, val) do { \ 359 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 360 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 361 } while (/* CONSTCOND */0) 362 363 #define MEM_WRITE_2(sc, addr, val) do { \ 364 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 365 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 366 } while (/* CONSTCOND */0) 367 368 #define MEM_WRITE_4(sc, addr, val) do { \ 369 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 370 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 371 } while (/* CONSTCOND */0) 372 373 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 374 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 375 CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \ 376 } while (/* CONSTCOND */0) 377 378 /* 379 * EEPROM access macro 380 */ 381 #define IPW_EEPROM_CTL(sc, val) do { \ 382 MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \ 383 DELAY(IPW_EEPROM_DELAY); \ 384 } while (0) 385