1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2004-2006 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /*- 34 * Intel(R) PRO/Wireless 2100 MiniPCI driver 35 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 36 */ 37 38 #include <sys/param.h> 39 #include <sys/sysctl.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/systm.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/module.h> 49 #include <sys/bus.h> 50 #include <sys/endian.h> 51 #include <sys/linker.h> 52 #include <sys/firmware.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 #include <sys/rman.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 61 #include <net/bpf.h> 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/ethernet.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 #include <netinet/if_ether.h> 77 78 #include <dev/ipw/if_ipwreg.h> 79 #include <dev/ipw/if_ipwvar.h> 80 81 #ifdef IPW_DEBUG 82 #define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 83 #define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 84 int ipw_debug = 0; 85 SYSCTL_INT(_debug, OID_AUTO, ipw, CTLFLAG_RW, &ipw_debug, 0, "ipw debug level"); 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 MODULE_DEPEND(ipw, pci, 1, 1, 1); 92 MODULE_DEPEND(ipw, wlan, 1, 1, 1); 93 MODULE_DEPEND(ipw, firmware, 1, 1, 1); 94 95 struct ipw_ident { 96 uint16_t vendor; 97 uint16_t device; 98 const char *name; 99 }; 100 101 static const struct ipw_ident ipw_ident_table[] = { 102 { 0x8086, 0x1043, "Intel(R) PRO/Wireless 2100 MiniPCI" }, 103 104 { 0, 0, NULL } 105 }; 106 107 static int ipw_dma_alloc(struct ipw_softc *); 108 static void ipw_release(struct ipw_softc *); 109 static int ipw_media_change(struct ifnet *); 110 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 111 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 112 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 113 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 114 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 115 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 116 struct ipw_soft_bd *, struct ipw_soft_buf *); 117 static void ipw_rx_intr(struct ipw_softc *); 118 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 119 static void ipw_tx_intr(struct ipw_softc *); 120 static void ipw_intr(void *); 121 static void ipw_dma_map_addr(void *, bus_dma_segment_t *, int, int); 122 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 123 static int ipw_tx_start(struct ifnet *, struct mbuf *, 124 struct ieee80211_node *); 125 static void ipw_start(struct ifnet *); 126 static void ipw_watchdog(struct ifnet *); 127 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 128 static void ipw_stop_master(struct ipw_softc *); 129 static int ipw_reset(struct ipw_softc *); 130 static int ipw_load_ucode(struct ipw_softc *, const char *, int); 131 static int ipw_load_firmware(struct ipw_softc *, const char *, int); 132 static int ipw_config(struct ipw_softc *); 133 static void ipw_init_task(void *, int); 134 static void ipw_init(void *); 135 static void ipw_stop(void *); 136 static int ipw_sysctl_stats(SYSCTL_HANDLER_ARGS); 137 static int ipw_sysctl_radio(SYSCTL_HANDLER_ARGS); 138 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 139 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 140 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 141 uint32_t *); 142 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 143 bus_size_t); 144 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, 145 const uint8_t *, bus_size_t); 146 147 static int ipw_probe(device_t); 148 static int ipw_attach(device_t); 149 static int ipw_detach(device_t); 150 static int ipw_shutdown(device_t); 151 static int ipw_suspend(device_t); 152 static int ipw_resume(device_t); 153 154 static device_method_t ipw_methods[] = { 155 /* Device interface */ 156 DEVMETHOD(device_probe, ipw_probe), 157 DEVMETHOD(device_attach, ipw_attach), 158 DEVMETHOD(device_detach, ipw_detach), 159 DEVMETHOD(device_shutdown, ipw_shutdown), 160 DEVMETHOD(device_suspend, ipw_suspend), 161 DEVMETHOD(device_resume, ipw_resume), 162 163 { 0, 0 } 164 }; 165 166 static driver_t ipw_driver = { 167 "ipw", 168 ipw_methods, 169 sizeof (struct ipw_softc) 170 }; 171 172 static devclass_t ipw_devclass; 173 174 DRIVER_MODULE(ipw, pci, ipw_driver, ipw_devclass, 0, 0); 175 176 static int 177 ipw_probe(device_t dev) 178 { 179 const struct ipw_ident *ident; 180 181 for (ident = ipw_ident_table; ident->name != NULL; ident++) { 182 if (pci_get_vendor(dev) == ident->vendor && 183 pci_get_device(dev) == ident->device) { 184 device_set_desc(dev, ident->name); 185 return 0; 186 } 187 } 188 return ENXIO; 189 } 190 191 /* Base Address Register */ 192 #define IPW_PCI_BAR0 0x10 193 194 static int 195 ipw_attach(device_t dev) 196 { 197 struct ipw_softc *sc = device_get_softc(dev); 198 struct ifnet *ifp; 199 struct ieee80211com *ic = &sc->sc_ic; 200 uint16_t val; 201 int error, i; 202 203 sc->sc_dev = dev; 204 205 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 206 MTX_DEF | MTX_RECURSE); 207 208 TASK_INIT(&sc->sc_init_task, 0, ipw_init_task, sc); 209 210 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 211 device_printf(dev, "chip is in D%d power mode " 212 "-- setting to D0\n", pci_get_powerstate(dev)); 213 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 214 } 215 216 pci_write_config(dev, 0x41, 0, 1); 217 218 /* enable bus-mastering */ 219 pci_enable_busmaster(dev); 220 221 sc->mem_rid = IPW_PCI_BAR0; 222 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 223 RF_ACTIVE); 224 if (sc->mem == NULL) { 225 device_printf(dev, "could not allocate memory resource\n"); 226 goto fail; 227 } 228 229 sc->sc_st = rman_get_bustag(sc->mem); 230 sc->sc_sh = rman_get_bushandle(sc->mem); 231 232 sc->irq_rid = 0; 233 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 234 RF_ACTIVE | RF_SHAREABLE); 235 if (sc->irq == NULL) { 236 device_printf(dev, "could not allocate interrupt resource\n"); 237 goto fail; 238 } 239 240 if (ipw_reset(sc) != 0) { 241 device_printf(dev, "could not reset adapter\n"); 242 goto fail; 243 } 244 245 if (ipw_dma_alloc(sc) != 0) { 246 device_printf(dev, "could not allocate DMA resources\n"); 247 goto fail; 248 } 249 250 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 251 if (ifp == NULL) { 252 device_printf(dev, "can not if_alloc()\n"); 253 goto fail; 254 } 255 256 ifp->if_softc = sc; 257 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 258 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 259 ifp->if_init = ipw_init; 260 ifp->if_ioctl = ipw_ioctl; 261 ifp->if_start = ipw_start; 262 ifp->if_watchdog = ipw_watchdog; 263 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 264 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 265 IFQ_SET_READY(&ifp->if_snd); 266 267 ic->ic_ifp = ifp; 268 ic->ic_phytype = IEEE80211_T_DS; 269 ic->ic_opmode = IEEE80211_M_STA; 270 ic->ic_state = IEEE80211_S_INIT; 271 272 /* set device capabilities */ 273 ic->ic_caps = 274 IEEE80211_C_IBSS | /* IBSS mode supported */ 275 IEEE80211_C_MONITOR | /* monitor mode supported */ 276 IEEE80211_C_TXPMGT | /* tx power management */ 277 IEEE80211_C_SHPREAMBLE; /* short preamble supported */ 278 279 /* read MAC address from EEPROM */ 280 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 281 ic->ic_myaddr[0] = val >> 8; 282 ic->ic_myaddr[1] = val & 0xff; 283 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 284 ic->ic_myaddr[2] = val >> 8; 285 ic->ic_myaddr[3] = val & 0xff; 286 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 287 ic->ic_myaddr[4] = val >> 8; 288 ic->ic_myaddr[5] = val & 0xff; 289 290 /* set supported .11b channels */ 291 for (i = 1; i < 14; i++) { 292 ic->ic_channels[i].ic_freq = 293 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 294 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 295 } 296 297 /* check support for radio transmitter switch in EEPROM */ 298 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 299 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 300 301 ieee80211_ifattach(ic); 302 /* override state transition machine */ 303 sc->sc_newstate = ic->ic_newstate; 304 ic->ic_newstate = ipw_newstate; 305 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 306 307 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 308 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 309 310 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 311 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 312 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 313 314 sc->sc_txtap_len = sizeof sc->sc_txtapu; 315 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 316 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 317 318 /* 319 * Add a few sysctl knobs. 320 */ 321 sc->dwelltime = 100; 322 323 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 324 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "radio", 325 CTLTYPE_INT | CTLFLAG_RD, sc, 0, ipw_sysctl_radio, "I", 326 "radio transmitter switch state (0=off, 1=on)"); 327 328 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 329 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats", 330 CTLTYPE_OPAQUE | CTLFLAG_RD, sc, 0, ipw_sysctl_stats, "S", 331 "statistics"); 332 333 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 334 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", 335 CTLFLAG_RW, &sc->dwelltime, 0, 336 "channel dwell time (ms) for AP/station scanning"); 337 338 /* 339 * Hook our interrupt after all initialization is complete. 340 */ 341 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 342 NULL, ipw_intr, sc, &sc->sc_ih); 343 if (error != 0) { 344 device_printf(dev, "could not set up interrupt\n"); 345 goto fail; 346 } 347 348 if (bootverbose) 349 ieee80211_announce(ic); 350 351 return 0; 352 353 fail: ipw_detach(dev); 354 return ENXIO; 355 } 356 357 static int 358 ipw_detach(device_t dev) 359 { 360 struct ipw_softc *sc = device_get_softc(dev); 361 struct ieee80211com *ic = &sc->sc_ic; 362 struct ifnet *ifp = ic->ic_ifp; 363 364 ipw_stop(sc); 365 366 if (ifp != NULL) { 367 bpfdetach(ifp); 368 ieee80211_ifdetach(ic); 369 } 370 371 ipw_release(sc); 372 373 if (sc->irq != NULL) { 374 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 375 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 376 } 377 378 if (sc->mem != NULL) 379 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 380 381 if (ifp != NULL) 382 if_free(ifp); 383 384 if (sc->sc_firmware != NULL) { 385 firmware_put(sc->sc_firmware, FIRMWARE_UNLOAD); 386 sc->sc_firmware = NULL; 387 } 388 389 mtx_destroy(&sc->sc_mtx); 390 391 return 0; 392 } 393 394 static int 395 ipw_dma_alloc(struct ipw_softc *sc) 396 { 397 struct ipw_soft_bd *sbd; 398 struct ipw_soft_hdr *shdr; 399 struct ipw_soft_buf *sbuf; 400 bus_addr_t physaddr; 401 int error, i; 402 403 /* 404 * Allocate and map tx ring. 405 */ 406 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 407 BUS_SPACE_MAXADDR, NULL, NULL, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, NULL, 408 NULL, &sc->tbd_dmat); 409 if (error != 0) { 410 device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); 411 goto fail; 412 } 413 414 error = bus_dmamem_alloc(sc->tbd_dmat, (void **)&sc->tbd_list, 415 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tbd_map); 416 if (error != 0) { 417 device_printf(sc->sc_dev, 418 "could not allocate tx ring DMA memory\n"); 419 goto fail; 420 } 421 422 error = bus_dmamap_load(sc->tbd_dmat, sc->tbd_map, sc->tbd_list, 423 IPW_TBD_SZ, ipw_dma_map_addr, &sc->tbd_phys, 0); 424 if (error != 0) { 425 device_printf(sc->sc_dev, "could not map tx ring DMA memory\n"); 426 goto fail; 427 } 428 429 /* 430 * Allocate and map rx ring. 431 */ 432 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 433 BUS_SPACE_MAXADDR, NULL, NULL, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, NULL, 434 NULL, &sc->rbd_dmat); 435 if (error != 0) { 436 device_printf(sc->sc_dev, "could not create rx ring DMA tag\n"); 437 goto fail; 438 } 439 440 error = bus_dmamem_alloc(sc->rbd_dmat, (void **)&sc->rbd_list, 441 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rbd_map); 442 if (error != 0) { 443 device_printf(sc->sc_dev, 444 "could not allocate rx ring DMA memory\n"); 445 goto fail; 446 } 447 448 error = bus_dmamap_load(sc->rbd_dmat, sc->rbd_map, sc->rbd_list, 449 IPW_RBD_SZ, ipw_dma_map_addr, &sc->rbd_phys, 0); 450 if (error != 0) { 451 device_printf(sc->sc_dev, "could not map rx ring DMA memory\n"); 452 goto fail; 453 } 454 455 /* 456 * Allocate and map status ring. 457 */ 458 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 459 BUS_SPACE_MAXADDR, NULL, NULL, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 0, 460 NULL, NULL, &sc->status_dmat); 461 if (error != 0) { 462 device_printf(sc->sc_dev, 463 "could not create status ring DMA tag\n"); 464 goto fail; 465 } 466 467 error = bus_dmamem_alloc(sc->status_dmat, (void **)&sc->status_list, 468 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->status_map); 469 if (error != 0) { 470 device_printf(sc->sc_dev, 471 "could not allocate status ring DMA memory\n"); 472 goto fail; 473 } 474 475 error = bus_dmamap_load(sc->status_dmat, sc->status_map, 476 sc->status_list, IPW_STATUS_SZ, ipw_dma_map_addr, &sc->status_phys, 477 0); 478 if (error != 0) { 479 device_printf(sc->sc_dev, 480 "could not map status ring DMA memory\n"); 481 goto fail; 482 } 483 484 /* 485 * Allocate command DMA map. 486 */ 487 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 488 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_cmd), 1, 489 sizeof (struct ipw_cmd), 0, NULL, NULL, &sc->cmd_dmat); 490 if (error != 0) { 491 device_printf(sc->sc_dev, "could not create command DMA tag\n"); 492 goto fail; 493 } 494 495 error = bus_dmamap_create(sc->cmd_dmat, 0, &sc->cmd_map); 496 if (error != 0) { 497 device_printf(sc->sc_dev, 498 "could not create command DMA map\n"); 499 goto fail; 500 } 501 502 /* 503 * Allocate headers DMA maps. 504 */ 505 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 506 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_hdr), 1, 507 sizeof (struct ipw_hdr), 0, NULL, NULL, &sc->hdr_dmat); 508 if (error != 0) { 509 device_printf(sc->sc_dev, "could not create header DMA tag\n"); 510 goto fail; 511 } 512 513 SLIST_INIT(&sc->free_shdr); 514 for (i = 0; i < IPW_NDATA; i++) { 515 shdr = &sc->shdr_list[i]; 516 error = bus_dmamap_create(sc->hdr_dmat, 0, &shdr->map); 517 if (error != 0) { 518 device_printf(sc->sc_dev, 519 "could not create header DMA map\n"); 520 goto fail; 521 } 522 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 523 } 524 525 /* 526 * Allocate tx buffers DMA maps. 527 */ 528 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 529 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_MAX_NSEG, MCLBYTES, 0, 530 NULL, NULL, &sc->txbuf_dmat); 531 if (error != 0) { 532 device_printf(sc->sc_dev, "could not create tx DMA tag\n"); 533 goto fail; 534 } 535 536 SLIST_INIT(&sc->free_sbuf); 537 for (i = 0; i < IPW_NDATA; i++) { 538 sbuf = &sc->tx_sbuf_list[i]; 539 error = bus_dmamap_create(sc->txbuf_dmat, 0, &sbuf->map); 540 if (error != 0) { 541 device_printf(sc->sc_dev, 542 "could not create tx DMA map\n"); 543 goto fail; 544 } 545 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 546 } 547 548 /* 549 * Initialize tx ring. 550 */ 551 for (i = 0; i < IPW_NTBD; i++) { 552 sbd = &sc->stbd_list[i]; 553 sbd->bd = &sc->tbd_list[i]; 554 sbd->type = IPW_SBD_TYPE_NOASSOC; 555 } 556 557 /* 558 * Pre-allocate rx buffers and DMA maps. 559 */ 560 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 561 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, 562 NULL, &sc->rxbuf_dmat); 563 if (error != 0) { 564 device_printf(sc->sc_dev, "could not create rx DMA tag\n"); 565 goto fail; 566 } 567 568 for (i = 0; i < IPW_NRBD; i++) { 569 sbd = &sc->srbd_list[i]; 570 sbuf = &sc->rx_sbuf_list[i]; 571 sbd->bd = &sc->rbd_list[i]; 572 573 sbuf->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 574 if (sbuf->m == NULL) { 575 device_printf(sc->sc_dev, 576 "could not allocate rx mbuf\n"); 577 error = ENOMEM; 578 goto fail; 579 } 580 581 error = bus_dmamap_create(sc->rxbuf_dmat, 0, &sbuf->map); 582 if (error != 0) { 583 device_printf(sc->sc_dev, 584 "could not create rx DMA map\n"); 585 goto fail; 586 } 587 588 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 589 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 590 &physaddr, 0); 591 if (error != 0) { 592 device_printf(sc->sc_dev, 593 "could not map rx DMA memory\n"); 594 goto fail; 595 } 596 597 sbd->type = IPW_SBD_TYPE_DATA; 598 sbd->priv = sbuf; 599 sbd->bd->physaddr = htole32(physaddr); 600 sbd->bd->len = htole32(MCLBYTES); 601 } 602 603 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 604 605 return 0; 606 607 fail: ipw_release(sc); 608 return error; 609 } 610 611 static void 612 ipw_release(struct ipw_softc *sc) 613 { 614 struct ipw_soft_buf *sbuf; 615 int i; 616 617 if (sc->tbd_dmat != NULL) { 618 if (sc->stbd_list != NULL) { 619 bus_dmamap_unload(sc->tbd_dmat, sc->tbd_map); 620 bus_dmamem_free(sc->tbd_dmat, sc->tbd_list, 621 sc->tbd_map); 622 } 623 bus_dma_tag_destroy(sc->tbd_dmat); 624 } 625 626 if (sc->rbd_dmat != NULL) { 627 if (sc->rbd_list != NULL) { 628 bus_dmamap_unload(sc->rbd_dmat, sc->rbd_map); 629 bus_dmamem_free(sc->rbd_dmat, sc->rbd_list, 630 sc->rbd_map); 631 } 632 bus_dma_tag_destroy(sc->rbd_dmat); 633 } 634 635 if (sc->status_dmat != NULL) { 636 if (sc->status_list != NULL) { 637 bus_dmamap_unload(sc->status_dmat, sc->status_map); 638 bus_dmamem_free(sc->status_dmat, sc->status_list, 639 sc->status_map); 640 } 641 bus_dma_tag_destroy(sc->status_dmat); 642 } 643 644 for (i = 0; i < IPW_NTBD; i++) 645 ipw_release_sbd(sc, &sc->stbd_list[i]); 646 647 if (sc->cmd_dmat != NULL) { 648 bus_dmamap_destroy(sc->cmd_dmat, sc->cmd_map); 649 bus_dma_tag_destroy(sc->cmd_dmat); 650 } 651 652 if (sc->hdr_dmat != NULL) { 653 for (i = 0; i < IPW_NDATA; i++) 654 bus_dmamap_destroy(sc->hdr_dmat, sc->shdr_list[i].map); 655 bus_dma_tag_destroy(sc->hdr_dmat); 656 } 657 658 if (sc->txbuf_dmat != NULL) { 659 for (i = 0; i < IPW_NDATA; i++) { 660 bus_dmamap_destroy(sc->txbuf_dmat, 661 sc->tx_sbuf_list[i].map); 662 } 663 bus_dma_tag_destroy(sc->txbuf_dmat); 664 } 665 666 if (sc->rxbuf_dmat != NULL) { 667 for (i = 0; i < IPW_NRBD; i++) { 668 sbuf = &sc->rx_sbuf_list[i]; 669 if (sbuf->m != NULL) { 670 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, 671 BUS_DMASYNC_POSTREAD); 672 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 673 m_freem(sbuf->m); 674 } 675 bus_dmamap_destroy(sc->rxbuf_dmat, sbuf->map); 676 } 677 bus_dma_tag_destroy(sc->rxbuf_dmat); 678 } 679 } 680 681 static int 682 ipw_shutdown(device_t dev) 683 { 684 struct ipw_softc *sc = device_get_softc(dev); 685 686 ipw_stop(sc); 687 688 return 0; 689 } 690 691 static int 692 ipw_suspend(device_t dev) 693 { 694 struct ipw_softc *sc = device_get_softc(dev); 695 696 ipw_stop(sc); 697 698 return 0; 699 } 700 701 static int 702 ipw_resume(device_t dev) 703 { 704 struct ipw_softc *sc = device_get_softc(dev); 705 struct ifnet *ifp = sc->sc_ic.ic_ifp; 706 707 mtx_lock(&sc->sc_mtx); 708 709 pci_write_config(dev, 0x41, 0, 1); 710 711 if (ifp->if_flags & IFF_UP) { 712 ifp->if_init(ifp->if_softc); 713 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 714 ifp->if_start(ifp); 715 } 716 717 mtx_unlock(&sc->sc_mtx); 718 719 return 0; 720 } 721 722 static int 723 ipw_media_change(struct ifnet *ifp) 724 { 725 struct ipw_softc *sc = ifp->if_softc; 726 int error; 727 728 mtx_lock(&sc->sc_mtx); 729 730 error = ieee80211_media_change(ifp); 731 if (error != ENETRESET) { 732 mtx_unlock(&sc->sc_mtx); 733 return error; 734 } 735 736 if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 737 ipw_init(sc); 738 739 mtx_unlock(&sc->sc_mtx); 740 741 return 0; 742 } 743 744 /* 745 * The firmware automatically adapts the transmit speed. We report its current 746 * value here. 747 */ 748 static void 749 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 750 { 751 #define N(a) (sizeof (a) / sizeof (a[0])) 752 struct ipw_softc *sc = ifp->if_softc; 753 struct ieee80211com *ic = &sc->sc_ic; 754 static const struct { 755 uint32_t val; 756 int rate; 757 } rates[] = { 758 { IPW_RATE_DS1, 2 }, 759 { IPW_RATE_DS2, 4 }, 760 { IPW_RATE_DS5, 11 }, 761 { IPW_RATE_DS11, 22 }, 762 }; 763 uint32_t val; 764 int rate, i; 765 766 imr->ifm_status = IFM_AVALID; 767 imr->ifm_active = IFM_IEEE80211; 768 if (ic->ic_state == IEEE80211_S_RUN) 769 imr->ifm_status |= IFM_ACTIVE; 770 771 /* read current transmission rate from adapter */ 772 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 773 774 /* convert ipw rate to 802.11 rate */ 775 for (i = 0; i < N(rates) && rates[i].val != val; i++); 776 rate = (i < N(rates)) ? rates[i].rate : 0; 777 778 imr->ifm_active |= IFM_IEEE80211_11B; 779 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 780 switch (ic->ic_opmode) { 781 case IEEE80211_M_STA: 782 break; 783 784 case IEEE80211_M_IBSS: 785 imr->ifm_active |= IFM_IEEE80211_IBSS; 786 break; 787 788 case IEEE80211_M_MONITOR: 789 imr->ifm_active |= IFM_IEEE80211_MONITOR; 790 break; 791 792 case IEEE80211_M_AHDEMO: 793 case IEEE80211_M_HOSTAP: 794 /* should not get there */ 795 break; 796 } 797 #undef N 798 } 799 800 static int 801 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 802 { 803 struct ifnet *ifp = ic->ic_ifp; 804 struct ipw_softc *sc = ifp->if_softc; 805 struct ieee80211_node *ni; 806 uint8_t macaddr[IEEE80211_ADDR_LEN]; 807 uint32_t len; 808 809 switch (nstate) { 810 case IEEE80211_S_RUN: 811 DELAY(200); /* firmware needs a short delay here */ 812 813 len = IEEE80211_ADDR_LEN; 814 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 815 816 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 817 if (ni == NULL) 818 break; 819 820 ieee80211_ref_node(ni); 821 ieee80211_sta_join(ic, ni); 822 ieee80211_node_authorize(ni); 823 824 if (ic->ic_opmode == IEEE80211_M_STA) 825 ieee80211_notify_node_join(ic, ni, 1); 826 break; 827 828 case IEEE80211_S_INIT: 829 case IEEE80211_S_SCAN: 830 case IEEE80211_S_AUTH: 831 case IEEE80211_S_ASSOC: 832 break; 833 } 834 835 ic->ic_state = nstate; 836 837 return 0; 838 } 839 840 /* 841 * Read 16 bits at address 'addr' from the serial EEPROM. 842 */ 843 static uint16_t 844 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 845 { 846 uint32_t tmp; 847 uint16_t val; 848 int n; 849 850 /* clock C once before the first command */ 851 IPW_EEPROM_CTL(sc, 0); 852 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 853 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 854 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 855 856 /* write start bit (1) */ 857 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 858 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 859 860 /* write READ opcode (10) */ 861 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 862 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 864 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 865 866 /* write address A7-A0 */ 867 for (n = 7; n >= 0; n--) { 868 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 869 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 871 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 872 } 873 874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 875 876 /* read data Q15-Q0 */ 877 val = 0; 878 for (n = 15; n >= 0; n--) { 879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 880 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 881 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 882 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 883 } 884 885 IPW_EEPROM_CTL(sc, 0); 886 887 /* clear Chip Select and clock C */ 888 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 889 IPW_EEPROM_CTL(sc, 0); 890 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 891 892 return le16toh(val); 893 } 894 895 static void 896 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 897 { 898 struct ipw_cmd *cmd; 899 900 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 901 902 cmd = mtod(sbuf->m, struct ipw_cmd *); 903 904 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 905 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 906 le32toh(cmd->status))); 907 908 wakeup(sc); 909 } 910 911 static void 912 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 913 { 914 struct ieee80211com *ic = &sc->sc_ic; 915 uint32_t state; 916 917 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 918 919 state = le32toh(*mtod(sbuf->m, uint32_t *)); 920 921 DPRINTFN(2, ("entering state %u\n", state)); 922 923 switch (state) { 924 case IPW_STATE_ASSOCIATED: 925 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 926 break; 927 928 case IPW_STATE_SCANNING: 929 /* don't leave run state on background scan */ 930 if (ic->ic_state != IEEE80211_S_RUN) 931 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 932 933 ic->ic_flags |= IEEE80211_F_SCAN; 934 break; 935 936 case IPW_STATE_SCAN_COMPLETE: 937 ieee80211_notify_scan_done(ic); 938 ic->ic_flags &= ~IEEE80211_F_SCAN; 939 break; 940 941 case IPW_STATE_ASSOCIATION_LOST: 942 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 943 break; 944 945 case IPW_STATE_RADIO_DISABLED: 946 ic->ic_ifp->if_flags &= ~IFF_UP; 947 ipw_stop(sc); 948 break; 949 } 950 } 951 952 /* 953 * XXX: Hack to set the current channel to the value advertised in beacons or 954 * probe responses. Only used during AP detection. 955 */ 956 static void 957 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 958 { 959 struct ieee80211_frame *wh; 960 uint8_t subtype; 961 uint8_t *frm, *efrm; 962 963 wh = mtod(m, struct ieee80211_frame *); 964 965 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 966 return; 967 968 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 969 970 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 971 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 972 return; 973 974 frm = (uint8_t *)(wh + 1); 975 efrm = mtod(m, uint8_t *) + m->m_len; 976 977 frm += 12; /* skip tstamp, bintval and capinfo fields */ 978 while (frm < efrm) { 979 if (*frm == IEEE80211_ELEMID_DSPARMS) 980 #if IEEE80211_CHAN_MAX < 255 981 if (frm[2] <= IEEE80211_CHAN_MAX) 982 #endif 983 ic->ic_curchan = &ic->ic_channels[frm[2]]; 984 985 frm += frm[1] + 2; 986 } 987 } 988 989 static void 990 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 991 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 992 { 993 struct ieee80211com *ic = &sc->sc_ic; 994 struct ifnet *ifp = ic->ic_ifp; 995 struct mbuf *mnew, *m; 996 struct ieee80211_frame *wh; 997 struct ieee80211_node *ni; 998 bus_addr_t physaddr; 999 int error; 1000 1001 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1002 status->rssi)); 1003 1004 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1005 le32toh(status->len) > MCLBYTES) 1006 return; 1007 1008 /* 1009 * Try to allocate a new mbuf for this ring element and load it before 1010 * processing the current mbuf. If the ring element cannot be loaded, 1011 * drop the received packet and reuse the old mbuf. In the unlikely 1012 * case that the old mbuf can't be reloaded either, explicitly panic. 1013 */ 1014 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1015 if (mnew == NULL) { 1016 ifp->if_ierrors++; 1017 return; 1018 } 1019 1020 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 1021 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 1022 1023 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, mtod(mnew, void *), 1024 MCLBYTES, ipw_dma_map_addr, &physaddr, 0); 1025 if (error != 0) { 1026 m_freem(mnew); 1027 1028 /* try to reload the old mbuf */ 1029 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 1030 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 1031 &physaddr, 0); 1032 if (error != 0) { 1033 /* very unlikely that it will fail... */ 1034 panic("%s: could not load old rx mbuf", 1035 device_get_name(sc->sc_dev)); 1036 } 1037 ifp->if_ierrors++; 1038 return; 1039 } 1040 1041 /* 1042 * New mbuf successfully loaded, update Rx ring and continue 1043 * processing. 1044 */ 1045 m = sbuf->m; 1046 sbuf->m = mnew; 1047 sbd->bd->physaddr = htole32(physaddr); 1048 1049 /* finalize mbuf */ 1050 m->m_pkthdr.rcvif = ifp; 1051 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1052 1053 if (bpf_peers_present(sc->sc_drvbpf)) { 1054 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1055 1056 tap->wr_flags = 0; 1057 tap->wr_antsignal = status->rssi; 1058 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1059 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1060 1061 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1062 } 1063 1064 if (ic->ic_state == IEEE80211_S_SCAN) 1065 ipw_fix_channel(ic, m); 1066 1067 wh = mtod(m, struct ieee80211_frame *); 1068 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1069 1070 /* send the frame to the 802.11 layer */ 1071 ieee80211_input(ic, m, ni, status->rssi, 0); 1072 1073 /* node is no longer needed */ 1074 ieee80211_free_node(ni); 1075 1076 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1077 } 1078 1079 static void 1080 ipw_rx_intr(struct ipw_softc *sc) 1081 { 1082 struct ipw_status *status; 1083 struct ipw_soft_bd *sbd; 1084 struct ipw_soft_buf *sbuf; 1085 uint32_t r, i; 1086 1087 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1088 return; 1089 1090 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1091 1092 bus_dmamap_sync(sc->status_dmat, sc->status_map, BUS_DMASYNC_POSTREAD); 1093 1094 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1095 status = &sc->status_list[i]; 1096 sbd = &sc->srbd_list[i]; 1097 sbuf = sbd->priv; 1098 1099 switch (le16toh(status->code) & 0xf) { 1100 case IPW_STATUS_CODE_COMMAND: 1101 ipw_command_intr(sc, sbuf); 1102 break; 1103 1104 case IPW_STATUS_CODE_NEWSTATE: 1105 ipw_newstate_intr(sc, sbuf); 1106 break; 1107 1108 case IPW_STATUS_CODE_DATA_802_3: 1109 case IPW_STATUS_CODE_DATA_802_11: 1110 ipw_data_intr(sc, status, sbd, sbuf); 1111 break; 1112 1113 case IPW_STATUS_CODE_NOTIFICATION: 1114 DPRINTFN(2, ("received notification\n")); 1115 break; 1116 1117 default: 1118 device_printf(sc->sc_dev, "unknown status code %u\n", 1119 le16toh(status->code)); 1120 } 1121 1122 /* firmware was killed, stop processing received frames */ 1123 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1124 return; 1125 1126 sbd->bd->flags = 0; 1127 } 1128 1129 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1130 1131 /* kick the firmware */ 1132 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1133 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1134 } 1135 1136 static void 1137 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1138 { 1139 struct ipw_soft_hdr *shdr; 1140 struct ipw_soft_buf *sbuf; 1141 1142 switch (sbd->type) { 1143 case IPW_SBD_TYPE_COMMAND: 1144 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, 1145 BUS_DMASYNC_POSTWRITE); 1146 bus_dmamap_unload(sc->cmd_dmat, sc->cmd_map); 1147 break; 1148 1149 case IPW_SBD_TYPE_HEADER: 1150 shdr = sbd->priv; 1151 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_POSTWRITE); 1152 bus_dmamap_unload(sc->hdr_dmat, shdr->map); 1153 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1154 break; 1155 1156 case IPW_SBD_TYPE_DATA: 1157 sbuf = sbd->priv; 1158 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, 1159 BUS_DMASYNC_POSTWRITE); 1160 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1161 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1162 1163 m_freem(sbuf->m); 1164 ieee80211_free_node(sbuf->ni); 1165 1166 sc->sc_tx_timer = 0; 1167 break; 1168 } 1169 1170 sbd->type = IPW_SBD_TYPE_NOASSOC; 1171 } 1172 1173 static void 1174 ipw_tx_intr(struct ipw_softc *sc) 1175 { 1176 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1177 struct ipw_soft_bd *sbd; 1178 uint32_t r, i; 1179 1180 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1181 return; 1182 1183 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1184 1185 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1186 sbd = &sc->stbd_list[i]; 1187 1188 if (sbd->type == IPW_SBD_TYPE_DATA) 1189 ifp->if_opackets++; 1190 1191 ipw_release_sbd(sc, sbd); 1192 sc->txfree++; 1193 } 1194 1195 /* remember what the firmware has processed */ 1196 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1197 1198 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1199 ipw_start(ifp); 1200 } 1201 1202 static void 1203 ipw_intr(void *arg) 1204 { 1205 struct ipw_softc *sc = arg; 1206 uint32_t r; 1207 1208 mtx_lock(&sc->sc_mtx); 1209 1210 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) { 1211 mtx_unlock(&sc->sc_mtx); 1212 return; 1213 } 1214 1215 /* disable interrupts */ 1216 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1217 1218 /* acknowledge all interrupts */ 1219 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1220 1221 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1222 device_printf(sc->sc_dev, "firmware error\n"); 1223 taskqueue_enqueue_fast(taskqueue_fast, &sc->sc_init_task); 1224 r = 0; /* don't process more interrupts */ 1225 } 1226 1227 if (r & IPW_INTR_FW_INIT_DONE) 1228 wakeup(sc); 1229 1230 if (r & IPW_INTR_RX_TRANSFER) 1231 ipw_rx_intr(sc); 1232 1233 if (r & IPW_INTR_TX_TRANSFER) 1234 ipw_tx_intr(sc); 1235 1236 /* re-enable interrupts */ 1237 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1238 1239 mtx_unlock(&sc->sc_mtx); 1240 } 1241 1242 static void 1243 ipw_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1244 { 1245 if (error != 0) 1246 return; 1247 1248 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1249 1250 *(bus_addr_t *)arg = segs[0].ds_addr; 1251 } 1252 1253 /* 1254 * Send a command to the firmware and wait for the acknowledgement. 1255 */ 1256 static int 1257 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1258 { 1259 struct ipw_soft_bd *sbd; 1260 bus_addr_t physaddr; 1261 int error; 1262 1263 sbd = &sc->stbd_list[sc->txcur]; 1264 1265 error = bus_dmamap_load(sc->cmd_dmat, sc->cmd_map, &sc->cmd, 1266 sizeof (struct ipw_cmd), ipw_dma_map_addr, &physaddr, 0); 1267 if (error != 0) { 1268 device_printf(sc->sc_dev, "could not map command DMA memory\n"); 1269 return error; 1270 } 1271 1272 sc->cmd.type = htole32(type); 1273 sc->cmd.subtype = 0; 1274 sc->cmd.len = htole32(len); 1275 sc->cmd.seq = 0; 1276 memcpy(sc->cmd.data, data, len); 1277 1278 sbd->type = IPW_SBD_TYPE_COMMAND; 1279 sbd->bd->physaddr = htole32(physaddr); 1280 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1281 sbd->bd->nfrag = 1; 1282 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1283 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1284 1285 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, BUS_DMASYNC_PREWRITE); 1286 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1287 1288 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1289 1290 /* kick firmware */ 1291 sc->txfree--; 1292 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1293 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1294 1295 /* wait at most one second for command to complete */ 1296 return msleep(sc, &sc->sc_mtx, 0, "ipwcmd", hz); 1297 } 1298 1299 static int 1300 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1301 { 1302 struct ipw_softc *sc = ifp->if_softc; 1303 struct ieee80211com *ic = &sc->sc_ic; 1304 struct ieee80211_frame *wh; 1305 struct ipw_soft_bd *sbd; 1306 struct ipw_soft_hdr *shdr; 1307 struct ipw_soft_buf *sbuf; 1308 struct ieee80211_key *k; 1309 struct mbuf *mnew; 1310 bus_dma_segment_t segs[IPW_MAX_NSEG]; 1311 bus_addr_t physaddr; 1312 int nsegs, error, i; 1313 1314 wh = mtod(m0, struct ieee80211_frame *); 1315 1316 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1317 k = ieee80211_crypto_encap(ic, ni, m0); 1318 if (k == NULL) { 1319 m_freem(m0); 1320 return ENOBUFS; 1321 } 1322 1323 /* packet header may have moved, reset our local pointer */ 1324 wh = mtod(m0, struct ieee80211_frame *); 1325 } 1326 1327 if (bpf_peers_present(sc->sc_drvbpf)) { 1328 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1329 1330 tap->wt_flags = 0; 1331 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1332 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1333 1334 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1335 } 1336 1337 shdr = SLIST_FIRST(&sc->free_shdr); 1338 sbuf = SLIST_FIRST(&sc->free_sbuf); 1339 KASSERT(shdr != NULL && sbuf != NULL, ("empty sw hdr/buf pool")); 1340 1341 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1342 shdr->hdr.subtype = 0; 1343 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1344 shdr->hdr.encrypt = 0; 1345 shdr->hdr.keyidx = 0; 1346 shdr->hdr.keysz = 0; 1347 shdr->hdr.fragmentsz = 0; 1348 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1349 if (ic->ic_opmode == IEEE80211_M_STA) 1350 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1351 else 1352 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1353 1354 /* trim IEEE802.11 header */ 1355 m_adj(m0, sizeof (struct ieee80211_frame)); 1356 1357 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, segs, 1358 &nsegs, 0); 1359 if (error != 0 && error != EFBIG) { 1360 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1361 error); 1362 m_freem(m0); 1363 return error; 1364 } 1365 if (error != 0) { 1366 mnew = m_defrag(m0, M_DONTWAIT); 1367 if (mnew == NULL) { 1368 device_printf(sc->sc_dev, 1369 "could not defragment mbuf\n"); 1370 m_freem(m0); 1371 return ENOBUFS; 1372 } 1373 m0 = mnew; 1374 1375 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, 1376 segs, &nsegs, 0); 1377 if (error != 0) { 1378 device_printf(sc->sc_dev, 1379 "could not map mbuf (error %d)\n", error); 1380 m_freem(m0); 1381 return error; 1382 } 1383 } 1384 1385 error = bus_dmamap_load(sc->hdr_dmat, shdr->map, &shdr->hdr, 1386 sizeof (struct ipw_hdr), ipw_dma_map_addr, &physaddr, 0); 1387 if (error != 0) { 1388 device_printf(sc->sc_dev, "could not map header DMA memory\n"); 1389 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1390 m_freem(m0); 1391 return error; 1392 } 1393 1394 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1395 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1396 1397 sbd = &sc->stbd_list[sc->txcur]; 1398 sbd->type = IPW_SBD_TYPE_HEADER; 1399 sbd->priv = shdr; 1400 sbd->bd->physaddr = htole32(physaddr); 1401 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1402 sbd->bd->nfrag = 1 + nsegs; 1403 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1404 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1405 1406 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, %6D, %6D)\n", 1407 shdr->hdr.type, shdr->hdr.subtype, shdr->hdr.encrypted, 1408 shdr->hdr.encrypt, shdr->hdr.src_addr, ":", shdr->hdr.dst_addr, 1409 ":")); 1410 1411 sc->txfree--; 1412 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1413 1414 sbuf->m = m0; 1415 sbuf->ni = ni; 1416 1417 for (i = 0; i < nsegs; i++) { 1418 sbd = &sc->stbd_list[sc->txcur]; 1419 1420 sbd->bd->physaddr = htole32(segs[i].ds_addr); 1421 sbd->bd->len = htole32(segs[i].ds_len); 1422 sbd->bd->nfrag = 0; 1423 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1424 if (i == nsegs - 1) { 1425 sbd->type = IPW_SBD_TYPE_DATA; 1426 sbd->priv = sbuf; 1427 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1428 } else { 1429 sbd->type = IPW_SBD_TYPE_NOASSOC; 1430 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1431 } 1432 1433 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, segs[i].ds_len)); 1434 1435 sc->txfree--; 1436 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1437 } 1438 1439 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_PREWRITE); 1440 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, BUS_DMASYNC_PREWRITE); 1441 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1442 1443 /* kick firmware */ 1444 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1445 1446 return 0; 1447 } 1448 1449 static void 1450 ipw_start(struct ifnet *ifp) 1451 { 1452 struct ipw_softc *sc = ifp->if_softc; 1453 struct ieee80211com *ic = &sc->sc_ic; 1454 struct mbuf *m0; 1455 struct ether_header *eh; 1456 struct ieee80211_node *ni; 1457 1458 mtx_lock(&sc->sc_mtx); 1459 1460 if (ic->ic_state != IEEE80211_S_RUN) { 1461 mtx_unlock(&sc->sc_mtx); 1462 return; 1463 } 1464 1465 for (;;) { 1466 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1467 if (m0 == NULL) 1468 break; 1469 1470 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1471 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1472 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1473 break; 1474 } 1475 1476 if (m0->m_len < sizeof (struct ether_header) && 1477 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1478 continue; 1479 1480 eh = mtod(m0, struct ether_header *); 1481 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1482 if (ni == NULL) { 1483 m_freem(m0); 1484 continue; 1485 } 1486 BPF_MTAP(ifp, m0); 1487 1488 m0 = ieee80211_encap(ic, m0, ni); 1489 if (m0 == NULL) { 1490 ieee80211_free_node(ni); 1491 continue; 1492 } 1493 1494 if (bpf_peers_present(ic->ic_rawbpf)) 1495 bpf_mtap(ic->ic_rawbpf, m0); 1496 1497 if (ipw_tx_start(ifp, m0, ni) != 0) { 1498 ieee80211_free_node(ni); 1499 ifp->if_oerrors++; 1500 break; 1501 } 1502 1503 /* start watchdog timer */ 1504 sc->sc_tx_timer = 5; 1505 ifp->if_timer = 1; 1506 } 1507 1508 mtx_unlock(&sc->sc_mtx); 1509 } 1510 1511 static void 1512 ipw_watchdog(struct ifnet *ifp) 1513 { 1514 struct ipw_softc *sc = ifp->if_softc; 1515 struct ieee80211com *ic = &sc->sc_ic; 1516 1517 mtx_lock(&sc->sc_mtx); 1518 1519 ifp->if_timer = 0; 1520 1521 if (sc->sc_tx_timer > 0) { 1522 if (--sc->sc_tx_timer == 0) { 1523 if_printf(ifp, "device timeout\n"); 1524 ifp->if_oerrors++; 1525 taskqueue_enqueue_fast(taskqueue_fast, 1526 &sc->sc_init_task); 1527 mtx_unlock(&sc->sc_mtx); 1528 return; 1529 } 1530 ifp->if_timer = 1; 1531 } 1532 1533 ieee80211_watchdog(ic); 1534 1535 mtx_unlock(&sc->sc_mtx); 1536 } 1537 1538 static int 1539 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1540 { 1541 struct ipw_softc *sc = ifp->if_softc; 1542 struct ieee80211com *ic = &sc->sc_ic; 1543 int error = 0; 1544 1545 mtx_lock(&sc->sc_mtx); 1546 1547 switch (cmd) { 1548 case SIOCSIFFLAGS: 1549 if (ifp->if_flags & IFF_UP) { 1550 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1551 ipw_init(sc); 1552 } else { 1553 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1554 ipw_stop(sc); 1555 } 1556 break; 1557 1558 default: 1559 error = ieee80211_ioctl(ic, cmd, data); 1560 } 1561 1562 if (error == ENETRESET) { 1563 if ((ifp->if_flags & IFF_UP) && 1564 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1565 ipw_init(sc); 1566 error = 0; 1567 } 1568 1569 mtx_unlock(&sc->sc_mtx); 1570 1571 return error; 1572 } 1573 1574 static void 1575 ipw_stop_master(struct ipw_softc *sc) 1576 { 1577 uint32_t tmp; 1578 int ntries; 1579 1580 /* disable interrupts */ 1581 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1582 1583 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1584 for (ntries = 0; ntries < 50; ntries++) { 1585 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1586 break; 1587 DELAY(10); 1588 } 1589 if (ntries == 50) 1590 device_printf(sc->sc_dev, "timeout waiting for master\n"); 1591 1592 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1593 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1594 1595 sc->flags &= ~IPW_FLAG_FW_INITED; 1596 } 1597 1598 static int 1599 ipw_reset(struct ipw_softc *sc) 1600 { 1601 uint32_t tmp; 1602 int ntries; 1603 1604 ipw_stop_master(sc); 1605 1606 /* move adapter to D0 state */ 1607 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1608 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1609 1610 /* wait for clock stabilization */ 1611 for (ntries = 0; ntries < 1000; ntries++) { 1612 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1613 break; 1614 DELAY(200); 1615 } 1616 if (ntries == 1000) 1617 return EIO; 1618 1619 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1620 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1621 1622 DELAY(10); 1623 1624 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1625 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1626 1627 return 0; 1628 } 1629 1630 /* 1631 * Upload the microcode to the device. 1632 */ 1633 static int 1634 ipw_load_ucode(struct ipw_softc *sc, const char *uc, int size) 1635 { 1636 int ntries; 1637 1638 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1639 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1640 1641 MEM_WRITE_2(sc, 0x220000, 0x0703); 1642 MEM_WRITE_2(sc, 0x220000, 0x0707); 1643 1644 MEM_WRITE_1(sc, 0x210014, 0x72); 1645 MEM_WRITE_1(sc, 0x210014, 0x72); 1646 1647 MEM_WRITE_1(sc, 0x210000, 0x40); 1648 MEM_WRITE_1(sc, 0x210000, 0x00); 1649 MEM_WRITE_1(sc, 0x210000, 0x40); 1650 1651 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1652 1653 MEM_WRITE_1(sc, 0x210000, 0x00); 1654 MEM_WRITE_1(sc, 0x210000, 0x00); 1655 MEM_WRITE_1(sc, 0x210000, 0x80); 1656 1657 MEM_WRITE_2(sc, 0x220000, 0x0703); 1658 MEM_WRITE_2(sc, 0x220000, 0x0707); 1659 1660 MEM_WRITE_1(sc, 0x210014, 0x72); 1661 MEM_WRITE_1(sc, 0x210014, 0x72); 1662 1663 MEM_WRITE_1(sc, 0x210000, 0x00); 1664 MEM_WRITE_1(sc, 0x210000, 0x80); 1665 1666 for (ntries = 0; ntries < 10; ntries++) { 1667 if (MEM_READ_1(sc, 0x210000) & 1) 1668 break; 1669 DELAY(10); 1670 } 1671 if (ntries == 10) { 1672 device_printf(sc->sc_dev, 1673 "timeout waiting for ucode to initialize\n"); 1674 return EIO; 1675 } 1676 1677 MEM_WRITE_4(sc, 0x3000e0, 0); 1678 1679 return 0; 1680 } 1681 1682 /* set of macros to handle unaligned little endian data in firmware image */ 1683 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1684 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1685 static int 1686 ipw_load_firmware(struct ipw_softc *sc, const char *fw, int size) 1687 { 1688 const uint8_t *p, *end; 1689 uint32_t tmp, dst; 1690 uint16_t len; 1691 int error; 1692 1693 p = fw; 1694 end = fw + size; 1695 while (p < end) { 1696 dst = GETLE32(p); p += 4; 1697 len = GETLE16(p); p += 2; 1698 1699 ipw_write_mem_1(sc, dst, p, len); 1700 p += len; 1701 } 1702 1703 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1704 IPW_IO_LED_OFF); 1705 1706 /* enable interrupts */ 1707 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1708 1709 /* kick the firmware */ 1710 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1711 1712 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1713 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1714 1715 /* wait at most one second for firmware initialization to complete */ 1716 if ((error = msleep(sc, &sc->sc_mtx, 0, "ipwinit", hz)) != 0) { 1717 device_printf(sc->sc_dev, "timeout waiting for firmware " 1718 "initialization to complete\n"); 1719 return error; 1720 } 1721 1722 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1723 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1724 IPW_IO_GPIO3_MASK); 1725 1726 return 0; 1727 } 1728 1729 static int 1730 ipw_config(struct ipw_softc *sc) 1731 { 1732 struct ieee80211com *ic = &sc->sc_ic; 1733 struct ifnet *ifp = ic->ic_ifp; 1734 struct ipw_security security; 1735 struct ieee80211_key *k; 1736 struct ipw_wep_key wepkey; 1737 struct ipw_scan_options options; 1738 struct ipw_configuration config; 1739 uint32_t data; 1740 int error, i; 1741 1742 switch (ic->ic_opmode) { 1743 case IEEE80211_M_STA: 1744 case IEEE80211_M_HOSTAP: 1745 data = htole32(IPW_MODE_BSS); 1746 break; 1747 case IEEE80211_M_IBSS: 1748 case IEEE80211_M_AHDEMO: 1749 data = htole32(IPW_MODE_IBSS); 1750 break; 1751 case IEEE80211_M_MONITOR: 1752 data = htole32(IPW_MODE_MONITOR); 1753 break; 1754 } 1755 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1756 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1757 if (error != 0) 1758 return error; 1759 1760 if (ic->ic_opmode == IEEE80211_M_IBSS || 1761 ic->ic_opmode == IEEE80211_M_MONITOR) { 1762 data = htole32(ieee80211_chan2ieee(ic, ic->ic_curchan)); 1763 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1764 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1765 if (error != 0) 1766 return error; 1767 } 1768 1769 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1770 DPRINTF(("Enabling adapter\n")); 1771 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1772 } 1773 1774 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 1775 DPRINTF(("Setting MAC address to %6D\n", ic->ic_myaddr, ":")); 1776 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1777 IEEE80211_ADDR_LEN); 1778 if (error != 0) 1779 return error; 1780 1781 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1782 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1783 if (ic->ic_opmode == IEEE80211_M_IBSS) 1784 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1785 if (ifp->if_flags & IFF_PROMISC) 1786 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1787 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1788 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1789 DPRINTF(("Setting configuration to 0x%x\n", le32toh(config.flags))); 1790 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1791 if (error != 0) 1792 return error; 1793 1794 data = htole32(0x3); /* 1, 2 */ 1795 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 1796 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1797 if (error != 0) 1798 return error; 1799 1800 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1801 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 1802 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1803 if (error != 0) 1804 return error; 1805 1806 data = htole32(IPW_POWER_MODE_CAM); 1807 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 1808 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1809 if (error != 0) 1810 return error; 1811 1812 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1813 data = htole32(32); /* default value */ 1814 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 1815 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1816 sizeof data); 1817 if (error != 0) 1818 return error; 1819 } 1820 1821 data = htole32(ic->ic_rtsthreshold); 1822 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 1823 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1824 if (error != 0) 1825 return error; 1826 1827 data = htole32(ic->ic_fragthreshold); 1828 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 1829 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1830 if (error != 0) 1831 return error; 1832 1833 #ifdef IPW_DEBUG 1834 if (ipw_debug > 0) { 1835 printf("Setting ESSID to "); 1836 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1837 printf("\n"); 1838 } 1839 #endif 1840 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1841 ic->ic_des_esslen); 1842 if (error != 0) 1843 return error; 1844 1845 /* no mandatory BSSID */ 1846 DPRINTF(("Setting mandatory BSSID to null\n")); 1847 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1848 if (error != 0) 1849 return error; 1850 1851 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1852 DPRINTF(("Setting desired BSSID to %6D\n", ic->ic_des_bssid, 1853 ":")); 1854 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1855 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1856 if (error != 0) 1857 return error; 1858 } 1859 1860 memset(&security, 0, sizeof security); 1861 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 1862 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1863 security.ciphers = htole32(IPW_CIPHER_NONE); 1864 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1865 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1866 sizeof security); 1867 if (error != 0) 1868 return error; 1869 1870 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1871 k = ic->ic_crypto.cs_nw_keys; 1872 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1873 if (k->wk_keylen == 0) 1874 continue; 1875 1876 wepkey.idx = i; 1877 wepkey.len = k->wk_keylen; 1878 memset(wepkey.key, 0, sizeof wepkey.key); 1879 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 1880 DPRINTF(("Setting wep key index %u len %u\n", 1881 wepkey.idx, wepkey.len)); 1882 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1883 sizeof wepkey); 1884 if (error != 0) 1885 return error; 1886 } 1887 1888 data = htole32(ic->ic_crypto.cs_def_txkey); 1889 DPRINTF(("Setting wep tx key index to %u\n", le32toh(data))); 1890 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1891 sizeof data); 1892 if (error != 0) 1893 return error; 1894 } 1895 1896 data = htole32((ic->ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 1897 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 1898 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1899 if (error != 0) 1900 return error; 1901 1902 #if 0 1903 struct ipw_wpa_ie ie; 1904 1905 memset(&ie, 0, sizeof ie); 1906 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 1907 DPRINTF(("Setting wpa ie\n")); 1908 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 1909 if (error != 0) 1910 return error; 1911 #endif 1912 1913 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1914 data = htole32(ic->ic_bintval); 1915 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 1916 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1917 sizeof data); 1918 if (error != 0) 1919 return error; 1920 } 1921 1922 options.flags = 0; 1923 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1924 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 1925 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1926 if (error != 0) 1927 return error; 1928 1929 /* finally, enable adapter (start scanning for an access point) */ 1930 DPRINTF(("Enabling adapter\n")); 1931 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1932 } 1933 1934 /* 1935 * Handler for sc_init_task. This is a simple wrapper around ipw_init(). 1936 * It is called on firmware panics or on watchdog timeouts. 1937 */ 1938 static void 1939 ipw_init_task(void *context, int pending) 1940 { 1941 ipw_init(context); 1942 } 1943 1944 static void 1945 ipw_init(void *priv) 1946 { 1947 struct ipw_softc *sc = priv; 1948 struct ieee80211com *ic = &sc->sc_ic; 1949 struct ifnet *ifp = ic->ic_ifp; 1950 const struct firmware *fp; 1951 const struct ipw_firmware_hdr *hdr; 1952 const char *imagename, *fw; 1953 int owned; 1954 1955 /* 1956 * ipw_init() is exposed through ifp->if_init so it might be called 1957 * without the driver's lock held. Since msleep() doesn't like being 1958 * called on a recursed mutex, we acquire the driver's lock only if 1959 * we're not already holding it. 1960 */ 1961 if (!(owned = mtx_owned(&sc->sc_mtx))) 1962 mtx_lock(&sc->sc_mtx); 1963 1964 /* 1965 * Avoid re-entrant calls. We need to release the mutex in ipw_init() 1966 * when loading the firmware and we don't want to be called during this 1967 * operation. 1968 */ 1969 if (sc->flags & IPW_FLAG_INIT_LOCKED) { 1970 if (!owned) 1971 mtx_unlock(&sc->sc_mtx); 1972 return; 1973 } 1974 sc->flags |= IPW_FLAG_INIT_LOCKED; 1975 1976 ipw_stop(sc); 1977 1978 if (ipw_reset(sc) != 0) { 1979 device_printf(sc->sc_dev, "could not reset adapter\n"); 1980 goto fail1; 1981 } 1982 1983 switch (ic->ic_opmode) { 1984 case IEEE80211_M_STA: 1985 imagename = "ipw_bss"; 1986 break; 1987 case IEEE80211_M_IBSS: 1988 imagename = "ipw_ibss"; 1989 break; 1990 case IEEE80211_M_MONITOR: 1991 imagename = "ipw_monitor"; 1992 break; 1993 default: 1994 imagename = NULL; /* should not get there */ 1995 } 1996 1997 /* 1998 * Load firmware image using the firmware(9) subsystem. We need to 1999 * release the driver's lock first. 2000 */ 2001 if (sc->sc_firmware == NULL || strcmp(sc->sc_firmware->name, 2002 imagename) != 0) { 2003 mtx_unlock(&sc->sc_mtx); 2004 if (sc->sc_firmware != NULL) 2005 firmware_put(sc->sc_firmware, FIRMWARE_UNLOAD); 2006 sc->sc_firmware = firmware_get(imagename); 2007 mtx_lock(&sc->sc_mtx); 2008 } 2009 2010 if (sc->sc_firmware == NULL) { 2011 device_printf(sc->sc_dev, 2012 "could not load firmware image '%s'\n", imagename); 2013 goto fail1; 2014 } 2015 2016 fp = sc->sc_firmware; 2017 if (fp->datasize < sizeof *hdr) { 2018 device_printf(sc->sc_dev, 2019 "firmware image too short %zu\n", fp->datasize); 2020 goto fail2; 2021 } 2022 2023 hdr = (const struct ipw_firmware_hdr *)fp->data; 2024 2025 if (fp->datasize < sizeof *hdr + le32toh(hdr->mainsz) + 2026 le32toh(hdr->ucodesz)) { 2027 device_printf(sc->sc_dev, 2028 "firmware image too short %zu\n", fp->datasize); 2029 goto fail2; 2030 } 2031 2032 fw = (const char *)fp->data + sizeof *hdr + le32toh(hdr->mainsz); 2033 if (ipw_load_ucode(sc, fw, le32toh(hdr->ucodesz)) != 0) { 2034 device_printf(sc->sc_dev, "could not load microcode\n"); 2035 goto fail2; 2036 } 2037 2038 ipw_stop_master(sc); 2039 2040 /* 2041 * Setup tx, rx and status rings. 2042 */ 2043 sc->txold = IPW_NTBD - 1; 2044 sc->txcur = 0; 2045 sc->txfree = IPW_NTBD - 2; 2046 sc->rxcur = IPW_NRBD - 1; 2047 2048 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_phys); 2049 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2050 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2051 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2052 2053 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_phys); 2054 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2055 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2056 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2057 2058 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_phys); 2059 2060 fw = (const char *)fp->data + sizeof *hdr; 2061 if (ipw_load_firmware(sc, fw, le32toh(hdr->mainsz)) != 0) { 2062 device_printf(sc->sc_dev, "could not load firmware\n"); 2063 goto fail2; 2064 } 2065 2066 sc->flags |= IPW_FLAG_FW_INITED; 2067 2068 /* retrieve information tables base addresses */ 2069 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2070 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2071 2072 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2073 2074 if (ipw_config(sc) != 0) { 2075 device_printf(sc->sc_dev, "device configuration failed\n"); 2076 goto fail1; 2077 } 2078 2079 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2080 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2081 2082 sc->flags &=~ IPW_FLAG_INIT_LOCKED; 2083 2084 if (!owned) 2085 mtx_unlock(&sc->sc_mtx); 2086 2087 return; 2088 2089 fail2: firmware_put(fp, FIRMWARE_UNLOAD); 2090 sc->sc_firmware = NULL; 2091 fail1: ifp->if_flags &= ~IFF_UP; 2092 ipw_stop(sc); 2093 sc->flags &=~ IPW_FLAG_INIT_LOCKED; 2094 if (!owned) 2095 mtx_unlock(&sc->sc_mtx); 2096 } 2097 2098 static void 2099 ipw_stop(void *priv) 2100 { 2101 struct ipw_softc *sc = priv; 2102 struct ieee80211com *ic = &sc->sc_ic; 2103 struct ifnet *ifp = ic->ic_ifp; 2104 int i; 2105 2106 mtx_lock(&sc->sc_mtx); 2107 2108 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2109 2110 ipw_stop_master(sc); 2111 2112 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2113 2114 /* 2115 * Release tx buffers. 2116 */ 2117 for (i = 0; i < IPW_NTBD; i++) 2118 ipw_release_sbd(sc, &sc->stbd_list[i]); 2119 2120 sc->sc_tx_timer = 0; 2121 ifp->if_timer = 0; 2122 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2123 2124 mtx_unlock(&sc->sc_mtx); 2125 } 2126 2127 static int 2128 ipw_sysctl_stats(SYSCTL_HANDLER_ARGS) 2129 { 2130 struct ipw_softc *sc = arg1; 2131 uint32_t i, size, buf[256]; 2132 2133 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 2134 memset(buf, 0, sizeof buf); 2135 return SYSCTL_OUT(req, buf, sizeof buf); 2136 } 2137 2138 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 2139 2140 size = min(CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA), 256); 2141 for (i = 1; i < size; i++) 2142 buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA)); 2143 2144 return SYSCTL_OUT(req, buf, sizeof buf); 2145 } 2146 2147 static int 2148 ipw_sysctl_radio(SYSCTL_HANDLER_ARGS) 2149 { 2150 struct ipw_softc *sc = arg1; 2151 int val; 2152 2153 val = !((sc->flags & IPW_FLAG_HAS_RADIO_SWITCH) && 2154 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED)); 2155 2156 return SYSCTL_OUT(req, &val, sizeof val); 2157 } 2158 2159 static uint32_t 2160 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 2161 { 2162 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 2163 } 2164 2165 static void 2166 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 2167 { 2168 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 2169 } 2170 2171 static int 2172 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 2173 { 2174 uint32_t addr, info; 2175 uint16_t count, size; 2176 uint32_t total; 2177 2178 /* addr[4] + count[2] + size[2] */ 2179 addr = MEM_READ_4(sc, sc->table2_base + off); 2180 info = MEM_READ_4(sc, sc->table2_base + off + 4); 2181 2182 count = info >> 16; 2183 size = info & 0xffff; 2184 total = count * size; 2185 2186 if (total > *len) { 2187 *len = total; 2188 return EINVAL; 2189 } 2190 2191 *len = total; 2192 ipw_read_mem_1(sc, addr, buf, total); 2193 2194 return 0; 2195 } 2196 2197 static void 2198 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2199 bus_size_t count) 2200 { 2201 for (; count > 0; offset++, datap++, count--) { 2202 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2203 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2204 } 2205 } 2206 2207 static void 2208 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, const uint8_t *datap, 2209 bus_size_t count) 2210 { 2211 for (; count > 0; offset++, datap++, count--) { 2212 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2213 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2214 } 2215 } 2216