1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2004, 2005 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /*- 34 * Intel(R) PRO/Wireless 2100 MiniPCI driver 35 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 36 */ 37 38 #include <sys/param.h> 39 #include <sys/sysctl.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/systm.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/bus.h> 48 #include <sys/endian.h> 49 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <machine/clock.h> 53 #include <sys/rman.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 58 #include <net/bpf.h> 59 #include <net/if.h> 60 #include <net/if_arp.h> 61 #include <net/ethernet.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_types.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in_var.h> 69 #include <netinet/ip.h> 70 #include <netinet/if_ether.h> 71 72 #include <net80211/ieee80211_var.h> 73 #include <net80211/ieee80211_radiotap.h> 74 75 #include <dev/ipw/if_ipwreg.h> 76 #include <dev/ipw/if_ipwvar.h> 77 78 #ifdef IPW_DEBUG 79 #define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 80 #define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 81 int ipw_debug = 0; 82 SYSCTL_INT(_debug, OID_AUTO, ipw, CTLFLAG_RW, &ipw_debug, 0, "ipw debug level"); 83 #else 84 #define DPRINTF(x) 85 #define DPRINTFN(n, x) 86 #endif 87 88 MODULE_DEPEND(ipw, pci, 1, 1, 1); 89 MODULE_DEPEND(ipw, wlan, 1, 1, 1); 90 91 struct ipw_ident { 92 uint16_t vendor; 93 uint16_t device; 94 const char *name; 95 }; 96 97 static const struct ipw_ident ipw_ident_table[] = { 98 { 0x8086, 0x1043, "Intel(R) PRO/Wireless 2100 MiniPCI" }, 99 100 { 0, 0, NULL } 101 }; 102 103 static int ipw_dma_alloc(struct ipw_softc *); 104 static void ipw_release(struct ipw_softc *); 105 static int ipw_media_change(struct ifnet *); 106 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 107 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 108 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 109 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 110 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 111 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 112 struct ipw_soft_bd *, struct ipw_soft_buf *); 113 static void ipw_rx_intr(struct ipw_softc *); 114 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 115 static void ipw_tx_intr(struct ipw_softc *); 116 static void ipw_intr(void *); 117 static void ipw_dma_map_addr(void *, bus_dma_segment_t *, int, int); 118 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 119 static int ipw_tx_start(struct ifnet *, struct mbuf *, 120 struct ieee80211_node *); 121 static void ipw_start(struct ifnet *); 122 static void ipw_watchdog(struct ifnet *); 123 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 124 static void ipw_stop_master(struct ipw_softc *); 125 static int ipw_reset(struct ipw_softc *); 126 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 127 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 128 static int ipw_cache_firmware(struct ipw_softc *, void *); 129 static void ipw_free_firmware(struct ipw_softc *); 130 static int ipw_config(struct ipw_softc *); 131 static void ipw_init(void *); 132 static void ipw_stop(void *); 133 #ifdef IPW_DEBUG 134 static int ipw_sysctl_stats(SYSCTL_HANDLER_ARGS); 135 #endif 136 static int ipw_sysctl_radio(SYSCTL_HANDLER_ARGS); 137 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 138 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 139 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 140 uint32_t *); 141 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 142 bus_size_t); 143 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 144 bus_size_t); 145 146 static int ipw_probe(device_t); 147 static int ipw_attach(device_t); 148 static int ipw_detach(device_t); 149 static int ipw_shutdown(device_t); 150 static int ipw_suspend(device_t); 151 static int ipw_resume(device_t); 152 153 static device_method_t ipw_methods[] = { 154 /* Device interface */ 155 DEVMETHOD(device_probe, ipw_probe), 156 DEVMETHOD(device_attach, ipw_attach), 157 DEVMETHOD(device_detach, ipw_detach), 158 DEVMETHOD(device_shutdown, ipw_shutdown), 159 DEVMETHOD(device_suspend, ipw_suspend), 160 DEVMETHOD(device_resume, ipw_resume), 161 162 { 0, 0 } 163 }; 164 165 static driver_t ipw_driver = { 166 "ipw", 167 ipw_methods, 168 sizeof (struct ipw_softc) 169 }; 170 171 static devclass_t ipw_devclass; 172 173 DRIVER_MODULE(ipw, pci, ipw_driver, ipw_devclass, 0, 0); 174 175 /* 176 * Supported rates for 802.11b mode (in 500Kbps unit). 177 */ 178 static const struct ieee80211_rateset ipw_rateset_11b = 179 { 4, { 2, 4, 11, 22 } }; 180 181 static __inline uint8_t 182 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 183 { 184 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 185 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 186 } 187 188 static __inline uint32_t 189 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 190 { 191 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 192 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 193 } 194 195 static int 196 ipw_probe(device_t dev) 197 { 198 const struct ipw_ident *ident; 199 200 for (ident = ipw_ident_table; ident->name != NULL; ident++) { 201 if (pci_get_vendor(dev) == ident->vendor && 202 pci_get_device(dev) == ident->device) { 203 device_set_desc(dev, ident->name); 204 return 0; 205 } 206 } 207 return ENXIO; 208 } 209 210 /* Base Address Register */ 211 #define IPW_PCI_BAR0 0x10 212 213 static int 214 ipw_attach(device_t dev) 215 { 216 struct ipw_softc *sc = device_get_softc(dev); 217 struct ifnet *ifp; 218 struct ieee80211com *ic = &sc->sc_ic; 219 uint16_t val; 220 int error, i; 221 222 sc->sc_dev = dev; 223 224 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 225 MTX_DEF | MTX_RECURSE); 226 227 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 228 device_printf(dev, "chip is in D%d power mode " 229 "-- setting to D0\n", pci_get_powerstate(dev)); 230 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 231 } 232 233 pci_write_config(dev, 0x41, 0, 1); 234 235 /* enable bus-mastering */ 236 pci_enable_busmaster(dev); 237 238 sc->mem_rid = IPW_PCI_BAR0; 239 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 240 RF_ACTIVE); 241 if (sc->mem == NULL) { 242 device_printf(dev, "could not allocate memory resource\n"); 243 goto fail; 244 } 245 246 sc->sc_st = rman_get_bustag(sc->mem); 247 sc->sc_sh = rman_get_bushandle(sc->mem); 248 249 sc->irq_rid = 0; 250 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 251 RF_ACTIVE | RF_SHAREABLE); 252 if (sc->irq == NULL) { 253 device_printf(dev, "could not allocate interrupt resource\n"); 254 goto fail; 255 } 256 257 if (ipw_reset(sc) != 0) { 258 device_printf(dev, "could not reset adapter\n"); 259 goto fail; 260 } 261 262 if (ipw_dma_alloc(sc) != 0) { 263 device_printf(dev, "could not allocate DMA resources\n"); 264 goto fail; 265 } 266 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 267 if (ifp == NULL) { 268 device_printf(dev, "can not if_alloc()\n"); 269 goto fail; 270 } 271 ifp->if_softc = sc; 272 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 273 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 274 ifp->if_init = ipw_init; 275 ifp->if_ioctl = ipw_ioctl; 276 ifp->if_start = ipw_start; 277 ifp->if_watchdog = ipw_watchdog; 278 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 279 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 280 IFQ_SET_READY(&ifp->if_snd); 281 282 ic->ic_ifp = ifp; 283 ic->ic_phytype = IEEE80211_T_DS; 284 ic->ic_opmode = IEEE80211_M_STA; 285 ic->ic_state = IEEE80211_S_INIT; 286 287 /* set device capabilities */ 288 ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT | 289 IEEE80211_C_PMGT | IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 290 IEEE80211_C_WPA; 291 292 /* read MAC address from EEPROM */ 293 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 294 ic->ic_myaddr[0] = val >> 8; 295 ic->ic_myaddr[1] = val & 0xff; 296 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 297 ic->ic_myaddr[2] = val >> 8; 298 ic->ic_myaddr[3] = val & 0xff; 299 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 300 ic->ic_myaddr[4] = val >> 8; 301 ic->ic_myaddr[5] = val & 0xff; 302 303 /* set supported .11b rates */ 304 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 305 306 /* set supported .11b channels (read from EEPROM) */ 307 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 308 val = 0x7ff; /* default to channels 1-11 */ 309 val <<= 1; 310 for (i = 1; i < 16; i++) { 311 if (val & (1 << i)) { 312 ic->ic_channels[i].ic_freq = 313 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 314 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 315 } 316 } 317 318 /* check support for radio transmitter switch in EEPROM */ 319 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 320 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 321 322 ieee80211_ifattach(ic); 323 /* override state transition machine */ 324 sc->sc_newstate = ic->ic_newstate; 325 ic->ic_newstate = ipw_newstate; 326 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 327 328 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 329 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 330 331 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 332 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 333 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 334 335 sc->sc_txtap_len = sizeof sc->sc_txtapu; 336 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 337 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 338 339 /* 340 * Add a few sysctl knobs. 341 */ 342 sc->dwelltime = 100; 343 344 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 345 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "radio", 346 CTLTYPE_INT | CTLFLAG_RD, sc, 0, ipw_sysctl_radio, "I", 347 "radio transmitter switch state (0=off, 1=on)"); 348 349 #ifdef IPW_DEBUG 350 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 351 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats", 352 CTLTYPE_OPAQUE | CTLFLAG_RD, sc, 0, ipw_sysctl_stats, "S", 353 "statistics"); 354 #endif 355 356 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 357 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", 358 CTLFLAG_RW, &sc->dwelltime, 0, 359 "channel dwell time (ms) for AP/station scanning"); 360 361 /* 362 * Hook our interrupt after all initialization is complete. 363 */ 364 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 365 ipw_intr, sc, &sc->sc_ih); 366 if (error != 0) { 367 device_printf(dev, "could not set up interrupt\n"); 368 goto fail; 369 } 370 371 if (bootverbose) 372 ieee80211_announce(ic); 373 374 return 0; 375 376 fail: ipw_detach(dev); 377 return ENXIO; 378 } 379 380 static int 381 ipw_detach(device_t dev) 382 { 383 struct ipw_softc *sc = device_get_softc(dev); 384 struct ieee80211com *ic = &sc->sc_ic; 385 struct ifnet *ifp = ic->ic_ifp; 386 387 IPW_LOCK(sc); 388 389 ipw_stop(sc); 390 ipw_free_firmware(sc); 391 392 IPW_UNLOCK(sc); 393 394 if (ifp != NULL) 395 bpfdetach(ifp); 396 ieee80211_ifdetach(ic); 397 if (ifp != NULL) 398 if_free(ifp); 399 400 ipw_release(sc); 401 402 if (sc->irq != NULL) { 403 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 404 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 405 } 406 407 if (sc->mem != NULL) 408 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 409 410 mtx_destroy(&sc->sc_mtx); 411 412 return 0; 413 } 414 415 static int 416 ipw_dma_alloc(struct ipw_softc *sc) 417 { 418 struct ipw_soft_bd *sbd; 419 struct ipw_soft_hdr *shdr; 420 struct ipw_soft_buf *sbuf; 421 bus_addr_t physaddr; 422 int error, i; 423 424 /* 425 * Allocate and map tx ring. 426 */ 427 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 428 BUS_SPACE_MAXADDR, NULL, NULL, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, NULL, 429 NULL, &sc->tbd_dmat); 430 if (error != 0) { 431 device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); 432 goto fail; 433 } 434 435 error = bus_dmamem_alloc(sc->tbd_dmat, (void **)&sc->tbd_list, 436 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tbd_map); 437 if (error != 0) { 438 device_printf(sc->sc_dev, 439 "could not allocate tx ring DMA memory\n"); 440 goto fail; 441 } 442 443 error = bus_dmamap_load(sc->tbd_dmat, sc->tbd_map, sc->tbd_list, 444 IPW_TBD_SZ, ipw_dma_map_addr, &sc->tbd_phys, 0); 445 if (error != 0) { 446 device_printf(sc->sc_dev, "could not map tx ring DMA memory\n"); 447 goto fail; 448 } 449 450 /* 451 * Allocate and map rx ring. 452 */ 453 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 454 BUS_SPACE_MAXADDR, NULL, NULL, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, NULL, 455 NULL, &sc->rbd_dmat); 456 if (error != 0) { 457 device_printf(sc->sc_dev, "could not create rx ring DMA tag\n"); 458 goto fail; 459 } 460 461 error = bus_dmamem_alloc(sc->rbd_dmat, (void **)&sc->rbd_list, 462 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rbd_map); 463 if (error != 0) { 464 device_printf(sc->sc_dev, 465 "could not allocate rx ring DMA memory\n"); 466 goto fail; 467 } 468 469 error = bus_dmamap_load(sc->rbd_dmat, sc->rbd_map, sc->rbd_list, 470 IPW_RBD_SZ, ipw_dma_map_addr, &sc->rbd_phys, 0); 471 if (error != 0) { 472 device_printf(sc->sc_dev, "could not map rx ring DMA memory\n"); 473 goto fail; 474 } 475 476 /* 477 * Allocate and map status ring. 478 */ 479 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 480 BUS_SPACE_MAXADDR, NULL, NULL, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 0, 481 NULL, NULL, &sc->status_dmat); 482 if (error != 0) { 483 device_printf(sc->sc_dev, 484 "could not create status ring DMA tag\n"); 485 goto fail; 486 } 487 488 error = bus_dmamem_alloc(sc->status_dmat, (void **)&sc->status_list, 489 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->status_map); 490 if (error != 0) { 491 device_printf(sc->sc_dev, 492 "could not allocate status ring DMA memory\n"); 493 goto fail; 494 } 495 496 error = bus_dmamap_load(sc->status_dmat, sc->status_map, 497 sc->status_list, IPW_STATUS_SZ, ipw_dma_map_addr, &sc->status_phys, 498 0); 499 if (error != 0) { 500 device_printf(sc->sc_dev, 501 "could not map status ring DMA memory\n"); 502 goto fail; 503 } 504 505 /* 506 * Allocate command DMA map. 507 */ 508 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 509 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_cmd), 1, 510 sizeof (struct ipw_cmd), 0, NULL, NULL, &sc->cmd_dmat); 511 if (error != 0) { 512 device_printf(sc->sc_dev, "could not create command DMA tag\n"); 513 goto fail; 514 } 515 516 error = bus_dmamap_create(sc->cmd_dmat, 0, &sc->cmd_map); 517 if (error != 0) { 518 device_printf(sc->sc_dev, 519 "could not create command DMA map\n"); 520 goto fail; 521 } 522 523 /* 524 * Allocate headers DMA maps. 525 */ 526 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 527 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_hdr), 1, 528 sizeof (struct ipw_hdr), 0, NULL, NULL, &sc->hdr_dmat); 529 if (error != 0) { 530 device_printf(sc->sc_dev, "could not create header DMA tag\n"); 531 goto fail; 532 } 533 534 SLIST_INIT(&sc->free_shdr); 535 for (i = 0; i < IPW_NDATA; i++) { 536 shdr = &sc->shdr_list[i]; 537 error = bus_dmamap_create(sc->hdr_dmat, 0, &shdr->map); 538 if (error != 0) { 539 device_printf(sc->sc_dev, 540 "could not create header DMA map\n"); 541 goto fail; 542 } 543 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 544 } 545 546 /* 547 * Allocate tx buffers DMA maps. 548 */ 549 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 550 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_MAX_NSEG, MCLBYTES, 0, 551 NULL, NULL, &sc->txbuf_dmat); 552 if (error != 0) { 553 device_printf(sc->sc_dev, "could not create tx DMA tag\n"); 554 goto fail; 555 } 556 557 SLIST_INIT(&sc->free_sbuf); 558 for (i = 0; i < IPW_NDATA; i++) { 559 sbuf = &sc->tx_sbuf_list[i]; 560 error = bus_dmamap_create(sc->txbuf_dmat, 0, &sbuf->map); 561 if (error != 0) { 562 device_printf(sc->sc_dev, 563 "could not create tx DMA map\n"); 564 goto fail; 565 } 566 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 567 } 568 569 /* 570 * Initialize tx ring. 571 */ 572 for (i = 0; i < IPW_NTBD; i++) { 573 sbd = &sc->stbd_list[i]; 574 sbd->bd = &sc->tbd_list[i]; 575 sbd->type = IPW_SBD_TYPE_NOASSOC; 576 } 577 578 /* 579 * Pre-allocate rx buffers and DMA maps. 580 */ 581 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 582 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_NRBD, MCLBYTES, 0, 583 NULL, NULL, &sc->rxbuf_dmat); 584 if (error != 0) { 585 device_printf(sc->sc_dev, "could not create rx DMA tag\n"); 586 goto fail; 587 } 588 589 for (i = 0; i < IPW_NRBD; i++) { 590 sbd = &sc->srbd_list[i]; 591 sbuf = &sc->rx_sbuf_list[i]; 592 sbd->bd = &sc->rbd_list[i]; 593 594 sbuf->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 595 if (sbuf->m == NULL) { 596 device_printf(sc->sc_dev, 597 "could not allocate rx mbuf\n"); 598 error = ENOMEM; 599 goto fail; 600 } 601 602 error = bus_dmamap_create(sc->rxbuf_dmat, 0, &sbuf->map); 603 if (error != 0) { 604 device_printf(sc->sc_dev, 605 "could not create rx DMA map\n"); 606 goto fail; 607 } 608 609 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 610 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 611 &physaddr, 0); 612 if (error != 0) { 613 device_printf(sc->sc_dev, 614 "could not map rx DMA memory\n"); 615 goto fail; 616 } 617 618 sbd->type = IPW_SBD_TYPE_DATA; 619 sbd->priv = sbuf; 620 sbd->bd->physaddr = htole32(physaddr); 621 sbd->bd->len = htole32(MCLBYTES); 622 } 623 624 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 625 626 return 0; 627 628 fail: ipw_release(sc); 629 return error; 630 } 631 632 static void 633 ipw_release(struct ipw_softc *sc) 634 { 635 struct ipw_soft_buf *sbuf; 636 int i; 637 638 if (sc->tbd_dmat != NULL) { 639 if (sc->stbd_list != NULL) { 640 bus_dmamap_unload(sc->tbd_dmat, sc->tbd_map); 641 bus_dmamem_free(sc->tbd_dmat, sc->tbd_list, 642 sc->tbd_map); 643 } 644 bus_dma_tag_destroy(sc->tbd_dmat); 645 } 646 647 if (sc->rbd_dmat != NULL) { 648 if (sc->rbd_list != NULL) { 649 bus_dmamap_unload(sc->rbd_dmat, sc->rbd_map); 650 bus_dmamem_free(sc->rbd_dmat, sc->rbd_list, 651 sc->rbd_map); 652 } 653 bus_dma_tag_destroy(sc->rbd_dmat); 654 } 655 656 if (sc->status_dmat != NULL) { 657 if (sc->status_list != NULL) { 658 bus_dmamap_unload(sc->status_dmat, sc->status_map); 659 bus_dmamem_free(sc->status_dmat, sc->status_list, 660 sc->status_map); 661 } 662 bus_dma_tag_destroy(sc->status_dmat); 663 } 664 665 for (i = 0; i < IPW_NTBD; i++) 666 ipw_release_sbd(sc, &sc->stbd_list[i]); 667 668 if (sc->cmd_dmat != NULL) { 669 bus_dmamap_destroy(sc->cmd_dmat, sc->cmd_map); 670 bus_dma_tag_destroy(sc->cmd_dmat); 671 } 672 673 if (sc->hdr_dmat != NULL) { 674 for (i = 0; i < IPW_NDATA; i++) 675 bus_dmamap_destroy(sc->hdr_dmat, sc->shdr_list[i].map); 676 bus_dma_tag_destroy(sc->hdr_dmat); 677 } 678 679 if (sc->txbuf_dmat != NULL) { 680 for (i = 0; i < IPW_NDATA; i++) { 681 bus_dmamap_destroy(sc->txbuf_dmat, 682 sc->tx_sbuf_list[i].map); 683 } 684 bus_dma_tag_destroy(sc->txbuf_dmat); 685 } 686 687 if (sc->rxbuf_dmat != NULL) { 688 for (i = 0; i < IPW_NRBD; i++) { 689 sbuf = &sc->rx_sbuf_list[i]; 690 if (sbuf->m != NULL) { 691 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, 692 BUS_DMASYNC_POSTREAD); 693 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 694 m_freem(sbuf->m); 695 } 696 bus_dmamap_destroy(sc->rxbuf_dmat, sbuf->map); 697 } 698 bus_dma_tag_destroy(sc->rxbuf_dmat); 699 } 700 } 701 702 static int 703 ipw_shutdown(device_t dev) 704 { 705 struct ipw_softc *sc = device_get_softc(dev); 706 707 ipw_stop(sc); 708 709 return 0; 710 } 711 712 static int 713 ipw_suspend(device_t dev) 714 { 715 struct ipw_softc *sc = device_get_softc(dev); 716 717 ipw_stop(sc); 718 719 return 0; 720 } 721 722 static int 723 ipw_resume(device_t dev) 724 { 725 struct ipw_softc *sc = device_get_softc(dev); 726 struct ifnet *ifp = sc->sc_ic.ic_ifp; 727 728 IPW_LOCK(sc); 729 730 pci_write_config(dev, 0x41, 0, 1); 731 732 if (ifp->if_flags & IFF_UP) { 733 ifp->if_init(ifp->if_softc); 734 if (ifp->if_flags & IFF_RUNNING) 735 ifp->if_start(ifp); 736 } 737 738 IPW_UNLOCK(sc); 739 740 return 0; 741 } 742 743 static int 744 ipw_media_change(struct ifnet *ifp) 745 { 746 struct ipw_softc *sc = ifp->if_softc; 747 int error; 748 749 IPW_LOCK(sc); 750 751 error = ieee80211_media_change(ifp); 752 if (error != ENETRESET) { 753 IPW_UNLOCK(sc); 754 return error; 755 } 756 757 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 758 ipw_init(sc); 759 760 IPW_UNLOCK(sc); 761 762 return 0; 763 } 764 765 /* 766 * The firmware automaticly adapt the transmit speed. We report the current 767 * transmit speed here. 768 */ 769 static void 770 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 771 { 772 #define N(a) (sizeof (a) / sizeof (a[0])) 773 struct ipw_softc *sc = ifp->if_softc; 774 struct ieee80211com *ic = &sc->sc_ic; 775 static const struct { 776 uint32_t val; 777 int rate; 778 } rates[] = { 779 { IPW_RATE_DS1, 2 }, 780 { IPW_RATE_DS2, 4 }, 781 { IPW_RATE_DS5, 11 }, 782 { IPW_RATE_DS11, 22 }, 783 }; 784 uint32_t val; 785 int rate, i; 786 787 imr->ifm_status = IFM_AVALID; 788 imr->ifm_active = IFM_IEEE80211; 789 if (ic->ic_state == IEEE80211_S_RUN) 790 imr->ifm_status |= IFM_ACTIVE; 791 792 /* read current transmission rate from adapter */ 793 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 794 795 /* convert ipw rate to 802.11 rate */ 796 for (i = 0; i < N(rates) && rates[i].val != val; i++); 797 rate = (i < N(rates)) ? rates[i].rate : 0; 798 799 imr->ifm_active |= IFM_IEEE80211_11B; 800 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 801 switch (ic->ic_opmode) { 802 case IEEE80211_M_STA: 803 break; 804 805 case IEEE80211_M_IBSS: 806 imr->ifm_active |= IFM_IEEE80211_IBSS; 807 break; 808 809 case IEEE80211_M_MONITOR: 810 imr->ifm_active |= IFM_IEEE80211_MONITOR; 811 break; 812 813 case IEEE80211_M_AHDEMO: 814 case IEEE80211_M_HOSTAP: 815 /* should not get there */ 816 break; 817 } 818 #undef N 819 } 820 821 static int 822 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 823 { 824 struct ifnet *ifp = ic->ic_ifp; 825 struct ipw_softc *sc = ifp->if_softc; 826 struct ieee80211_node *ni; 827 uint8_t macaddr[IEEE80211_ADDR_LEN]; 828 uint32_t len; 829 830 switch (nstate) { 831 case IEEE80211_S_RUN: 832 DELAY(200); /* firmware needs a short delay here */ 833 834 len = IEEE80211_ADDR_LEN; 835 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 836 837 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 838 if (ni == NULL) 839 break; 840 841 ieee80211_ref_node(ni); 842 ieee80211_sta_join(ic, ni); 843 ieee80211_node_authorize(ic, ni); 844 845 if (ic->ic_opmode == IEEE80211_M_STA) 846 ieee80211_notify_node_join(ic, ni, 1); 847 break; 848 849 case IEEE80211_S_INIT: 850 case IEEE80211_S_SCAN: 851 case IEEE80211_S_AUTH: 852 case IEEE80211_S_ASSOC: 853 break; 854 } 855 856 ic->ic_state = nstate; 857 return 0; 858 } 859 860 /* 861 * Read 16 bits at address 'addr' from the serial EEPROM. 862 */ 863 static uint16_t 864 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 865 { 866 uint32_t tmp; 867 uint16_t val; 868 int n; 869 870 /* clock C once before the first command */ 871 IPW_EEPROM_CTL(sc, 0); 872 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 875 876 /* write start bit (1) */ 877 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 878 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 879 880 /* write READ opcode (10) */ 881 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 882 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 883 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 884 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 885 886 /* write address A7-A0 */ 887 for (n = 7; n >= 0; n--) { 888 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 889 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 890 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 891 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 892 } 893 894 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 895 896 /* read data Q15-Q0 */ 897 val = 0; 898 for (n = 15; n >= 0; n--) { 899 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 900 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 901 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 902 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 903 } 904 905 IPW_EEPROM_CTL(sc, 0); 906 907 /* clear Chip Select and clock C */ 908 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 909 IPW_EEPROM_CTL(sc, 0); 910 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 911 912 return le16toh(val); 913 } 914 915 static void 916 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 917 { 918 struct ipw_cmd *cmd; 919 920 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 921 922 cmd = mtod(sbuf->m, struct ipw_cmd *); 923 924 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 925 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 926 le32toh(cmd->status))); 927 928 wakeup(sc); 929 } 930 931 static void 932 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 933 { 934 struct ieee80211com *ic = &sc->sc_ic; 935 uint32_t state; 936 937 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 938 939 state = le32toh(*mtod(sbuf->m, uint32_t *)); 940 941 DPRINTFN(2, ("entering state %u\n", state)); 942 943 switch (state) { 944 case IPW_STATE_ASSOCIATED: 945 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 946 break; 947 948 case IPW_STATE_SCANNING: 949 /* don't leave run state on background scan */ 950 if (ic->ic_state != IEEE80211_S_RUN) 951 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 952 953 ic->ic_flags |= IEEE80211_F_SCAN; 954 break; 955 956 case IPW_STATE_SCAN_COMPLETE: 957 ieee80211_notify_scan_done(ic); 958 ic->ic_flags &= ~IEEE80211_F_SCAN; 959 break; 960 961 case IPW_STATE_ASSOCIATION_LOST: 962 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 963 break; 964 965 case IPW_STATE_RADIO_DISABLED: 966 ic->ic_ifp->if_flags &= ~IFF_UP; 967 ipw_stop(sc); 968 break; 969 } 970 } 971 972 /* 973 * XXX: Hack to set the current channel to the value advertised in beacons or 974 * probe responses. Only used during AP detection. 975 */ 976 static void 977 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 978 { 979 struct ieee80211_frame *wh; 980 uint8_t subtype; 981 uint8_t *frm, *efrm; 982 983 wh = mtod(m, struct ieee80211_frame *); 984 985 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 986 return; 987 988 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 989 990 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 991 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 992 return; 993 994 frm = (uint8_t *)(wh + 1); 995 efrm = mtod(m, uint8_t *) + m->m_len; 996 997 frm += 12; /* skip tstamp, bintval and capinfo fields */ 998 while (frm < efrm) { 999 if (*frm == IEEE80211_ELEMID_DSPARMS) 1000 #if IEEE80211_CHAN_MAX < 255 1001 if (frm[2] <= IEEE80211_CHAN_MAX) 1002 #endif 1003 ic->ic_bss->ni_chan = &ic->ic_channels[frm[2]]; 1004 1005 frm += frm[1] + 2; 1006 } 1007 } 1008 1009 static void 1010 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1011 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1012 { 1013 struct ieee80211com *ic = &sc->sc_ic; 1014 struct ifnet *ifp = ic->ic_ifp; 1015 struct mbuf *m; 1016 struct ieee80211_frame *wh; 1017 struct ieee80211_node *ni; 1018 bus_addr_t physaddr; 1019 int error; 1020 1021 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 1022 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 1023 1024 /* finalize mbuf */ 1025 m = sbuf->m; 1026 m->m_pkthdr.rcvif = ifp; 1027 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1028 1029 if (sc->sc_drvbpf != NULL) { 1030 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1031 1032 tap->wr_flags = 0; 1033 tap->wr_antsignal = status->rssi; 1034 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1035 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1036 1037 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1038 } 1039 1040 if (ic->ic_state == IEEE80211_S_SCAN) 1041 ipw_fix_channel(ic, m); 1042 1043 wh = mtod(m, struct ieee80211_frame *); 1044 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1045 1046 /* send the frame to the 802.11 layer */ 1047 ieee80211_input(ic, m, ni, status->rssi, 0); 1048 1049 /* node is no longer needed */ 1050 ieee80211_free_node(ni); 1051 1052 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1053 if (m == NULL) { 1054 device_printf(sc->sc_dev, "could not allocate rx mbuf\n"); 1055 sbuf->m = NULL; 1056 return; 1057 } 1058 1059 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, mtod(m, void *), 1060 MCLBYTES, ipw_dma_map_addr, &physaddr, 0); 1061 if (error != 0) { 1062 device_printf(sc->sc_dev, "could not map rx DMA memory\n"); 1063 m_freem(m); 1064 sbuf->m = NULL; 1065 return; 1066 } 1067 1068 sbuf->m = m; 1069 sbd->bd->physaddr = htole32(physaddr); 1070 1071 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1072 status->rssi)); 1073 1074 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1075 } 1076 1077 static void 1078 ipw_rx_intr(struct ipw_softc *sc) 1079 { 1080 struct ipw_status *status; 1081 struct ipw_soft_bd *sbd; 1082 struct ipw_soft_buf *sbuf; 1083 uint32_t r, i; 1084 1085 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1086 return; 1087 1088 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1089 1090 bus_dmamap_sync(sc->status_dmat, sc->status_map, BUS_DMASYNC_POSTREAD); 1091 1092 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1093 status = &sc->status_list[i]; 1094 sbd = &sc->srbd_list[i]; 1095 sbuf = sbd->priv; 1096 1097 switch (le16toh(status->code) & 0xf) { 1098 case IPW_STATUS_CODE_COMMAND: 1099 ipw_command_intr(sc, sbuf); 1100 break; 1101 1102 case IPW_STATUS_CODE_NEWSTATE: 1103 ipw_newstate_intr(sc, sbuf); 1104 break; 1105 1106 case IPW_STATUS_CODE_DATA_802_3: 1107 case IPW_STATUS_CODE_DATA_802_11: 1108 ipw_data_intr(sc, status, sbd, sbuf); 1109 break; 1110 1111 case IPW_STATUS_CODE_NOTIFICATION: 1112 DPRINTFN(2, ("received notification\n")); 1113 break; 1114 1115 default: 1116 device_printf(sc->sc_dev, "unknown status code %u\n", 1117 le16toh(status->code)); 1118 } 1119 1120 /* firmware was killed, stop processing received frames */ 1121 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1122 return; 1123 1124 sbd->bd->flags = 0; 1125 } 1126 1127 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1128 1129 /* kick the firmware */ 1130 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1131 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1132 } 1133 1134 static void 1135 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1136 { 1137 struct ipw_soft_hdr *shdr; 1138 struct ipw_soft_buf *sbuf; 1139 1140 switch (sbd->type) { 1141 case IPW_SBD_TYPE_COMMAND: 1142 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, 1143 BUS_DMASYNC_POSTWRITE); 1144 bus_dmamap_unload(sc->cmd_dmat, sc->cmd_map); 1145 break; 1146 1147 case IPW_SBD_TYPE_HEADER: 1148 shdr = sbd->priv; 1149 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_POSTWRITE); 1150 bus_dmamap_unload(sc->hdr_dmat, shdr->map); 1151 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1152 break; 1153 1154 case IPW_SBD_TYPE_DATA: 1155 sbuf = sbd->priv; 1156 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, 1157 BUS_DMASYNC_POSTWRITE); 1158 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1159 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1160 1161 m_freem(sbuf->m); 1162 ieee80211_free_node(sbuf->ni); 1163 1164 sc->sc_tx_timer = 0; 1165 break; 1166 } 1167 1168 sbd->type = IPW_SBD_TYPE_NOASSOC; 1169 } 1170 1171 static void 1172 ipw_tx_intr(struct ipw_softc *sc) 1173 { 1174 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1175 struct ipw_soft_bd *sbd; 1176 uint32_t r, i; 1177 1178 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1179 return; 1180 1181 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1182 1183 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1184 sbd = &sc->stbd_list[i]; 1185 1186 if (sbd->type == IPW_SBD_TYPE_DATA) 1187 ifp->if_opackets++; 1188 1189 ipw_release_sbd(sc, sbd); 1190 sc->txfree++; 1191 } 1192 1193 /* remember what the firmware has processed */ 1194 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1195 1196 ifp->if_flags &= ~IFF_OACTIVE; 1197 ipw_start(ifp); 1198 } 1199 1200 static void 1201 ipw_intr(void *arg) 1202 { 1203 struct ipw_softc *sc = arg; 1204 uint32_t r; 1205 1206 IPW_LOCK(sc); 1207 1208 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) { 1209 IPW_UNLOCK(sc); 1210 return; 1211 } 1212 1213 /* disable interrupts */ 1214 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1215 1216 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1217 device_printf(sc->sc_dev, "fatal error\n"); 1218 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1219 ipw_stop(sc); 1220 } 1221 1222 if (r & IPW_INTR_FW_INIT_DONE) { 1223 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1224 wakeup(sc); 1225 } 1226 1227 if (r & IPW_INTR_RX_TRANSFER) 1228 ipw_rx_intr(sc); 1229 1230 if (r & IPW_INTR_TX_TRANSFER) 1231 ipw_tx_intr(sc); 1232 1233 /* acknowledge all interrupts */ 1234 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1235 1236 /* re-enable interrupts */ 1237 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1238 1239 IPW_UNLOCK(sc); 1240 } 1241 1242 static void 1243 ipw_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1244 { 1245 if (error != 0) 1246 return; 1247 1248 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1249 1250 *(bus_addr_t *)arg = segs[0].ds_addr; 1251 } 1252 1253 /* 1254 * Send a command to the firmware and wait for the acknowledgement. 1255 */ 1256 static int 1257 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1258 { 1259 struct ipw_soft_bd *sbd; 1260 bus_addr_t physaddr; 1261 int error; 1262 1263 sbd = &sc->stbd_list[sc->txcur]; 1264 1265 error = bus_dmamap_load(sc->cmd_dmat, sc->cmd_map, &sc->cmd, 1266 sizeof (struct ipw_cmd), ipw_dma_map_addr, &physaddr, 0); 1267 if (error != 0) { 1268 device_printf(sc->sc_dev, "could not map command DMA memory\n"); 1269 return error; 1270 } 1271 1272 sc->cmd.type = htole32(type); 1273 sc->cmd.subtype = 0; 1274 sc->cmd.len = htole32(len); 1275 sc->cmd.seq = 0; 1276 bcopy(data, sc->cmd.data, len); 1277 1278 sbd->type = IPW_SBD_TYPE_COMMAND; 1279 sbd->bd->physaddr = htole32(physaddr); 1280 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1281 sbd->bd->nfrag = 1; 1282 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1283 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1284 1285 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, BUS_DMASYNC_PREWRITE); 1286 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1287 1288 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1289 1290 /* kick firmware */ 1291 sc->txfree--; 1292 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1293 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1294 1295 /* wait at most one second for command to complete */ 1296 return msleep(sc, &sc->sc_mtx, 0, "ipwcmd", hz); 1297 } 1298 1299 static int 1300 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1301 { 1302 struct ipw_softc *sc = ifp->if_softc; 1303 struct ieee80211com *ic = &sc->sc_ic; 1304 struct ieee80211_frame *wh; 1305 struct ipw_soft_bd *sbd; 1306 struct ipw_soft_hdr *shdr; 1307 struct ipw_soft_buf *sbuf; 1308 struct ieee80211_key *k; 1309 struct mbuf *mnew; 1310 bus_dma_segment_t segs[IPW_MAX_NSEG]; 1311 bus_addr_t physaddr; 1312 int nsegs, error, i; 1313 1314 wh = mtod(m0, struct ieee80211_frame *); 1315 1316 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1317 k = ieee80211_crypto_encap(ic, ni, m0); 1318 if (k == NULL) 1319 return ENOBUFS; 1320 1321 /* packet header may have moved, reset our local pointer */ 1322 wh = mtod(m0, struct ieee80211_frame *); 1323 } 1324 1325 if (sc->sc_drvbpf != NULL) { 1326 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1327 1328 tap->wt_flags = 0; 1329 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1330 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1331 1332 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1333 } 1334 1335 shdr = SLIST_FIRST(&sc->free_shdr); 1336 sbuf = SLIST_FIRST(&sc->free_sbuf); 1337 KASSERT(shdr != NULL && sbuf != NULL, ("empty sw hdr/buf pool")); 1338 1339 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1340 shdr->hdr.subtype = 0; 1341 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1342 shdr->hdr.encrypt = 0; 1343 shdr->hdr.keyidx = 0; 1344 shdr->hdr.keysz = 0; 1345 shdr->hdr.fragmentsz = 0; 1346 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1347 if (ic->ic_opmode == IEEE80211_M_STA) 1348 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1349 else 1350 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1351 1352 /* trim IEEE802.11 header */ 1353 m_adj(m0, sizeof (struct ieee80211_frame)); 1354 1355 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, segs, 1356 &nsegs, 0); 1357 if (error != 0 && error != EFBIG) { 1358 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1359 error); 1360 m_freem(m0); 1361 return error; 1362 } 1363 if (error != 0) { 1364 mnew = m_defrag(m0, M_DONTWAIT); 1365 if (mnew == NULL) { 1366 device_printf(sc->sc_dev, 1367 "could not defragment mbuf\n"); 1368 m_freem(m0); 1369 return ENOBUFS; 1370 } 1371 m0 = mnew; 1372 1373 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, 1374 segs, &nsegs, 0); 1375 if (error != 0) { 1376 device_printf(sc->sc_dev, 1377 "could not map mbuf (error %d)\n", error); 1378 m_freem(m0); 1379 return error; 1380 } 1381 } 1382 1383 error = bus_dmamap_load(sc->hdr_dmat, shdr->map, &shdr->hdr, 1384 sizeof (struct ipw_hdr), ipw_dma_map_addr, &physaddr, 0); 1385 if (error != 0) { 1386 device_printf(sc->sc_dev, "could not map header DMA memory\n"); 1387 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1388 m_freem(m0); 1389 return error; 1390 } 1391 1392 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1393 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1394 1395 sbd = &sc->stbd_list[sc->txcur]; 1396 sbd->type = IPW_SBD_TYPE_HEADER; 1397 sbd->priv = shdr; 1398 sbd->bd->physaddr = htole32(physaddr); 1399 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1400 sbd->bd->nfrag = 1 + nsegs; 1401 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1402 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1403 1404 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, %6D, %6D)\n", 1405 shdr->hdr.type, shdr->hdr.subtype, shdr->hdr.encrypted, 1406 shdr->hdr.encrypt, shdr->hdr.src_addr, ":", shdr->hdr.dst_addr, 1407 ":")); 1408 1409 sc->txfree--; 1410 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1411 1412 sbuf->m = m0; 1413 sbuf->ni = ni; 1414 1415 for (i = 0; i < nsegs; i++) { 1416 sbd = &sc->stbd_list[sc->txcur]; 1417 1418 sbd->bd->physaddr = htole32(segs[i].ds_addr); 1419 sbd->bd->len = htole32(segs[i].ds_len); 1420 sbd->bd->nfrag = 0; 1421 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1422 if (i == nsegs - 1) { 1423 sbd->type = IPW_SBD_TYPE_DATA; 1424 sbd->priv = sbuf; 1425 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1426 } else { 1427 sbd->type = IPW_SBD_TYPE_NOASSOC; 1428 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1429 } 1430 1431 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, segs[i].ds_len)); 1432 1433 sc->txfree--; 1434 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1435 } 1436 1437 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_PREWRITE); 1438 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, BUS_DMASYNC_PREWRITE); 1439 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1440 1441 /* kick firmware */ 1442 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1443 1444 return 0; 1445 } 1446 1447 static void 1448 ipw_start(struct ifnet *ifp) 1449 { 1450 struct ipw_softc *sc = ifp->if_softc; 1451 struct ieee80211com *ic = &sc->sc_ic; 1452 struct mbuf *m0; 1453 struct ether_header *eh; 1454 struct ieee80211_node *ni; 1455 1456 IPW_LOCK(sc); 1457 1458 if (ic->ic_state != IEEE80211_S_RUN) { 1459 IPW_UNLOCK(sc); 1460 return; 1461 } 1462 1463 for (;;) { 1464 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1465 if (m0 == NULL) 1466 break; 1467 1468 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1469 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1470 ifp->if_flags |= IFF_OACTIVE; 1471 break; 1472 } 1473 1474 if (m0->m_len < sizeof (struct ether_header) && 1475 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1476 continue; 1477 1478 eh = mtod(m0, struct ether_header *); 1479 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1480 if (ni == NULL) { 1481 m_freem(m0); 1482 continue; 1483 } 1484 BPF_MTAP(ifp, m0); 1485 1486 m0 = ieee80211_encap(ic, m0, ni); 1487 if (m0 == NULL) { 1488 ieee80211_free_node(ni); 1489 continue; 1490 } 1491 1492 if (ic->ic_rawbpf != NULL) 1493 bpf_mtap(ic->ic_rawbpf, m0); 1494 1495 if (ipw_tx_start(ifp, m0, ni) != 0) { 1496 ieee80211_free_node(ni); 1497 ifp->if_oerrors++; 1498 break; 1499 } 1500 1501 /* start watchdog timer */ 1502 sc->sc_tx_timer = 5; 1503 ifp->if_timer = 1; 1504 } 1505 1506 IPW_UNLOCK(sc); 1507 } 1508 1509 static void 1510 ipw_watchdog(struct ifnet *ifp) 1511 { 1512 struct ipw_softc *sc = ifp->if_softc; 1513 struct ieee80211com *ic = &sc->sc_ic; 1514 1515 ifp->if_timer = 0; 1516 1517 if (sc->sc_tx_timer > 0) { 1518 if (--sc->sc_tx_timer == 0) { 1519 if_printf(ifp, "device timeout\n"); 1520 ifp->if_oerrors++; 1521 ifp->if_flags &= ~IFF_UP; 1522 ipw_stop(sc); 1523 return; 1524 } 1525 ifp->if_timer = 1; 1526 } 1527 1528 ieee80211_watchdog(ic); 1529 } 1530 1531 static int 1532 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1533 { 1534 struct ipw_softc *sc = ifp->if_softc; 1535 struct ieee80211com *ic = &sc->sc_ic; 1536 struct ifreq *ifr; 1537 int error = 0; 1538 1539 IPW_LOCK(sc); 1540 1541 switch (cmd) { 1542 case SIOCSIFFLAGS: 1543 if (ifp->if_flags & IFF_UP) { 1544 if (!(ifp->if_flags & IFF_RUNNING)) 1545 ipw_init(sc); 1546 } else { 1547 if (ifp->if_flags & IFF_RUNNING) 1548 ipw_stop(sc); 1549 } 1550 break; 1551 1552 case SIOCSLOADFW: 1553 /* only super-user can do that! */ 1554 if ((error = suser(curthread)) != 0) 1555 break; 1556 1557 ifr = (struct ifreq *)data; 1558 error = ipw_cache_firmware(sc, ifr->ifr_data); 1559 break; 1560 1561 case SIOCSKILLFW: 1562 /* only super-user can do that! */ 1563 if ((error = suser(curthread)) != 0) 1564 break; 1565 1566 ifp->if_flags &= ~IFF_UP; 1567 ipw_stop(sc); 1568 ipw_free_firmware(sc); 1569 break; 1570 1571 default: 1572 error = ieee80211_ioctl(ic, cmd, data); 1573 } 1574 1575 if (error == ENETRESET) { 1576 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1577 (IFF_UP | IFF_RUNNING)) 1578 ipw_init(sc); 1579 error = 0; 1580 } 1581 1582 IPW_UNLOCK(sc); 1583 1584 return error; 1585 } 1586 1587 static void 1588 ipw_stop_master(struct ipw_softc *sc) 1589 { 1590 int ntries; 1591 1592 /* disable interrupts */ 1593 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1594 1595 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1596 for (ntries = 0; ntries < 50; ntries++) { 1597 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1598 break; 1599 DELAY(10); 1600 } 1601 if (ntries == 50) 1602 device_printf(sc->sc_dev, "timeout waiting for master\n"); 1603 1604 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1605 IPW_RST_PRINCETON_RESET); 1606 1607 sc->flags &= ~IPW_FLAG_FW_INITED; 1608 } 1609 1610 static int 1611 ipw_reset(struct ipw_softc *sc) 1612 { 1613 int ntries; 1614 1615 ipw_stop_master(sc); 1616 1617 /* move adapter to D0 state */ 1618 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1619 IPW_CTL_INIT); 1620 1621 /* wait for clock stabilization */ 1622 for (ntries = 0; ntries < 1000; ntries++) { 1623 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1624 break; 1625 DELAY(200); 1626 } 1627 if (ntries == 1000) 1628 return EIO; 1629 1630 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1631 IPW_RST_SW_RESET); 1632 1633 DELAY(10); 1634 1635 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1636 IPW_CTL_INIT); 1637 1638 return 0; 1639 } 1640 1641 /* 1642 * Upload the microcode to the device. 1643 */ 1644 static int 1645 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1646 { 1647 int ntries; 1648 1649 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1650 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1651 1652 MEM_WRITE_2(sc, 0x220000, 0x0703); 1653 MEM_WRITE_2(sc, 0x220000, 0x0707); 1654 1655 MEM_WRITE_1(sc, 0x210014, 0x72); 1656 MEM_WRITE_1(sc, 0x210014, 0x72); 1657 1658 MEM_WRITE_1(sc, 0x210000, 0x40); 1659 MEM_WRITE_1(sc, 0x210000, 0x00); 1660 MEM_WRITE_1(sc, 0x210000, 0x40); 1661 1662 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1663 1664 MEM_WRITE_1(sc, 0x210000, 0x00); 1665 MEM_WRITE_1(sc, 0x210000, 0x00); 1666 MEM_WRITE_1(sc, 0x210000, 0x80); 1667 1668 MEM_WRITE_2(sc, 0x220000, 0x0703); 1669 MEM_WRITE_2(sc, 0x220000, 0x0707); 1670 1671 MEM_WRITE_1(sc, 0x210014, 0x72); 1672 MEM_WRITE_1(sc, 0x210014, 0x72); 1673 1674 MEM_WRITE_1(sc, 0x210000, 0x00); 1675 MEM_WRITE_1(sc, 0x210000, 0x80); 1676 1677 for (ntries = 0; ntries < 10; ntries++) { 1678 if (MEM_READ_1(sc, 0x210000) & 1) 1679 break; 1680 DELAY(10); 1681 } 1682 if (ntries == 10) { 1683 device_printf(sc->sc_dev, 1684 "timeout waiting for ucode to initialize\n"); 1685 return EIO; 1686 } 1687 1688 MEM_WRITE_4(sc, 0x3000e0, 0); 1689 1690 return 0; 1691 } 1692 1693 /* set of macros to handle unaligned little endian data in firmware image */ 1694 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1695 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1696 static int 1697 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1698 { 1699 u_char *p, *end; 1700 uint32_t dst; 1701 uint16_t len; 1702 int error; 1703 1704 p = fw; 1705 end = fw + size; 1706 while (p < end) { 1707 dst = GETLE32(p); p += 4; 1708 len = GETLE16(p); p += 2; 1709 1710 ipw_write_mem_1(sc, dst, p, len); 1711 p += len; 1712 } 1713 1714 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1715 IPW_IO_LED_OFF); 1716 1717 /* enable interrupts */ 1718 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1719 1720 /* kick the firmware */ 1721 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1722 1723 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1724 IPW_CTL_ALLOW_STANDBY); 1725 1726 /* wait at most one second for firmware initialization to complete */ 1727 if ((error = msleep(sc, &sc->sc_mtx, 0, "ipwinit", hz)) != 0) { 1728 device_printf(sc->sc_dev, "timeout waiting for firmware " 1729 "initialization to complete\n"); 1730 return error; 1731 } 1732 1733 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1734 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1735 1736 return 0; 1737 } 1738 1739 /* 1740 * Store firmware into kernel memory so we can download it when we need to, 1741 * e.g when the adapter wakes up from suspend mode. 1742 */ 1743 static int 1744 ipw_cache_firmware(struct ipw_softc *sc, void *data) 1745 { 1746 struct ipw_firmware *fw = &sc->fw; 1747 struct ipw_firmware_hdr hdr; 1748 u_char *p = data; 1749 int error; 1750 1751 ipw_free_firmware(sc); 1752 1753 IPW_UNLOCK(sc); 1754 1755 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1756 goto fail1; 1757 1758 fw->main_size = le32toh(hdr.main_size); 1759 fw->ucode_size = le32toh(hdr.ucode_size); 1760 p += sizeof hdr; 1761 1762 fw->main = malloc(fw->main_size, M_DEVBUF, M_NOWAIT); 1763 if (fw->main == NULL) { 1764 error = ENOMEM; 1765 goto fail1; 1766 } 1767 1768 fw->ucode = malloc(fw->ucode_size, M_DEVBUF, M_NOWAIT); 1769 if (fw->ucode == NULL) { 1770 error = ENOMEM; 1771 goto fail2; 1772 } 1773 1774 if ((error = copyin(p, fw->main, fw->main_size)) != 0) 1775 goto fail3; 1776 1777 p += fw->main_size; 1778 if ((error = copyin(p, fw->ucode, fw->ucode_size)) != 0) 1779 goto fail3; 1780 1781 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1782 fw->ucode_size)); 1783 1784 IPW_LOCK(sc); 1785 1786 sc->flags |= IPW_FLAG_FW_CACHED; 1787 1788 return 0; 1789 1790 fail3: free(fw->ucode, M_DEVBUF); 1791 fail2: free(fw->main, M_DEVBUF); 1792 fail1: IPW_LOCK(sc); 1793 1794 return error; 1795 } 1796 1797 static void 1798 ipw_free_firmware(struct ipw_softc *sc) 1799 { 1800 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1801 return; 1802 1803 free(sc->fw.main, M_DEVBUF); 1804 free(sc->fw.ucode, M_DEVBUF); 1805 1806 sc->flags &= ~IPW_FLAG_FW_CACHED; 1807 } 1808 1809 static int 1810 ipw_config(struct ipw_softc *sc) 1811 { 1812 struct ieee80211com *ic = &sc->sc_ic; 1813 struct ifnet *ifp = ic->ic_ifp; 1814 struct ipw_security security; 1815 struct ieee80211_key *k; 1816 struct ipw_wep_key wepkey; 1817 struct ipw_scan_options options; 1818 struct ipw_configuration config; 1819 uint32_t data; 1820 int error, i; 1821 1822 switch (ic->ic_opmode) { 1823 case IEEE80211_M_STA: 1824 case IEEE80211_M_HOSTAP: 1825 data = htole32(IPW_MODE_BSS); 1826 break; 1827 1828 case IEEE80211_M_IBSS: 1829 case IEEE80211_M_AHDEMO: 1830 data = htole32(IPW_MODE_IBSS); 1831 break; 1832 1833 case IEEE80211_M_MONITOR: 1834 data = htole32(IPW_MODE_MONITOR); 1835 break; 1836 } 1837 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1838 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1839 if (error != 0) 1840 return error; 1841 1842 if (ic->ic_opmode == IEEE80211_M_IBSS || 1843 ic->ic_opmode == IEEE80211_M_MONITOR) { 1844 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1845 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1846 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1847 if (error != 0) 1848 return error; 1849 } 1850 1851 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1852 DPRINTF(("Enabling adapter\n")); 1853 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1854 } 1855 1856 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 1857 DPRINTF(("Setting MAC address to %6D\n", ic->ic_myaddr, ":")); 1858 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1859 IEEE80211_ADDR_LEN); 1860 if (error != 0) 1861 return error; 1862 1863 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1864 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1865 if (ic->ic_opmode == IEEE80211_M_IBSS) 1866 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1867 if (ifp->if_flags & IFF_PROMISC) 1868 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1869 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1870 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1871 DPRINTF(("Setting configuration to 0x%x\n", le32toh(config.flags))); 1872 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1873 if (error != 0) 1874 return error; 1875 1876 data = htole32(0x3); /* 1, 2 */ 1877 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 1878 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1879 if (error != 0) 1880 return error; 1881 1882 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1883 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 1884 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1885 if (error != 0) 1886 return error; 1887 1888 data = htole32(IPW_POWER_MODE_CAM); 1889 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 1890 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1891 if (error != 0) 1892 return error; 1893 1894 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1895 data = htole32(32); /* default value */ 1896 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 1897 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1898 sizeof data); 1899 if (error != 0) 1900 return error; 1901 } 1902 1903 data = htole32(ic->ic_rtsthreshold); 1904 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 1905 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1906 if (error != 0) 1907 return error; 1908 1909 data = htole32(ic->ic_fragthreshold); 1910 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 1911 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1912 if (error != 0) 1913 return error; 1914 1915 #ifdef IPW_DEBUG 1916 if (ipw_debug > 0) { 1917 printf("Setting ESSID to "); 1918 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1919 printf("\n"); 1920 } 1921 #endif 1922 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1923 ic->ic_des_esslen); 1924 if (error != 0) 1925 return error; 1926 1927 /* no mandatory BSSID */ 1928 DPRINTF(("Setting mandatory BSSID to null\n")); 1929 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1930 if (error != 0) 1931 return error; 1932 1933 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1934 DPRINTF(("Setting desired BSSID to %6D\n", ic->ic_des_bssid, 1935 ":")); 1936 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1937 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1938 if (error != 0) 1939 return error; 1940 } 1941 1942 bzero(&security, sizeof security); 1943 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 1944 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1945 security.ciphers = htole32(IPW_CIPHER_NONE); 1946 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1947 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1948 sizeof security); 1949 if (error != 0) 1950 return error; 1951 1952 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1953 k = ic->ic_crypto.cs_nw_keys; 1954 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1955 if (k->wk_keylen == 0) 1956 continue; 1957 1958 wepkey.idx = i; 1959 wepkey.len = k->wk_keylen; 1960 bzero(wepkey.key, sizeof wepkey.key); 1961 bcopy(k->wk_key, wepkey.key, k->wk_keylen); 1962 DPRINTF(("Setting wep key index %u len %u\n", 1963 wepkey.idx, wepkey.len)); 1964 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1965 sizeof wepkey); 1966 if (error != 0) 1967 return error; 1968 } 1969 1970 data = htole32(ic->ic_crypto.cs_def_txkey); 1971 DPRINTF(("Setting wep tx key index to %u\n", le32toh(data))); 1972 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1973 sizeof data); 1974 if (error != 0) 1975 return error; 1976 } 1977 1978 data = htole32((ic->ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 1979 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 1980 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1981 if (error != 0) 1982 return error; 1983 1984 #if 0 1985 struct ipw_wpa_ie ie; 1986 1987 bzero(&ie, sizeof ie); 1988 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 1989 DPRINTF(("Setting wpa ie\n")); 1990 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 1991 if (error != 0) 1992 return error; 1993 #endif 1994 1995 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1996 data = htole32(ic->ic_lintval); 1997 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 1998 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1999 sizeof data); 2000 if (error != 0) 2001 return error; 2002 } 2003 2004 options.flags = 0; 2005 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 2006 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2007 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2008 if (error != 0) 2009 return error; 2010 2011 /* finally, enable adapter (start scanning for an access point) */ 2012 DPRINTF(("Enabling adapter\n")); 2013 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2014 } 2015 2016 static void 2017 ipw_init(void *priv) 2018 { 2019 struct ipw_softc *sc = priv; 2020 struct ieee80211com *ic = &sc->sc_ic; 2021 struct ifnet *ifp = ic->ic_ifp; 2022 struct ipw_firmware *fw = &sc->fw; 2023 2024 /* exit immediately if firmware has not been ioctl'd */ 2025 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2026 if (!(sc->flags & IPW_FLAG_FW_WARNED)) 2027 device_printf(sc->sc_dev, "Please load firmware\n"); 2028 sc->flags |= IPW_FLAG_FW_WARNED; 2029 ifp->if_flags &= ~IFF_UP; 2030 return; 2031 } 2032 2033 ipw_stop(sc); 2034 2035 if (ipw_reset(sc) != 0) { 2036 device_printf(sc->sc_dev, "could not reset adapter\n"); 2037 goto fail; 2038 } 2039 2040 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2041 device_printf(sc->sc_dev, "could not load microcode\n"); 2042 goto fail; 2043 } 2044 2045 ipw_stop_master(sc); 2046 2047 /* 2048 * Setup tx, rx and status rings. 2049 */ 2050 sc->txold = IPW_NTBD - 1; 2051 sc->txcur = 0; 2052 sc->txfree = IPW_NTBD - 2; 2053 sc->rxcur = IPW_NRBD - 1; 2054 2055 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_phys); 2056 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2057 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2058 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2059 2060 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_phys); 2061 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2062 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2063 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2064 2065 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_phys); 2066 2067 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2068 device_printf(sc->sc_dev, "could not load firmware\n"); 2069 goto fail; 2070 } 2071 2072 sc->flags |= IPW_FLAG_FW_INITED; 2073 2074 /* retrieve information tables base addresses */ 2075 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2076 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2077 2078 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2079 2080 if (ipw_config(sc) != 0) { 2081 device_printf(sc->sc_dev, "device configuration failed\n"); 2082 goto fail; 2083 } 2084 2085 ifp->if_flags &= ~IFF_OACTIVE; 2086 ifp->if_flags |= IFF_RUNNING; 2087 2088 return; 2089 2090 fail: ifp->if_flags &= ~IFF_UP; 2091 ipw_stop(sc); 2092 } 2093 2094 static void 2095 ipw_stop(void *priv) 2096 { 2097 struct ipw_softc *sc = priv; 2098 struct ieee80211com *ic = &sc->sc_ic; 2099 struct ifnet *ifp = ic->ic_ifp; 2100 int i; 2101 2102 ipw_stop_master(sc); 2103 2104 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2105 2106 /* 2107 * Release tx buffers. 2108 */ 2109 for (i = 0; i < IPW_NTBD; i++) 2110 ipw_release_sbd(sc, &sc->stbd_list[i]); 2111 2112 sc->sc_tx_timer = 0; 2113 ifp->if_timer = 0; 2114 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2115 2116 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2117 } 2118 2119 #ifdef IPW_DEBUG 2120 static int 2121 ipw_sysctl_stats(SYSCTL_HANDLER_ARGS) 2122 { 2123 struct ipw_softc *sc = arg1; 2124 uint32_t i, size, buf[256]; 2125 2126 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 2127 bzero(buf, sizeof buf); 2128 return SYSCTL_OUT(req, buf, sizeof buf); 2129 } 2130 2131 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 2132 2133 size = min(CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA), 256); 2134 for (i = 1; i < size; i++) 2135 buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA)); 2136 2137 return SYSCTL_OUT(req, buf, sizeof buf); 2138 } 2139 #endif 2140 2141 static int 2142 ipw_sysctl_radio(SYSCTL_HANDLER_ARGS) 2143 { 2144 struct ipw_softc *sc = arg1; 2145 int val; 2146 2147 val = !((sc->flags & IPW_FLAG_HAS_RADIO_SWITCH) && 2148 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED)); 2149 2150 return SYSCTL_OUT(req, &val, sizeof val); 2151 } 2152 2153 static uint32_t 2154 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 2155 { 2156 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 2157 } 2158 2159 static void 2160 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 2161 { 2162 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 2163 } 2164 2165 static int 2166 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 2167 { 2168 uint32_t addr, info; 2169 uint16_t count, size; 2170 uint32_t total; 2171 2172 /* addr[4] + count[2] + size[2] */ 2173 addr = MEM_READ_4(sc, sc->table2_base + off); 2174 info = MEM_READ_4(sc, sc->table2_base + off + 4); 2175 2176 count = info >> 16; 2177 size = info & 0xffff; 2178 total = count * size; 2179 2180 if (total > *len) { 2181 *len = total; 2182 return EINVAL; 2183 } 2184 2185 *len = total; 2186 ipw_read_mem_1(sc, addr, buf, total); 2187 2188 return 0; 2189 } 2190 2191 static void 2192 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2193 bus_size_t count) 2194 { 2195 for (; count > 0; offset++, datap++, count--) { 2196 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2197 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2198 } 2199 } 2200 2201 static void 2202 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2203 bus_size_t count) 2204 { 2205 for (; count > 0; offset++, datap++, count--) { 2206 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2207 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2208 } 2209 } 2210