1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2004-2006 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /*- 34 * Intel(R) PRO/Wireless 2100 MiniPCI driver 35 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 36 */ 37 38 #include <sys/param.h> 39 #include <sys/sysctl.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/systm.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/module.h> 49 #include <sys/bus.h> 50 #include <sys/endian.h> 51 #include <sys/linker.h> 52 #include <sys/firmware.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 #include <sys/rman.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 61 #include <net/bpf.h> 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/ethernet.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 #include <netinet/if_ether.h> 77 78 #include <dev/ipw/if_ipwreg.h> 79 #include <dev/ipw/if_ipwvar.h> 80 81 #ifdef IPW_DEBUG 82 #define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 83 #define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 84 int ipw_debug = 0; 85 SYSCTL_INT(_debug, OID_AUTO, ipw, CTLFLAG_RW, &ipw_debug, 0, "ipw debug level"); 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 MODULE_DEPEND(ipw, pci, 1, 1, 1); 92 MODULE_DEPEND(ipw, wlan, 1, 1, 1); 93 MODULE_DEPEND(ipw, firmware, 1, 1, 1); 94 95 struct ipw_ident { 96 uint16_t vendor; 97 uint16_t device; 98 const char *name; 99 }; 100 101 static const struct ipw_ident ipw_ident_table[] = { 102 { 0x8086, 0x1043, "Intel(R) PRO/Wireless 2100 MiniPCI" }, 103 104 { 0, 0, NULL } 105 }; 106 107 static int ipw_dma_alloc(struct ipw_softc *); 108 static void ipw_release(struct ipw_softc *); 109 static int ipw_media_change(struct ifnet *); 110 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 111 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 112 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 113 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 114 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 115 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 116 struct ipw_soft_bd *, struct ipw_soft_buf *); 117 static void ipw_rx_intr(struct ipw_softc *); 118 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 119 static void ipw_tx_intr(struct ipw_softc *); 120 static void ipw_intr(void *); 121 static void ipw_dma_map_addr(void *, bus_dma_segment_t *, int, int); 122 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 123 static int ipw_tx_start(struct ifnet *, struct mbuf *, 124 struct ieee80211_node *); 125 static void ipw_start(struct ifnet *); 126 static void ipw_watchdog(struct ifnet *); 127 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 128 static void ipw_stop_master(struct ipw_softc *); 129 static int ipw_reset(struct ipw_softc *); 130 static int ipw_load_ucode(struct ipw_softc *, const char *, int); 131 static int ipw_load_firmware(struct ipw_softc *, const char *, int); 132 static int ipw_config(struct ipw_softc *); 133 static void ipw_init_task(void *, int); 134 static void ipw_init(void *); 135 static void ipw_stop(void *); 136 static int ipw_sysctl_stats(SYSCTL_HANDLER_ARGS); 137 static int ipw_sysctl_radio(SYSCTL_HANDLER_ARGS); 138 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 139 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 140 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 141 uint32_t *); 142 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 143 bus_size_t); 144 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, 145 const uint8_t *, bus_size_t); 146 147 static int ipw_probe(device_t); 148 static int ipw_attach(device_t); 149 static int ipw_detach(device_t); 150 static int ipw_shutdown(device_t); 151 static int ipw_suspend(device_t); 152 static int ipw_resume(device_t); 153 154 static device_method_t ipw_methods[] = { 155 /* Device interface */ 156 DEVMETHOD(device_probe, ipw_probe), 157 DEVMETHOD(device_attach, ipw_attach), 158 DEVMETHOD(device_detach, ipw_detach), 159 DEVMETHOD(device_shutdown, ipw_shutdown), 160 DEVMETHOD(device_suspend, ipw_suspend), 161 DEVMETHOD(device_resume, ipw_resume), 162 163 { 0, 0 } 164 }; 165 166 static driver_t ipw_driver = { 167 "ipw", 168 ipw_methods, 169 sizeof (struct ipw_softc) 170 }; 171 172 static devclass_t ipw_devclass; 173 174 DRIVER_MODULE(ipw, pci, ipw_driver, ipw_devclass, 0, 0); 175 176 /* 177 * Supported rates for 802.11b mode (in 500Kbps unit). 178 */ 179 static const struct ieee80211_rateset ipw_rateset_11b = 180 { 4, { 2, 4, 11, 22 } }; 181 182 static int 183 ipw_probe(device_t dev) 184 { 185 const struct ipw_ident *ident; 186 187 for (ident = ipw_ident_table; ident->name != NULL; ident++) { 188 if (pci_get_vendor(dev) == ident->vendor && 189 pci_get_device(dev) == ident->device) { 190 device_set_desc(dev, ident->name); 191 return 0; 192 } 193 } 194 return ENXIO; 195 } 196 197 /* Base Address Register */ 198 #define IPW_PCI_BAR0 0x10 199 200 static int 201 ipw_attach(device_t dev) 202 { 203 struct ipw_softc *sc = device_get_softc(dev); 204 struct ifnet *ifp; 205 struct ieee80211com *ic = &sc->sc_ic; 206 uint16_t val; 207 int error, i; 208 209 sc->sc_dev = dev; 210 211 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 212 MTX_DEF | MTX_RECURSE); 213 214 TASK_INIT(&sc->sc_init_task, 0, ipw_init_task, sc); 215 216 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 217 device_printf(dev, "chip is in D%d power mode " 218 "-- setting to D0\n", pci_get_powerstate(dev)); 219 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 220 } 221 222 pci_write_config(dev, 0x41, 0, 1); 223 224 /* enable bus-mastering */ 225 pci_enable_busmaster(dev); 226 227 sc->mem_rid = IPW_PCI_BAR0; 228 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 229 RF_ACTIVE); 230 if (sc->mem == NULL) { 231 device_printf(dev, "could not allocate memory resource\n"); 232 goto fail; 233 } 234 235 sc->sc_st = rman_get_bustag(sc->mem); 236 sc->sc_sh = rman_get_bushandle(sc->mem); 237 238 sc->irq_rid = 0; 239 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 240 RF_ACTIVE | RF_SHAREABLE); 241 if (sc->irq == NULL) { 242 device_printf(dev, "could not allocate interrupt resource\n"); 243 goto fail; 244 } 245 246 if (ipw_reset(sc) != 0) { 247 device_printf(dev, "could not reset adapter\n"); 248 goto fail; 249 } 250 251 if (ipw_dma_alloc(sc) != 0) { 252 device_printf(dev, "could not allocate DMA resources\n"); 253 goto fail; 254 } 255 256 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 257 if (ifp == NULL) { 258 device_printf(dev, "can not if_alloc()\n"); 259 goto fail; 260 } 261 262 ifp->if_softc = sc; 263 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 264 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 265 ifp->if_init = ipw_init; 266 ifp->if_ioctl = ipw_ioctl; 267 ifp->if_start = ipw_start; 268 ifp->if_watchdog = ipw_watchdog; 269 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 270 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 271 IFQ_SET_READY(&ifp->if_snd); 272 273 ic->ic_ifp = ifp; 274 ic->ic_phytype = IEEE80211_T_DS; 275 ic->ic_opmode = IEEE80211_M_STA; 276 ic->ic_state = IEEE80211_S_INIT; 277 278 /* set device capabilities */ 279 ic->ic_caps = 280 IEEE80211_C_IBSS | /* IBSS mode supported */ 281 IEEE80211_C_MONITOR | /* monitor mode supported */ 282 IEEE80211_C_TXPMGT | /* tx power management */ 283 IEEE80211_C_SHPREAMBLE; /* short preamble supported */ 284 285 /* read MAC address from EEPROM */ 286 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 287 ic->ic_myaddr[0] = val >> 8; 288 ic->ic_myaddr[1] = val & 0xff; 289 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 290 ic->ic_myaddr[2] = val >> 8; 291 ic->ic_myaddr[3] = val & 0xff; 292 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 293 ic->ic_myaddr[4] = val >> 8; 294 ic->ic_myaddr[5] = val & 0xff; 295 296 /* set supported .11b rates */ 297 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 298 299 /* set supported .11b channels */ 300 for (i = 1; i < 14; i++) { 301 ic->ic_channels[i].ic_freq = 302 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 303 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 304 } 305 306 /* check support for radio transmitter switch in EEPROM */ 307 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 308 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 309 310 ieee80211_ifattach(ic); 311 /* override state transition machine */ 312 sc->sc_newstate = ic->ic_newstate; 313 ic->ic_newstate = ipw_newstate; 314 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 315 316 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 317 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 318 319 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 320 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 321 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 322 323 sc->sc_txtap_len = sizeof sc->sc_txtapu; 324 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 325 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 326 327 /* 328 * Add a few sysctl knobs. 329 */ 330 sc->dwelltime = 100; 331 332 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 333 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "radio", 334 CTLTYPE_INT | CTLFLAG_RD, sc, 0, ipw_sysctl_radio, "I", 335 "radio transmitter switch state (0=off, 1=on)"); 336 337 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 338 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats", 339 CTLTYPE_OPAQUE | CTLFLAG_RD, sc, 0, ipw_sysctl_stats, "S", 340 "statistics"); 341 342 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 343 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", 344 CTLFLAG_RW, &sc->dwelltime, 0, 345 "channel dwell time (ms) for AP/station scanning"); 346 347 /* 348 * Hook our interrupt after all initialization is complete. 349 */ 350 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 351 ipw_intr, sc, &sc->sc_ih); 352 if (error != 0) { 353 device_printf(dev, "could not set up interrupt\n"); 354 goto fail; 355 } 356 357 if (bootverbose) 358 ieee80211_announce(ic); 359 360 return 0; 361 362 fail: ipw_detach(dev); 363 return ENXIO; 364 } 365 366 static int 367 ipw_detach(device_t dev) 368 { 369 struct ipw_softc *sc = device_get_softc(dev); 370 struct ieee80211com *ic = &sc->sc_ic; 371 struct ifnet *ifp = ic->ic_ifp; 372 373 ipw_stop(sc); 374 375 if (ifp != NULL) { 376 bpfdetach(ifp); 377 ieee80211_ifdetach(ic); 378 } 379 380 ipw_release(sc); 381 382 if (sc->irq != NULL) { 383 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 384 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 385 } 386 387 if (sc->mem != NULL) 388 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 389 390 if (ifp != NULL) 391 if_free(ifp); 392 393 mtx_destroy(&sc->sc_mtx); 394 395 return 0; 396 } 397 398 static int 399 ipw_dma_alloc(struct ipw_softc *sc) 400 { 401 struct ipw_soft_bd *sbd; 402 struct ipw_soft_hdr *shdr; 403 struct ipw_soft_buf *sbuf; 404 bus_addr_t physaddr; 405 int error, i; 406 407 /* 408 * Allocate and map tx ring. 409 */ 410 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 411 BUS_SPACE_MAXADDR, NULL, NULL, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, NULL, 412 NULL, &sc->tbd_dmat); 413 if (error != 0) { 414 device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); 415 goto fail; 416 } 417 418 error = bus_dmamem_alloc(sc->tbd_dmat, (void **)&sc->tbd_list, 419 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tbd_map); 420 if (error != 0) { 421 device_printf(sc->sc_dev, 422 "could not allocate tx ring DMA memory\n"); 423 goto fail; 424 } 425 426 error = bus_dmamap_load(sc->tbd_dmat, sc->tbd_map, sc->tbd_list, 427 IPW_TBD_SZ, ipw_dma_map_addr, &sc->tbd_phys, 0); 428 if (error != 0) { 429 device_printf(sc->sc_dev, "could not map tx ring DMA memory\n"); 430 goto fail; 431 } 432 433 /* 434 * Allocate and map rx ring. 435 */ 436 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 437 BUS_SPACE_MAXADDR, NULL, NULL, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, NULL, 438 NULL, &sc->rbd_dmat); 439 if (error != 0) { 440 device_printf(sc->sc_dev, "could not create rx ring DMA tag\n"); 441 goto fail; 442 } 443 444 error = bus_dmamem_alloc(sc->rbd_dmat, (void **)&sc->rbd_list, 445 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rbd_map); 446 if (error != 0) { 447 device_printf(sc->sc_dev, 448 "could not allocate rx ring DMA memory\n"); 449 goto fail; 450 } 451 452 error = bus_dmamap_load(sc->rbd_dmat, sc->rbd_map, sc->rbd_list, 453 IPW_RBD_SZ, ipw_dma_map_addr, &sc->rbd_phys, 0); 454 if (error != 0) { 455 device_printf(sc->sc_dev, "could not map rx ring DMA memory\n"); 456 goto fail; 457 } 458 459 /* 460 * Allocate and map status ring. 461 */ 462 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 463 BUS_SPACE_MAXADDR, NULL, NULL, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 0, 464 NULL, NULL, &sc->status_dmat); 465 if (error != 0) { 466 device_printf(sc->sc_dev, 467 "could not create status ring DMA tag\n"); 468 goto fail; 469 } 470 471 error = bus_dmamem_alloc(sc->status_dmat, (void **)&sc->status_list, 472 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->status_map); 473 if (error != 0) { 474 device_printf(sc->sc_dev, 475 "could not allocate status ring DMA memory\n"); 476 goto fail; 477 } 478 479 error = bus_dmamap_load(sc->status_dmat, sc->status_map, 480 sc->status_list, IPW_STATUS_SZ, ipw_dma_map_addr, &sc->status_phys, 481 0); 482 if (error != 0) { 483 device_printf(sc->sc_dev, 484 "could not map status ring DMA memory\n"); 485 goto fail; 486 } 487 488 /* 489 * Allocate command DMA map. 490 */ 491 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 492 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_cmd), 1, 493 sizeof (struct ipw_cmd), 0, NULL, NULL, &sc->cmd_dmat); 494 if (error != 0) { 495 device_printf(sc->sc_dev, "could not create command DMA tag\n"); 496 goto fail; 497 } 498 499 error = bus_dmamap_create(sc->cmd_dmat, 0, &sc->cmd_map); 500 if (error != 0) { 501 device_printf(sc->sc_dev, 502 "could not create command DMA map\n"); 503 goto fail; 504 } 505 506 /* 507 * Allocate headers DMA maps. 508 */ 509 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 510 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_hdr), 1, 511 sizeof (struct ipw_hdr), 0, NULL, NULL, &sc->hdr_dmat); 512 if (error != 0) { 513 device_printf(sc->sc_dev, "could not create header DMA tag\n"); 514 goto fail; 515 } 516 517 SLIST_INIT(&sc->free_shdr); 518 for (i = 0; i < IPW_NDATA; i++) { 519 shdr = &sc->shdr_list[i]; 520 error = bus_dmamap_create(sc->hdr_dmat, 0, &shdr->map); 521 if (error != 0) { 522 device_printf(sc->sc_dev, 523 "could not create header DMA map\n"); 524 goto fail; 525 } 526 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 527 } 528 529 /* 530 * Allocate tx buffers DMA maps. 531 */ 532 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 533 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_MAX_NSEG, MCLBYTES, 0, 534 NULL, NULL, &sc->txbuf_dmat); 535 if (error != 0) { 536 device_printf(sc->sc_dev, "could not create tx DMA tag\n"); 537 goto fail; 538 } 539 540 SLIST_INIT(&sc->free_sbuf); 541 for (i = 0; i < IPW_NDATA; i++) { 542 sbuf = &sc->tx_sbuf_list[i]; 543 error = bus_dmamap_create(sc->txbuf_dmat, 0, &sbuf->map); 544 if (error != 0) { 545 device_printf(sc->sc_dev, 546 "could not create tx DMA map\n"); 547 goto fail; 548 } 549 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 550 } 551 552 /* 553 * Initialize tx ring. 554 */ 555 for (i = 0; i < IPW_NTBD; i++) { 556 sbd = &sc->stbd_list[i]; 557 sbd->bd = &sc->tbd_list[i]; 558 sbd->type = IPW_SBD_TYPE_NOASSOC; 559 } 560 561 /* 562 * Pre-allocate rx buffers and DMA maps. 563 */ 564 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 565 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, 566 NULL, &sc->rxbuf_dmat); 567 if (error != 0) { 568 device_printf(sc->sc_dev, "could not create rx DMA tag\n"); 569 goto fail; 570 } 571 572 for (i = 0; i < IPW_NRBD; i++) { 573 sbd = &sc->srbd_list[i]; 574 sbuf = &sc->rx_sbuf_list[i]; 575 sbd->bd = &sc->rbd_list[i]; 576 577 sbuf->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 578 if (sbuf->m == NULL) { 579 device_printf(sc->sc_dev, 580 "could not allocate rx mbuf\n"); 581 error = ENOMEM; 582 goto fail; 583 } 584 585 error = bus_dmamap_create(sc->rxbuf_dmat, 0, &sbuf->map); 586 if (error != 0) { 587 device_printf(sc->sc_dev, 588 "could not create rx DMA map\n"); 589 goto fail; 590 } 591 592 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 593 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 594 &physaddr, 0); 595 if (error != 0) { 596 device_printf(sc->sc_dev, 597 "could not map rx DMA memory\n"); 598 goto fail; 599 } 600 601 sbd->type = IPW_SBD_TYPE_DATA; 602 sbd->priv = sbuf; 603 sbd->bd->physaddr = htole32(physaddr); 604 sbd->bd->len = htole32(MCLBYTES); 605 } 606 607 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 608 609 return 0; 610 611 fail: ipw_release(sc); 612 return error; 613 } 614 615 static void 616 ipw_release(struct ipw_softc *sc) 617 { 618 struct ipw_soft_buf *sbuf; 619 int i; 620 621 if (sc->tbd_dmat != NULL) { 622 if (sc->stbd_list != NULL) { 623 bus_dmamap_unload(sc->tbd_dmat, sc->tbd_map); 624 bus_dmamem_free(sc->tbd_dmat, sc->tbd_list, 625 sc->tbd_map); 626 } 627 bus_dma_tag_destroy(sc->tbd_dmat); 628 } 629 630 if (sc->rbd_dmat != NULL) { 631 if (sc->rbd_list != NULL) { 632 bus_dmamap_unload(sc->rbd_dmat, sc->rbd_map); 633 bus_dmamem_free(sc->rbd_dmat, sc->rbd_list, 634 sc->rbd_map); 635 } 636 bus_dma_tag_destroy(sc->rbd_dmat); 637 } 638 639 if (sc->status_dmat != NULL) { 640 if (sc->status_list != NULL) { 641 bus_dmamap_unload(sc->status_dmat, sc->status_map); 642 bus_dmamem_free(sc->status_dmat, sc->status_list, 643 sc->status_map); 644 } 645 bus_dma_tag_destroy(sc->status_dmat); 646 } 647 648 for (i = 0; i < IPW_NTBD; i++) 649 ipw_release_sbd(sc, &sc->stbd_list[i]); 650 651 if (sc->cmd_dmat != NULL) { 652 bus_dmamap_destroy(sc->cmd_dmat, sc->cmd_map); 653 bus_dma_tag_destroy(sc->cmd_dmat); 654 } 655 656 if (sc->hdr_dmat != NULL) { 657 for (i = 0; i < IPW_NDATA; i++) 658 bus_dmamap_destroy(sc->hdr_dmat, sc->shdr_list[i].map); 659 bus_dma_tag_destroy(sc->hdr_dmat); 660 } 661 662 if (sc->txbuf_dmat != NULL) { 663 for (i = 0; i < IPW_NDATA; i++) { 664 bus_dmamap_destroy(sc->txbuf_dmat, 665 sc->tx_sbuf_list[i].map); 666 } 667 bus_dma_tag_destroy(sc->txbuf_dmat); 668 } 669 670 if (sc->rxbuf_dmat != NULL) { 671 for (i = 0; i < IPW_NRBD; i++) { 672 sbuf = &sc->rx_sbuf_list[i]; 673 if (sbuf->m != NULL) { 674 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, 675 BUS_DMASYNC_POSTREAD); 676 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 677 m_freem(sbuf->m); 678 } 679 bus_dmamap_destroy(sc->rxbuf_dmat, sbuf->map); 680 } 681 bus_dma_tag_destroy(sc->rxbuf_dmat); 682 } 683 } 684 685 static int 686 ipw_shutdown(device_t dev) 687 { 688 struct ipw_softc *sc = device_get_softc(dev); 689 690 ipw_stop(sc); 691 692 return 0; 693 } 694 695 static int 696 ipw_suspend(device_t dev) 697 { 698 struct ipw_softc *sc = device_get_softc(dev); 699 700 ipw_stop(sc); 701 702 return 0; 703 } 704 705 static int 706 ipw_resume(device_t dev) 707 { 708 struct ipw_softc *sc = device_get_softc(dev); 709 struct ifnet *ifp = sc->sc_ic.ic_ifp; 710 711 mtx_lock(&sc->sc_mtx); 712 713 pci_write_config(dev, 0x41, 0, 1); 714 715 if (ifp->if_flags & IFF_UP) { 716 ifp->if_init(ifp->if_softc); 717 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 718 ifp->if_start(ifp); 719 } 720 721 mtx_unlock(&sc->sc_mtx); 722 723 return 0; 724 } 725 726 static int 727 ipw_media_change(struct ifnet *ifp) 728 { 729 struct ipw_softc *sc = ifp->if_softc; 730 int error; 731 732 mtx_lock(&sc->sc_mtx); 733 734 error = ieee80211_media_change(ifp); 735 if (error != ENETRESET) { 736 mtx_unlock(&sc->sc_mtx); 737 return error; 738 } 739 740 if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 741 ipw_init(sc); 742 743 mtx_unlock(&sc->sc_mtx); 744 745 return 0; 746 } 747 748 /* 749 * The firmware automatically adapts the transmit speed. We report its current 750 * value here. 751 */ 752 static void 753 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 754 { 755 #define N(a) (sizeof (a) / sizeof (a[0])) 756 struct ipw_softc *sc = ifp->if_softc; 757 struct ieee80211com *ic = &sc->sc_ic; 758 static const struct { 759 uint32_t val; 760 int rate; 761 } rates[] = { 762 { IPW_RATE_DS1, 2 }, 763 { IPW_RATE_DS2, 4 }, 764 { IPW_RATE_DS5, 11 }, 765 { IPW_RATE_DS11, 22 }, 766 }; 767 uint32_t val; 768 int rate, i; 769 770 imr->ifm_status = IFM_AVALID; 771 imr->ifm_active = IFM_IEEE80211; 772 if (ic->ic_state == IEEE80211_S_RUN) 773 imr->ifm_status |= IFM_ACTIVE; 774 775 /* read current transmission rate from adapter */ 776 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 777 778 /* convert ipw rate to 802.11 rate */ 779 for (i = 0; i < N(rates) && rates[i].val != val; i++); 780 rate = (i < N(rates)) ? rates[i].rate : 0; 781 782 imr->ifm_active |= IFM_IEEE80211_11B; 783 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 784 switch (ic->ic_opmode) { 785 case IEEE80211_M_STA: 786 break; 787 788 case IEEE80211_M_IBSS: 789 imr->ifm_active |= IFM_IEEE80211_IBSS; 790 break; 791 792 case IEEE80211_M_MONITOR: 793 imr->ifm_active |= IFM_IEEE80211_MONITOR; 794 break; 795 796 case IEEE80211_M_AHDEMO: 797 case IEEE80211_M_HOSTAP: 798 /* should not get there */ 799 break; 800 } 801 #undef N 802 } 803 804 static int 805 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 806 { 807 struct ifnet *ifp = ic->ic_ifp; 808 struct ipw_softc *sc = ifp->if_softc; 809 struct ieee80211_node *ni; 810 uint8_t macaddr[IEEE80211_ADDR_LEN]; 811 uint32_t len; 812 813 switch (nstate) { 814 case IEEE80211_S_RUN: 815 DELAY(200); /* firmware needs a short delay here */ 816 817 len = IEEE80211_ADDR_LEN; 818 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 819 820 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 821 if (ni == NULL) 822 break; 823 824 ieee80211_ref_node(ni); 825 ieee80211_sta_join(ic, ni); 826 ieee80211_node_authorize(ni); 827 828 if (ic->ic_opmode == IEEE80211_M_STA) 829 ieee80211_notify_node_join(ic, ni, 1); 830 break; 831 832 case IEEE80211_S_INIT: 833 case IEEE80211_S_SCAN: 834 case IEEE80211_S_AUTH: 835 case IEEE80211_S_ASSOC: 836 break; 837 } 838 839 ic->ic_state = nstate; 840 841 return 0; 842 } 843 844 /* 845 * Read 16 bits at address 'addr' from the serial EEPROM. 846 */ 847 static uint16_t 848 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 849 { 850 uint32_t tmp; 851 uint16_t val; 852 int n; 853 854 /* clock C once before the first command */ 855 IPW_EEPROM_CTL(sc, 0); 856 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 857 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 858 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 859 860 /* write start bit (1) */ 861 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 862 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 863 864 /* write READ opcode (10) */ 865 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 866 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 867 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 868 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 869 870 /* write address A7-A0 */ 871 for (n = 7; n >= 0; n--) { 872 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 873 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 875 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 876 } 877 878 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 879 880 /* read data Q15-Q0 */ 881 val = 0; 882 for (n = 15; n >= 0; n--) { 883 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 884 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 885 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 886 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 887 } 888 889 IPW_EEPROM_CTL(sc, 0); 890 891 /* clear Chip Select and clock C */ 892 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 893 IPW_EEPROM_CTL(sc, 0); 894 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 895 896 return le16toh(val); 897 } 898 899 static void 900 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 901 { 902 struct ipw_cmd *cmd; 903 904 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 905 906 cmd = mtod(sbuf->m, struct ipw_cmd *); 907 908 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 909 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 910 le32toh(cmd->status))); 911 912 wakeup(sc); 913 } 914 915 static void 916 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 917 { 918 struct ieee80211com *ic = &sc->sc_ic; 919 uint32_t state; 920 921 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 922 923 state = le32toh(*mtod(sbuf->m, uint32_t *)); 924 925 DPRINTFN(2, ("entering state %u\n", state)); 926 927 switch (state) { 928 case IPW_STATE_ASSOCIATED: 929 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 930 break; 931 932 case IPW_STATE_SCANNING: 933 /* don't leave run state on background scan */ 934 if (ic->ic_state != IEEE80211_S_RUN) 935 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 936 937 ic->ic_flags |= IEEE80211_F_SCAN; 938 break; 939 940 case IPW_STATE_SCAN_COMPLETE: 941 ieee80211_notify_scan_done(ic); 942 ic->ic_flags &= ~IEEE80211_F_SCAN; 943 break; 944 945 case IPW_STATE_ASSOCIATION_LOST: 946 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 947 break; 948 949 case IPW_STATE_RADIO_DISABLED: 950 ic->ic_ifp->if_flags &= ~IFF_UP; 951 ipw_stop(sc); 952 break; 953 } 954 } 955 956 /* 957 * XXX: Hack to set the current channel to the value advertised in beacons or 958 * probe responses. Only used during AP detection. 959 */ 960 static void 961 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 962 { 963 struct ieee80211_frame *wh; 964 uint8_t subtype; 965 uint8_t *frm, *efrm; 966 967 wh = mtod(m, struct ieee80211_frame *); 968 969 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 970 return; 971 972 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 973 974 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 975 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 976 return; 977 978 frm = (uint8_t *)(wh + 1); 979 efrm = mtod(m, uint8_t *) + m->m_len; 980 981 frm += 12; /* skip tstamp, bintval and capinfo fields */ 982 while (frm < efrm) { 983 if (*frm == IEEE80211_ELEMID_DSPARMS) 984 #if IEEE80211_CHAN_MAX < 255 985 if (frm[2] <= IEEE80211_CHAN_MAX) 986 #endif 987 ic->ic_curchan = &ic->ic_channels[frm[2]]; 988 989 frm += frm[1] + 2; 990 } 991 } 992 993 static void 994 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 995 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 996 { 997 struct ieee80211com *ic = &sc->sc_ic; 998 struct ifnet *ifp = ic->ic_ifp; 999 struct mbuf *mnew, *m; 1000 struct ieee80211_frame *wh; 1001 struct ieee80211_node *ni; 1002 bus_addr_t physaddr; 1003 int error; 1004 1005 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1006 status->rssi)); 1007 1008 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1009 le32toh(status->len) > MCLBYTES) 1010 return; 1011 1012 /* 1013 * Try to allocate a new mbuf for this ring element and load it before 1014 * processing the current mbuf. If the ring element cannot be loaded, 1015 * drop the received packet and reuse the old mbuf. In the unlikely 1016 * case that the old mbuf can't be reloaded either, explicitly panic. 1017 */ 1018 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1019 if (mnew == NULL) { 1020 ifp->if_ierrors++; 1021 return; 1022 } 1023 1024 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 1025 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 1026 1027 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, mtod(mnew, void *), 1028 MCLBYTES, ipw_dma_map_addr, &physaddr, 0); 1029 if (error != 0) { 1030 m_freem(mnew); 1031 1032 /* try to reload the old mbuf */ 1033 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 1034 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 1035 &physaddr, 0); 1036 if (error != 0) { 1037 /* very unlikely that it will fail... */ 1038 panic("%s: could not load old rx mbuf", 1039 device_get_name(sc->sc_dev)); 1040 } 1041 ifp->if_ierrors++; 1042 return; 1043 } 1044 1045 /* 1046 * New mbuf successfully loaded, update Rx ring and continue 1047 * processing. 1048 */ 1049 m = sbuf->m; 1050 sbuf->m = mnew; 1051 sbd->bd->physaddr = htole32(physaddr); 1052 1053 /* finalize mbuf */ 1054 m->m_pkthdr.rcvif = ifp; 1055 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1056 1057 if (bpf_peers_present(sc->sc_drvbpf)) { 1058 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1059 1060 tap->wr_flags = 0; 1061 tap->wr_antsignal = status->rssi; 1062 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1063 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1064 1065 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1066 } 1067 1068 if (ic->ic_state == IEEE80211_S_SCAN) 1069 ipw_fix_channel(ic, m); 1070 1071 wh = mtod(m, struct ieee80211_frame *); 1072 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1073 1074 /* send the frame to the 802.11 layer */ 1075 ieee80211_input(ic, m, ni, status->rssi, 0); 1076 1077 /* node is no longer needed */ 1078 ieee80211_free_node(ni); 1079 1080 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1081 } 1082 1083 static void 1084 ipw_rx_intr(struct ipw_softc *sc) 1085 { 1086 struct ipw_status *status; 1087 struct ipw_soft_bd *sbd; 1088 struct ipw_soft_buf *sbuf; 1089 uint32_t r, i; 1090 1091 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1092 return; 1093 1094 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1095 1096 bus_dmamap_sync(sc->status_dmat, sc->status_map, BUS_DMASYNC_POSTREAD); 1097 1098 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1099 status = &sc->status_list[i]; 1100 sbd = &sc->srbd_list[i]; 1101 sbuf = sbd->priv; 1102 1103 switch (le16toh(status->code) & 0xf) { 1104 case IPW_STATUS_CODE_COMMAND: 1105 ipw_command_intr(sc, sbuf); 1106 break; 1107 1108 case IPW_STATUS_CODE_NEWSTATE: 1109 ipw_newstate_intr(sc, sbuf); 1110 break; 1111 1112 case IPW_STATUS_CODE_DATA_802_3: 1113 case IPW_STATUS_CODE_DATA_802_11: 1114 ipw_data_intr(sc, status, sbd, sbuf); 1115 break; 1116 1117 case IPW_STATUS_CODE_NOTIFICATION: 1118 DPRINTFN(2, ("received notification\n")); 1119 break; 1120 1121 default: 1122 device_printf(sc->sc_dev, "unknown status code %u\n", 1123 le16toh(status->code)); 1124 } 1125 1126 /* firmware was killed, stop processing received frames */ 1127 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1128 return; 1129 1130 sbd->bd->flags = 0; 1131 } 1132 1133 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1134 1135 /* kick the firmware */ 1136 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1137 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1138 } 1139 1140 static void 1141 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1142 { 1143 struct ipw_soft_hdr *shdr; 1144 struct ipw_soft_buf *sbuf; 1145 1146 switch (sbd->type) { 1147 case IPW_SBD_TYPE_COMMAND: 1148 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, 1149 BUS_DMASYNC_POSTWRITE); 1150 bus_dmamap_unload(sc->cmd_dmat, sc->cmd_map); 1151 break; 1152 1153 case IPW_SBD_TYPE_HEADER: 1154 shdr = sbd->priv; 1155 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_POSTWRITE); 1156 bus_dmamap_unload(sc->hdr_dmat, shdr->map); 1157 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1158 break; 1159 1160 case IPW_SBD_TYPE_DATA: 1161 sbuf = sbd->priv; 1162 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, 1163 BUS_DMASYNC_POSTWRITE); 1164 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1165 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1166 1167 m_freem(sbuf->m); 1168 ieee80211_free_node(sbuf->ni); 1169 1170 sc->sc_tx_timer = 0; 1171 break; 1172 } 1173 1174 sbd->type = IPW_SBD_TYPE_NOASSOC; 1175 } 1176 1177 static void 1178 ipw_tx_intr(struct ipw_softc *sc) 1179 { 1180 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1181 struct ipw_soft_bd *sbd; 1182 uint32_t r, i; 1183 1184 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1185 return; 1186 1187 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1188 1189 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1190 sbd = &sc->stbd_list[i]; 1191 1192 if (sbd->type == IPW_SBD_TYPE_DATA) 1193 ifp->if_opackets++; 1194 1195 ipw_release_sbd(sc, sbd); 1196 sc->txfree++; 1197 } 1198 1199 /* remember what the firmware has processed */ 1200 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1201 1202 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1203 ipw_start(ifp); 1204 } 1205 1206 static void 1207 ipw_intr(void *arg) 1208 { 1209 struct ipw_softc *sc = arg; 1210 uint32_t r; 1211 1212 mtx_lock(&sc->sc_mtx); 1213 1214 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) { 1215 mtx_unlock(&sc->sc_mtx); 1216 return; 1217 } 1218 1219 /* disable interrupts */ 1220 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1221 1222 /* acknowledge all interrupts */ 1223 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1224 1225 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1226 device_printf(sc->sc_dev, "firmware error\n"); 1227 taskqueue_enqueue_fast(taskqueue_fast, &sc->sc_init_task); 1228 r = 0; /* don't process more interrupts */ 1229 } 1230 1231 if (r & IPW_INTR_FW_INIT_DONE) 1232 wakeup(sc); 1233 1234 if (r & IPW_INTR_RX_TRANSFER) 1235 ipw_rx_intr(sc); 1236 1237 if (r & IPW_INTR_TX_TRANSFER) 1238 ipw_tx_intr(sc); 1239 1240 /* re-enable interrupts */ 1241 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1242 1243 mtx_unlock(&sc->sc_mtx); 1244 } 1245 1246 static void 1247 ipw_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1248 { 1249 if (error != 0) 1250 return; 1251 1252 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1253 1254 *(bus_addr_t *)arg = segs[0].ds_addr; 1255 } 1256 1257 /* 1258 * Send a command to the firmware and wait for the acknowledgement. 1259 */ 1260 static int 1261 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1262 { 1263 struct ipw_soft_bd *sbd; 1264 bus_addr_t physaddr; 1265 int error; 1266 1267 sbd = &sc->stbd_list[sc->txcur]; 1268 1269 error = bus_dmamap_load(sc->cmd_dmat, sc->cmd_map, &sc->cmd, 1270 sizeof (struct ipw_cmd), ipw_dma_map_addr, &physaddr, 0); 1271 if (error != 0) { 1272 device_printf(sc->sc_dev, "could not map command DMA memory\n"); 1273 return error; 1274 } 1275 1276 sc->cmd.type = htole32(type); 1277 sc->cmd.subtype = 0; 1278 sc->cmd.len = htole32(len); 1279 sc->cmd.seq = 0; 1280 memcpy(sc->cmd.data, data, len); 1281 1282 sbd->type = IPW_SBD_TYPE_COMMAND; 1283 sbd->bd->physaddr = htole32(physaddr); 1284 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1285 sbd->bd->nfrag = 1; 1286 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1287 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1288 1289 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, BUS_DMASYNC_PREWRITE); 1290 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1291 1292 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1293 1294 /* kick firmware */ 1295 sc->txfree--; 1296 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1297 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1298 1299 /* wait at most one second for command to complete */ 1300 return msleep(sc, &sc->sc_mtx, 0, "ipwcmd", hz); 1301 } 1302 1303 static int 1304 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1305 { 1306 struct ipw_softc *sc = ifp->if_softc; 1307 struct ieee80211com *ic = &sc->sc_ic; 1308 struct ieee80211_frame *wh; 1309 struct ipw_soft_bd *sbd; 1310 struct ipw_soft_hdr *shdr; 1311 struct ipw_soft_buf *sbuf; 1312 struct ieee80211_key *k; 1313 struct mbuf *mnew; 1314 bus_dma_segment_t segs[IPW_MAX_NSEG]; 1315 bus_addr_t physaddr; 1316 int nsegs, error, i; 1317 1318 wh = mtod(m0, struct ieee80211_frame *); 1319 1320 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1321 k = ieee80211_crypto_encap(ic, ni, m0); 1322 if (k == NULL) { 1323 m_freem(m0); 1324 return ENOBUFS; 1325 } 1326 1327 /* packet header may have moved, reset our local pointer */ 1328 wh = mtod(m0, struct ieee80211_frame *); 1329 } 1330 1331 if (bpf_peers_present(sc->sc_drvbpf)) { 1332 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1333 1334 tap->wt_flags = 0; 1335 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1336 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1337 1338 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1339 } 1340 1341 shdr = SLIST_FIRST(&sc->free_shdr); 1342 sbuf = SLIST_FIRST(&sc->free_sbuf); 1343 KASSERT(shdr != NULL && sbuf != NULL, ("empty sw hdr/buf pool")); 1344 1345 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1346 shdr->hdr.subtype = 0; 1347 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1348 shdr->hdr.encrypt = 0; 1349 shdr->hdr.keyidx = 0; 1350 shdr->hdr.keysz = 0; 1351 shdr->hdr.fragmentsz = 0; 1352 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1353 if (ic->ic_opmode == IEEE80211_M_STA) 1354 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1355 else 1356 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1357 1358 /* trim IEEE802.11 header */ 1359 m_adj(m0, sizeof (struct ieee80211_frame)); 1360 1361 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, segs, 1362 &nsegs, 0); 1363 if (error != 0 && error != EFBIG) { 1364 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1365 error); 1366 m_freem(m0); 1367 return error; 1368 } 1369 if (error != 0) { 1370 mnew = m_defrag(m0, M_DONTWAIT); 1371 if (mnew == NULL) { 1372 device_printf(sc->sc_dev, 1373 "could not defragment mbuf\n"); 1374 m_freem(m0); 1375 return ENOBUFS; 1376 } 1377 m0 = mnew; 1378 1379 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, 1380 segs, &nsegs, 0); 1381 if (error != 0) { 1382 device_printf(sc->sc_dev, 1383 "could not map mbuf (error %d)\n", error); 1384 m_freem(m0); 1385 return error; 1386 } 1387 } 1388 1389 error = bus_dmamap_load(sc->hdr_dmat, shdr->map, &shdr->hdr, 1390 sizeof (struct ipw_hdr), ipw_dma_map_addr, &physaddr, 0); 1391 if (error != 0) { 1392 device_printf(sc->sc_dev, "could not map header DMA memory\n"); 1393 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1394 m_freem(m0); 1395 return error; 1396 } 1397 1398 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1399 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1400 1401 sbd = &sc->stbd_list[sc->txcur]; 1402 sbd->type = IPW_SBD_TYPE_HEADER; 1403 sbd->priv = shdr; 1404 sbd->bd->physaddr = htole32(physaddr); 1405 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1406 sbd->bd->nfrag = 1 + nsegs; 1407 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1408 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1409 1410 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, %6D, %6D)\n", 1411 shdr->hdr.type, shdr->hdr.subtype, shdr->hdr.encrypted, 1412 shdr->hdr.encrypt, shdr->hdr.src_addr, ":", shdr->hdr.dst_addr, 1413 ":")); 1414 1415 sc->txfree--; 1416 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1417 1418 sbuf->m = m0; 1419 sbuf->ni = ni; 1420 1421 for (i = 0; i < nsegs; i++) { 1422 sbd = &sc->stbd_list[sc->txcur]; 1423 1424 sbd->bd->physaddr = htole32(segs[i].ds_addr); 1425 sbd->bd->len = htole32(segs[i].ds_len); 1426 sbd->bd->nfrag = 0; 1427 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1428 if (i == nsegs - 1) { 1429 sbd->type = IPW_SBD_TYPE_DATA; 1430 sbd->priv = sbuf; 1431 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1432 } else { 1433 sbd->type = IPW_SBD_TYPE_NOASSOC; 1434 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1435 } 1436 1437 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, segs[i].ds_len)); 1438 1439 sc->txfree--; 1440 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1441 } 1442 1443 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_PREWRITE); 1444 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, BUS_DMASYNC_PREWRITE); 1445 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1446 1447 /* kick firmware */ 1448 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1449 1450 return 0; 1451 } 1452 1453 static void 1454 ipw_start(struct ifnet *ifp) 1455 { 1456 struct ipw_softc *sc = ifp->if_softc; 1457 struct ieee80211com *ic = &sc->sc_ic; 1458 struct mbuf *m0; 1459 struct ether_header *eh; 1460 struct ieee80211_node *ni; 1461 1462 mtx_lock(&sc->sc_mtx); 1463 1464 if (ic->ic_state != IEEE80211_S_RUN) { 1465 mtx_unlock(&sc->sc_mtx); 1466 return; 1467 } 1468 1469 for (;;) { 1470 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1471 if (m0 == NULL) 1472 break; 1473 1474 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1475 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1476 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1477 break; 1478 } 1479 1480 if (m0->m_len < sizeof (struct ether_header) && 1481 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1482 continue; 1483 1484 eh = mtod(m0, struct ether_header *); 1485 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1486 if (ni == NULL) { 1487 m_freem(m0); 1488 continue; 1489 } 1490 BPF_MTAP(ifp, m0); 1491 1492 m0 = ieee80211_encap(ic, m0, ni); 1493 if (m0 == NULL) { 1494 ieee80211_free_node(ni); 1495 continue; 1496 } 1497 1498 if (bpf_peers_present(ic->ic_rawbpf)) 1499 bpf_mtap(ic->ic_rawbpf, m0); 1500 1501 if (ipw_tx_start(ifp, m0, ni) != 0) { 1502 ieee80211_free_node(ni); 1503 ifp->if_oerrors++; 1504 break; 1505 } 1506 1507 /* start watchdog timer */ 1508 sc->sc_tx_timer = 5; 1509 ifp->if_timer = 1; 1510 } 1511 1512 mtx_unlock(&sc->sc_mtx); 1513 } 1514 1515 static void 1516 ipw_watchdog(struct ifnet *ifp) 1517 { 1518 struct ipw_softc *sc = ifp->if_softc; 1519 struct ieee80211com *ic = &sc->sc_ic; 1520 1521 mtx_lock(&sc->sc_mtx); 1522 1523 ifp->if_timer = 0; 1524 1525 if (sc->sc_tx_timer > 0) { 1526 if (--sc->sc_tx_timer == 0) { 1527 if_printf(ifp, "device timeout\n"); 1528 ifp->if_oerrors++; 1529 taskqueue_enqueue_fast(taskqueue_fast, 1530 &sc->sc_init_task); 1531 mtx_unlock(&sc->sc_mtx); 1532 return; 1533 } 1534 ifp->if_timer = 1; 1535 } 1536 1537 ieee80211_watchdog(ic); 1538 1539 mtx_unlock(&sc->sc_mtx); 1540 } 1541 1542 static int 1543 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1544 { 1545 struct ipw_softc *sc = ifp->if_softc; 1546 struct ieee80211com *ic = &sc->sc_ic; 1547 int error = 0; 1548 1549 mtx_lock(&sc->sc_mtx); 1550 1551 switch (cmd) { 1552 case SIOCSIFFLAGS: 1553 if (ifp->if_flags & IFF_UP) { 1554 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1555 ipw_init(sc); 1556 } else { 1557 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1558 ipw_stop(sc); 1559 } 1560 break; 1561 1562 default: 1563 error = ieee80211_ioctl(ic, cmd, data); 1564 } 1565 1566 if (error == ENETRESET) { 1567 if ((ifp->if_flags & IFF_UP) && 1568 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1569 ipw_init(sc); 1570 error = 0; 1571 } 1572 1573 mtx_unlock(&sc->sc_mtx); 1574 1575 return error; 1576 } 1577 1578 static void 1579 ipw_stop_master(struct ipw_softc *sc) 1580 { 1581 uint32_t tmp; 1582 int ntries; 1583 1584 /* disable interrupts */ 1585 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1586 1587 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1588 for (ntries = 0; ntries < 50; ntries++) { 1589 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1590 break; 1591 DELAY(10); 1592 } 1593 if (ntries == 50) 1594 device_printf(sc->sc_dev, "timeout waiting for master\n"); 1595 1596 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1597 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1598 1599 sc->flags &= ~IPW_FLAG_FW_INITED; 1600 } 1601 1602 static int 1603 ipw_reset(struct ipw_softc *sc) 1604 { 1605 uint32_t tmp; 1606 int ntries; 1607 1608 ipw_stop_master(sc); 1609 1610 /* move adapter to D0 state */ 1611 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1612 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1613 1614 /* wait for clock stabilization */ 1615 for (ntries = 0; ntries < 1000; ntries++) { 1616 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1617 break; 1618 DELAY(200); 1619 } 1620 if (ntries == 1000) 1621 return EIO; 1622 1623 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1624 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1625 1626 DELAY(10); 1627 1628 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1629 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1630 1631 return 0; 1632 } 1633 1634 /* 1635 * Upload the microcode to the device. 1636 */ 1637 static int 1638 ipw_load_ucode(struct ipw_softc *sc, const char *uc, int size) 1639 { 1640 int ntries; 1641 1642 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1643 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1644 1645 MEM_WRITE_2(sc, 0x220000, 0x0703); 1646 MEM_WRITE_2(sc, 0x220000, 0x0707); 1647 1648 MEM_WRITE_1(sc, 0x210014, 0x72); 1649 MEM_WRITE_1(sc, 0x210014, 0x72); 1650 1651 MEM_WRITE_1(sc, 0x210000, 0x40); 1652 MEM_WRITE_1(sc, 0x210000, 0x00); 1653 MEM_WRITE_1(sc, 0x210000, 0x40); 1654 1655 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1656 1657 MEM_WRITE_1(sc, 0x210000, 0x00); 1658 MEM_WRITE_1(sc, 0x210000, 0x00); 1659 MEM_WRITE_1(sc, 0x210000, 0x80); 1660 1661 MEM_WRITE_2(sc, 0x220000, 0x0703); 1662 MEM_WRITE_2(sc, 0x220000, 0x0707); 1663 1664 MEM_WRITE_1(sc, 0x210014, 0x72); 1665 MEM_WRITE_1(sc, 0x210014, 0x72); 1666 1667 MEM_WRITE_1(sc, 0x210000, 0x00); 1668 MEM_WRITE_1(sc, 0x210000, 0x80); 1669 1670 for (ntries = 0; ntries < 10; ntries++) { 1671 if (MEM_READ_1(sc, 0x210000) & 1) 1672 break; 1673 DELAY(10); 1674 } 1675 if (ntries == 10) { 1676 device_printf(sc->sc_dev, 1677 "timeout waiting for ucode to initialize\n"); 1678 return EIO; 1679 } 1680 1681 MEM_WRITE_4(sc, 0x3000e0, 0); 1682 1683 return 0; 1684 } 1685 1686 /* set of macros to handle unaligned little endian data in firmware image */ 1687 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1688 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1689 static int 1690 ipw_load_firmware(struct ipw_softc *sc, const char *fw, int size) 1691 { 1692 const uint8_t *p, *end; 1693 uint32_t tmp, dst; 1694 uint16_t len; 1695 int error; 1696 1697 p = fw; 1698 end = fw + size; 1699 while (p < end) { 1700 dst = GETLE32(p); p += 4; 1701 len = GETLE16(p); p += 2; 1702 1703 ipw_write_mem_1(sc, dst, p, len); 1704 p += len; 1705 } 1706 1707 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1708 IPW_IO_LED_OFF); 1709 1710 /* enable interrupts */ 1711 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1712 1713 /* kick the firmware */ 1714 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1715 1716 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1717 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1718 1719 /* wait at most one second for firmware initialization to complete */ 1720 if ((error = msleep(sc, &sc->sc_mtx, 0, "ipwinit", hz)) != 0) { 1721 device_printf(sc->sc_dev, "timeout waiting for firmware " 1722 "initialization to complete\n"); 1723 return error; 1724 } 1725 1726 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1727 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1728 IPW_IO_GPIO3_MASK); 1729 1730 return 0; 1731 } 1732 1733 static int 1734 ipw_config(struct ipw_softc *sc) 1735 { 1736 struct ieee80211com *ic = &sc->sc_ic; 1737 struct ifnet *ifp = ic->ic_ifp; 1738 struct ipw_security security; 1739 struct ieee80211_key *k; 1740 struct ipw_wep_key wepkey; 1741 struct ipw_scan_options options; 1742 struct ipw_configuration config; 1743 uint32_t data; 1744 int error, i; 1745 1746 switch (ic->ic_opmode) { 1747 case IEEE80211_M_STA: 1748 case IEEE80211_M_HOSTAP: 1749 data = htole32(IPW_MODE_BSS); 1750 break; 1751 case IEEE80211_M_IBSS: 1752 case IEEE80211_M_AHDEMO: 1753 data = htole32(IPW_MODE_IBSS); 1754 break; 1755 case IEEE80211_M_MONITOR: 1756 data = htole32(IPW_MODE_MONITOR); 1757 break; 1758 } 1759 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1760 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1761 if (error != 0) 1762 return error; 1763 1764 if (ic->ic_opmode == IEEE80211_M_IBSS || 1765 ic->ic_opmode == IEEE80211_M_MONITOR) { 1766 data = htole32(ieee80211_chan2ieee(ic, ic->ic_curchan)); 1767 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1768 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1769 if (error != 0) 1770 return error; 1771 } 1772 1773 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1774 DPRINTF(("Enabling adapter\n")); 1775 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1776 } 1777 1778 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 1779 DPRINTF(("Setting MAC address to %6D\n", ic->ic_myaddr, ":")); 1780 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1781 IEEE80211_ADDR_LEN); 1782 if (error != 0) 1783 return error; 1784 1785 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1786 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1787 if (ic->ic_opmode == IEEE80211_M_IBSS) 1788 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1789 if (ifp->if_flags & IFF_PROMISC) 1790 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1791 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1792 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1793 DPRINTF(("Setting configuration to 0x%x\n", le32toh(config.flags))); 1794 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1795 if (error != 0) 1796 return error; 1797 1798 data = htole32(0x3); /* 1, 2 */ 1799 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 1800 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1801 if (error != 0) 1802 return error; 1803 1804 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1805 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 1806 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1807 if (error != 0) 1808 return error; 1809 1810 data = htole32(IPW_POWER_MODE_CAM); 1811 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 1812 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1813 if (error != 0) 1814 return error; 1815 1816 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1817 data = htole32(32); /* default value */ 1818 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 1819 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1820 sizeof data); 1821 if (error != 0) 1822 return error; 1823 } 1824 1825 data = htole32(ic->ic_rtsthreshold); 1826 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 1827 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1828 if (error != 0) 1829 return error; 1830 1831 data = htole32(ic->ic_fragthreshold); 1832 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 1833 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1834 if (error != 0) 1835 return error; 1836 1837 #ifdef IPW_DEBUG 1838 if (ipw_debug > 0) { 1839 printf("Setting ESSID to "); 1840 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1841 printf("\n"); 1842 } 1843 #endif 1844 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1845 ic->ic_des_esslen); 1846 if (error != 0) 1847 return error; 1848 1849 /* no mandatory BSSID */ 1850 DPRINTF(("Setting mandatory BSSID to null\n")); 1851 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1852 if (error != 0) 1853 return error; 1854 1855 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1856 DPRINTF(("Setting desired BSSID to %6D\n", ic->ic_des_bssid, 1857 ":")); 1858 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1859 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1860 if (error != 0) 1861 return error; 1862 } 1863 1864 memset(&security, 0, sizeof security); 1865 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 1866 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1867 security.ciphers = htole32(IPW_CIPHER_NONE); 1868 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1869 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1870 sizeof security); 1871 if (error != 0) 1872 return error; 1873 1874 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1875 k = ic->ic_crypto.cs_nw_keys; 1876 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1877 if (k->wk_keylen == 0) 1878 continue; 1879 1880 wepkey.idx = i; 1881 wepkey.len = k->wk_keylen; 1882 memset(wepkey.key, 0, sizeof wepkey.key); 1883 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 1884 DPRINTF(("Setting wep key index %u len %u\n", 1885 wepkey.idx, wepkey.len)); 1886 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1887 sizeof wepkey); 1888 if (error != 0) 1889 return error; 1890 } 1891 1892 data = htole32(ic->ic_crypto.cs_def_txkey); 1893 DPRINTF(("Setting wep tx key index to %u\n", le32toh(data))); 1894 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1895 sizeof data); 1896 if (error != 0) 1897 return error; 1898 } 1899 1900 data = htole32((ic->ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 1901 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 1902 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1903 if (error != 0) 1904 return error; 1905 1906 #if 0 1907 struct ipw_wpa_ie ie; 1908 1909 memset(&ie, 0, sizeof ie); 1910 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 1911 DPRINTF(("Setting wpa ie\n")); 1912 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 1913 if (error != 0) 1914 return error; 1915 #endif 1916 1917 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1918 data = htole32(ic->ic_bintval); 1919 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 1920 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1921 sizeof data); 1922 if (error != 0) 1923 return error; 1924 } 1925 1926 options.flags = 0; 1927 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1928 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 1929 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1930 if (error != 0) 1931 return error; 1932 1933 /* finally, enable adapter (start scanning for an access point) */ 1934 DPRINTF(("Enabling adapter\n")); 1935 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1936 } 1937 1938 /* 1939 * Handler for sc_init_task. This is a simple wrapper around ipw_init(). 1940 * It is called on firmware panics or on watchdog timeouts. 1941 */ 1942 static void 1943 ipw_init_task(void *context, int pending) 1944 { 1945 ipw_init(context); 1946 } 1947 1948 static void 1949 ipw_init(void *priv) 1950 { 1951 struct ipw_softc *sc = priv; 1952 struct ieee80211com *ic = &sc->sc_ic; 1953 struct ifnet *ifp = ic->ic_ifp; 1954 struct firmware *fp; 1955 const struct ipw_firmware_hdr *hdr; 1956 const char *imagename, *fw; 1957 int owned; 1958 1959 /* 1960 * ipw_init() is exposed through ifp->if_init so it might be called 1961 * without the driver's lock held. Since msleep() doesn't like being 1962 * called on a recursed mutex, we acquire the driver's lock only if 1963 * we're not already holding it. 1964 */ 1965 if (!(owned = mtx_owned(&sc->sc_mtx))) 1966 mtx_lock(&sc->sc_mtx); 1967 1968 /* 1969 * Avoid re-entrant calls. We need to release the mutex in ipw_init() 1970 * when loading the firmware and we don't want to be called during this 1971 * operation. 1972 */ 1973 if (sc->flags & IPW_FLAG_INIT_LOCKED) { 1974 if (!owned) 1975 mtx_unlock(&sc->sc_mtx); 1976 return; 1977 } 1978 sc->flags |= IPW_FLAG_INIT_LOCKED; 1979 1980 ipw_stop(sc); 1981 1982 if (ipw_reset(sc) != 0) { 1983 device_printf(sc->sc_dev, "could not reset adapter\n"); 1984 goto fail1; 1985 } 1986 1987 switch (ic->ic_opmode) { 1988 case IEEE80211_M_STA: 1989 imagename = "ipw_bss"; 1990 break; 1991 case IEEE80211_M_IBSS: 1992 imagename = "ipw_ibss"; 1993 break; 1994 case IEEE80211_M_MONITOR: 1995 imagename = "ipw_monitor"; 1996 break; 1997 default: 1998 imagename = NULL; /* should not get there */ 1999 } 2000 2001 /* 2002 * Load firmware image using the firmware(9) subsystem. We need to 2003 * release the driver's lock first. 2004 */ 2005 mtx_unlock(&sc->sc_mtx); 2006 fp = firmware_get(imagename); 2007 mtx_lock(&sc->sc_mtx); 2008 2009 if (fp == NULL) { 2010 device_printf(sc->sc_dev, 2011 "could not load firmware image '%s'\n", imagename); 2012 goto fail1; 2013 } 2014 2015 if (fp->datasize < sizeof *hdr) { 2016 device_printf(sc->sc_dev, 2017 "firmware image too short %zu\n", fp->datasize); 2018 goto fail2; 2019 } 2020 2021 hdr = (const struct ipw_firmware_hdr *)fp->data; 2022 2023 if (fp->datasize < sizeof *hdr + le32toh(hdr->mainsz) + 2024 le32toh(hdr->ucodesz)) { 2025 device_printf(sc->sc_dev, 2026 "firmware image too short %zu\n", fp->datasize); 2027 goto fail2; 2028 } 2029 2030 fw = (const char *)fp->data + sizeof *hdr + le32toh(hdr->mainsz); 2031 if (ipw_load_ucode(sc, fw, le32toh(hdr->ucodesz)) != 0) { 2032 device_printf(sc->sc_dev, "could not load microcode\n"); 2033 goto fail2; 2034 } 2035 2036 ipw_stop_master(sc); 2037 2038 /* 2039 * Setup tx, rx and status rings. 2040 */ 2041 sc->txold = IPW_NTBD - 1; 2042 sc->txcur = 0; 2043 sc->txfree = IPW_NTBD - 2; 2044 sc->rxcur = IPW_NRBD - 1; 2045 2046 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_phys); 2047 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2048 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2049 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2050 2051 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_phys); 2052 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2053 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2054 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2055 2056 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_phys); 2057 2058 fw = (const char *)fp->data + sizeof *hdr; 2059 if (ipw_load_firmware(sc, fw, le32toh(hdr->mainsz)) != 0) { 2060 device_printf(sc->sc_dev, "could not load firmware\n"); 2061 goto fail2; 2062 } 2063 2064 firmware_put(fp, FIRMWARE_UNLOAD); 2065 sc->flags |= IPW_FLAG_FW_INITED; 2066 2067 /* retrieve information tables base addresses */ 2068 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2069 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2070 2071 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2072 2073 if (ipw_config(sc) != 0) { 2074 device_printf(sc->sc_dev, "device configuration failed\n"); 2075 goto fail1; 2076 } 2077 2078 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2079 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2080 2081 sc->flags &=~ IPW_FLAG_INIT_LOCKED; 2082 2083 if (!owned) 2084 mtx_unlock(&sc->sc_mtx); 2085 2086 return; 2087 2088 fail2: firmware_put(fp, FIRMWARE_UNLOAD); 2089 fail1: ifp->if_flags &= ~IFF_UP; 2090 ipw_stop(sc); 2091 sc->flags &=~ IPW_FLAG_INIT_LOCKED; 2092 if (!owned) 2093 mtx_unlock(&sc->sc_mtx); 2094 } 2095 2096 static void 2097 ipw_stop(void *priv) 2098 { 2099 struct ipw_softc *sc = priv; 2100 struct ieee80211com *ic = &sc->sc_ic; 2101 struct ifnet *ifp = ic->ic_ifp; 2102 int i; 2103 2104 mtx_lock(&sc->sc_mtx); 2105 2106 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2107 2108 ipw_stop_master(sc); 2109 2110 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2111 2112 /* 2113 * Release tx buffers. 2114 */ 2115 for (i = 0; i < IPW_NTBD; i++) 2116 ipw_release_sbd(sc, &sc->stbd_list[i]); 2117 2118 sc->sc_tx_timer = 0; 2119 ifp->if_timer = 0; 2120 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2121 2122 mtx_unlock(&sc->sc_mtx); 2123 } 2124 2125 static int 2126 ipw_sysctl_stats(SYSCTL_HANDLER_ARGS) 2127 { 2128 struct ipw_softc *sc = arg1; 2129 uint32_t i, size, buf[256]; 2130 2131 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 2132 memset(buf, 0, sizeof buf); 2133 return SYSCTL_OUT(req, buf, sizeof buf); 2134 } 2135 2136 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 2137 2138 size = min(CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA), 256); 2139 for (i = 1; i < size; i++) 2140 buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA)); 2141 2142 return SYSCTL_OUT(req, buf, sizeof buf); 2143 } 2144 2145 static int 2146 ipw_sysctl_radio(SYSCTL_HANDLER_ARGS) 2147 { 2148 struct ipw_softc *sc = arg1; 2149 int val; 2150 2151 val = !((sc->flags & IPW_FLAG_HAS_RADIO_SWITCH) && 2152 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED)); 2153 2154 return SYSCTL_OUT(req, &val, sizeof val); 2155 } 2156 2157 static uint32_t 2158 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 2159 { 2160 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 2161 } 2162 2163 static void 2164 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 2165 { 2166 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 2167 } 2168 2169 static int 2170 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 2171 { 2172 uint32_t addr, info; 2173 uint16_t count, size; 2174 uint32_t total; 2175 2176 /* addr[4] + count[2] + size[2] */ 2177 addr = MEM_READ_4(sc, sc->table2_base + off); 2178 info = MEM_READ_4(sc, sc->table2_base + off + 4); 2179 2180 count = info >> 16; 2181 size = info & 0xffff; 2182 total = count * size; 2183 2184 if (total > *len) { 2185 *len = total; 2186 return EINVAL; 2187 } 2188 2189 *len = total; 2190 ipw_read_mem_1(sc, addr, buf, total); 2191 2192 return 0; 2193 } 2194 2195 static void 2196 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2197 bus_size_t count) 2198 { 2199 for (; count > 0; offset++, datap++, count--) { 2200 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2201 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2202 } 2203 } 2204 2205 static void 2206 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, const uint8_t *datap, 2207 bus_size_t count) 2208 { 2209 for (; count > 0; offset++, datap++, count--) { 2210 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2211 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2212 } 2213 } 2214