1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2004, 2005 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /*- 34 * Intel(R) PRO/Wireless 2100 MiniPCI driver 35 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 36 */ 37 38 #include <sys/param.h> 39 #include <sys/sysctl.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/systm.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/bus.h> 48 #include <sys/endian.h> 49 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <machine/clock.h> 53 #include <sys/rman.h> 54 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcivar.h> 57 58 #include <net/bpf.h> 59 #include <net/if.h> 60 #include <net/if_arp.h> 61 #include <net/ethernet.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_types.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in_var.h> 69 #include <netinet/ip.h> 70 #include <netinet/if_ether.h> 71 72 #include <net80211/ieee80211_var.h> 73 #include <net80211/ieee80211_radiotap.h> 74 75 #include <dev/ipw/if_ipwreg.h> 76 #include <dev/ipw/if_ipwvar.h> 77 78 #ifdef IPW_DEBUG 79 #define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 80 #define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 81 int ipw_debug = 0; 82 SYSCTL_INT(_debug, OID_AUTO, ipw, CTLFLAG_RW, &ipw_debug, 0, "ipw debug level"); 83 #else 84 #define DPRINTF(x) 85 #define DPRINTFN(n, x) 86 #endif 87 88 MODULE_DEPEND(ipw, pci, 1, 1, 1); 89 MODULE_DEPEND(ipw, wlan, 1, 1, 1); 90 91 struct ipw_ident { 92 uint16_t vendor; 93 uint16_t device; 94 const char *name; 95 }; 96 97 static const struct ipw_ident ipw_ident_table[] = { 98 { 0x8086, 0x1043, "Intel(R) PRO/Wireless 2100 MiniPCI" }, 99 100 { 0, 0, NULL } 101 }; 102 103 static int ipw_dma_alloc(struct ipw_softc *); 104 static void ipw_release(struct ipw_softc *); 105 static int ipw_media_change(struct ifnet *); 106 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 107 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 108 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 109 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 110 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 111 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 112 struct ipw_soft_bd *, struct ipw_soft_buf *); 113 static void ipw_rx_intr(struct ipw_softc *); 114 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 115 static void ipw_tx_intr(struct ipw_softc *); 116 static void ipw_intr(void *); 117 static void ipw_dma_map_addr(void *, bus_dma_segment_t *, int, int); 118 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 119 static int ipw_tx_start(struct ifnet *, struct mbuf *, 120 struct ieee80211_node *); 121 static void ipw_start(struct ifnet *); 122 static void ipw_watchdog(struct ifnet *); 123 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 124 static void ipw_stop_master(struct ipw_softc *); 125 static int ipw_reset(struct ipw_softc *); 126 static int ipw_load_ucode(struct ipw_softc *, u_char *, int); 127 static int ipw_load_firmware(struct ipw_softc *, u_char *, int); 128 static int ipw_cache_firmware(struct ipw_softc *, void *); 129 static void ipw_free_firmware(struct ipw_softc *); 130 static int ipw_config(struct ipw_softc *); 131 static void ipw_init(void *); 132 static void ipw_stop(void *); 133 #ifdef IPW_DEBUG 134 static int ipw_sysctl_stats(SYSCTL_HANDLER_ARGS); 135 #endif 136 static int ipw_sysctl_radio(SYSCTL_HANDLER_ARGS); 137 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 138 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 139 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 140 uint32_t *); 141 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 142 bus_size_t); 143 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 144 bus_size_t); 145 146 static int ipw_probe(device_t); 147 static int ipw_attach(device_t); 148 static int ipw_detach(device_t); 149 static int ipw_shutdown(device_t); 150 static int ipw_suspend(device_t); 151 static int ipw_resume(device_t); 152 153 static device_method_t ipw_methods[] = { 154 /* Device interface */ 155 DEVMETHOD(device_probe, ipw_probe), 156 DEVMETHOD(device_attach, ipw_attach), 157 DEVMETHOD(device_detach, ipw_detach), 158 DEVMETHOD(device_shutdown, ipw_shutdown), 159 DEVMETHOD(device_suspend, ipw_suspend), 160 DEVMETHOD(device_resume, ipw_resume), 161 162 { 0, 0 } 163 }; 164 165 static driver_t ipw_driver = { 166 "ipw", 167 ipw_methods, 168 sizeof (struct ipw_softc) 169 }; 170 171 static devclass_t ipw_devclass; 172 173 DRIVER_MODULE(ipw, pci, ipw_driver, ipw_devclass, 0, 0); 174 175 /* 176 * Supported rates for 802.11b mode (in 500Kbps unit). 177 */ 178 static const struct ieee80211_rateset ipw_rateset_11b = 179 { 4, { 2, 4, 11, 22 } }; 180 181 static __inline uint8_t 182 MEM_READ_1(struct ipw_softc *sc, uint32_t addr) 183 { 184 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 185 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); 186 } 187 188 static __inline uint32_t 189 MEM_READ_4(struct ipw_softc *sc, uint32_t addr) 190 { 191 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); 192 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); 193 } 194 195 static int 196 ipw_probe(device_t dev) 197 { 198 const struct ipw_ident *ident; 199 200 for (ident = ipw_ident_table; ident->name != NULL; ident++) { 201 if (pci_get_vendor(dev) == ident->vendor && 202 pci_get_device(dev) == ident->device) { 203 device_set_desc(dev, ident->name); 204 return 0; 205 } 206 } 207 return ENXIO; 208 } 209 210 /* Base Address Register */ 211 #define IPW_PCI_BAR0 0x10 212 213 static int 214 ipw_attach(device_t dev) 215 { 216 struct ipw_softc *sc = device_get_softc(dev); 217 struct ifnet *ifp = &sc->sc_arp.ac_if; 218 struct ieee80211com *ic = &sc->sc_ic; 219 uint16_t val; 220 int error, i; 221 222 sc->sc_dev = dev; 223 224 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 225 MTX_DEF | MTX_RECURSE); 226 227 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 228 device_printf(dev, "chip is in D%d power mode " 229 "-- setting to D0\n", pci_get_powerstate(dev)); 230 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 231 } 232 233 pci_write_config(dev, 0x41, 0, 1); 234 235 /* enable bus-mastering */ 236 pci_enable_busmaster(dev); 237 238 sc->mem_rid = IPW_PCI_BAR0; 239 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 240 RF_ACTIVE); 241 if (sc->mem == NULL) { 242 device_printf(dev, "could not allocate memory resource\n"); 243 goto fail; 244 } 245 246 sc->sc_st = rman_get_bustag(sc->mem); 247 sc->sc_sh = rman_get_bushandle(sc->mem); 248 249 sc->irq_rid = 0; 250 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 251 RF_ACTIVE | RF_SHAREABLE); 252 if (sc->irq == NULL) { 253 device_printf(dev, "could not allocate interrupt resource\n"); 254 goto fail; 255 } 256 257 if (ipw_reset(sc) != 0) { 258 device_printf(dev, "could not reset adapter\n"); 259 goto fail; 260 } 261 262 if (ipw_dma_alloc(sc) != 0) { 263 device_printf(dev, "could not allocate DMA resources\n"); 264 goto fail; 265 } 266 267 ifp->if_softc = sc; 268 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 269 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 270 ifp->if_init = ipw_init; 271 ifp->if_ioctl = ipw_ioctl; 272 ifp->if_start = ipw_start; 273 ifp->if_watchdog = ipw_watchdog; 274 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 275 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 276 IFQ_SET_READY(&ifp->if_snd); 277 278 ic->ic_ifp = ifp; 279 ic->ic_phytype = IEEE80211_T_DS; 280 ic->ic_opmode = IEEE80211_M_STA; 281 ic->ic_state = IEEE80211_S_INIT; 282 283 /* set device capabilities */ 284 ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT | 285 IEEE80211_C_PMGT | IEEE80211_C_IBSS | IEEE80211_C_MONITOR | 286 IEEE80211_C_WPA; 287 288 /* read MAC address from EEPROM */ 289 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 290 ic->ic_myaddr[0] = val >> 8; 291 ic->ic_myaddr[1] = val & 0xff; 292 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 293 ic->ic_myaddr[2] = val >> 8; 294 ic->ic_myaddr[3] = val & 0xff; 295 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 296 ic->ic_myaddr[4] = val >> 8; 297 ic->ic_myaddr[5] = val & 0xff; 298 299 /* set supported .11b rates */ 300 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; 301 302 /* set supported .11b channels (read from EEPROM) */ 303 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 304 val = 0x7ff; /* default to channels 1-11 */ 305 val <<= 1; 306 for (i = 1; i < 16; i++) { 307 if (val & (1 << i)) { 308 ic->ic_channels[i].ic_freq = 309 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); 310 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; 311 } 312 } 313 314 /* check support for radio transmitter switch in EEPROM */ 315 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 316 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 317 318 ieee80211_ifattach(ic); 319 /* override state transition machine */ 320 sc->sc_newstate = ic->ic_newstate; 321 ic->ic_newstate = ipw_newstate; 322 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 323 324 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 325 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 326 327 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 328 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 329 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 330 331 sc->sc_txtap_len = sizeof sc->sc_txtapu; 332 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 333 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 334 335 /* 336 * Add a few sysctl knobs. 337 */ 338 sc->dwelltime = 100; 339 340 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 341 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "radio", 342 CTLTYPE_INT | CTLFLAG_RD, sc, 0, ipw_sysctl_radio, "I", 343 "radio transmitter switch state (0=off, 1=on)"); 344 345 #ifdef IPW_DEBUG 346 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 347 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats", 348 CTLTYPE_OPAQUE | CTLFLAG_RD, sc, 0, ipw_sysctl_stats, "S", 349 "statistics"); 350 #endif 351 352 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 353 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", 354 CTLFLAG_RW, &sc->dwelltime, 0, 355 "channel dwell time (ms) for AP/station scanning"); 356 357 /* 358 * Hook our interrupt after all initialization is complete. 359 */ 360 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 361 ipw_intr, sc, &sc->sc_ih); 362 if (error != 0) { 363 device_printf(dev, "could not set up interrupt\n"); 364 goto fail; 365 } 366 367 if (bootverbose) 368 ieee80211_announce(ic); 369 370 return 0; 371 372 fail: ipw_detach(dev); 373 return ENXIO; 374 } 375 376 static int 377 ipw_detach(device_t dev) 378 { 379 struct ipw_softc *sc = device_get_softc(dev); 380 struct ieee80211com *ic = &sc->sc_ic; 381 struct ifnet *ifp = ic->ic_ifp; 382 383 IPW_LOCK(sc); 384 385 ipw_stop(sc); 386 ipw_free_firmware(sc); 387 388 IPW_UNLOCK(sc); 389 390 bpfdetach(ifp); 391 ieee80211_ifdetach(ic); 392 393 ipw_release(sc); 394 395 if (sc->irq != NULL) { 396 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 397 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 398 } 399 400 if (sc->mem != NULL) 401 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 402 403 mtx_destroy(&sc->sc_mtx); 404 405 return 0; 406 } 407 408 static int 409 ipw_dma_alloc(struct ipw_softc *sc) 410 { 411 struct ipw_soft_bd *sbd; 412 struct ipw_soft_hdr *shdr; 413 struct ipw_soft_buf *sbuf; 414 bus_addr_t physaddr; 415 int error, i; 416 417 /* 418 * Allocate and map tx ring. 419 */ 420 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 421 BUS_SPACE_MAXADDR, NULL, NULL, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, NULL, 422 NULL, &sc->tbd_dmat); 423 if (error != 0) { 424 device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); 425 goto fail; 426 } 427 428 error = bus_dmamem_alloc(sc->tbd_dmat, (void **)&sc->tbd_list, 429 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tbd_map); 430 if (error != 0) { 431 device_printf(sc->sc_dev, 432 "could not allocate tx ring DMA memory\n"); 433 goto fail; 434 } 435 436 error = bus_dmamap_load(sc->tbd_dmat, sc->tbd_map, sc->tbd_list, 437 IPW_TBD_SZ, ipw_dma_map_addr, &sc->tbd_phys, 0); 438 if (error != 0) { 439 device_printf(sc->sc_dev, "could not map tx ring DMA memory\n"); 440 goto fail; 441 } 442 443 /* 444 * Allocate and map rx ring. 445 */ 446 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 447 BUS_SPACE_MAXADDR, NULL, NULL, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, NULL, 448 NULL, &sc->rbd_dmat); 449 if (error != 0) { 450 device_printf(sc->sc_dev, "could not create rx ring DMA tag\n"); 451 goto fail; 452 } 453 454 error = bus_dmamem_alloc(sc->rbd_dmat, (void **)&sc->rbd_list, 455 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rbd_map); 456 if (error != 0) { 457 device_printf(sc->sc_dev, 458 "could not allocate rx ring DMA memory\n"); 459 goto fail; 460 } 461 462 error = bus_dmamap_load(sc->rbd_dmat, sc->rbd_map, sc->rbd_list, 463 IPW_RBD_SZ, ipw_dma_map_addr, &sc->rbd_phys, 0); 464 if (error != 0) { 465 device_printf(sc->sc_dev, "could not map rx ring DMA memory\n"); 466 goto fail; 467 } 468 469 /* 470 * Allocate and map status ring. 471 */ 472 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 473 BUS_SPACE_MAXADDR, NULL, NULL, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 0, 474 NULL, NULL, &sc->status_dmat); 475 if (error != 0) { 476 device_printf(sc->sc_dev, 477 "could not create status ring DMA tag\n"); 478 goto fail; 479 } 480 481 error = bus_dmamem_alloc(sc->status_dmat, (void **)&sc->status_list, 482 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->status_map); 483 if (error != 0) { 484 device_printf(sc->sc_dev, 485 "could not allocate status ring DMA memory\n"); 486 goto fail; 487 } 488 489 error = bus_dmamap_load(sc->status_dmat, sc->status_map, 490 sc->status_list, IPW_STATUS_SZ, ipw_dma_map_addr, &sc->status_phys, 491 0); 492 if (error != 0) { 493 device_printf(sc->sc_dev, 494 "could not map status ring DMA memory\n"); 495 goto fail; 496 } 497 498 /* 499 * Allocate command DMA map. 500 */ 501 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 502 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_cmd), 1, 503 sizeof (struct ipw_cmd), 0, NULL, NULL, &sc->cmd_dmat); 504 if (error != 0) { 505 device_printf(sc->sc_dev, "could not create command DMA tag\n"); 506 goto fail; 507 } 508 509 error = bus_dmamap_create(sc->cmd_dmat, 0, &sc->cmd_map); 510 if (error != 0) { 511 device_printf(sc->sc_dev, 512 "could not create command DMA map\n"); 513 goto fail; 514 } 515 516 /* 517 * Allocate headers DMA maps. 518 */ 519 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 520 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_hdr), 1, 521 sizeof (struct ipw_hdr), 0, NULL, NULL, &sc->hdr_dmat); 522 if (error != 0) { 523 device_printf(sc->sc_dev, "could not create header DMA tag\n"); 524 goto fail; 525 } 526 527 SLIST_INIT(&sc->free_shdr); 528 for (i = 0; i < IPW_NDATA; i++) { 529 shdr = &sc->shdr_list[i]; 530 error = bus_dmamap_create(sc->hdr_dmat, 0, &shdr->map); 531 if (error != 0) { 532 device_printf(sc->sc_dev, 533 "could not create header DMA map\n"); 534 goto fail; 535 } 536 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 537 } 538 539 /* 540 * Allocate tx buffers DMA maps. 541 */ 542 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 543 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_MAX_NSEG, MCLBYTES, 0, 544 NULL, NULL, &sc->txbuf_dmat); 545 if (error != 0) { 546 device_printf(sc->sc_dev, "could not create tx DMA tag\n"); 547 goto fail; 548 } 549 550 SLIST_INIT(&sc->free_sbuf); 551 for (i = 0; i < IPW_NDATA; i++) { 552 sbuf = &sc->tx_sbuf_list[i]; 553 error = bus_dmamap_create(sc->txbuf_dmat, 0, &sbuf->map); 554 if (error != 0) { 555 device_printf(sc->sc_dev, 556 "could not create tx DMA map\n"); 557 goto fail; 558 } 559 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 560 } 561 562 /* 563 * Initialize tx ring. 564 */ 565 for (i = 0; i < IPW_NTBD; i++) { 566 sbd = &sc->stbd_list[i]; 567 sbd->bd = &sc->tbd_list[i]; 568 sbd->type = IPW_SBD_TYPE_NOASSOC; 569 } 570 571 /* 572 * Pre-allocate rx buffers and DMA maps. 573 */ 574 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 575 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_NRBD, MCLBYTES, 0, 576 NULL, NULL, &sc->rxbuf_dmat); 577 if (error != 0) { 578 device_printf(sc->sc_dev, "could not create rx DMA tag\n"); 579 goto fail; 580 } 581 582 for (i = 0; i < IPW_NRBD; i++) { 583 sbd = &sc->srbd_list[i]; 584 sbuf = &sc->rx_sbuf_list[i]; 585 sbd->bd = &sc->rbd_list[i]; 586 587 sbuf->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 588 if (sbuf->m == NULL) { 589 device_printf(sc->sc_dev, 590 "could not allocate rx mbuf\n"); 591 error = ENOMEM; 592 goto fail; 593 } 594 595 error = bus_dmamap_create(sc->rxbuf_dmat, 0, &sbuf->map); 596 if (error != 0) { 597 device_printf(sc->sc_dev, 598 "could not create rx DMA map\n"); 599 goto fail; 600 } 601 602 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 603 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 604 &physaddr, 0); 605 if (error != 0) { 606 device_printf(sc->sc_dev, 607 "could not map rx DMA memory\n"); 608 goto fail; 609 } 610 611 sbd->type = IPW_SBD_TYPE_DATA; 612 sbd->priv = sbuf; 613 sbd->bd->physaddr = htole32(physaddr); 614 sbd->bd->len = htole32(MCLBYTES); 615 } 616 617 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 618 619 return 0; 620 621 fail: ipw_release(sc); 622 return error; 623 } 624 625 static void 626 ipw_release(struct ipw_softc *sc) 627 { 628 struct ipw_soft_buf *sbuf; 629 int i; 630 631 if (sc->tbd_dmat != NULL) { 632 if (sc->stbd_list != NULL) { 633 bus_dmamap_unload(sc->tbd_dmat, sc->tbd_map); 634 bus_dmamem_free(sc->tbd_dmat, sc->tbd_list, 635 sc->tbd_map); 636 } 637 bus_dma_tag_destroy(sc->tbd_dmat); 638 } 639 640 if (sc->rbd_dmat != NULL) { 641 if (sc->rbd_list != NULL) { 642 bus_dmamap_unload(sc->rbd_dmat, sc->rbd_map); 643 bus_dmamem_free(sc->rbd_dmat, sc->rbd_list, 644 sc->rbd_map); 645 } 646 bus_dma_tag_destroy(sc->rbd_dmat); 647 } 648 649 if (sc->status_dmat != NULL) { 650 if (sc->status_list != NULL) { 651 bus_dmamap_unload(sc->status_dmat, sc->status_map); 652 bus_dmamem_free(sc->status_dmat, sc->status_list, 653 sc->status_map); 654 } 655 bus_dma_tag_destroy(sc->status_dmat); 656 } 657 658 for (i = 0; i < IPW_NTBD; i++) 659 ipw_release_sbd(sc, &sc->stbd_list[i]); 660 661 if (sc->cmd_dmat != NULL) { 662 bus_dmamap_destroy(sc->cmd_dmat, sc->cmd_map); 663 bus_dma_tag_destroy(sc->cmd_dmat); 664 } 665 666 if (sc->hdr_dmat != NULL) { 667 for (i = 0; i < IPW_NDATA; i++) 668 bus_dmamap_destroy(sc->hdr_dmat, sc->shdr_list[i].map); 669 bus_dma_tag_destroy(sc->hdr_dmat); 670 } 671 672 if (sc->txbuf_dmat != NULL) { 673 for (i = 0; i < IPW_NDATA; i++) { 674 bus_dmamap_destroy(sc->txbuf_dmat, 675 sc->tx_sbuf_list[i].map); 676 } 677 bus_dma_tag_destroy(sc->txbuf_dmat); 678 } 679 680 if (sc->rxbuf_dmat != NULL) { 681 for (i = 0; i < IPW_NRBD; i++) { 682 sbuf = &sc->rx_sbuf_list[i]; 683 if (sbuf->m != NULL) { 684 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, 685 BUS_DMASYNC_POSTREAD); 686 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 687 m_freem(sbuf->m); 688 } 689 bus_dmamap_destroy(sc->rxbuf_dmat, sbuf->map); 690 } 691 bus_dma_tag_destroy(sc->rxbuf_dmat); 692 } 693 } 694 695 static int 696 ipw_shutdown(device_t dev) 697 { 698 struct ipw_softc *sc = device_get_softc(dev); 699 700 ipw_stop(sc); 701 702 return 0; 703 } 704 705 static int 706 ipw_suspend(device_t dev) 707 { 708 struct ipw_softc *sc = device_get_softc(dev); 709 710 ipw_stop(sc); 711 712 return 0; 713 } 714 715 static int 716 ipw_resume(device_t dev) 717 { 718 struct ipw_softc *sc = device_get_softc(dev); 719 struct ifnet *ifp = sc->sc_ic.ic_ifp; 720 721 IPW_LOCK(sc); 722 723 pci_write_config(dev, 0x41, 0, 1); 724 725 if (ifp->if_flags & IFF_UP) { 726 ifp->if_init(ifp->if_softc); 727 if (ifp->if_flags & IFF_RUNNING) 728 ifp->if_start(ifp); 729 } 730 731 IPW_UNLOCK(sc); 732 733 return 0; 734 } 735 736 static int 737 ipw_media_change(struct ifnet *ifp) 738 { 739 struct ipw_softc *sc = ifp->if_softc; 740 int error; 741 742 IPW_LOCK(sc); 743 744 error = ieee80211_media_change(ifp); 745 if (error != ENETRESET) { 746 IPW_UNLOCK(sc); 747 return error; 748 } 749 750 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 751 ipw_init(sc); 752 753 IPW_UNLOCK(sc); 754 755 return 0; 756 } 757 758 /* 759 * The firmware automaticly adapt the transmit speed. We report the current 760 * transmit speed here. 761 */ 762 static void 763 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 764 { 765 #define N(a) (sizeof (a) / sizeof (a[0])) 766 struct ipw_softc *sc = ifp->if_softc; 767 struct ieee80211com *ic = &sc->sc_ic; 768 static const struct { 769 uint32_t val; 770 int rate; 771 } rates[] = { 772 { IPW_RATE_DS1, 2 }, 773 { IPW_RATE_DS2, 4 }, 774 { IPW_RATE_DS5, 11 }, 775 { IPW_RATE_DS11, 22 }, 776 }; 777 uint32_t val; 778 int rate, i; 779 780 imr->ifm_status = IFM_AVALID; 781 imr->ifm_active = IFM_IEEE80211; 782 if (ic->ic_state == IEEE80211_S_RUN) 783 imr->ifm_status |= IFM_ACTIVE; 784 785 /* read current transmission rate from adapter */ 786 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 787 788 /* convert ipw rate to 802.11 rate */ 789 for (i = 0; i < N(rates) && rates[i].val != val; i++); 790 rate = (i < N(rates)) ? rates[i].rate : 0; 791 792 imr->ifm_active |= IFM_IEEE80211_11B; 793 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 794 switch (ic->ic_opmode) { 795 case IEEE80211_M_STA: 796 break; 797 798 case IEEE80211_M_IBSS: 799 imr->ifm_active |= IFM_IEEE80211_IBSS; 800 break; 801 802 case IEEE80211_M_MONITOR: 803 imr->ifm_active |= IFM_IEEE80211_MONITOR; 804 break; 805 806 case IEEE80211_M_AHDEMO: 807 case IEEE80211_M_HOSTAP: 808 /* should not get there */ 809 break; 810 } 811 #undef N 812 } 813 814 static int 815 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 816 { 817 struct ifnet *ifp = ic->ic_ifp; 818 struct ipw_softc *sc = ifp->if_softc; 819 struct ieee80211_node *ni; 820 uint8_t macaddr[IEEE80211_ADDR_LEN]; 821 uint32_t len; 822 823 switch (nstate) { 824 case IEEE80211_S_RUN: 825 DELAY(200); /* firmware needs a short delay here */ 826 827 len = IEEE80211_ADDR_LEN; 828 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 829 830 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 831 if (ni == NULL) 832 break; 833 834 ieee80211_ref_node(ni); 835 ieee80211_sta_join(ic, ni); 836 ieee80211_node_authorize(ic, ni); 837 838 if (ic->ic_opmode == IEEE80211_M_STA) 839 ieee80211_notify_node_join(ic, ni, 1); 840 break; 841 842 case IEEE80211_S_INIT: 843 case IEEE80211_S_SCAN: 844 case IEEE80211_S_AUTH: 845 case IEEE80211_S_ASSOC: 846 break; 847 } 848 849 ic->ic_state = nstate; 850 return 0; 851 } 852 853 /* 854 * Read 16 bits at address 'addr' from the serial EEPROM. 855 */ 856 static uint16_t 857 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 858 { 859 uint32_t tmp; 860 uint16_t val; 861 int n; 862 863 /* clock C once before the first command */ 864 IPW_EEPROM_CTL(sc, 0); 865 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 866 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 867 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 868 869 /* write start bit (1) */ 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 871 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 872 873 /* write READ opcode (10) */ 874 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 875 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 876 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 877 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 878 879 /* write address A7-A0 */ 880 for (n = 7; n >= 0; n--) { 881 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 882 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 883 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 884 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 885 } 886 887 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 888 889 /* read data Q15-Q0 */ 890 val = 0; 891 for (n = 15; n >= 0; n--) { 892 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 893 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 894 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 895 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 896 } 897 898 IPW_EEPROM_CTL(sc, 0); 899 900 /* clear Chip Select and clock C */ 901 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 902 IPW_EEPROM_CTL(sc, 0); 903 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 904 905 return le16toh(val); 906 } 907 908 static void 909 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 910 { 911 struct ipw_cmd *cmd; 912 913 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 914 915 cmd = mtod(sbuf->m, struct ipw_cmd *); 916 917 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 918 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 919 le32toh(cmd->status))); 920 921 wakeup(sc); 922 } 923 924 static void 925 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 926 { 927 struct ieee80211com *ic = &sc->sc_ic; 928 uint32_t state; 929 930 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 931 932 state = le32toh(*mtod(sbuf->m, uint32_t *)); 933 934 DPRINTFN(2, ("entering state %u\n", state)); 935 936 switch (state) { 937 case IPW_STATE_ASSOCIATED: 938 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 939 break; 940 941 case IPW_STATE_SCANNING: 942 /* don't leave run state on background scan */ 943 if (ic->ic_state != IEEE80211_S_RUN) 944 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 945 946 ic->ic_flags |= IEEE80211_F_SCAN; 947 break; 948 949 case IPW_STATE_SCAN_COMPLETE: 950 ieee80211_notify_scan_done(ic); 951 ic->ic_flags &= ~IEEE80211_F_SCAN; 952 break; 953 954 case IPW_STATE_ASSOCIATION_LOST: 955 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 956 break; 957 958 case IPW_STATE_RADIO_DISABLED: 959 ic->ic_ifp->if_flags &= ~IFF_UP; 960 ipw_stop(sc); 961 break; 962 } 963 } 964 965 /* 966 * XXX: Hack to set the current channel to the value advertised in beacons or 967 * probe responses. Only used during AP detection. 968 */ 969 static void 970 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 971 { 972 struct ieee80211_frame *wh; 973 uint8_t subtype; 974 uint8_t *frm, *efrm; 975 976 wh = mtod(m, struct ieee80211_frame *); 977 978 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 979 return; 980 981 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 982 983 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 984 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 985 return; 986 987 frm = (uint8_t *)(wh + 1); 988 efrm = mtod(m, uint8_t *) + m->m_len; 989 990 frm += 12; /* skip tstamp, bintval and capinfo fields */ 991 while (frm < efrm) { 992 if (*frm == IEEE80211_ELEMID_DSPARMS) 993 #if IEEE80211_CHAN_MAX < 255 994 if (frm[2] <= IEEE80211_CHAN_MAX) 995 #endif 996 ic->ic_bss->ni_chan = &ic->ic_channels[frm[2]]; 997 998 frm += frm[1] + 2; 999 } 1000 } 1001 1002 static void 1003 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1004 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1005 { 1006 struct ieee80211com *ic = &sc->sc_ic; 1007 struct ifnet *ifp = ic->ic_ifp; 1008 struct mbuf *m; 1009 struct ieee80211_frame *wh; 1010 struct ieee80211_node *ni; 1011 bus_addr_t physaddr; 1012 int error; 1013 1014 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 1015 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 1016 1017 /* finalize mbuf */ 1018 m = sbuf->m; 1019 m->m_pkthdr.rcvif = ifp; 1020 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1021 1022 if (sc->sc_drvbpf != NULL) { 1023 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1024 1025 tap->wr_flags = 0; 1026 tap->wr_antsignal = status->rssi; 1027 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1028 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1029 1030 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1031 } 1032 1033 if (ic->ic_state == IEEE80211_S_SCAN) 1034 ipw_fix_channel(ic, m); 1035 1036 wh = mtod(m, struct ieee80211_frame *); 1037 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1038 1039 /* send the frame to the 802.11 layer */ 1040 ieee80211_input(ic, m, ni, status->rssi, 0); 1041 1042 /* node is no longer needed */ 1043 ieee80211_free_node(ni); 1044 1045 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1046 if (m == NULL) { 1047 device_printf(sc->sc_dev, "could not allocate rx mbuf\n"); 1048 sbuf->m = NULL; 1049 return; 1050 } 1051 1052 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, mtod(m, void *), 1053 MCLBYTES, ipw_dma_map_addr, &physaddr, 0); 1054 if (error != 0) { 1055 device_printf(sc->sc_dev, "could not map rx DMA memory\n"); 1056 m_freem(m); 1057 sbuf->m = NULL; 1058 return; 1059 } 1060 1061 sbuf->m = m; 1062 sbd->bd->physaddr = htole32(physaddr); 1063 1064 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1065 status->rssi)); 1066 1067 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1068 } 1069 1070 static void 1071 ipw_rx_intr(struct ipw_softc *sc) 1072 { 1073 struct ipw_status *status; 1074 struct ipw_soft_bd *sbd; 1075 struct ipw_soft_buf *sbuf; 1076 uint32_t r, i; 1077 1078 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1079 return; 1080 1081 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1082 1083 bus_dmamap_sync(sc->status_dmat, sc->status_map, BUS_DMASYNC_POSTREAD); 1084 1085 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1086 status = &sc->status_list[i]; 1087 sbd = &sc->srbd_list[i]; 1088 sbuf = sbd->priv; 1089 1090 switch (le16toh(status->code) & 0xf) { 1091 case IPW_STATUS_CODE_COMMAND: 1092 ipw_command_intr(sc, sbuf); 1093 break; 1094 1095 case IPW_STATUS_CODE_NEWSTATE: 1096 ipw_newstate_intr(sc, sbuf); 1097 break; 1098 1099 case IPW_STATUS_CODE_DATA_802_3: 1100 case IPW_STATUS_CODE_DATA_802_11: 1101 ipw_data_intr(sc, status, sbd, sbuf); 1102 break; 1103 1104 case IPW_STATUS_CODE_NOTIFICATION: 1105 DPRINTFN(2, ("received notification\n")); 1106 break; 1107 1108 default: 1109 device_printf(sc->sc_dev, "unknown status code %u\n", 1110 le16toh(status->code)); 1111 } 1112 1113 /* firmware was killed, stop processing received frames */ 1114 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1115 return; 1116 1117 sbd->bd->flags = 0; 1118 } 1119 1120 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1121 1122 /* kick the firmware */ 1123 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1124 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1125 } 1126 1127 static void 1128 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1129 { 1130 struct ipw_soft_hdr *shdr; 1131 struct ipw_soft_buf *sbuf; 1132 1133 switch (sbd->type) { 1134 case IPW_SBD_TYPE_COMMAND: 1135 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, 1136 BUS_DMASYNC_POSTWRITE); 1137 bus_dmamap_unload(sc->cmd_dmat, sc->cmd_map); 1138 break; 1139 1140 case IPW_SBD_TYPE_HEADER: 1141 shdr = sbd->priv; 1142 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_POSTWRITE); 1143 bus_dmamap_unload(sc->hdr_dmat, shdr->map); 1144 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1145 break; 1146 1147 case IPW_SBD_TYPE_DATA: 1148 sbuf = sbd->priv; 1149 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, 1150 BUS_DMASYNC_POSTWRITE); 1151 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1152 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1153 1154 m_freem(sbuf->m); 1155 ieee80211_free_node(sbuf->ni); 1156 1157 sc->sc_tx_timer = 0; 1158 break; 1159 } 1160 1161 sbd->type = IPW_SBD_TYPE_NOASSOC; 1162 } 1163 1164 static void 1165 ipw_tx_intr(struct ipw_softc *sc) 1166 { 1167 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1168 struct ipw_soft_bd *sbd; 1169 uint32_t r, i; 1170 1171 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1172 return; 1173 1174 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1175 1176 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1177 sbd = &sc->stbd_list[i]; 1178 1179 if (sbd->type == IPW_SBD_TYPE_DATA) 1180 ifp->if_opackets++; 1181 1182 ipw_release_sbd(sc, sbd); 1183 sc->txfree++; 1184 } 1185 1186 /* remember what the firmware has processed */ 1187 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1188 1189 ifp->if_flags &= ~IFF_OACTIVE; 1190 ipw_start(ifp); 1191 } 1192 1193 static void 1194 ipw_intr(void *arg) 1195 { 1196 struct ipw_softc *sc = arg; 1197 uint32_t r; 1198 1199 IPW_LOCK(sc); 1200 1201 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) { 1202 IPW_UNLOCK(sc); 1203 return; 1204 } 1205 1206 /* disable interrupts */ 1207 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1208 1209 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1210 device_printf(sc->sc_dev, "fatal error\n"); 1211 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; 1212 ipw_stop(sc); 1213 } 1214 1215 if (r & IPW_INTR_FW_INIT_DONE) { 1216 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) 1217 wakeup(sc); 1218 } 1219 1220 if (r & IPW_INTR_RX_TRANSFER) 1221 ipw_rx_intr(sc); 1222 1223 if (r & IPW_INTR_TX_TRANSFER) 1224 ipw_tx_intr(sc); 1225 1226 /* acknowledge all interrupts */ 1227 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1228 1229 /* re-enable interrupts */ 1230 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1231 1232 IPW_UNLOCK(sc); 1233 } 1234 1235 static void 1236 ipw_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1237 { 1238 if (error != 0) 1239 return; 1240 1241 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1242 1243 *(bus_addr_t *)arg = segs[0].ds_addr; 1244 } 1245 1246 /* 1247 * Send a command to the firmware and wait for the acknowledgement. 1248 */ 1249 static int 1250 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1251 { 1252 struct ipw_soft_bd *sbd; 1253 bus_addr_t physaddr; 1254 int error; 1255 1256 sbd = &sc->stbd_list[sc->txcur]; 1257 1258 error = bus_dmamap_load(sc->cmd_dmat, sc->cmd_map, &sc->cmd, 1259 sizeof (struct ipw_cmd), ipw_dma_map_addr, &physaddr, 0); 1260 if (error != 0) { 1261 device_printf(sc->sc_dev, "could not map command DMA memory\n"); 1262 return error; 1263 } 1264 1265 sc->cmd.type = htole32(type); 1266 sc->cmd.subtype = 0; 1267 sc->cmd.len = htole32(len); 1268 sc->cmd.seq = 0; 1269 bcopy(data, sc->cmd.data, len); 1270 1271 sbd->type = IPW_SBD_TYPE_COMMAND; 1272 sbd->bd->physaddr = htole32(physaddr); 1273 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1274 sbd->bd->nfrag = 1; 1275 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1276 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1277 1278 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, BUS_DMASYNC_PREWRITE); 1279 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1280 1281 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1282 1283 /* kick firmware */ 1284 sc->txfree--; 1285 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1286 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1287 1288 /* wait at most one second for command to complete */ 1289 return msleep(sc, &sc->sc_mtx, 0, "ipwcmd", hz); 1290 } 1291 1292 static int 1293 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1294 { 1295 struct ipw_softc *sc = ifp->if_softc; 1296 struct ieee80211com *ic = &sc->sc_ic; 1297 struct ieee80211_frame *wh; 1298 struct ipw_soft_bd *sbd; 1299 struct ipw_soft_hdr *shdr; 1300 struct ipw_soft_buf *sbuf; 1301 struct ieee80211_key *k; 1302 struct mbuf *mnew; 1303 bus_dma_segment_t segs[IPW_MAX_NSEG]; 1304 bus_addr_t physaddr; 1305 int nsegs, error, i; 1306 1307 wh = mtod(m0, struct ieee80211_frame *); 1308 1309 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1310 k = ieee80211_crypto_encap(ic, ni, m0); 1311 if (k == NULL) 1312 return ENOBUFS; 1313 1314 /* packet header may have moved, reset our local pointer */ 1315 wh = mtod(m0, struct ieee80211_frame *); 1316 } 1317 1318 if (sc->sc_drvbpf != NULL) { 1319 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1320 1321 tap->wt_flags = 0; 1322 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1323 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1324 1325 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1326 } 1327 1328 shdr = SLIST_FIRST(&sc->free_shdr); 1329 sbuf = SLIST_FIRST(&sc->free_sbuf); 1330 KASSERT(shdr != NULL && sbuf != NULL, ("empty sw hdr/buf pool")); 1331 1332 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1333 shdr->hdr.subtype = 0; 1334 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1335 shdr->hdr.encrypt = 0; 1336 shdr->hdr.keyidx = 0; 1337 shdr->hdr.keysz = 0; 1338 shdr->hdr.fragmentsz = 0; 1339 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1340 if (ic->ic_opmode == IEEE80211_M_STA) 1341 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1342 else 1343 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1344 1345 /* trim IEEE802.11 header */ 1346 m_adj(m0, sizeof (struct ieee80211_frame)); 1347 1348 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, segs, 1349 &nsegs, 0); 1350 if (error != 0 && error != EFBIG) { 1351 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1352 error); 1353 m_freem(m0); 1354 return error; 1355 } 1356 if (error != 0) { 1357 mnew = m_defrag(m0, M_DONTWAIT); 1358 if (mnew == NULL) { 1359 device_printf(sc->sc_dev, 1360 "could not defragment mbuf\n"); 1361 m_freem(m0); 1362 return ENOBUFS; 1363 } 1364 m0 = mnew; 1365 1366 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, 1367 segs, &nsegs, 0); 1368 if (error != 0) { 1369 device_printf(sc->sc_dev, 1370 "could not map mbuf (error %d)\n", error); 1371 m_freem(m0); 1372 return error; 1373 } 1374 } 1375 1376 error = bus_dmamap_load(sc->hdr_dmat, shdr->map, &shdr->hdr, 1377 sizeof (struct ipw_hdr), ipw_dma_map_addr, &physaddr, 0); 1378 if (error != 0) { 1379 device_printf(sc->sc_dev, "could not map header DMA memory\n"); 1380 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1381 m_freem(m0); 1382 return error; 1383 } 1384 1385 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1386 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1387 1388 sbd = &sc->stbd_list[sc->txcur]; 1389 sbd->type = IPW_SBD_TYPE_HEADER; 1390 sbd->priv = shdr; 1391 sbd->bd->physaddr = htole32(physaddr); 1392 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1393 sbd->bd->nfrag = 1 + nsegs; 1394 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1395 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1396 1397 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, %6D, %6D)\n", 1398 shdr->hdr.type, shdr->hdr.subtype, shdr->hdr.encrypted, 1399 shdr->hdr.encrypt, shdr->hdr.src_addr, ":", shdr->hdr.dst_addr, 1400 ":")); 1401 1402 sc->txfree--; 1403 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1404 1405 sbuf->m = m0; 1406 sbuf->ni = ni; 1407 1408 for (i = 0; i < nsegs; i++) { 1409 sbd = &sc->stbd_list[sc->txcur]; 1410 1411 sbd->bd->physaddr = htole32(segs[i].ds_addr); 1412 sbd->bd->len = htole32(segs[i].ds_len); 1413 sbd->bd->nfrag = 0; 1414 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1415 if (i == nsegs - 1) { 1416 sbd->type = IPW_SBD_TYPE_DATA; 1417 sbd->priv = sbuf; 1418 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1419 } else { 1420 sbd->type = IPW_SBD_TYPE_NOASSOC; 1421 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1422 } 1423 1424 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, segs[i].ds_len)); 1425 1426 sc->txfree--; 1427 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1428 } 1429 1430 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_PREWRITE); 1431 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, BUS_DMASYNC_PREWRITE); 1432 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1433 1434 /* kick firmware */ 1435 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1436 1437 return 0; 1438 } 1439 1440 static void 1441 ipw_start(struct ifnet *ifp) 1442 { 1443 struct ipw_softc *sc = ifp->if_softc; 1444 struct ieee80211com *ic = &sc->sc_ic; 1445 struct mbuf *m0; 1446 struct ether_header *eh; 1447 struct ieee80211_node *ni; 1448 1449 IPW_LOCK(sc); 1450 1451 if (ic->ic_state != IEEE80211_S_RUN) { 1452 IPW_UNLOCK(sc); 1453 return; 1454 } 1455 1456 for (;;) { 1457 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1458 if (m0 == NULL) 1459 break; 1460 1461 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1462 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1463 ifp->if_flags |= IFF_OACTIVE; 1464 break; 1465 } 1466 1467 if (m0->m_len < sizeof (struct ether_header) && 1468 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1469 continue; 1470 1471 eh = mtod(m0, struct ether_header *); 1472 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1473 if (ni == NULL) { 1474 m_freem(m0); 1475 continue; 1476 } 1477 BPF_MTAP(ifp, m0); 1478 1479 m0 = ieee80211_encap(ic, m0, ni); 1480 if (m0 == NULL) { 1481 ieee80211_free_node(ni); 1482 continue; 1483 } 1484 1485 if (ic->ic_rawbpf != NULL) 1486 bpf_mtap(ic->ic_rawbpf, m0); 1487 1488 if (ipw_tx_start(ifp, m0, ni) != 0) { 1489 ieee80211_free_node(ni); 1490 ifp->if_oerrors++; 1491 break; 1492 } 1493 1494 /* start watchdog timer */ 1495 sc->sc_tx_timer = 5; 1496 ifp->if_timer = 1; 1497 } 1498 1499 IPW_UNLOCK(sc); 1500 } 1501 1502 static void 1503 ipw_watchdog(struct ifnet *ifp) 1504 { 1505 struct ipw_softc *sc = ifp->if_softc; 1506 struct ieee80211com *ic = &sc->sc_ic; 1507 1508 ifp->if_timer = 0; 1509 1510 if (sc->sc_tx_timer > 0) { 1511 if (--sc->sc_tx_timer == 0) { 1512 if_printf(ifp, "device timeout\n"); 1513 ifp->if_oerrors++; 1514 ifp->if_flags &= ~IFF_UP; 1515 ipw_stop(sc); 1516 return; 1517 } 1518 ifp->if_timer = 1; 1519 } 1520 1521 ieee80211_watchdog(ic); 1522 } 1523 1524 static int 1525 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1526 { 1527 struct ipw_softc *sc = ifp->if_softc; 1528 struct ieee80211com *ic = &sc->sc_ic; 1529 struct ifreq *ifr; 1530 int error = 0; 1531 1532 IPW_LOCK(sc); 1533 1534 switch (cmd) { 1535 case SIOCSIFFLAGS: 1536 if (ifp->if_flags & IFF_UP) { 1537 if (!(ifp->if_flags & IFF_RUNNING)) 1538 ipw_init(sc); 1539 } else { 1540 if (ifp->if_flags & IFF_RUNNING) 1541 ipw_stop(sc); 1542 } 1543 break; 1544 1545 case SIOCSLOADFW: 1546 /* only super-user can do that! */ 1547 if ((error = suser(curthread)) != 0) 1548 break; 1549 1550 ifr = (struct ifreq *)data; 1551 error = ipw_cache_firmware(sc, ifr->ifr_data); 1552 break; 1553 1554 case SIOCSKILLFW: 1555 /* only super-user can do that! */ 1556 if ((error = suser(curthread)) != 0) 1557 break; 1558 1559 ifp->if_flags &= ~IFF_UP; 1560 ipw_stop(sc); 1561 ipw_free_firmware(sc); 1562 break; 1563 1564 default: 1565 error = ieee80211_ioctl(ic, cmd, data); 1566 } 1567 1568 if (error == ENETRESET) { 1569 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1570 (IFF_UP | IFF_RUNNING)) 1571 ipw_init(sc); 1572 error = 0; 1573 } 1574 1575 IPW_UNLOCK(sc); 1576 1577 return error; 1578 } 1579 1580 static void 1581 ipw_stop_master(struct ipw_softc *sc) 1582 { 1583 int ntries; 1584 1585 /* disable interrupts */ 1586 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1587 1588 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1589 for (ntries = 0; ntries < 50; ntries++) { 1590 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1591 break; 1592 DELAY(10); 1593 } 1594 if (ntries == 50) 1595 device_printf(sc->sc_dev, "timeout waiting for master\n"); 1596 1597 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1598 IPW_RST_PRINCETON_RESET); 1599 1600 sc->flags &= ~IPW_FLAG_FW_INITED; 1601 } 1602 1603 static int 1604 ipw_reset(struct ipw_softc *sc) 1605 { 1606 int ntries; 1607 1608 ipw_stop_master(sc); 1609 1610 /* move adapter to D0 state */ 1611 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1612 IPW_CTL_INIT); 1613 1614 /* wait for clock stabilization */ 1615 for (ntries = 0; ntries < 1000; ntries++) { 1616 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1617 break; 1618 DELAY(200); 1619 } 1620 if (ntries == 1000) 1621 return EIO; 1622 1623 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | 1624 IPW_RST_SW_RESET); 1625 1626 DELAY(10); 1627 1628 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1629 IPW_CTL_INIT); 1630 1631 return 0; 1632 } 1633 1634 /* 1635 * Upload the microcode to the device. 1636 */ 1637 static int 1638 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) 1639 { 1640 int ntries; 1641 1642 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1643 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1644 1645 MEM_WRITE_2(sc, 0x220000, 0x0703); 1646 MEM_WRITE_2(sc, 0x220000, 0x0707); 1647 1648 MEM_WRITE_1(sc, 0x210014, 0x72); 1649 MEM_WRITE_1(sc, 0x210014, 0x72); 1650 1651 MEM_WRITE_1(sc, 0x210000, 0x40); 1652 MEM_WRITE_1(sc, 0x210000, 0x00); 1653 MEM_WRITE_1(sc, 0x210000, 0x40); 1654 1655 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1656 1657 MEM_WRITE_1(sc, 0x210000, 0x00); 1658 MEM_WRITE_1(sc, 0x210000, 0x00); 1659 MEM_WRITE_1(sc, 0x210000, 0x80); 1660 1661 MEM_WRITE_2(sc, 0x220000, 0x0703); 1662 MEM_WRITE_2(sc, 0x220000, 0x0707); 1663 1664 MEM_WRITE_1(sc, 0x210014, 0x72); 1665 MEM_WRITE_1(sc, 0x210014, 0x72); 1666 1667 MEM_WRITE_1(sc, 0x210000, 0x00); 1668 MEM_WRITE_1(sc, 0x210000, 0x80); 1669 1670 for (ntries = 0; ntries < 10; ntries++) { 1671 if (MEM_READ_1(sc, 0x210000) & 1) 1672 break; 1673 DELAY(10); 1674 } 1675 if (ntries == 10) { 1676 device_printf(sc->sc_dev, 1677 "timeout waiting for ucode to initialize\n"); 1678 return EIO; 1679 } 1680 1681 MEM_WRITE_4(sc, 0x3000e0, 0); 1682 1683 return 0; 1684 } 1685 1686 /* set of macros to handle unaligned little endian data in firmware image */ 1687 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1688 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1689 static int 1690 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) 1691 { 1692 u_char *p, *end; 1693 uint32_t dst; 1694 uint16_t len; 1695 int error; 1696 1697 p = fw; 1698 end = fw + size; 1699 while (p < end) { 1700 dst = GETLE32(p); p += 4; 1701 len = GETLE16(p); p += 2; 1702 1703 ipw_write_mem_1(sc, dst, p, len); 1704 p += len; 1705 } 1706 1707 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1708 IPW_IO_LED_OFF); 1709 1710 /* enable interrupts */ 1711 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1712 1713 /* kick the firmware */ 1714 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1715 1716 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | 1717 IPW_CTL_ALLOW_STANDBY); 1718 1719 /* wait at most one second for firmware initialization to complete */ 1720 if ((error = msleep(sc, &sc->sc_mtx, 0, "ipwinit", hz)) != 0) { 1721 device_printf(sc->sc_dev, "timeout waiting for firmware " 1722 "initialization to complete\n"); 1723 return error; 1724 } 1725 1726 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | 1727 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); 1728 1729 return 0; 1730 } 1731 1732 /* 1733 * Store firmware into kernel memory so we can download it when we need to, 1734 * e.g when the adapter wakes up from suspend mode. 1735 */ 1736 static int 1737 ipw_cache_firmware(struct ipw_softc *sc, void *data) 1738 { 1739 struct ipw_firmware *fw = &sc->fw; 1740 struct ipw_firmware_hdr hdr; 1741 u_char *p = data; 1742 int error; 1743 1744 ipw_free_firmware(sc); 1745 1746 IPW_UNLOCK(sc); 1747 1748 if ((error = copyin(data, &hdr, sizeof hdr)) != 0) 1749 goto fail1; 1750 1751 fw->main_size = le32toh(hdr.main_size); 1752 fw->ucode_size = le32toh(hdr.ucode_size); 1753 p += sizeof hdr; 1754 1755 fw->main = malloc(fw->main_size, M_DEVBUF, M_NOWAIT); 1756 if (fw->main == NULL) { 1757 error = ENOMEM; 1758 goto fail1; 1759 } 1760 1761 fw->ucode = malloc(fw->ucode_size, M_DEVBUF, M_NOWAIT); 1762 if (fw->ucode == NULL) { 1763 error = ENOMEM; 1764 goto fail2; 1765 } 1766 1767 if ((error = copyin(p, fw->main, fw->main_size)) != 0) 1768 goto fail3; 1769 1770 p += fw->main_size; 1771 if ((error = copyin(p, fw->ucode, fw->ucode_size)) != 0) 1772 goto fail3; 1773 1774 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, 1775 fw->ucode_size)); 1776 1777 IPW_LOCK(sc); 1778 1779 sc->flags |= IPW_FLAG_FW_CACHED; 1780 1781 return 0; 1782 1783 fail3: free(fw->ucode, M_DEVBUF); 1784 fail2: free(fw->main, M_DEVBUF); 1785 fail1: IPW_LOCK(sc); 1786 1787 return error; 1788 } 1789 1790 static void 1791 ipw_free_firmware(struct ipw_softc *sc) 1792 { 1793 if (!(sc->flags & IPW_FLAG_FW_CACHED)) 1794 return; 1795 1796 free(sc->fw.main, M_DEVBUF); 1797 free(sc->fw.ucode, M_DEVBUF); 1798 1799 sc->flags &= ~IPW_FLAG_FW_CACHED; 1800 } 1801 1802 static int 1803 ipw_config(struct ipw_softc *sc) 1804 { 1805 struct ieee80211com *ic = &sc->sc_ic; 1806 struct ifnet *ifp = ic->ic_ifp; 1807 struct ipw_security security; 1808 struct ieee80211_key *k; 1809 struct ipw_wep_key wepkey; 1810 struct ipw_scan_options options; 1811 struct ipw_configuration config; 1812 uint32_t data; 1813 int error, i; 1814 1815 switch (ic->ic_opmode) { 1816 case IEEE80211_M_STA: 1817 case IEEE80211_M_HOSTAP: 1818 data = htole32(IPW_MODE_BSS); 1819 break; 1820 1821 case IEEE80211_M_IBSS: 1822 case IEEE80211_M_AHDEMO: 1823 data = htole32(IPW_MODE_IBSS); 1824 break; 1825 1826 case IEEE80211_M_MONITOR: 1827 data = htole32(IPW_MODE_MONITOR); 1828 break; 1829 } 1830 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1831 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1832 if (error != 0) 1833 return error; 1834 1835 if (ic->ic_opmode == IEEE80211_M_IBSS || 1836 ic->ic_opmode == IEEE80211_M_MONITOR) { 1837 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); 1838 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1839 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1840 if (error != 0) 1841 return error; 1842 } 1843 1844 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1845 DPRINTF(("Enabling adapter\n")); 1846 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1847 } 1848 1849 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 1850 DPRINTF(("Setting MAC address to %6D\n", ic->ic_myaddr, ":")); 1851 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1852 IEEE80211_ADDR_LEN); 1853 if (error != 0) 1854 return error; 1855 1856 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1857 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1858 if (ic->ic_opmode == IEEE80211_M_IBSS) 1859 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1860 if (ifp->if_flags & IFF_PROMISC) 1861 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1862 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1863 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1864 DPRINTF(("Setting configuration to 0x%x\n", le32toh(config.flags))); 1865 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1866 if (error != 0) 1867 return error; 1868 1869 data = htole32(0x3); /* 1, 2 */ 1870 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 1871 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1872 if (error != 0) 1873 return error; 1874 1875 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1876 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 1877 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1878 if (error != 0) 1879 return error; 1880 1881 data = htole32(IPW_POWER_MODE_CAM); 1882 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 1883 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1884 if (error != 0) 1885 return error; 1886 1887 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1888 data = htole32(32); /* default value */ 1889 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 1890 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1891 sizeof data); 1892 if (error != 0) 1893 return error; 1894 } 1895 1896 data = htole32(ic->ic_rtsthreshold); 1897 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 1898 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1899 if (error != 0) 1900 return error; 1901 1902 data = htole32(ic->ic_fragthreshold); 1903 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 1904 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1905 if (error != 0) 1906 return error; 1907 1908 #ifdef IPW_DEBUG 1909 if (ipw_debug > 0) { 1910 printf("Setting ESSID to "); 1911 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1912 printf("\n"); 1913 } 1914 #endif 1915 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, 1916 ic->ic_des_esslen); 1917 if (error != 0) 1918 return error; 1919 1920 /* no mandatory BSSID */ 1921 DPRINTF(("Setting mandatory BSSID to null\n")); 1922 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1923 if (error != 0) 1924 return error; 1925 1926 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1927 DPRINTF(("Setting desired BSSID to %6D\n", ic->ic_des_bssid, 1928 ":")); 1929 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1930 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1931 if (error != 0) 1932 return error; 1933 } 1934 1935 bzero(&security, sizeof security); 1936 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 1937 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1938 security.ciphers = htole32(IPW_CIPHER_NONE); 1939 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1940 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1941 sizeof security); 1942 if (error != 0) 1943 return error; 1944 1945 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1946 k = ic->ic_crypto.cs_nw_keys; 1947 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1948 if (k->wk_keylen == 0) 1949 continue; 1950 1951 wepkey.idx = i; 1952 wepkey.len = k->wk_keylen; 1953 bzero(wepkey.key, sizeof wepkey.key); 1954 bcopy(k->wk_key, wepkey.key, k->wk_keylen); 1955 DPRINTF(("Setting wep key index %u len %u\n", 1956 wepkey.idx, wepkey.len)); 1957 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1958 sizeof wepkey); 1959 if (error != 0) 1960 return error; 1961 } 1962 1963 data = htole32(ic->ic_crypto.cs_def_txkey); 1964 DPRINTF(("Setting wep tx key index to %u\n", le32toh(data))); 1965 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1966 sizeof data); 1967 if (error != 0) 1968 return error; 1969 } 1970 1971 data = htole32((ic->ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 1972 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 1973 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1974 if (error != 0) 1975 return error; 1976 1977 #if 0 1978 struct ipw_wpa_ie ie; 1979 1980 bzero(&ie, sizeof ie); 1981 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 1982 DPRINTF(("Setting wpa ie\n")); 1983 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 1984 if (error != 0) 1985 return error; 1986 #endif 1987 1988 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1989 data = htole32(ic->ic_lintval); 1990 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 1991 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1992 sizeof data); 1993 if (error != 0) 1994 return error; 1995 } 1996 1997 options.flags = 0; 1998 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1999 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 2000 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 2001 if (error != 0) 2002 return error; 2003 2004 /* finally, enable adapter (start scanning for an access point) */ 2005 DPRINTF(("Enabling adapter\n")); 2006 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 2007 } 2008 2009 static void 2010 ipw_init(void *priv) 2011 { 2012 struct ipw_softc *sc = priv; 2013 struct ieee80211com *ic = &sc->sc_ic; 2014 struct ifnet *ifp = ic->ic_ifp; 2015 struct ipw_firmware *fw = &sc->fw; 2016 2017 /* exit immediately if firmware has not been ioctl'd */ 2018 if (!(sc->flags & IPW_FLAG_FW_CACHED)) { 2019 if (!(sc->flags & IPW_FLAG_FW_WARNED)) 2020 device_printf(sc->sc_dev, "Please load firmware\n"); 2021 sc->flags |= IPW_FLAG_FW_WARNED; 2022 ifp->if_flags &= ~IFF_UP; 2023 return; 2024 } 2025 2026 ipw_stop(sc); 2027 2028 if (ipw_reset(sc) != 0) { 2029 device_printf(sc->sc_dev, "could not reset adapter\n"); 2030 goto fail; 2031 } 2032 2033 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { 2034 device_printf(sc->sc_dev, "could not load microcode\n"); 2035 goto fail; 2036 } 2037 2038 ipw_stop_master(sc); 2039 2040 /* 2041 * Setup tx, rx and status rings. 2042 */ 2043 sc->txold = IPW_NTBD - 1; 2044 sc->txcur = 0; 2045 sc->txfree = IPW_NTBD - 2; 2046 sc->rxcur = IPW_NRBD - 1; 2047 2048 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_phys); 2049 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2050 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2051 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2052 2053 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_phys); 2054 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2055 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2056 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2057 2058 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_phys); 2059 2060 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { 2061 device_printf(sc->sc_dev, "could not load firmware\n"); 2062 goto fail; 2063 } 2064 2065 sc->flags |= IPW_FLAG_FW_INITED; 2066 2067 /* retrieve information tables base addresses */ 2068 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2069 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2070 2071 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2072 2073 if (ipw_config(sc) != 0) { 2074 device_printf(sc->sc_dev, "device configuration failed\n"); 2075 goto fail; 2076 } 2077 2078 ifp->if_flags &= ~IFF_OACTIVE; 2079 ifp->if_flags |= IFF_RUNNING; 2080 2081 return; 2082 2083 fail: ifp->if_flags &= ~IFF_UP; 2084 ipw_stop(sc); 2085 } 2086 2087 static void 2088 ipw_stop(void *priv) 2089 { 2090 struct ipw_softc *sc = priv; 2091 struct ieee80211com *ic = &sc->sc_ic; 2092 struct ifnet *ifp = ic->ic_ifp; 2093 int i; 2094 2095 ipw_stop_master(sc); 2096 2097 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2098 2099 /* 2100 * Release tx buffers. 2101 */ 2102 for (i = 0; i < IPW_NTBD; i++) 2103 ipw_release_sbd(sc, &sc->stbd_list[i]); 2104 2105 sc->sc_tx_timer = 0; 2106 ifp->if_timer = 0; 2107 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2108 2109 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2110 } 2111 2112 #ifdef IPW_DEBUG 2113 static int 2114 ipw_sysctl_stats(SYSCTL_HANDLER_ARGS) 2115 { 2116 struct ipw_softc *sc = arg1; 2117 uint32_t i, size, buf[256]; 2118 2119 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 2120 bzero(buf, sizeof buf); 2121 return SYSCTL_OUT(req, buf, sizeof buf); 2122 } 2123 2124 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 2125 2126 size = min(CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA), 256); 2127 for (i = 1; i < size; i++) 2128 buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA)); 2129 2130 return SYSCTL_OUT(req, buf, sizeof buf); 2131 } 2132 #endif 2133 2134 static int 2135 ipw_sysctl_radio(SYSCTL_HANDLER_ARGS) 2136 { 2137 struct ipw_softc *sc = arg1; 2138 int val; 2139 2140 val = !((sc->flags & IPW_FLAG_HAS_RADIO_SWITCH) && 2141 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED)); 2142 2143 return SYSCTL_OUT(req, &val, sizeof val); 2144 } 2145 2146 static uint32_t 2147 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 2148 { 2149 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 2150 } 2151 2152 static void 2153 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 2154 { 2155 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 2156 } 2157 2158 static int 2159 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 2160 { 2161 uint32_t addr, info; 2162 uint16_t count, size; 2163 uint32_t total; 2164 2165 /* addr[4] + count[2] + size[2] */ 2166 addr = MEM_READ_4(sc, sc->table2_base + off); 2167 info = MEM_READ_4(sc, sc->table2_base + off + 4); 2168 2169 count = info >> 16; 2170 size = info & 0xffff; 2171 total = count * size; 2172 2173 if (total > *len) { 2174 *len = total; 2175 return EINVAL; 2176 } 2177 2178 *len = total; 2179 ipw_read_mem_1(sc, addr, buf, total); 2180 2181 return 0; 2182 } 2183 2184 static void 2185 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2186 bus_size_t count) 2187 { 2188 for (; count > 0; offset++, datap++, count--) { 2189 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2190 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2191 } 2192 } 2193 2194 static void 2195 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2196 bus_size_t count) 2197 { 2198 for (; count > 0; offset++, datap++, count--) { 2199 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2200 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2201 } 2202 } 2203