1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2004-2006 5 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /*- 34 * Intel(R) PRO/Wireless 2100 MiniPCI driver 35 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm 36 */ 37 38 #include <sys/param.h> 39 #include <sys/sysctl.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/kernel.h> 43 #include <sys/socket.h> 44 #include <sys/systm.h> 45 #include <sys/malloc.h> 46 #include <sys/queue.h> 47 #include <sys/taskqueue.h> 48 #include <sys/module.h> 49 #include <sys/bus.h> 50 #include <sys/endian.h> 51 #include <sys/linker.h> 52 #include <sys/firmware.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 #include <sys/rman.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 61 #include <net/bpf.h> 62 #include <net/if.h> 63 #include <net/if_arp.h> 64 #include <net/ethernet.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_radiotap.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 #include <netinet/if_ether.h> 77 78 #include <dev/ipw/if_ipwreg.h> 79 #include <dev/ipw/if_ipwvar.h> 80 81 #ifdef IPW_DEBUG 82 #define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) 83 #define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) 84 int ipw_debug = 0; 85 SYSCTL_INT(_debug, OID_AUTO, ipw, CTLFLAG_RW, &ipw_debug, 0, "ipw debug level"); 86 #else 87 #define DPRINTF(x) 88 #define DPRINTFN(n, x) 89 #endif 90 91 MODULE_DEPEND(ipw, pci, 1, 1, 1); 92 MODULE_DEPEND(ipw, wlan, 1, 1, 1); 93 MODULE_DEPEND(ipw, firmware, 1, 1, 1); 94 95 struct ipw_ident { 96 uint16_t vendor; 97 uint16_t device; 98 const char *name; 99 }; 100 101 static const struct ipw_ident ipw_ident_table[] = { 102 { 0x8086, 0x1043, "Intel(R) PRO/Wireless 2100 MiniPCI" }, 103 104 { 0, 0, NULL } 105 }; 106 107 static int ipw_dma_alloc(struct ipw_softc *); 108 static void ipw_release(struct ipw_softc *); 109 static int ipw_media_change(struct ifnet *); 110 static void ipw_media_status(struct ifnet *, struct ifmediareq *); 111 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); 112 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); 113 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); 114 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); 115 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, 116 struct ipw_soft_bd *, struct ipw_soft_buf *); 117 static void ipw_rx_intr(struct ipw_softc *); 118 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); 119 static void ipw_tx_intr(struct ipw_softc *); 120 static void ipw_intr(void *); 121 static void ipw_dma_map_addr(void *, bus_dma_segment_t *, int, int); 122 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); 123 static int ipw_tx_start(struct ifnet *, struct mbuf *, 124 struct ieee80211_node *); 125 static void ipw_start(struct ifnet *); 126 static void ipw_watchdog(struct ifnet *); 127 static int ipw_ioctl(struct ifnet *, u_long, caddr_t); 128 static void ipw_stop_master(struct ipw_softc *); 129 static int ipw_reset(struct ipw_softc *); 130 static int ipw_load_ucode(struct ipw_softc *, const char *, int); 131 static int ipw_load_firmware(struct ipw_softc *, const char *, int); 132 static int ipw_config(struct ipw_softc *); 133 static void ipw_init_task(void *, int); 134 static void ipw_init(void *); 135 static void ipw_stop(void *); 136 static int ipw_sysctl_stats(SYSCTL_HANDLER_ARGS); 137 static int ipw_sysctl_radio(SYSCTL_HANDLER_ARGS); 138 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); 139 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); 140 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, 141 uint32_t *); 142 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, 143 bus_size_t); 144 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, 145 const uint8_t *, bus_size_t); 146 147 static int ipw_probe(device_t); 148 static int ipw_attach(device_t); 149 static int ipw_detach(device_t); 150 static int ipw_shutdown(device_t); 151 static int ipw_suspend(device_t); 152 static int ipw_resume(device_t); 153 154 static device_method_t ipw_methods[] = { 155 /* Device interface */ 156 DEVMETHOD(device_probe, ipw_probe), 157 DEVMETHOD(device_attach, ipw_attach), 158 DEVMETHOD(device_detach, ipw_detach), 159 DEVMETHOD(device_shutdown, ipw_shutdown), 160 DEVMETHOD(device_suspend, ipw_suspend), 161 DEVMETHOD(device_resume, ipw_resume), 162 163 { 0, 0 } 164 }; 165 166 static driver_t ipw_driver = { 167 "ipw", 168 ipw_methods, 169 sizeof (struct ipw_softc) 170 }; 171 172 static devclass_t ipw_devclass; 173 174 DRIVER_MODULE(ipw, pci, ipw_driver, ipw_devclass, 0, 0); 175 176 static int 177 ipw_probe(device_t dev) 178 { 179 const struct ipw_ident *ident; 180 181 for (ident = ipw_ident_table; ident->name != NULL; ident++) { 182 if (pci_get_vendor(dev) == ident->vendor && 183 pci_get_device(dev) == ident->device) { 184 device_set_desc(dev, ident->name); 185 return 0; 186 } 187 } 188 return ENXIO; 189 } 190 191 /* Base Address Register */ 192 #define IPW_PCI_BAR0 0x10 193 194 static int 195 ipw_attach(device_t dev) 196 { 197 struct ipw_softc *sc = device_get_softc(dev); 198 struct ifnet *ifp; 199 struct ieee80211com *ic = &sc->sc_ic; 200 struct ieee80211_channel *c; 201 uint16_t val; 202 int error, i; 203 204 sc->sc_dev = dev; 205 206 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 207 MTX_DEF | MTX_RECURSE); 208 209 TASK_INIT(&sc->sc_init_task, 0, ipw_init_task, sc); 210 211 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 212 device_printf(dev, "chip is in D%d power mode " 213 "-- setting to D0\n", pci_get_powerstate(dev)); 214 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 215 } 216 217 pci_write_config(dev, 0x41, 0, 1); 218 219 /* enable bus-mastering */ 220 pci_enable_busmaster(dev); 221 222 sc->mem_rid = IPW_PCI_BAR0; 223 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 224 RF_ACTIVE); 225 if (sc->mem == NULL) { 226 device_printf(dev, "could not allocate memory resource\n"); 227 goto fail; 228 } 229 230 sc->sc_st = rman_get_bustag(sc->mem); 231 sc->sc_sh = rman_get_bushandle(sc->mem); 232 233 sc->irq_rid = 0; 234 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, 235 RF_ACTIVE | RF_SHAREABLE); 236 if (sc->irq == NULL) { 237 device_printf(dev, "could not allocate interrupt resource\n"); 238 goto fail; 239 } 240 241 if (ipw_reset(sc) != 0) { 242 device_printf(dev, "could not reset adapter\n"); 243 goto fail; 244 } 245 246 if (ipw_dma_alloc(sc) != 0) { 247 device_printf(dev, "could not allocate DMA resources\n"); 248 goto fail; 249 } 250 251 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 252 if (ifp == NULL) { 253 device_printf(dev, "can not if_alloc()\n"); 254 goto fail; 255 } 256 257 ifp->if_softc = sc; 258 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 259 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 260 ifp->if_init = ipw_init; 261 ifp->if_ioctl = ipw_ioctl; 262 ifp->if_start = ipw_start; 263 ifp->if_watchdog = ipw_watchdog; 264 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 265 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 266 IFQ_SET_READY(&ifp->if_snd); 267 268 ic->ic_ifp = ifp; 269 ic->ic_phytype = IEEE80211_T_DS; 270 ic->ic_opmode = IEEE80211_M_STA; 271 ic->ic_state = IEEE80211_S_INIT; 272 273 /* set device capabilities */ 274 ic->ic_caps = 275 IEEE80211_C_IBSS | /* IBSS mode supported */ 276 IEEE80211_C_MONITOR | /* monitor mode supported */ 277 IEEE80211_C_TXPMGT | /* tx power management */ 278 IEEE80211_C_SHPREAMBLE; /* short preamble supported */ 279 280 /* read MAC address from EEPROM */ 281 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); 282 ic->ic_myaddr[0] = val >> 8; 283 ic->ic_myaddr[1] = val & 0xff; 284 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); 285 ic->ic_myaddr[2] = val >> 8; 286 ic->ic_myaddr[3] = val & 0xff; 287 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); 288 ic->ic_myaddr[4] = val >> 8; 289 ic->ic_myaddr[5] = val & 0xff; 290 291 /* set supported .11b channels (read from EEPROM) */ 292 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) 293 val = 0x7ff; /* default to channels 1-11 */ 294 val <<= 1; 295 for (i = 1; i < 16; i++) { 296 if (val & (1 << i)) { 297 c = &ic->ic_channels[ic->ic_nchans++]; 298 c->ic_freq = ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 299 c->ic_flags = IEEE80211_CHAN_B; 300 c->ic_ieee = i; 301 } 302 } 303 304 /* check support for radio transmitter switch in EEPROM */ 305 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) 306 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; 307 308 ieee80211_ifattach(ic); 309 /* override state transition machine */ 310 sc->sc_newstate = ic->ic_newstate; 311 ic->ic_newstate = ipw_newstate; 312 ieee80211_media_init(ic, ipw_media_change, ipw_media_status); 313 314 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 315 sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); 316 317 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 318 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 319 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); 320 321 sc->sc_txtap_len = sizeof sc->sc_txtapu; 322 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 323 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); 324 325 /* 326 * Add a few sysctl knobs. 327 */ 328 sc->dwelltime = 100; 329 330 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 331 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "radio", 332 CTLTYPE_INT | CTLFLAG_RD, sc, 0, ipw_sysctl_radio, "I", 333 "radio transmitter switch state (0=off, 1=on)"); 334 335 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 336 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats", 337 CTLTYPE_OPAQUE | CTLFLAG_RD, sc, 0, ipw_sysctl_stats, "S", 338 "statistics"); 339 340 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 341 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", 342 CTLFLAG_RW, &sc->dwelltime, 0, 343 "channel dwell time (ms) for AP/station scanning"); 344 345 /* 346 * Hook our interrupt after all initialization is complete. 347 */ 348 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 349 NULL, ipw_intr, sc, &sc->sc_ih); 350 if (error != 0) { 351 device_printf(dev, "could not set up interrupt\n"); 352 goto fail; 353 } 354 355 if (bootverbose) 356 ieee80211_announce(ic); 357 358 return 0; 359 360 fail: ipw_detach(dev); 361 return ENXIO; 362 } 363 364 static int 365 ipw_detach(device_t dev) 366 { 367 struct ipw_softc *sc = device_get_softc(dev); 368 struct ieee80211com *ic = &sc->sc_ic; 369 struct ifnet *ifp = ic->ic_ifp; 370 371 ipw_stop(sc); 372 373 if (ifp != NULL) { 374 bpfdetach(ifp); 375 ieee80211_ifdetach(ic); 376 } 377 378 ipw_release(sc); 379 380 if (sc->irq != NULL) { 381 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 382 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); 383 } 384 385 if (sc->mem != NULL) 386 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); 387 388 if (ifp != NULL) 389 if_free(ifp); 390 391 if (sc->sc_firmware != NULL) { 392 firmware_put(sc->sc_firmware, FIRMWARE_UNLOAD); 393 sc->sc_firmware = NULL; 394 } 395 396 mtx_destroy(&sc->sc_mtx); 397 398 return 0; 399 } 400 401 static int 402 ipw_dma_alloc(struct ipw_softc *sc) 403 { 404 struct ipw_soft_bd *sbd; 405 struct ipw_soft_hdr *shdr; 406 struct ipw_soft_buf *sbuf; 407 bus_addr_t physaddr; 408 int error, i; 409 410 /* 411 * Allocate and map tx ring. 412 */ 413 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 414 BUS_SPACE_MAXADDR, NULL, NULL, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, NULL, 415 NULL, &sc->tbd_dmat); 416 if (error != 0) { 417 device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); 418 goto fail; 419 } 420 421 error = bus_dmamem_alloc(sc->tbd_dmat, (void **)&sc->tbd_list, 422 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tbd_map); 423 if (error != 0) { 424 device_printf(sc->sc_dev, 425 "could not allocate tx ring DMA memory\n"); 426 goto fail; 427 } 428 429 error = bus_dmamap_load(sc->tbd_dmat, sc->tbd_map, sc->tbd_list, 430 IPW_TBD_SZ, ipw_dma_map_addr, &sc->tbd_phys, 0); 431 if (error != 0) { 432 device_printf(sc->sc_dev, "could not map tx ring DMA memory\n"); 433 goto fail; 434 } 435 436 /* 437 * Allocate and map rx ring. 438 */ 439 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 440 BUS_SPACE_MAXADDR, NULL, NULL, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, NULL, 441 NULL, &sc->rbd_dmat); 442 if (error != 0) { 443 device_printf(sc->sc_dev, "could not create rx ring DMA tag\n"); 444 goto fail; 445 } 446 447 error = bus_dmamem_alloc(sc->rbd_dmat, (void **)&sc->rbd_list, 448 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rbd_map); 449 if (error != 0) { 450 device_printf(sc->sc_dev, 451 "could not allocate rx ring DMA memory\n"); 452 goto fail; 453 } 454 455 error = bus_dmamap_load(sc->rbd_dmat, sc->rbd_map, sc->rbd_list, 456 IPW_RBD_SZ, ipw_dma_map_addr, &sc->rbd_phys, 0); 457 if (error != 0) { 458 device_printf(sc->sc_dev, "could not map rx ring DMA memory\n"); 459 goto fail; 460 } 461 462 /* 463 * Allocate and map status ring. 464 */ 465 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, 466 BUS_SPACE_MAXADDR, NULL, NULL, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 0, 467 NULL, NULL, &sc->status_dmat); 468 if (error != 0) { 469 device_printf(sc->sc_dev, 470 "could not create status ring DMA tag\n"); 471 goto fail; 472 } 473 474 error = bus_dmamem_alloc(sc->status_dmat, (void **)&sc->status_list, 475 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->status_map); 476 if (error != 0) { 477 device_printf(sc->sc_dev, 478 "could not allocate status ring DMA memory\n"); 479 goto fail; 480 } 481 482 error = bus_dmamap_load(sc->status_dmat, sc->status_map, 483 sc->status_list, IPW_STATUS_SZ, ipw_dma_map_addr, &sc->status_phys, 484 0); 485 if (error != 0) { 486 device_printf(sc->sc_dev, 487 "could not map status ring DMA memory\n"); 488 goto fail; 489 } 490 491 /* 492 * Allocate command DMA map. 493 */ 494 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 495 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_cmd), 1, 496 sizeof (struct ipw_cmd), 0, NULL, NULL, &sc->cmd_dmat); 497 if (error != 0) { 498 device_printf(sc->sc_dev, "could not create command DMA tag\n"); 499 goto fail; 500 } 501 502 error = bus_dmamap_create(sc->cmd_dmat, 0, &sc->cmd_map); 503 if (error != 0) { 504 device_printf(sc->sc_dev, 505 "could not create command DMA map\n"); 506 goto fail; 507 } 508 509 /* 510 * Allocate headers DMA maps. 511 */ 512 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 513 BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_hdr), 1, 514 sizeof (struct ipw_hdr), 0, NULL, NULL, &sc->hdr_dmat); 515 if (error != 0) { 516 device_printf(sc->sc_dev, "could not create header DMA tag\n"); 517 goto fail; 518 } 519 520 SLIST_INIT(&sc->free_shdr); 521 for (i = 0; i < IPW_NDATA; i++) { 522 shdr = &sc->shdr_list[i]; 523 error = bus_dmamap_create(sc->hdr_dmat, 0, &shdr->map); 524 if (error != 0) { 525 device_printf(sc->sc_dev, 526 "could not create header DMA map\n"); 527 goto fail; 528 } 529 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 530 } 531 532 /* 533 * Allocate tx buffers DMA maps. 534 */ 535 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 536 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_MAX_NSEG, MCLBYTES, 0, 537 NULL, NULL, &sc->txbuf_dmat); 538 if (error != 0) { 539 device_printf(sc->sc_dev, "could not create tx DMA tag\n"); 540 goto fail; 541 } 542 543 SLIST_INIT(&sc->free_sbuf); 544 for (i = 0; i < IPW_NDATA; i++) { 545 sbuf = &sc->tx_sbuf_list[i]; 546 error = bus_dmamap_create(sc->txbuf_dmat, 0, &sbuf->map); 547 if (error != 0) { 548 device_printf(sc->sc_dev, 549 "could not create tx DMA map\n"); 550 goto fail; 551 } 552 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 553 } 554 555 /* 556 * Initialize tx ring. 557 */ 558 for (i = 0; i < IPW_NTBD; i++) { 559 sbd = &sc->stbd_list[i]; 560 sbd->bd = &sc->tbd_list[i]; 561 sbd->type = IPW_SBD_TYPE_NOASSOC; 562 } 563 564 /* 565 * Pre-allocate rx buffers and DMA maps. 566 */ 567 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 568 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, 569 NULL, &sc->rxbuf_dmat); 570 if (error != 0) { 571 device_printf(sc->sc_dev, "could not create rx DMA tag\n"); 572 goto fail; 573 } 574 575 for (i = 0; i < IPW_NRBD; i++) { 576 sbd = &sc->srbd_list[i]; 577 sbuf = &sc->rx_sbuf_list[i]; 578 sbd->bd = &sc->rbd_list[i]; 579 580 sbuf->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 581 if (sbuf->m == NULL) { 582 device_printf(sc->sc_dev, 583 "could not allocate rx mbuf\n"); 584 error = ENOMEM; 585 goto fail; 586 } 587 588 error = bus_dmamap_create(sc->rxbuf_dmat, 0, &sbuf->map); 589 if (error != 0) { 590 device_printf(sc->sc_dev, 591 "could not create rx DMA map\n"); 592 goto fail; 593 } 594 595 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 596 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 597 &physaddr, 0); 598 if (error != 0) { 599 device_printf(sc->sc_dev, 600 "could not map rx DMA memory\n"); 601 goto fail; 602 } 603 604 sbd->type = IPW_SBD_TYPE_DATA; 605 sbd->priv = sbuf; 606 sbd->bd->physaddr = htole32(physaddr); 607 sbd->bd->len = htole32(MCLBYTES); 608 } 609 610 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 611 612 return 0; 613 614 fail: ipw_release(sc); 615 return error; 616 } 617 618 static void 619 ipw_release(struct ipw_softc *sc) 620 { 621 struct ipw_soft_buf *sbuf; 622 int i; 623 624 if (sc->tbd_dmat != NULL) { 625 if (sc->stbd_list != NULL) { 626 bus_dmamap_unload(sc->tbd_dmat, sc->tbd_map); 627 bus_dmamem_free(sc->tbd_dmat, sc->tbd_list, 628 sc->tbd_map); 629 } 630 bus_dma_tag_destroy(sc->tbd_dmat); 631 } 632 633 if (sc->rbd_dmat != NULL) { 634 if (sc->rbd_list != NULL) { 635 bus_dmamap_unload(sc->rbd_dmat, sc->rbd_map); 636 bus_dmamem_free(sc->rbd_dmat, sc->rbd_list, 637 sc->rbd_map); 638 } 639 bus_dma_tag_destroy(sc->rbd_dmat); 640 } 641 642 if (sc->status_dmat != NULL) { 643 if (sc->status_list != NULL) { 644 bus_dmamap_unload(sc->status_dmat, sc->status_map); 645 bus_dmamem_free(sc->status_dmat, sc->status_list, 646 sc->status_map); 647 } 648 bus_dma_tag_destroy(sc->status_dmat); 649 } 650 651 for (i = 0; i < IPW_NTBD; i++) 652 ipw_release_sbd(sc, &sc->stbd_list[i]); 653 654 if (sc->cmd_dmat != NULL) { 655 bus_dmamap_destroy(sc->cmd_dmat, sc->cmd_map); 656 bus_dma_tag_destroy(sc->cmd_dmat); 657 } 658 659 if (sc->hdr_dmat != NULL) { 660 for (i = 0; i < IPW_NDATA; i++) 661 bus_dmamap_destroy(sc->hdr_dmat, sc->shdr_list[i].map); 662 bus_dma_tag_destroy(sc->hdr_dmat); 663 } 664 665 if (sc->txbuf_dmat != NULL) { 666 for (i = 0; i < IPW_NDATA; i++) { 667 bus_dmamap_destroy(sc->txbuf_dmat, 668 sc->tx_sbuf_list[i].map); 669 } 670 bus_dma_tag_destroy(sc->txbuf_dmat); 671 } 672 673 if (sc->rxbuf_dmat != NULL) { 674 for (i = 0; i < IPW_NRBD; i++) { 675 sbuf = &sc->rx_sbuf_list[i]; 676 if (sbuf->m != NULL) { 677 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, 678 BUS_DMASYNC_POSTREAD); 679 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 680 m_freem(sbuf->m); 681 } 682 bus_dmamap_destroy(sc->rxbuf_dmat, sbuf->map); 683 } 684 bus_dma_tag_destroy(sc->rxbuf_dmat); 685 } 686 } 687 688 static int 689 ipw_shutdown(device_t dev) 690 { 691 struct ipw_softc *sc = device_get_softc(dev); 692 693 ipw_stop(sc); 694 695 return 0; 696 } 697 698 static int 699 ipw_suspend(device_t dev) 700 { 701 struct ipw_softc *sc = device_get_softc(dev); 702 703 ipw_stop(sc); 704 705 return 0; 706 } 707 708 static int 709 ipw_resume(device_t dev) 710 { 711 struct ipw_softc *sc = device_get_softc(dev); 712 struct ifnet *ifp = sc->sc_ic.ic_ifp; 713 714 mtx_lock(&sc->sc_mtx); 715 716 pci_write_config(dev, 0x41, 0, 1); 717 718 if (ifp->if_flags & IFF_UP) { 719 ifp->if_init(ifp->if_softc); 720 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 721 ifp->if_start(ifp); 722 } 723 724 mtx_unlock(&sc->sc_mtx); 725 726 return 0; 727 } 728 729 static int 730 ipw_media_change(struct ifnet *ifp) 731 { 732 struct ipw_softc *sc = ifp->if_softc; 733 int error; 734 735 mtx_lock(&sc->sc_mtx); 736 737 error = ieee80211_media_change(ifp); 738 if (error != ENETRESET) { 739 mtx_unlock(&sc->sc_mtx); 740 return error; 741 } 742 743 if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 744 ipw_init(sc); 745 746 mtx_unlock(&sc->sc_mtx); 747 748 return 0; 749 } 750 751 /* 752 * The firmware automatically adapts the transmit speed. We report its current 753 * value here. 754 */ 755 static void 756 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 757 { 758 #define N(a) (sizeof (a) / sizeof (a[0])) 759 struct ipw_softc *sc = ifp->if_softc; 760 struct ieee80211com *ic = &sc->sc_ic; 761 static const struct { 762 uint32_t val; 763 int rate; 764 } rates[] = { 765 { IPW_RATE_DS1, 2 }, 766 { IPW_RATE_DS2, 4 }, 767 { IPW_RATE_DS5, 11 }, 768 { IPW_RATE_DS11, 22 }, 769 }; 770 uint32_t val; 771 int rate, i; 772 773 imr->ifm_status = IFM_AVALID; 774 imr->ifm_active = IFM_IEEE80211; 775 if (ic->ic_state == IEEE80211_S_RUN) 776 imr->ifm_status |= IFM_ACTIVE; 777 778 /* read current transmission rate from adapter */ 779 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; 780 781 /* convert ipw rate to 802.11 rate */ 782 for (i = 0; i < N(rates) && rates[i].val != val; i++); 783 rate = (i < N(rates)) ? rates[i].rate : 0; 784 785 imr->ifm_active |= IFM_IEEE80211_11B; 786 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); 787 switch (ic->ic_opmode) { 788 case IEEE80211_M_STA: 789 break; 790 791 case IEEE80211_M_IBSS: 792 imr->ifm_active |= IFM_IEEE80211_IBSS; 793 break; 794 795 case IEEE80211_M_MONITOR: 796 imr->ifm_active |= IFM_IEEE80211_MONITOR; 797 break; 798 799 case IEEE80211_M_AHDEMO: 800 case IEEE80211_M_HOSTAP: 801 case IEEE80211_M_WDS: 802 /* should not get there */ 803 break; 804 } 805 #undef N 806 } 807 808 static int 809 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 810 { 811 struct ifnet *ifp = ic->ic_ifp; 812 struct ipw_softc *sc = ifp->if_softc; 813 uint8_t macaddr[IEEE80211_ADDR_LEN]; 814 uint32_t len; 815 816 switch (nstate) { 817 case IEEE80211_S_RUN: 818 DELAY(200); /* firmware needs a short delay here */ 819 820 len = IEEE80211_ADDR_LEN; 821 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); 822 823 #if 0 824 ni = ieee80211_find_node(&ic->ic_scan, macaddr); 825 if (ni == NULL) 826 break; 827 828 ieee80211_ref_node(ni); 829 ieee80211_sta_join(ic, ni); 830 ieee80211_node_authorize(ni); 831 832 if (ic->ic_opmode == IEEE80211_M_STA) 833 ieee80211_notify_node_join(ic, ni, 1); 834 #endif 835 break; 836 837 case IEEE80211_S_INIT: 838 case IEEE80211_S_SCAN: 839 case IEEE80211_S_AUTH: 840 case IEEE80211_S_ASSOC: 841 break; 842 } 843 844 ic->ic_state = nstate; 845 846 return 0; 847 } 848 849 /* 850 * Read 16 bits at address 'addr' from the serial EEPROM. 851 */ 852 static uint16_t 853 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) 854 { 855 uint32_t tmp; 856 uint16_t val; 857 int n; 858 859 /* clock C once before the first command */ 860 IPW_EEPROM_CTL(sc, 0); 861 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 862 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 863 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 864 865 /* write start bit (1) */ 866 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 867 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 868 869 /* write READ opcode (10) */ 870 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); 871 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); 872 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 873 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 874 875 /* write address A7-A0 */ 876 for (n = 7; n >= 0; n--) { 877 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 878 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); 879 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | 880 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); 881 } 882 883 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 884 885 /* read data Q15-Q0 */ 886 val = 0; 887 for (n = 15; n >= 0; n--) { 888 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); 889 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 890 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); 891 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; 892 } 893 894 IPW_EEPROM_CTL(sc, 0); 895 896 /* clear Chip Select and clock C */ 897 IPW_EEPROM_CTL(sc, IPW_EEPROM_S); 898 IPW_EEPROM_CTL(sc, 0); 899 IPW_EEPROM_CTL(sc, IPW_EEPROM_C); 900 901 return le16toh(val); 902 } 903 904 static void 905 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 906 { 907 struct ipw_cmd *cmd; 908 909 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 910 911 cmd = mtod(sbuf->m, struct ipw_cmd *); 912 913 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), 914 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), 915 le32toh(cmd->status))); 916 917 wakeup(sc); 918 } 919 920 static void 921 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) 922 { 923 struct ieee80211com *ic = &sc->sc_ic; 924 uint32_t state; 925 926 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 927 928 state = le32toh(*mtod(sbuf->m, uint32_t *)); 929 930 DPRINTFN(2, ("entering state %u\n", state)); 931 932 switch (state) { 933 case IPW_STATE_ASSOCIATED: 934 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 935 break; 936 937 case IPW_STATE_SCANNING: 938 /* don't leave run state on background scan */ 939 if (ic->ic_state != IEEE80211_S_RUN) 940 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 941 942 ic->ic_flags |= IEEE80211_F_SCAN; 943 break; 944 945 case IPW_STATE_SCAN_COMPLETE: 946 ieee80211_notify_scan_done(ic); 947 ic->ic_flags &= ~IEEE80211_F_SCAN; 948 break; 949 950 case IPW_STATE_ASSOCIATION_LOST: 951 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 952 break; 953 954 case IPW_STATE_RADIO_DISABLED: 955 ic->ic_ifp->if_flags &= ~IFF_UP; 956 ipw_stop(sc); 957 break; 958 } 959 } 960 961 /* 962 * XXX: Hack to set the current channel to the value advertised in beacons or 963 * probe responses. Only used during AP detection. 964 */ 965 static void 966 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) 967 { 968 struct ieee80211_frame *wh; 969 uint8_t subtype; 970 uint8_t *frm, *efrm; 971 972 wh = mtod(m, struct ieee80211_frame *); 973 974 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) 975 return; 976 977 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 978 979 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && 980 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) 981 return; 982 983 frm = (uint8_t *)(wh + 1); 984 efrm = mtod(m, uint8_t *) + m->m_len; 985 986 frm += 12; /* skip tstamp, bintval and capinfo fields */ 987 while (frm < efrm) { 988 if (*frm == IEEE80211_ELEMID_DSPARMS) 989 #if IEEE80211_CHAN_MAX < 255 990 if (frm[2] <= IEEE80211_CHAN_MAX) 991 #endif 992 ic->ic_bsschan = ieee80211_find_channel(ic, 993 ieee80211_ieee2mhz(frm[2], 0), 994 IEEE80211_MODE_AUTO); 995 996 frm += frm[1] + 2; 997 } 998 } 999 1000 static void 1001 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, 1002 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) 1003 { 1004 struct ieee80211com *ic = &sc->sc_ic; 1005 struct ifnet *ifp = ic->ic_ifp; 1006 struct mbuf *mnew, *m; 1007 struct ieee80211_frame *wh; 1008 struct ieee80211_node *ni; 1009 bus_addr_t physaddr; 1010 int error; 1011 1012 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), 1013 status->rssi)); 1014 1015 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) || 1016 le32toh(status->len) > MCLBYTES) 1017 return; 1018 1019 /* 1020 * Try to allocate a new mbuf for this ring element and load it before 1021 * processing the current mbuf. If the ring element cannot be loaded, 1022 * drop the received packet and reuse the old mbuf. In the unlikely 1023 * case that the old mbuf can't be reloaded either, explicitly panic. 1024 */ 1025 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1026 if (mnew == NULL) { 1027 ifp->if_ierrors++; 1028 return; 1029 } 1030 1031 bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); 1032 bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); 1033 1034 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, mtod(mnew, void *), 1035 MCLBYTES, ipw_dma_map_addr, &physaddr, 0); 1036 if (error != 0) { 1037 m_freem(mnew); 1038 1039 /* try to reload the old mbuf */ 1040 error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, 1041 mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, 1042 &physaddr, 0); 1043 if (error != 0) { 1044 /* very unlikely that it will fail... */ 1045 panic("%s: could not load old rx mbuf", 1046 device_get_name(sc->sc_dev)); 1047 } 1048 ifp->if_ierrors++; 1049 return; 1050 } 1051 1052 /* 1053 * New mbuf successfully loaded, update Rx ring and continue 1054 * processing. 1055 */ 1056 m = sbuf->m; 1057 sbuf->m = mnew; 1058 sbd->bd->physaddr = htole32(physaddr); 1059 1060 /* finalize mbuf */ 1061 m->m_pkthdr.rcvif = ifp; 1062 m->m_pkthdr.len = m->m_len = le32toh(status->len); 1063 1064 if (bpf_peers_present(sc->sc_drvbpf)) { 1065 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; 1066 1067 tap->wr_flags = 0; 1068 tap->wr_antsignal = status->rssi; 1069 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1070 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1071 1072 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1073 } 1074 1075 if (ic->ic_state == IEEE80211_S_SCAN) 1076 ipw_fix_channel(ic, m); 1077 1078 wh = mtod(m, struct ieee80211_frame *); 1079 mtx_unlock(&sc->sc_mtx); 1080 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1081 1082 /* send the frame to the 802.11 layer */ 1083 ieee80211_input(ic, m, ni, status->rssi, -95/*XXX*/, 0); 1084 1085 /* node is no longer needed */ 1086 ieee80211_free_node(ni); 1087 mtx_lock(&sc->sc_mtx); 1088 1089 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1090 } 1091 1092 static void 1093 ipw_rx_intr(struct ipw_softc *sc) 1094 { 1095 struct ipw_status *status; 1096 struct ipw_soft_bd *sbd; 1097 struct ipw_soft_buf *sbuf; 1098 uint32_t r, i; 1099 1100 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1101 return; 1102 1103 r = CSR_READ_4(sc, IPW_CSR_RX_READ); 1104 1105 bus_dmamap_sync(sc->status_dmat, sc->status_map, BUS_DMASYNC_POSTREAD); 1106 1107 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { 1108 status = &sc->status_list[i]; 1109 sbd = &sc->srbd_list[i]; 1110 sbuf = sbd->priv; 1111 1112 switch (le16toh(status->code) & 0xf) { 1113 case IPW_STATUS_CODE_COMMAND: 1114 ipw_command_intr(sc, sbuf); 1115 break; 1116 1117 case IPW_STATUS_CODE_NEWSTATE: 1118 ipw_newstate_intr(sc, sbuf); 1119 break; 1120 1121 case IPW_STATUS_CODE_DATA_802_3: 1122 case IPW_STATUS_CODE_DATA_802_11: 1123 ipw_data_intr(sc, status, sbd, sbuf); 1124 break; 1125 1126 case IPW_STATUS_CODE_NOTIFICATION: 1127 DPRINTFN(2, ("received notification\n")); 1128 break; 1129 1130 default: 1131 device_printf(sc->sc_dev, "unknown status code %u\n", 1132 le16toh(status->code)); 1133 } 1134 1135 /* firmware was killed, stop processing received frames */ 1136 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1137 return; 1138 1139 sbd->bd->flags = 0; 1140 } 1141 1142 bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); 1143 1144 /* kick the firmware */ 1145 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; 1146 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 1147 } 1148 1149 static void 1150 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) 1151 { 1152 struct ipw_soft_hdr *shdr; 1153 struct ipw_soft_buf *sbuf; 1154 1155 switch (sbd->type) { 1156 case IPW_SBD_TYPE_COMMAND: 1157 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, 1158 BUS_DMASYNC_POSTWRITE); 1159 bus_dmamap_unload(sc->cmd_dmat, sc->cmd_map); 1160 break; 1161 1162 case IPW_SBD_TYPE_HEADER: 1163 shdr = sbd->priv; 1164 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_POSTWRITE); 1165 bus_dmamap_unload(sc->hdr_dmat, shdr->map); 1166 SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); 1167 break; 1168 1169 case IPW_SBD_TYPE_DATA: 1170 sbuf = sbd->priv; 1171 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, 1172 BUS_DMASYNC_POSTWRITE); 1173 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1174 SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); 1175 1176 if (sbuf->m->m_flags & M_TXCB) 1177 ieee80211_process_callback(sbuf->ni, sbuf->m, 0/*XXX*/); 1178 m_freem(sbuf->m); 1179 ieee80211_free_node(sbuf->ni); 1180 1181 sc->sc_tx_timer = 0; 1182 break; 1183 } 1184 1185 sbd->type = IPW_SBD_TYPE_NOASSOC; 1186 } 1187 1188 static void 1189 ipw_tx_intr(struct ipw_softc *sc) 1190 { 1191 struct ifnet *ifp = sc->sc_ic.ic_ifp; 1192 struct ipw_soft_bd *sbd; 1193 uint32_t r, i; 1194 1195 if (!(sc->flags & IPW_FLAG_FW_INITED)) 1196 return; 1197 1198 r = CSR_READ_4(sc, IPW_CSR_TX_READ); 1199 1200 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { 1201 sbd = &sc->stbd_list[i]; 1202 1203 if (sbd->type == IPW_SBD_TYPE_DATA) 1204 ifp->if_opackets++; 1205 1206 ipw_release_sbd(sc, sbd); 1207 sc->txfree++; 1208 } 1209 1210 /* remember what the firmware has processed */ 1211 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; 1212 1213 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1214 ipw_start(ifp); 1215 } 1216 1217 static void 1218 ipw_intr(void *arg) 1219 { 1220 struct ipw_softc *sc = arg; 1221 uint32_t r; 1222 1223 mtx_lock(&sc->sc_mtx); 1224 1225 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) { 1226 mtx_unlock(&sc->sc_mtx); 1227 return; 1228 } 1229 1230 /* disable interrupts */ 1231 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1232 1233 /* acknowledge all interrupts */ 1234 CSR_WRITE_4(sc, IPW_CSR_INTR, r); 1235 1236 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { 1237 device_printf(sc->sc_dev, "firmware error\n"); 1238 taskqueue_enqueue_fast(taskqueue_fast, &sc->sc_init_task); 1239 r = 0; /* don't process more interrupts */ 1240 } 1241 1242 if (r & IPW_INTR_FW_INIT_DONE) 1243 wakeup(sc); 1244 1245 if (r & IPW_INTR_RX_TRANSFER) 1246 ipw_rx_intr(sc); 1247 1248 if (r & IPW_INTR_TX_TRANSFER) 1249 ipw_tx_intr(sc); 1250 1251 /* re-enable interrupts */ 1252 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1253 1254 mtx_unlock(&sc->sc_mtx); 1255 } 1256 1257 static void 1258 ipw_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1259 { 1260 if (error != 0) 1261 return; 1262 1263 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1264 1265 *(bus_addr_t *)arg = segs[0].ds_addr; 1266 } 1267 1268 /* 1269 * Send a command to the firmware and wait for the acknowledgement. 1270 */ 1271 static int 1272 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) 1273 { 1274 struct ipw_soft_bd *sbd; 1275 bus_addr_t physaddr; 1276 int error; 1277 1278 sbd = &sc->stbd_list[sc->txcur]; 1279 1280 error = bus_dmamap_load(sc->cmd_dmat, sc->cmd_map, &sc->cmd, 1281 sizeof (struct ipw_cmd), ipw_dma_map_addr, &physaddr, 0); 1282 if (error != 0) { 1283 device_printf(sc->sc_dev, "could not map command DMA memory\n"); 1284 return error; 1285 } 1286 1287 sc->cmd.type = htole32(type); 1288 sc->cmd.subtype = 0; 1289 sc->cmd.len = htole32(len); 1290 sc->cmd.seq = 0; 1291 memcpy(sc->cmd.data, data, len); 1292 1293 sbd->type = IPW_SBD_TYPE_COMMAND; 1294 sbd->bd->physaddr = htole32(physaddr); 1295 sbd->bd->len = htole32(sizeof (struct ipw_cmd)); 1296 sbd->bd->nfrag = 1; 1297 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | 1298 IPW_BD_FLAG_TX_LAST_FRAGMENT; 1299 1300 bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, BUS_DMASYNC_PREWRITE); 1301 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1302 1303 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); 1304 1305 /* kick firmware */ 1306 sc->txfree--; 1307 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1308 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1309 1310 /* wait at most one second for command to complete */ 1311 return msleep(sc, &sc->sc_mtx, 0, "ipwcmd", hz); 1312 } 1313 1314 static int 1315 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) 1316 { 1317 struct ipw_softc *sc = ifp->if_softc; 1318 struct ieee80211com *ic = &sc->sc_ic; 1319 struct ieee80211_frame *wh; 1320 struct ipw_soft_bd *sbd; 1321 struct ipw_soft_hdr *shdr; 1322 struct ipw_soft_buf *sbuf; 1323 struct ieee80211_key *k; 1324 struct mbuf *mnew; 1325 bus_dma_segment_t segs[IPW_MAX_NSEG]; 1326 bus_addr_t physaddr; 1327 int nsegs, error, i; 1328 1329 wh = mtod(m0, struct ieee80211_frame *); 1330 1331 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1332 k = ieee80211_crypto_encap(ic, ni, m0); 1333 if (k == NULL) { 1334 m_freem(m0); 1335 return ENOBUFS; 1336 } 1337 1338 /* packet header may have moved, reset our local pointer */ 1339 wh = mtod(m0, struct ieee80211_frame *); 1340 } 1341 1342 if (bpf_peers_present(sc->sc_drvbpf)) { 1343 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; 1344 1345 tap->wt_flags = 0; 1346 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1347 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1348 1349 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); 1350 } 1351 1352 shdr = SLIST_FIRST(&sc->free_shdr); 1353 sbuf = SLIST_FIRST(&sc->free_sbuf); 1354 KASSERT(shdr != NULL && sbuf != NULL, ("empty sw hdr/buf pool")); 1355 1356 shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); 1357 shdr->hdr.subtype = 0; 1358 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; 1359 shdr->hdr.encrypt = 0; 1360 shdr->hdr.keyidx = 0; 1361 shdr->hdr.keysz = 0; 1362 shdr->hdr.fragmentsz = 0; 1363 IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); 1364 if (ic->ic_opmode == IEEE80211_M_STA) 1365 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); 1366 else 1367 IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); 1368 1369 /* trim IEEE802.11 header */ 1370 m_adj(m0, sizeof (struct ieee80211_frame)); 1371 1372 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, segs, 1373 &nsegs, 0); 1374 if (error != 0 && error != EFBIG) { 1375 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1376 error); 1377 m_freem(m0); 1378 return error; 1379 } 1380 if (error != 0) { 1381 mnew = m_defrag(m0, M_DONTWAIT); 1382 if (mnew == NULL) { 1383 device_printf(sc->sc_dev, 1384 "could not defragment mbuf\n"); 1385 m_freem(m0); 1386 return ENOBUFS; 1387 } 1388 m0 = mnew; 1389 1390 error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, 1391 segs, &nsegs, 0); 1392 if (error != 0) { 1393 device_printf(sc->sc_dev, 1394 "could not map mbuf (error %d)\n", error); 1395 m_freem(m0); 1396 return error; 1397 } 1398 } 1399 1400 error = bus_dmamap_load(sc->hdr_dmat, shdr->map, &shdr->hdr, 1401 sizeof (struct ipw_hdr), ipw_dma_map_addr, &physaddr, 0); 1402 if (error != 0) { 1403 device_printf(sc->sc_dev, "could not map header DMA memory\n"); 1404 bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); 1405 m_freem(m0); 1406 return error; 1407 } 1408 1409 SLIST_REMOVE_HEAD(&sc->free_sbuf, next); 1410 SLIST_REMOVE_HEAD(&sc->free_shdr, next); 1411 1412 sbd = &sc->stbd_list[sc->txcur]; 1413 sbd->type = IPW_SBD_TYPE_HEADER; 1414 sbd->priv = shdr; 1415 sbd->bd->physaddr = htole32(physaddr); 1416 sbd->bd->len = htole32(sizeof (struct ipw_hdr)); 1417 sbd->bd->nfrag = 1 + nsegs; 1418 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | 1419 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1420 1421 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, %6D, %6D)\n", 1422 shdr->hdr.type, shdr->hdr.subtype, shdr->hdr.encrypted, 1423 shdr->hdr.encrypt, shdr->hdr.src_addr, ":", shdr->hdr.dst_addr, 1424 ":")); 1425 1426 sc->txfree--; 1427 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1428 1429 sbuf->m = m0; 1430 sbuf->ni = ni; 1431 1432 for (i = 0; i < nsegs; i++) { 1433 sbd = &sc->stbd_list[sc->txcur]; 1434 1435 sbd->bd->physaddr = htole32(segs[i].ds_addr); 1436 sbd->bd->len = htole32(segs[i].ds_len); 1437 sbd->bd->nfrag = 0; 1438 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; 1439 if (i == nsegs - 1) { 1440 sbd->type = IPW_SBD_TYPE_DATA; 1441 sbd->priv = sbuf; 1442 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; 1443 } else { 1444 sbd->type = IPW_SBD_TYPE_NOASSOC; 1445 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; 1446 } 1447 1448 DPRINTFN(5, ("sending fragment (%d, %d)\n", i, segs[i].ds_len)); 1449 1450 sc->txfree--; 1451 sc->txcur = (sc->txcur + 1) % IPW_NTBD; 1452 } 1453 1454 bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_PREWRITE); 1455 bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, BUS_DMASYNC_PREWRITE); 1456 bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); 1457 1458 /* kick firmware */ 1459 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 1460 1461 return 0; 1462 } 1463 1464 static void 1465 ipw_start(struct ifnet *ifp) 1466 { 1467 struct ipw_softc *sc = ifp->if_softc; 1468 struct ieee80211com *ic = &sc->sc_ic; 1469 struct mbuf *m0; 1470 struct ether_header *eh; 1471 struct ieee80211_node *ni; 1472 1473 mtx_lock(&sc->sc_mtx); 1474 1475 if (ic->ic_state != IEEE80211_S_RUN) { 1476 mtx_unlock(&sc->sc_mtx); 1477 return; 1478 } 1479 1480 for (;;) { 1481 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 1482 if (m0 == NULL) 1483 break; 1484 1485 if (sc->txfree < 1 + IPW_MAX_NSEG) { 1486 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 1487 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1488 break; 1489 } 1490 1491 if (m0->m_len < sizeof (struct ether_header) && 1492 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) 1493 continue; 1494 1495 eh = mtod(m0, struct ether_header *); 1496 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1497 if (ni == NULL) { 1498 m_freem(m0); 1499 continue; 1500 } 1501 BPF_MTAP(ifp, m0); 1502 1503 m0 = ieee80211_encap(ic, m0, ni); 1504 if (m0 == NULL) { 1505 ieee80211_free_node(ni); 1506 continue; 1507 } 1508 1509 if (bpf_peers_present(ic->ic_rawbpf)) 1510 bpf_mtap(ic->ic_rawbpf, m0); 1511 1512 if (ipw_tx_start(ifp, m0, ni) != 0) { 1513 ieee80211_free_node(ni); 1514 ifp->if_oerrors++; 1515 break; 1516 } 1517 1518 /* start watchdog timer */ 1519 sc->sc_tx_timer = 5; 1520 ifp->if_timer = 1; 1521 } 1522 1523 mtx_unlock(&sc->sc_mtx); 1524 } 1525 1526 static void 1527 ipw_watchdog(struct ifnet *ifp) 1528 { 1529 struct ipw_softc *sc = ifp->if_softc; 1530 1531 mtx_lock(&sc->sc_mtx); 1532 1533 ifp->if_timer = 0; 1534 1535 if (sc->sc_tx_timer > 0) { 1536 if (--sc->sc_tx_timer == 0) { 1537 if_printf(ifp, "device timeout\n"); 1538 ifp->if_oerrors++; 1539 taskqueue_enqueue_fast(taskqueue_fast, 1540 &sc->sc_init_task); 1541 mtx_unlock(&sc->sc_mtx); 1542 return; 1543 } 1544 ifp->if_timer = 1; 1545 } 1546 1547 mtx_unlock(&sc->sc_mtx); 1548 } 1549 1550 static int 1551 ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1552 { 1553 struct ipw_softc *sc = ifp->if_softc; 1554 struct ieee80211com *ic = &sc->sc_ic; 1555 int error = 0; 1556 1557 mtx_lock(&sc->sc_mtx); 1558 1559 switch (cmd) { 1560 case SIOCSIFFLAGS: 1561 if (ifp->if_flags & IFF_UP) { 1562 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1563 ipw_init(sc); 1564 } else { 1565 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1566 ipw_stop(sc); 1567 } 1568 break; 1569 1570 default: 1571 error = ieee80211_ioctl(ic, cmd, data); 1572 } 1573 1574 if (error == ENETRESET) { 1575 if ((ifp->if_flags & IFF_UP) && 1576 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1577 ipw_init(sc); 1578 error = 0; 1579 } 1580 1581 mtx_unlock(&sc->sc_mtx); 1582 1583 return error; 1584 } 1585 1586 static void 1587 ipw_stop_master(struct ipw_softc *sc) 1588 { 1589 uint32_t tmp; 1590 int ntries; 1591 1592 /* disable interrupts */ 1593 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); 1594 1595 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); 1596 for (ntries = 0; ntries < 50; ntries++) { 1597 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) 1598 break; 1599 DELAY(10); 1600 } 1601 if (ntries == 50) 1602 device_printf(sc->sc_dev, "timeout waiting for master\n"); 1603 1604 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1605 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_PRINCETON_RESET); 1606 1607 sc->flags &= ~IPW_FLAG_FW_INITED; 1608 } 1609 1610 static int 1611 ipw_reset(struct ipw_softc *sc) 1612 { 1613 uint32_t tmp; 1614 int ntries; 1615 1616 ipw_stop_master(sc); 1617 1618 /* move adapter to D0 state */ 1619 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1620 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1621 1622 /* wait for clock stabilization */ 1623 for (ntries = 0; ntries < 1000; ntries++) { 1624 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) 1625 break; 1626 DELAY(200); 1627 } 1628 if (ntries == 1000) 1629 return EIO; 1630 1631 tmp = CSR_READ_4(sc, IPW_CSR_RST); 1632 CSR_WRITE_4(sc, IPW_CSR_RST, tmp | IPW_RST_SW_RESET); 1633 1634 DELAY(10); 1635 1636 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1637 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_INIT); 1638 1639 return 0; 1640 } 1641 1642 /* 1643 * Upload the microcode to the device. 1644 */ 1645 static int 1646 ipw_load_ucode(struct ipw_softc *sc, const char *uc, int size) 1647 { 1648 int ntries; 1649 1650 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); 1651 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1652 1653 MEM_WRITE_2(sc, 0x220000, 0x0703); 1654 MEM_WRITE_2(sc, 0x220000, 0x0707); 1655 1656 MEM_WRITE_1(sc, 0x210014, 0x72); 1657 MEM_WRITE_1(sc, 0x210014, 0x72); 1658 1659 MEM_WRITE_1(sc, 0x210000, 0x40); 1660 MEM_WRITE_1(sc, 0x210000, 0x00); 1661 MEM_WRITE_1(sc, 0x210000, 0x40); 1662 1663 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); 1664 1665 MEM_WRITE_1(sc, 0x210000, 0x00); 1666 MEM_WRITE_1(sc, 0x210000, 0x00); 1667 MEM_WRITE_1(sc, 0x210000, 0x80); 1668 1669 MEM_WRITE_2(sc, 0x220000, 0x0703); 1670 MEM_WRITE_2(sc, 0x220000, 0x0707); 1671 1672 MEM_WRITE_1(sc, 0x210014, 0x72); 1673 MEM_WRITE_1(sc, 0x210014, 0x72); 1674 1675 MEM_WRITE_1(sc, 0x210000, 0x00); 1676 MEM_WRITE_1(sc, 0x210000, 0x80); 1677 1678 for (ntries = 0; ntries < 10; ntries++) { 1679 if (MEM_READ_1(sc, 0x210000) & 1) 1680 break; 1681 DELAY(10); 1682 } 1683 if (ntries == 10) { 1684 device_printf(sc->sc_dev, 1685 "timeout waiting for ucode to initialize\n"); 1686 return EIO; 1687 } 1688 1689 MEM_WRITE_4(sc, 0x3000e0, 0); 1690 1691 return 0; 1692 } 1693 1694 /* set of macros to handle unaligned little endian data in firmware image */ 1695 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) 1696 #define GETLE16(p) ((p)[0] | (p)[1] << 8) 1697 static int 1698 ipw_load_firmware(struct ipw_softc *sc, const char *fw, int size) 1699 { 1700 const uint8_t *p, *end; 1701 uint32_t tmp, dst; 1702 uint16_t len; 1703 int error; 1704 1705 p = fw; 1706 end = fw + size; 1707 while (p < end) { 1708 dst = GETLE32(p); p += 4; 1709 len = GETLE16(p); p += 2; 1710 1711 ipw_write_mem_1(sc, dst, p, len); 1712 p += len; 1713 } 1714 1715 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | 1716 IPW_IO_LED_OFF); 1717 1718 /* enable interrupts */ 1719 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); 1720 1721 /* kick the firmware */ 1722 CSR_WRITE_4(sc, IPW_CSR_RST, 0); 1723 1724 tmp = CSR_READ_4(sc, IPW_CSR_CTL); 1725 CSR_WRITE_4(sc, IPW_CSR_CTL, tmp | IPW_CTL_ALLOW_STANDBY); 1726 1727 /* wait at most one second for firmware initialization to complete */ 1728 if ((error = msleep(sc, &sc->sc_mtx, 0, "ipwinit", hz)) != 0) { 1729 device_printf(sc->sc_dev, "timeout waiting for firmware " 1730 "initialization to complete\n"); 1731 return error; 1732 } 1733 1734 tmp = CSR_READ_4(sc, IPW_CSR_IO); 1735 CSR_WRITE_4(sc, IPW_CSR_IO, tmp | IPW_IO_GPIO1_MASK | 1736 IPW_IO_GPIO3_MASK); 1737 1738 return 0; 1739 } 1740 1741 static int 1742 ipw_config(struct ipw_softc *sc) 1743 { 1744 struct ieee80211com *ic = &sc->sc_ic; 1745 struct ifnet *ifp = ic->ic_ifp; 1746 struct ipw_security security; 1747 struct ieee80211_key *k; 1748 struct ipw_wep_key wepkey; 1749 struct ipw_scan_options options; 1750 struct ipw_configuration config; 1751 uint32_t data; 1752 int error, i; 1753 1754 switch (ic->ic_opmode) { 1755 case IEEE80211_M_STA: 1756 case IEEE80211_M_HOSTAP: 1757 case IEEE80211_M_WDS: /* XXX */ 1758 data = htole32(IPW_MODE_BSS); 1759 break; 1760 case IEEE80211_M_IBSS: 1761 case IEEE80211_M_AHDEMO: 1762 data = htole32(IPW_MODE_IBSS); 1763 break; 1764 case IEEE80211_M_MONITOR: 1765 data = htole32(IPW_MODE_MONITOR); 1766 break; 1767 } 1768 DPRINTF(("Setting mode to %u\n", le32toh(data))); 1769 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); 1770 if (error != 0) 1771 return error; 1772 1773 if (ic->ic_opmode == IEEE80211_M_IBSS || 1774 ic->ic_opmode == IEEE80211_M_MONITOR) { 1775 data = htole32(ieee80211_chan2ieee(ic, ic->ic_curchan)); 1776 DPRINTF(("Setting channel to %u\n", le32toh(data))); 1777 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); 1778 if (error != 0) 1779 return error; 1780 } 1781 1782 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1783 DPRINTF(("Enabling adapter\n")); 1784 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1785 } 1786 1787 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 1788 DPRINTF(("Setting MAC address to %6D\n", ic->ic_myaddr, ":")); 1789 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, 1790 IEEE80211_ADDR_LEN); 1791 if (error != 0) 1792 return error; 1793 1794 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | 1795 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); 1796 if (ic->ic_opmode == IEEE80211_M_IBSS) 1797 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); 1798 if (ifp->if_flags & IFF_PROMISC) 1799 config.flags |= htole32(IPW_CFG_PROMISCUOUS); 1800 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ 1801 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ 1802 DPRINTF(("Setting configuration to 0x%x\n", le32toh(config.flags))); 1803 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); 1804 if (error != 0) 1805 return error; 1806 1807 data = htole32(0x3); /* 1, 2 */ 1808 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); 1809 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); 1810 if (error != 0) 1811 return error; 1812 1813 data = htole32(0xf); /* 1, 2, 5.5, 11 */ 1814 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); 1815 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); 1816 if (error != 0) 1817 return error; 1818 1819 data = htole32(IPW_POWER_MODE_CAM); 1820 DPRINTF(("Setting power mode to %u\n", le32toh(data))); 1821 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); 1822 if (error != 0) 1823 return error; 1824 1825 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1826 data = htole32(32); /* default value */ 1827 DPRINTF(("Setting tx power index to %u\n", le32toh(data))); 1828 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, 1829 sizeof data); 1830 if (error != 0) 1831 return error; 1832 } 1833 1834 data = htole32(ic->ic_rtsthreshold); 1835 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); 1836 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); 1837 if (error != 0) 1838 return error; 1839 1840 data = htole32(ic->ic_fragthreshold); 1841 DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); 1842 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); 1843 if (error != 0) 1844 return error; 1845 1846 #ifdef IPW_DEBUG 1847 if (ipw_debug > 0) { 1848 printf("Setting ESSID to "); 1849 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); 1850 printf("\n"); 1851 } 1852 #endif 1853 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_ssid[0].ssid, 1854 ic->ic_des_ssid[0].len); 1855 if (error != 0) 1856 return error; 1857 1858 /* no mandatory BSSID */ 1859 DPRINTF(("Setting mandatory BSSID to null\n")); 1860 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); 1861 if (error != 0) 1862 return error; 1863 1864 if (ic->ic_flags & IEEE80211_F_DESBSSID) { 1865 DPRINTF(("Setting desired BSSID to %6D\n", ic->ic_des_bssid, 1866 ":")); 1867 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, 1868 ic->ic_des_bssid, IEEE80211_ADDR_LEN); 1869 if (error != 0) 1870 return error; 1871 } 1872 1873 memset(&security, 0, sizeof security); 1874 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? 1875 IPW_AUTH_SHARED : IPW_AUTH_OPEN; 1876 security.ciphers = htole32(IPW_CIPHER_NONE); 1877 DPRINTF(("Setting authmode to %u\n", security.authmode)); 1878 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, 1879 sizeof security); 1880 if (error != 0) 1881 return error; 1882 1883 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1884 k = ic->ic_crypto.cs_nw_keys; 1885 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { 1886 if (k->wk_keylen == 0) 1887 continue; 1888 1889 wepkey.idx = i; 1890 wepkey.len = k->wk_keylen; 1891 memset(wepkey.key, 0, sizeof wepkey.key); 1892 memcpy(wepkey.key, k->wk_key, k->wk_keylen); 1893 DPRINTF(("Setting wep key index %u len %u\n", 1894 wepkey.idx, wepkey.len)); 1895 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, 1896 sizeof wepkey); 1897 if (error != 0) 1898 return error; 1899 } 1900 1901 data = htole32(ic->ic_crypto.cs_def_txkey); 1902 DPRINTF(("Setting wep tx key index to %u\n", le32toh(data))); 1903 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, 1904 sizeof data); 1905 if (error != 0) 1906 return error; 1907 } 1908 1909 data = htole32((ic->ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); 1910 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); 1911 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); 1912 if (error != 0) 1913 return error; 1914 1915 #if 0 1916 struct ipw_wpa_ie ie; 1917 1918 memset(&ie, 0, sizeof ie); 1919 ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); 1920 DPRINTF(("Setting wpa ie\n")); 1921 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); 1922 if (error != 0) 1923 return error; 1924 #endif 1925 1926 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1927 data = htole32(ic->ic_bintval); 1928 DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); 1929 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, 1930 sizeof data); 1931 if (error != 0) 1932 return error; 1933 } 1934 1935 options.flags = 0; 1936 options.channels = htole32(0x3fff); /* scan channels 1-14 */ 1937 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); 1938 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); 1939 if (error != 0) 1940 return error; 1941 1942 /* finally, enable adapter (start scanning for an access point) */ 1943 DPRINTF(("Enabling adapter\n")); 1944 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); 1945 } 1946 1947 /* 1948 * Handler for sc_init_task. This is a simple wrapper around ipw_init(). 1949 * It is called on firmware panics or on watchdog timeouts. 1950 */ 1951 static void 1952 ipw_init_task(void *context, int pending) 1953 { 1954 ipw_init(context); 1955 } 1956 1957 static void 1958 ipw_init(void *priv) 1959 { 1960 struct ipw_softc *sc = priv; 1961 struct ieee80211com *ic = &sc->sc_ic; 1962 struct ifnet *ifp = ic->ic_ifp; 1963 const struct firmware *fp; 1964 const struct ipw_firmware_hdr *hdr; 1965 const char *imagename, *fw; 1966 int owned; 1967 1968 /* 1969 * ipw_init() is exposed through ifp->if_init so it might be called 1970 * without the driver's lock held. Since msleep() doesn't like being 1971 * called on a recursed mutex, we acquire the driver's lock only if 1972 * we're not already holding it. 1973 */ 1974 if (!(owned = mtx_owned(&sc->sc_mtx))) 1975 mtx_lock(&sc->sc_mtx); 1976 1977 /* 1978 * Avoid re-entrant calls. We need to release the mutex in ipw_init() 1979 * when loading the firmware and we don't want to be called during this 1980 * operation. 1981 */ 1982 if (sc->flags & IPW_FLAG_INIT_LOCKED) { 1983 if (!owned) 1984 mtx_unlock(&sc->sc_mtx); 1985 return; 1986 } 1987 sc->flags |= IPW_FLAG_INIT_LOCKED; 1988 1989 ipw_stop(sc); 1990 1991 if (ipw_reset(sc) != 0) { 1992 device_printf(sc->sc_dev, "could not reset adapter\n"); 1993 goto fail1; 1994 } 1995 1996 switch (ic->ic_opmode) { 1997 case IEEE80211_M_STA: 1998 imagename = "ipw_bss"; 1999 break; 2000 case IEEE80211_M_IBSS: 2001 imagename = "ipw_ibss"; 2002 break; 2003 case IEEE80211_M_MONITOR: 2004 imagename = "ipw_monitor"; 2005 break; 2006 default: 2007 imagename = NULL; /* should not get there */ 2008 } 2009 2010 /* 2011 * Load firmware image using the firmware(9) subsystem. We need to 2012 * release the driver's lock first. 2013 */ 2014 if (sc->sc_firmware == NULL || strcmp(sc->sc_firmware->name, 2015 imagename) != 0) { 2016 mtx_unlock(&sc->sc_mtx); 2017 if (sc->sc_firmware != NULL) 2018 firmware_put(sc->sc_firmware, FIRMWARE_UNLOAD); 2019 sc->sc_firmware = firmware_get(imagename); 2020 mtx_lock(&sc->sc_mtx); 2021 } 2022 2023 if (sc->sc_firmware == NULL) { 2024 device_printf(sc->sc_dev, 2025 "could not load firmware image '%s'\n", imagename); 2026 goto fail1; 2027 } 2028 2029 fp = sc->sc_firmware; 2030 if (fp->datasize < sizeof *hdr) { 2031 device_printf(sc->sc_dev, 2032 "firmware image too short %zu\n", fp->datasize); 2033 goto fail2; 2034 } 2035 2036 hdr = (const struct ipw_firmware_hdr *)fp->data; 2037 2038 if (fp->datasize < sizeof *hdr + le32toh(hdr->mainsz) + 2039 le32toh(hdr->ucodesz)) { 2040 device_printf(sc->sc_dev, 2041 "firmware image too short %zu\n", fp->datasize); 2042 goto fail2; 2043 } 2044 2045 fw = (const char *)fp->data + sizeof *hdr + le32toh(hdr->mainsz); 2046 if (ipw_load_ucode(sc, fw, le32toh(hdr->ucodesz)) != 0) { 2047 device_printf(sc->sc_dev, "could not load microcode\n"); 2048 goto fail2; 2049 } 2050 2051 ipw_stop_master(sc); 2052 2053 /* 2054 * Setup tx, rx and status rings. 2055 */ 2056 sc->txold = IPW_NTBD - 1; 2057 sc->txcur = 0; 2058 sc->txfree = IPW_NTBD - 2; 2059 sc->rxcur = IPW_NRBD - 1; 2060 2061 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_phys); 2062 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); 2063 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); 2064 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); 2065 2066 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_phys); 2067 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); 2068 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); 2069 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); 2070 2071 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_phys); 2072 2073 fw = (const char *)fp->data + sizeof *hdr; 2074 if (ipw_load_firmware(sc, fw, le32toh(hdr->mainsz)) != 0) { 2075 device_printf(sc->sc_dev, "could not load firmware\n"); 2076 goto fail2; 2077 } 2078 2079 sc->flags |= IPW_FLAG_FW_INITED; 2080 2081 /* retrieve information tables base addresses */ 2082 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); 2083 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); 2084 2085 ipw_write_table1(sc, IPW_INFO_LOCK, 0); 2086 2087 if (ipw_config(sc) != 0) { 2088 device_printf(sc->sc_dev, "device configuration failed\n"); 2089 goto fail1; 2090 } 2091 2092 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2093 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2094 2095 sc->flags &=~ IPW_FLAG_INIT_LOCKED; 2096 2097 if (!owned) 2098 mtx_unlock(&sc->sc_mtx); 2099 2100 return; 2101 2102 fail2: firmware_put(fp, FIRMWARE_UNLOAD); 2103 sc->sc_firmware = NULL; 2104 fail1: ifp->if_flags &= ~IFF_UP; 2105 ipw_stop(sc); 2106 sc->flags &=~ IPW_FLAG_INIT_LOCKED; 2107 if (!owned) 2108 mtx_unlock(&sc->sc_mtx); 2109 } 2110 2111 static void 2112 ipw_stop(void *priv) 2113 { 2114 struct ipw_softc *sc = priv; 2115 struct ieee80211com *ic = &sc->sc_ic; 2116 struct ifnet *ifp = ic->ic_ifp; 2117 int i; 2118 2119 mtx_lock(&sc->sc_mtx); 2120 2121 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2122 2123 ipw_stop_master(sc); 2124 2125 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); 2126 2127 /* 2128 * Release tx buffers. 2129 */ 2130 for (i = 0; i < IPW_NTBD; i++) 2131 ipw_release_sbd(sc, &sc->stbd_list[i]); 2132 2133 sc->sc_tx_timer = 0; 2134 ifp->if_timer = 0; 2135 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2136 2137 mtx_unlock(&sc->sc_mtx); 2138 } 2139 2140 static int 2141 ipw_sysctl_stats(SYSCTL_HANDLER_ARGS) 2142 { 2143 struct ipw_softc *sc = arg1; 2144 uint32_t i, size, buf[256]; 2145 2146 if (!(sc->flags & IPW_FLAG_FW_INITED)) { 2147 memset(buf, 0, sizeof buf); 2148 return SYSCTL_OUT(req, buf, sizeof buf); 2149 } 2150 2151 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); 2152 2153 size = min(CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA), 256); 2154 for (i = 1; i < size; i++) 2155 buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA)); 2156 2157 return SYSCTL_OUT(req, buf, sizeof buf); 2158 } 2159 2160 static int 2161 ipw_sysctl_radio(SYSCTL_HANDLER_ARGS) 2162 { 2163 struct ipw_softc *sc = arg1; 2164 int val; 2165 2166 val = !((sc->flags & IPW_FLAG_HAS_RADIO_SWITCH) && 2167 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED)); 2168 2169 return SYSCTL_OUT(req, &val, sizeof val); 2170 } 2171 2172 static uint32_t 2173 ipw_read_table1(struct ipw_softc *sc, uint32_t off) 2174 { 2175 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); 2176 } 2177 2178 static void 2179 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) 2180 { 2181 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); 2182 } 2183 2184 static int 2185 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) 2186 { 2187 uint32_t addr, info; 2188 uint16_t count, size; 2189 uint32_t total; 2190 2191 /* addr[4] + count[2] + size[2] */ 2192 addr = MEM_READ_4(sc, sc->table2_base + off); 2193 info = MEM_READ_4(sc, sc->table2_base + off + 4); 2194 2195 count = info >> 16; 2196 size = info & 0xffff; 2197 total = count * size; 2198 2199 if (total > *len) { 2200 *len = total; 2201 return EINVAL; 2202 } 2203 2204 *len = total; 2205 ipw_read_mem_1(sc, addr, buf, total); 2206 2207 return 0; 2208 } 2209 2210 static void 2211 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, 2212 bus_size_t count) 2213 { 2214 for (; count > 0; offset++, datap++, count--) { 2215 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2216 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); 2217 } 2218 } 2219 2220 static void 2221 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, const uint8_t *datap, 2222 bus_size_t count) 2223 { 2224 for (; count > 0; offset++, datap++, count--) { 2225 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); 2226 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); 2227 } 2228 } 2229