1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/domainset.h> 38 #include <sys/malloc.h> 39 #include <sys/bus.h> 40 #include <sys/conf.h> 41 #include <sys/interrupt.h> 42 #include <sys/kernel.h> 43 #include <sys/ktr.h> 44 #include <sys/lock.h> 45 #include <sys/proc.h> 46 #include <sys/memdesc.h> 47 #include <sys/mutex.h> 48 #include <sys/sysctl.h> 49 #include <sys/rman.h> 50 #include <sys/taskqueue.h> 51 #include <sys/tree.h> 52 #include <sys/uio.h> 53 #include <sys/vmem.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <vm/vm.h> 57 #include <vm/vm_extern.h> 58 #include <vm/vm_kern.h> 59 #include <vm/vm_object.h> 60 #include <vm/vm_page.h> 61 #include <vm/vm_map.h> 62 #include <dev/iommu/iommu.h> 63 #include <machine/atomic.h> 64 #include <machine/bus.h> 65 #include <machine/md_var.h> 66 #include <machine/iommu.h> 67 #include <dev/iommu/busdma_iommu.h> 68 69 /* 70 * busdma_iommu.c, the implementation of the busdma(9) interface using 71 * IOMMU units from Intel VT-d. 72 */ 73 74 static bool 75 iommu_bus_dma_is_dev_disabled(int domain, int bus, int slot, int func) 76 { 77 char str[128], *env; 78 int default_bounce; 79 bool ret; 80 static const char bounce_str[] = "bounce"; 81 static const char iommu_str[] = "iommu"; 82 static const char dmar_str[] = "dmar"; /* compatibility */ 83 84 default_bounce = 0; 85 env = kern_getenv("hw.busdma.default"); 86 if (env != NULL) { 87 if (strcmp(env, bounce_str) == 0) 88 default_bounce = 1; 89 else if (strcmp(env, iommu_str) == 0 || 90 strcmp(env, dmar_str) == 0) 91 default_bounce = 0; 92 freeenv(env); 93 } 94 95 snprintf(str, sizeof(str), "hw.busdma.pci%d.%d.%d.%d", 96 domain, bus, slot, func); 97 env = kern_getenv(str); 98 if (env == NULL) 99 return (default_bounce != 0); 100 if (strcmp(env, bounce_str) == 0) 101 ret = true; 102 else if (strcmp(env, iommu_str) == 0 || 103 strcmp(env, dmar_str) == 0) 104 ret = false; 105 else 106 ret = default_bounce != 0; 107 freeenv(env); 108 return (ret); 109 } 110 111 /* 112 * Given original device, find the requester ID that will be seen by 113 * the IOMMU unit and used for page table lookup. PCI bridges may take 114 * ownership of transactions from downstream devices, so it may not be 115 * the same as the BSF of the target device. In those cases, all 116 * devices downstream of the bridge must share a single mapping 117 * domain, and must collectively be assigned to use either IOMMU or 118 * bounce mapping. 119 */ 120 device_t 121 iommu_get_requester(device_t dev, uint16_t *rid) 122 { 123 devclass_t pci_class; 124 device_t l, pci, pcib, pcip, pcibp, requester; 125 int cap_offset; 126 uint16_t pcie_flags; 127 bool bridge_is_pcie; 128 129 pci_class = devclass_find("pci"); 130 l = requester = dev; 131 132 *rid = pci_get_rid(dev); 133 134 /* 135 * Walk the bridge hierarchy from the target device to the 136 * host port to find the translating bridge nearest the IOMMU 137 * unit. 138 */ 139 for (;;) { 140 pci = device_get_parent(l); 141 KASSERT(pci != NULL, ("iommu_get_requester(%s): NULL parent " 142 "for %s", device_get_name(dev), device_get_name(l))); 143 KASSERT(device_get_devclass(pci) == pci_class, 144 ("iommu_get_requester(%s): non-pci parent %s for %s", 145 device_get_name(dev), device_get_name(pci), 146 device_get_name(l))); 147 148 pcib = device_get_parent(pci); 149 KASSERT(pcib != NULL, ("iommu_get_requester(%s): NULL bridge " 150 "for %s", device_get_name(dev), device_get_name(pci))); 151 152 /* 153 * The parent of our "bridge" isn't another PCI bus, 154 * so pcib isn't a PCI->PCI bridge but rather a host 155 * port, and the requester ID won't be translated 156 * further. 157 */ 158 pcip = device_get_parent(pcib); 159 if (device_get_devclass(pcip) != pci_class) 160 break; 161 pcibp = device_get_parent(pcip); 162 163 if (pci_find_cap(l, PCIY_EXPRESS, &cap_offset) == 0) { 164 /* 165 * Do not stop the loop even if the target 166 * device is PCIe, because it is possible (but 167 * unlikely) to have a PCI->PCIe bridge 168 * somewhere in the hierarchy. 169 */ 170 l = pcib; 171 } else { 172 /* 173 * Device is not PCIe, it cannot be seen as a 174 * requester by IOMMU unit. Check whether the 175 * bridge is PCIe. 176 */ 177 bridge_is_pcie = pci_find_cap(pcib, PCIY_EXPRESS, 178 &cap_offset) == 0; 179 requester = pcib; 180 181 /* 182 * Check for a buggy PCIe/PCI bridge that 183 * doesn't report the express capability. If 184 * the bridge above it is express but isn't a 185 * PCI bridge, then we know pcib is actually a 186 * PCIe/PCI bridge. 187 */ 188 if (!bridge_is_pcie && pci_find_cap(pcibp, 189 PCIY_EXPRESS, &cap_offset) == 0) { 190 pcie_flags = pci_read_config(pcibp, 191 cap_offset + PCIER_FLAGS, 2); 192 if ((pcie_flags & PCIEM_FLAGS_TYPE) != 193 PCIEM_TYPE_PCI_BRIDGE) 194 bridge_is_pcie = true; 195 } 196 197 if (bridge_is_pcie) { 198 /* 199 * The current device is not PCIe, but 200 * the bridge above it is. This is a 201 * PCIe->PCI bridge. Assume that the 202 * requester ID will be the secondary 203 * bus number with slot and function 204 * set to zero. 205 * 206 * XXX: Doesn't handle the case where 207 * the bridge is PCIe->PCI-X, and the 208 * bridge will only take ownership of 209 * requests in some cases. We should 210 * provide context entries with the 211 * same page tables for taken and 212 * non-taken transactions. 213 */ 214 *rid = PCI_RID(pci_get_bus(l), 0, 0); 215 l = pcibp; 216 } else { 217 /* 218 * Neither the device nor the bridge 219 * above it are PCIe. This is a 220 * conventional PCI->PCI bridge, which 221 * will use the bridge's BSF as the 222 * requester ID. 223 */ 224 *rid = pci_get_rid(pcib); 225 l = pcib; 226 } 227 } 228 } 229 return (requester); 230 } 231 232 struct iommu_ctx * 233 iommu_instantiate_ctx(struct iommu_unit *unit, device_t dev, bool rmrr) 234 { 235 device_t requester; 236 struct iommu_ctx *ctx; 237 bool disabled; 238 uint16_t rid; 239 240 requester = iommu_get_requester(dev, &rid); 241 242 /* 243 * If the user requested the IOMMU disabled for the device, we 244 * cannot disable the IOMMU unit, due to possibility of other 245 * devices on the same IOMMU unit still requiring translation. 246 * Instead provide the identity mapping for the device 247 * context. 248 */ 249 disabled = iommu_bus_dma_is_dev_disabled(pci_get_domain(requester), 250 pci_get_bus(requester), pci_get_slot(requester), 251 pci_get_function(requester)); 252 ctx = iommu_get_ctx(unit, requester, rid, disabled, rmrr); 253 if (ctx == NULL) 254 return (NULL); 255 if (disabled) { 256 /* 257 * Keep the first reference on context, release the 258 * later refs. 259 */ 260 IOMMU_LOCK(unit); 261 if ((ctx->flags & IOMMU_CTX_DISABLED) == 0) { 262 ctx->flags |= IOMMU_CTX_DISABLED; 263 IOMMU_UNLOCK(unit); 264 } else { 265 iommu_free_ctx_locked(unit, ctx); 266 } 267 ctx = NULL; 268 } 269 return (ctx); 270 } 271 272 bus_dma_tag_t 273 acpi_iommu_get_dma_tag(device_t dev, device_t child) 274 { 275 struct iommu_unit *unit; 276 struct iommu_ctx *ctx; 277 bus_dma_tag_t res; 278 279 unit = iommu_find(child, bootverbose); 280 /* Not in scope of any IOMMU ? */ 281 if (unit == NULL) 282 return (NULL); 283 if (!unit->dma_enabled) 284 return (NULL); 285 286 #if defined(__amd64__) || defined(__i386__) 287 dmar_quirks_pre_use(unit); 288 dmar_instantiate_rmrr_ctxs(unit); 289 #endif 290 291 ctx = iommu_instantiate_ctx(unit, child, false); 292 res = ctx == NULL ? NULL : (bus_dma_tag_t)ctx->tag; 293 return (res); 294 } 295 296 bool 297 bus_dma_iommu_set_buswide(device_t dev) 298 { 299 struct iommu_unit *unit; 300 device_t parent; 301 u_int busno, slot, func; 302 303 parent = device_get_parent(dev); 304 if (device_get_devclass(parent) != devclass_find("pci")) 305 return (false); 306 unit = iommu_find(dev, bootverbose); 307 if (unit == NULL) 308 return (false); 309 busno = pci_get_bus(dev); 310 slot = pci_get_slot(dev); 311 func = pci_get_function(dev); 312 if (slot != 0 || func != 0) { 313 if (bootverbose) { 314 device_printf(dev, 315 "iommu%d pci%d:%d:%d requested buswide busdma\n", 316 unit->unit, busno, slot, func); 317 } 318 return (false); 319 } 320 iommu_set_buswide_ctx(unit, busno); 321 return (true); 322 } 323 324 void 325 iommu_set_buswide_ctx(struct iommu_unit *unit, u_int busno) 326 { 327 328 MPASS(busno <= PCI_BUSMAX); 329 IOMMU_LOCK(unit); 330 unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] |= 331 1 << (busno % (NBBY * sizeof(uint32_t))); 332 IOMMU_UNLOCK(unit); 333 } 334 335 bool 336 iommu_is_buswide_ctx(struct iommu_unit *unit, u_int busno) 337 { 338 339 MPASS(busno <= PCI_BUSMAX); 340 return ((unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] & 341 (1U << (busno % (NBBY * sizeof(uint32_t))))) != 0); 342 } 343 344 static MALLOC_DEFINE(M_IOMMU_DMAMAP, "iommu_dmamap", "IOMMU DMA Map"); 345 346 static void iommu_bus_schedule_dmamap(struct iommu_unit *unit, 347 struct bus_dmamap_iommu *map); 348 349 static int 350 iommu_bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, 351 bus_addr_t boundary, bus_addr_t lowaddr, bus_addr_t highaddr, 352 bus_dma_filter_t *filter, void *filterarg, bus_size_t maxsize, 353 int nsegments, bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc, 354 void *lockfuncarg, bus_dma_tag_t *dmat) 355 { 356 struct bus_dma_tag_iommu *newtag, *oldtag; 357 int error; 358 359 *dmat = NULL; 360 error = common_bus_dma_tag_create(parent != NULL ? 361 &((struct bus_dma_tag_iommu *)parent)->common : NULL, alignment, 362 boundary, lowaddr, highaddr, filter, filterarg, maxsize, 363 nsegments, maxsegsz, flags, lockfunc, lockfuncarg, 364 sizeof(struct bus_dma_tag_iommu), (void **)&newtag); 365 if (error != 0) 366 goto out; 367 368 oldtag = (struct bus_dma_tag_iommu *)parent; 369 newtag->common.impl = &bus_dma_iommu_impl; 370 newtag->ctx = oldtag->ctx; 371 newtag->owner = oldtag->owner; 372 373 *dmat = (bus_dma_tag_t)newtag; 374 out: 375 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 376 __func__, newtag, (newtag != NULL ? newtag->common.flags : 0), 377 error); 378 return (error); 379 } 380 381 static int 382 iommu_bus_dma_tag_set_domain(bus_dma_tag_t dmat) 383 { 384 385 return (0); 386 } 387 388 static int 389 iommu_bus_dma_tag_destroy(bus_dma_tag_t dmat1) 390 { 391 struct bus_dma_tag_iommu *dmat, *dmat_copy, *parent; 392 int error; 393 394 error = 0; 395 dmat_copy = dmat = (struct bus_dma_tag_iommu *)dmat1; 396 397 if (dmat != NULL) { 398 if (dmat->map_count != 0) { 399 error = EBUSY; 400 goto out; 401 } 402 while (dmat != NULL) { 403 parent = (struct bus_dma_tag_iommu *)dmat->common.parent; 404 if (atomic_fetchadd_int(&dmat->common.ref_count, -1) == 405 1) { 406 if (dmat == dmat->ctx->tag) 407 iommu_free_ctx(dmat->ctx); 408 free(dmat->segments, M_IOMMU_DMAMAP); 409 free(dmat, M_DEVBUF); 410 dmat = parent; 411 } else 412 dmat = NULL; 413 } 414 } 415 out: 416 CTR3(KTR_BUSDMA, "%s tag %p error %d", __func__, dmat_copy, error); 417 return (error); 418 } 419 420 static bool 421 iommu_bus_dma_id_mapped(bus_dma_tag_t dmat, vm_paddr_t buf, bus_size_t buflen) 422 { 423 424 return (false); 425 } 426 427 static int 428 iommu_bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) 429 { 430 struct bus_dma_tag_iommu *tag; 431 struct bus_dmamap_iommu *map; 432 433 tag = (struct bus_dma_tag_iommu *)dmat; 434 map = malloc_domainset(sizeof(*map), M_IOMMU_DMAMAP, 435 DOMAINSET_PREF(tag->common.domain), M_NOWAIT | M_ZERO); 436 if (map == NULL) { 437 *mapp = NULL; 438 return (ENOMEM); 439 } 440 if (tag->segments == NULL) { 441 tag->segments = malloc_domainset(sizeof(bus_dma_segment_t) * 442 tag->common.nsegments, M_IOMMU_DMAMAP, 443 DOMAINSET_PREF(tag->common.domain), M_NOWAIT); 444 if (tag->segments == NULL) { 445 free(map, M_IOMMU_DMAMAP); 446 *mapp = NULL; 447 return (ENOMEM); 448 } 449 } 450 TAILQ_INIT(&map->map_entries); 451 map->tag = tag; 452 map->locked = true; 453 map->cansleep = false; 454 tag->map_count++; 455 *mapp = (bus_dmamap_t)map; 456 457 return (0); 458 } 459 460 static int 461 iommu_bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map1) 462 { 463 struct bus_dma_tag_iommu *tag; 464 struct bus_dmamap_iommu *map; 465 struct iommu_domain *domain; 466 467 tag = (struct bus_dma_tag_iommu *)dmat; 468 map = (struct bus_dmamap_iommu *)map1; 469 if (map != NULL) { 470 domain = tag->ctx->domain; 471 IOMMU_DOMAIN_LOCK(domain); 472 if (!TAILQ_EMPTY(&map->map_entries)) { 473 IOMMU_DOMAIN_UNLOCK(domain); 474 return (EBUSY); 475 } 476 IOMMU_DOMAIN_UNLOCK(domain); 477 free(map, M_IOMMU_DMAMAP); 478 } 479 tag->map_count--; 480 return (0); 481 } 482 483 484 static int 485 iommu_bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, 486 bus_dmamap_t *mapp) 487 { 488 struct bus_dma_tag_iommu *tag; 489 struct bus_dmamap_iommu *map; 490 int error, mflags; 491 vm_memattr_t attr; 492 493 error = iommu_bus_dmamap_create(dmat, flags, mapp); 494 if (error != 0) 495 return (error); 496 497 mflags = (flags & BUS_DMA_NOWAIT) != 0 ? M_NOWAIT : M_WAITOK; 498 mflags |= (flags & BUS_DMA_ZERO) != 0 ? M_ZERO : 0; 499 attr = (flags & BUS_DMA_NOCACHE) != 0 ? VM_MEMATTR_UNCACHEABLE : 500 VM_MEMATTR_DEFAULT; 501 502 tag = (struct bus_dma_tag_iommu *)dmat; 503 map = (struct bus_dmamap_iommu *)*mapp; 504 505 if (tag->common.maxsize < PAGE_SIZE && 506 tag->common.alignment <= tag->common.maxsize && 507 attr == VM_MEMATTR_DEFAULT) { 508 *vaddr = malloc_domainset(tag->common.maxsize, M_DEVBUF, 509 DOMAINSET_PREF(tag->common.domain), mflags); 510 map->flags |= BUS_DMAMAP_IOMMU_MALLOC; 511 } else { 512 *vaddr = (void *)kmem_alloc_attr_domainset( 513 DOMAINSET_PREF(tag->common.domain), tag->common.maxsize, 514 mflags, 0ul, BUS_SPACE_MAXADDR, attr); 515 map->flags |= BUS_DMAMAP_IOMMU_KMEM_ALLOC; 516 } 517 if (*vaddr == NULL) { 518 iommu_bus_dmamap_destroy(dmat, *mapp); 519 *mapp = NULL; 520 return (ENOMEM); 521 } 522 return (0); 523 } 524 525 static void 526 iommu_bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map1) 527 { 528 struct bus_dma_tag_iommu *tag; 529 struct bus_dmamap_iommu *map; 530 531 tag = (struct bus_dma_tag_iommu *)dmat; 532 map = (struct bus_dmamap_iommu *)map1; 533 534 if ((map->flags & BUS_DMAMAP_IOMMU_MALLOC) != 0) { 535 free(vaddr, M_DEVBUF); 536 map->flags &= ~BUS_DMAMAP_IOMMU_MALLOC; 537 } else { 538 KASSERT((map->flags & BUS_DMAMAP_IOMMU_KMEM_ALLOC) != 0, 539 ("iommu_bus_dmamem_free for non alloced map %p", map)); 540 kmem_free((vm_offset_t)vaddr, tag->common.maxsize); 541 map->flags &= ~BUS_DMAMAP_IOMMU_KMEM_ALLOC; 542 } 543 544 iommu_bus_dmamap_destroy(dmat, map1); 545 } 546 547 static int 548 iommu_bus_dmamap_load_something1(struct bus_dma_tag_iommu *tag, 549 struct bus_dmamap_iommu *map, vm_page_t *ma, int offset, bus_size_t buflen, 550 int flags, bus_dma_segment_t *segs, int *segp, 551 struct iommu_map_entries_tailq *unroll_list) 552 { 553 struct iommu_ctx *ctx; 554 struct iommu_domain *domain; 555 struct iommu_map_entry *entry; 556 iommu_gaddr_t size; 557 bus_size_t buflen1; 558 int error, idx, gas_flags, seg; 559 560 KASSERT(offset < IOMMU_PAGE_SIZE, ("offset %d", offset)); 561 if (segs == NULL) 562 segs = tag->segments; 563 ctx = tag->ctx; 564 domain = ctx->domain; 565 seg = *segp; 566 error = 0; 567 idx = 0; 568 while (buflen > 0) { 569 seg++; 570 if (seg >= tag->common.nsegments) { 571 error = EFBIG; 572 break; 573 } 574 buflen1 = buflen > tag->common.maxsegsz ? 575 tag->common.maxsegsz : buflen; 576 size = round_page(offset + buflen1); 577 578 /* 579 * (Too) optimistically allow split if there are more 580 * then one segments left. 581 */ 582 gas_flags = map->cansleep ? IOMMU_MF_CANWAIT : 0; 583 if (seg + 1 < tag->common.nsegments) 584 gas_flags |= IOMMU_MF_CANSPLIT; 585 586 error = iommu_map(domain, &tag->common, size, offset, 587 IOMMU_MAP_ENTRY_READ | 588 ((flags & BUS_DMA_NOWRITE) == 0 ? IOMMU_MAP_ENTRY_WRITE : 0), 589 gas_flags, ma + idx, &entry); 590 if (error != 0) 591 break; 592 if ((gas_flags & IOMMU_MF_CANSPLIT) != 0) { 593 KASSERT(size >= entry->end - entry->start, 594 ("split increased entry size %jx %jx %jx", 595 (uintmax_t)size, (uintmax_t)entry->start, 596 (uintmax_t)entry->end)); 597 size = entry->end - entry->start; 598 if (buflen1 > size) 599 buflen1 = size; 600 } else { 601 KASSERT(entry->end - entry->start == size, 602 ("no split allowed %jx %jx %jx", 603 (uintmax_t)size, (uintmax_t)entry->start, 604 (uintmax_t)entry->end)); 605 } 606 if (offset + buflen1 > size) 607 buflen1 = size - offset; 608 if (buflen1 > tag->common.maxsegsz) 609 buflen1 = tag->common.maxsegsz; 610 611 KASSERT(((entry->start + offset) & (tag->common.alignment - 1)) 612 == 0, 613 ("alignment failed: ctx %p start 0x%jx offset %x " 614 "align 0x%jx", ctx, (uintmax_t)entry->start, offset, 615 (uintmax_t)tag->common.alignment)); 616 KASSERT(entry->end <= tag->common.lowaddr || 617 entry->start >= tag->common.highaddr, 618 ("entry placement failed: ctx %p start 0x%jx end 0x%jx " 619 "lowaddr 0x%jx highaddr 0x%jx", ctx, 620 (uintmax_t)entry->start, (uintmax_t)entry->end, 621 (uintmax_t)tag->common.lowaddr, 622 (uintmax_t)tag->common.highaddr)); 623 KASSERT(iommu_test_boundary(entry->start + offset, buflen1, 624 tag->common.boundary), 625 ("boundary failed: ctx %p start 0x%jx end 0x%jx " 626 "boundary 0x%jx", ctx, (uintmax_t)entry->start, 627 (uintmax_t)entry->end, (uintmax_t)tag->common.boundary)); 628 KASSERT(buflen1 <= tag->common.maxsegsz, 629 ("segment too large: ctx %p start 0x%jx end 0x%jx " 630 "buflen1 0x%jx maxsegsz 0x%jx", ctx, 631 (uintmax_t)entry->start, (uintmax_t)entry->end, 632 (uintmax_t)buflen1, (uintmax_t)tag->common.maxsegsz)); 633 634 IOMMU_DOMAIN_LOCK(domain); 635 TAILQ_INSERT_TAIL(&map->map_entries, entry, dmamap_link); 636 entry->flags |= IOMMU_MAP_ENTRY_MAP; 637 IOMMU_DOMAIN_UNLOCK(domain); 638 TAILQ_INSERT_TAIL(unroll_list, entry, unroll_link); 639 640 segs[seg].ds_addr = entry->start + offset; 641 segs[seg].ds_len = buflen1; 642 643 idx += OFF_TO_IDX(trunc_page(offset + buflen1)); 644 offset += buflen1; 645 offset &= IOMMU_PAGE_MASK; 646 buflen -= buflen1; 647 } 648 if (error == 0) 649 *segp = seg; 650 return (error); 651 } 652 653 static int 654 iommu_bus_dmamap_load_something(struct bus_dma_tag_iommu *tag, 655 struct bus_dmamap_iommu *map, vm_page_t *ma, int offset, bus_size_t buflen, 656 int flags, bus_dma_segment_t *segs, int *segp) 657 { 658 struct iommu_ctx *ctx; 659 struct iommu_domain *domain; 660 struct iommu_map_entry *entry, *entry1; 661 struct iommu_map_entries_tailq unroll_list; 662 int error; 663 664 ctx = tag->ctx; 665 domain = ctx->domain; 666 atomic_add_long(&ctx->loads, 1); 667 668 TAILQ_INIT(&unroll_list); 669 error = iommu_bus_dmamap_load_something1(tag, map, ma, offset, 670 buflen, flags, segs, segp, &unroll_list); 671 if (error != 0) { 672 /* 673 * The busdma interface does not allow us to report 674 * partial buffer load, so unfortunately we have to 675 * revert all work done. 676 */ 677 IOMMU_DOMAIN_LOCK(domain); 678 TAILQ_FOREACH_SAFE(entry, &unroll_list, unroll_link, 679 entry1) { 680 /* 681 * No entries other than what we have created 682 * during the failed run might have been 683 * inserted there in between, since we own ctx 684 * pglock. 685 */ 686 TAILQ_REMOVE(&map->map_entries, entry, dmamap_link); 687 TAILQ_REMOVE(&unroll_list, entry, unroll_link); 688 TAILQ_INSERT_TAIL(&domain->unload_entries, entry, 689 dmamap_link); 690 } 691 IOMMU_DOMAIN_UNLOCK(domain); 692 taskqueue_enqueue(domain->iommu->delayed_taskqueue, 693 &domain->unload_task); 694 } 695 696 if (error == ENOMEM && (flags & BUS_DMA_NOWAIT) == 0 && 697 !map->cansleep) 698 error = EINPROGRESS; 699 if (error == EINPROGRESS) 700 iommu_bus_schedule_dmamap(domain->iommu, map); 701 return (error); 702 } 703 704 static int 705 iommu_bus_dmamap_load_ma(bus_dma_tag_t dmat, bus_dmamap_t map1, 706 struct vm_page **ma, bus_size_t tlen, int ma_offs, int flags, 707 bus_dma_segment_t *segs, int *segp) 708 { 709 struct bus_dma_tag_iommu *tag; 710 struct bus_dmamap_iommu *map; 711 712 tag = (struct bus_dma_tag_iommu *)dmat; 713 map = (struct bus_dmamap_iommu *)map1; 714 return (iommu_bus_dmamap_load_something(tag, map, ma, ma_offs, tlen, 715 flags, segs, segp)); 716 } 717 718 static int 719 iommu_bus_dmamap_load_phys(bus_dma_tag_t dmat, bus_dmamap_t map1, 720 vm_paddr_t buf, bus_size_t buflen, int flags, bus_dma_segment_t *segs, 721 int *segp) 722 { 723 struct bus_dma_tag_iommu *tag; 724 struct bus_dmamap_iommu *map; 725 vm_page_t *ma, fma; 726 vm_paddr_t pstart, pend, paddr; 727 int error, i, ma_cnt, mflags, offset; 728 729 tag = (struct bus_dma_tag_iommu *)dmat; 730 map = (struct bus_dmamap_iommu *)map1; 731 pstart = trunc_page(buf); 732 pend = round_page(buf + buflen); 733 offset = buf & PAGE_MASK; 734 ma_cnt = OFF_TO_IDX(pend - pstart); 735 mflags = map->cansleep ? M_WAITOK : M_NOWAIT; 736 ma = malloc(sizeof(vm_page_t) * ma_cnt, M_DEVBUF, mflags); 737 if (ma == NULL) 738 return (ENOMEM); 739 fma = NULL; 740 for (i = 0; i < ma_cnt; i++) { 741 paddr = pstart + ptoa(i); 742 ma[i] = PHYS_TO_VM_PAGE(paddr); 743 if (ma[i] == NULL || VM_PAGE_TO_PHYS(ma[i]) != paddr) { 744 /* 745 * If PHYS_TO_VM_PAGE() returned NULL or the 746 * vm_page was not initialized we'll use a 747 * fake page. 748 */ 749 if (fma == NULL) { 750 fma = malloc(sizeof(struct vm_page) * ma_cnt, 751 M_DEVBUF, M_ZERO | mflags); 752 if (fma == NULL) { 753 free(ma, M_DEVBUF); 754 return (ENOMEM); 755 } 756 } 757 vm_page_initfake(&fma[i], pstart + ptoa(i), 758 VM_MEMATTR_DEFAULT); 759 ma[i] = &fma[i]; 760 } 761 } 762 error = iommu_bus_dmamap_load_something(tag, map, ma, offset, buflen, 763 flags, segs, segp); 764 free(fma, M_DEVBUF); 765 free(ma, M_DEVBUF); 766 return (error); 767 } 768 769 static int 770 iommu_bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dmamap_t map1, void *buf, 771 bus_size_t buflen, pmap_t pmap, int flags, bus_dma_segment_t *segs, 772 int *segp) 773 { 774 struct bus_dma_tag_iommu *tag; 775 struct bus_dmamap_iommu *map; 776 vm_page_t *ma, fma; 777 vm_paddr_t pstart, pend, paddr; 778 int error, i, ma_cnt, mflags, offset; 779 780 tag = (struct bus_dma_tag_iommu *)dmat; 781 map = (struct bus_dmamap_iommu *)map1; 782 pstart = trunc_page((vm_offset_t)buf); 783 pend = round_page((vm_offset_t)buf + buflen); 784 offset = (vm_offset_t)buf & PAGE_MASK; 785 ma_cnt = OFF_TO_IDX(pend - pstart); 786 mflags = map->cansleep ? M_WAITOK : M_NOWAIT; 787 ma = malloc(sizeof(vm_page_t) * ma_cnt, M_DEVBUF, mflags); 788 if (ma == NULL) 789 return (ENOMEM); 790 fma = NULL; 791 for (i = 0; i < ma_cnt; i++, pstart += PAGE_SIZE) { 792 if (pmap == kernel_pmap) 793 paddr = pmap_kextract(pstart); 794 else 795 paddr = pmap_extract(pmap, pstart); 796 ma[i] = PHYS_TO_VM_PAGE(paddr); 797 if (ma[i] == NULL || VM_PAGE_TO_PHYS(ma[i]) != paddr) { 798 /* 799 * If PHYS_TO_VM_PAGE() returned NULL or the 800 * vm_page was not initialized we'll use a 801 * fake page. 802 */ 803 if (fma == NULL) { 804 fma = malloc(sizeof(struct vm_page) * ma_cnt, 805 M_DEVBUF, M_ZERO | mflags); 806 if (fma == NULL) { 807 free(ma, M_DEVBUF); 808 return (ENOMEM); 809 } 810 } 811 vm_page_initfake(&fma[i], paddr, VM_MEMATTR_DEFAULT); 812 ma[i] = &fma[i]; 813 } 814 } 815 error = iommu_bus_dmamap_load_something(tag, map, ma, offset, buflen, 816 flags, segs, segp); 817 free(ma, M_DEVBUF); 818 free(fma, M_DEVBUF); 819 return (error); 820 } 821 822 static void 823 iommu_bus_dmamap_waitok(bus_dma_tag_t dmat, bus_dmamap_t map1, 824 struct memdesc *mem, bus_dmamap_callback_t *callback, void *callback_arg) 825 { 826 struct bus_dmamap_iommu *map; 827 828 if (map1 == NULL) 829 return; 830 map = (struct bus_dmamap_iommu *)map1; 831 map->mem = *mem; 832 map->tag = (struct bus_dma_tag_iommu *)dmat; 833 map->callback = callback; 834 map->callback_arg = callback_arg; 835 } 836 837 static bus_dma_segment_t * 838 iommu_bus_dmamap_complete(bus_dma_tag_t dmat, bus_dmamap_t map1, 839 bus_dma_segment_t *segs, int nsegs, int error) 840 { 841 struct bus_dma_tag_iommu *tag; 842 struct bus_dmamap_iommu *map; 843 844 tag = (struct bus_dma_tag_iommu *)dmat; 845 map = (struct bus_dmamap_iommu *)map1; 846 847 if (!map->locked) { 848 KASSERT(map->cansleep, 849 ("map not locked and not sleepable context %p", map)); 850 851 /* 852 * We are called from the delayed context. Relock the 853 * driver. 854 */ 855 (tag->common.lockfunc)(tag->common.lockfuncarg, BUS_DMA_LOCK); 856 map->locked = true; 857 } 858 859 if (segs == NULL) 860 segs = tag->segments; 861 return (segs); 862 } 863 864 /* 865 * The limitations of busdma KPI forces the iommu to perform the actual 866 * unload, consisting of the unmapping of the map entries page tables, 867 * from the delayed context on i386, since page table page mapping 868 * might require a sleep to be successfull. The unfortunate 869 * consequence is that the DMA requests can be served some time after 870 * the bus_dmamap_unload() call returned. 871 * 872 * On amd64, we assume that sf allocation cannot fail. 873 */ 874 static void 875 iommu_bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map1) 876 { 877 struct bus_dma_tag_iommu *tag; 878 struct bus_dmamap_iommu *map; 879 struct iommu_ctx *ctx; 880 struct iommu_domain *domain; 881 #if defined(__amd64__) 882 struct iommu_map_entries_tailq entries; 883 #endif 884 885 tag = (struct bus_dma_tag_iommu *)dmat; 886 map = (struct bus_dmamap_iommu *)map1; 887 ctx = tag->ctx; 888 domain = ctx->domain; 889 atomic_add_long(&ctx->unloads, 1); 890 891 #if defined(__i386__) 892 IOMMU_DOMAIN_LOCK(domain); 893 TAILQ_CONCAT(&domain->unload_entries, &map->map_entries, dmamap_link); 894 IOMMU_DOMAIN_UNLOCK(domain); 895 taskqueue_enqueue(domain->iommu->delayed_taskqueue, 896 &domain->unload_task); 897 #else /* defined(__amd64__) */ 898 TAILQ_INIT(&entries); 899 IOMMU_DOMAIN_LOCK(domain); 900 TAILQ_CONCAT(&entries, &map->map_entries, dmamap_link); 901 IOMMU_DOMAIN_UNLOCK(domain); 902 THREAD_NO_SLEEPING(); 903 iommu_domain_unload(domain, &entries, false); 904 THREAD_SLEEPING_OK(); 905 KASSERT(TAILQ_EMPTY(&entries), ("lazy iommu_ctx_unload %p", ctx)); 906 #endif 907 } 908 909 static void 910 iommu_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, 911 bus_dmasync_op_t op) 912 { 913 } 914 915 struct bus_dma_impl bus_dma_iommu_impl = { 916 .tag_create = iommu_bus_dma_tag_create, 917 .tag_destroy = iommu_bus_dma_tag_destroy, 918 .tag_set_domain = iommu_bus_dma_tag_set_domain, 919 .id_mapped = iommu_bus_dma_id_mapped, 920 .map_create = iommu_bus_dmamap_create, 921 .map_destroy = iommu_bus_dmamap_destroy, 922 .mem_alloc = iommu_bus_dmamem_alloc, 923 .mem_free = iommu_bus_dmamem_free, 924 .load_phys = iommu_bus_dmamap_load_phys, 925 .load_buffer = iommu_bus_dmamap_load_buffer, 926 .load_ma = iommu_bus_dmamap_load_ma, 927 .map_waitok = iommu_bus_dmamap_waitok, 928 .map_complete = iommu_bus_dmamap_complete, 929 .map_unload = iommu_bus_dmamap_unload, 930 .map_sync = iommu_bus_dmamap_sync, 931 }; 932 933 static void 934 iommu_bus_task_dmamap(void *arg, int pending) 935 { 936 struct bus_dma_tag_iommu *tag; 937 struct bus_dmamap_iommu *map; 938 struct iommu_unit *unit; 939 940 unit = arg; 941 IOMMU_LOCK(unit); 942 while ((map = TAILQ_FIRST(&unit->delayed_maps)) != NULL) { 943 TAILQ_REMOVE(&unit->delayed_maps, map, delay_link); 944 IOMMU_UNLOCK(unit); 945 tag = map->tag; 946 map->cansleep = true; 947 map->locked = false; 948 bus_dmamap_load_mem((bus_dma_tag_t)tag, (bus_dmamap_t)map, 949 &map->mem, map->callback, map->callback_arg, 950 BUS_DMA_WAITOK); 951 map->cansleep = false; 952 if (map->locked) { 953 (tag->common.lockfunc)(tag->common.lockfuncarg, 954 BUS_DMA_UNLOCK); 955 } else 956 map->locked = true; 957 map->cansleep = false; 958 IOMMU_LOCK(unit); 959 } 960 IOMMU_UNLOCK(unit); 961 } 962 963 static void 964 iommu_bus_schedule_dmamap(struct iommu_unit *unit, struct bus_dmamap_iommu *map) 965 { 966 967 map->locked = false; 968 IOMMU_LOCK(unit); 969 TAILQ_INSERT_TAIL(&unit->delayed_maps, map, delay_link); 970 IOMMU_UNLOCK(unit); 971 taskqueue_enqueue(unit->delayed_taskqueue, &unit->dmamap_load_task); 972 } 973 974 int 975 iommu_init_busdma(struct iommu_unit *unit) 976 { 977 int error; 978 979 unit->dma_enabled = 1; 980 error = TUNABLE_INT_FETCH("hw.iommu.dma", &unit->dma_enabled); 981 if (error == 0) /* compatibility */ 982 TUNABLE_INT_FETCH("hw.dmar.dma", &unit->dma_enabled); 983 TAILQ_INIT(&unit->delayed_maps); 984 TASK_INIT(&unit->dmamap_load_task, 0, iommu_bus_task_dmamap, unit); 985 unit->delayed_taskqueue = taskqueue_create("iommu", M_WAITOK, 986 taskqueue_thread_enqueue, &unit->delayed_taskqueue); 987 taskqueue_start_threads(&unit->delayed_taskqueue, 1, PI_DISK, 988 "iommu%d busdma taskq", unit->unit); 989 return (0); 990 } 991 992 void 993 iommu_fini_busdma(struct iommu_unit *unit) 994 { 995 996 if (unit->delayed_taskqueue == NULL) 997 return; 998 999 taskqueue_drain(unit->delayed_taskqueue, &unit->dmamap_load_task); 1000 taskqueue_free(unit->delayed_taskqueue); 1001 unit->delayed_taskqueue = NULL; 1002 } 1003 1004 int 1005 bus_dma_iommu_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map1, 1006 vm_paddr_t start, vm_size_t length, int flags) 1007 { 1008 struct bus_dma_tag_common *tc; 1009 struct bus_dma_tag_iommu *tag; 1010 struct bus_dmamap_iommu *map; 1011 struct iommu_ctx *ctx; 1012 struct iommu_domain *domain; 1013 struct iommu_map_entry *entry; 1014 vm_page_t *ma; 1015 vm_size_t i; 1016 int error; 1017 bool waitok; 1018 1019 MPASS((start & PAGE_MASK) == 0); 1020 MPASS((length & PAGE_MASK) == 0); 1021 MPASS(length > 0); 1022 MPASS(start + length >= start); 1023 MPASS((flags & ~(BUS_DMA_NOWAIT | BUS_DMA_NOWRITE)) == 0); 1024 1025 tc = (struct bus_dma_tag_common *)dmat; 1026 if (tc->impl != &bus_dma_iommu_impl) 1027 return (0); 1028 1029 tag = (struct bus_dma_tag_iommu *)dmat; 1030 ctx = tag->ctx; 1031 domain = ctx->domain; 1032 map = (struct bus_dmamap_iommu *)map1; 1033 waitok = (flags & BUS_DMA_NOWAIT) != 0; 1034 1035 entry = iommu_map_alloc_entry(domain, waitok ? 0 : IOMMU_PGF_WAITOK); 1036 if (entry == NULL) 1037 return (ENOMEM); 1038 entry->start = start; 1039 entry->end = start + length; 1040 ma = malloc(sizeof(vm_page_t) * atop(length), M_TEMP, waitok ? 1041 M_WAITOK : M_NOWAIT); 1042 if (ma == NULL) { 1043 iommu_map_free_entry(domain, entry); 1044 return (ENOMEM); 1045 } 1046 for (i = 0; i < atop(length); i++) { 1047 ma[i] = vm_page_getfake(entry->start + PAGE_SIZE * i, 1048 VM_MEMATTR_DEFAULT); 1049 } 1050 error = iommu_map_region(domain, entry, IOMMU_MAP_ENTRY_READ | 1051 ((flags & BUS_DMA_NOWRITE) ? 0 : IOMMU_MAP_ENTRY_WRITE), 1052 waitok ? IOMMU_MF_CANWAIT : 0, ma); 1053 if (error == 0) { 1054 IOMMU_DOMAIN_LOCK(domain); 1055 TAILQ_INSERT_TAIL(&map->map_entries, entry, dmamap_link); 1056 entry->flags |= IOMMU_MAP_ENTRY_MAP; 1057 IOMMU_DOMAIN_UNLOCK(domain); 1058 } else { 1059 iommu_domain_unload_entry(entry, true); 1060 } 1061 for (i = 0; i < atop(length); i++) 1062 vm_page_putfake(ma[i]); 1063 free(ma, M_TEMP); 1064 return (error); 1065 } 1066 1067 static void 1068 iommu_domain_unload_task(void *arg, int pending) 1069 { 1070 struct iommu_domain *domain; 1071 struct iommu_map_entries_tailq entries; 1072 1073 domain = arg; 1074 TAILQ_INIT(&entries); 1075 1076 for (;;) { 1077 IOMMU_DOMAIN_LOCK(domain); 1078 TAILQ_SWAP(&domain->unload_entries, &entries, 1079 iommu_map_entry, dmamap_link); 1080 IOMMU_DOMAIN_UNLOCK(domain); 1081 if (TAILQ_EMPTY(&entries)) 1082 break; 1083 iommu_domain_unload(domain, &entries, true); 1084 } 1085 } 1086 1087 void 1088 iommu_domain_init(struct iommu_unit *unit, struct iommu_domain *domain, 1089 const struct iommu_domain_map_ops *ops) 1090 { 1091 1092 domain->ops = ops; 1093 domain->iommu = unit; 1094 1095 TASK_INIT(&domain->unload_task, 0, iommu_domain_unload_task, domain); 1096 RB_INIT(&domain->rb_root); 1097 TAILQ_INIT(&domain->unload_entries); 1098 mtx_init(&domain->lock, "iodom", NULL, MTX_DEF); 1099 } 1100 1101 void 1102 iommu_domain_fini(struct iommu_domain *domain) 1103 { 1104 1105 mtx_destroy(&domain->lock); 1106 } 1107