1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 __FBSDID("$FreeBSD$"); 28 29 #ifndef __IOAT_TEST_H__ 30 #define __IOAT_TEST_H__ 31 32 enum ioat_res { 33 IOAT_TEST_OK = 0, 34 IOAT_TEST_NO_DMA_ENGINE, 35 IOAT_TEST_NO_MEMORY, 36 IOAT_TEST_MISCOMPARE, 37 IOAT_TEST_INVALID_INPUT, 38 IOAT_NUM_RES 39 }; 40 41 enum ioat_test_kind { 42 IOAT_TEST_FILL = 0, 43 IOAT_TEST_DMA, 44 IOAT_TEST_RAW_DMA, 45 IOAT_TEST_DMA_8K, 46 IOAT_TEST_MEMCPY, 47 IOAT_TEST_DMA_8K_PB, 48 IOAT_TEST_DMA_CRC, 49 IOAT_TEST_DMA_CRC_COPY, 50 IOAT_NUM_TESTKINDS 51 }; 52 53 struct test_transaction; 54 55 struct ioat_test { 56 volatile uint32_t status[IOAT_NUM_RES]; 57 uint32_t channel_index; 58 59 enum ioat_test_kind testkind; 60 61 /* HW max of 1MB */ 62 uint32_t buffer_size; 63 uint32_t chain_depth; 64 uint32_t transactions; 65 66 /* 67 * If non-zero, duration is time in ms; 68 * If zero, bounded by 'transactions' above. 69 */ 70 uint32_t duration; 71 72 /* If true, check for miscompares after a copy. */ 73 bool verify; 74 75 /* DMA directly to/from some memory address */ 76 uint64_t raw_target; 77 void *raw_vtarget; 78 bool raw_write; 79 bool raw_is_virtual; 80 81 bool zero_stats; 82 /* Configure coalesce period */ 83 uint16_t coalesce_period; 84 85 /* Internal usage -- not test inputs */ 86 TAILQ_HEAD(, test_transaction) free_q; 87 TAILQ_HEAD(, test_transaction) pend_q; 88 volatile bool too_late; 89 }; 90 91 #define IOAT_DMATEST _IOWR('i', 0, struct ioat_test) 92 93 #endif /* __IOAT_TEST_H__ */ 94