1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 #ifndef __IOAT_TEST_H__ 27 #define __IOAT_TEST_H__ 28 29 enum ioat_res { 30 IOAT_TEST_OK = 0, 31 IOAT_TEST_NO_DMA_ENGINE, 32 IOAT_TEST_NO_MEMORY, 33 IOAT_TEST_MISCOMPARE, 34 IOAT_TEST_INVALID_INPUT, 35 IOAT_NUM_RES 36 }; 37 38 enum ioat_test_kind { 39 IOAT_TEST_FILL = 0, 40 IOAT_TEST_DMA, 41 IOAT_TEST_RAW_DMA, 42 IOAT_TEST_DMA_8K, 43 IOAT_TEST_MEMCPY, 44 IOAT_TEST_DMA_8K_PB, 45 IOAT_TEST_DMA_CRC, 46 IOAT_TEST_DMA_CRC_COPY, 47 IOAT_NUM_TESTKINDS 48 }; 49 50 struct test_transaction; 51 52 struct ioat_test { 53 volatile uint32_t status[IOAT_NUM_RES]; 54 uint32_t channel_index; 55 56 enum ioat_test_kind testkind; 57 58 /* HW max of 1MB */ 59 uint32_t buffer_size; 60 uint32_t chain_depth; 61 uint32_t transactions; 62 63 /* 64 * If non-zero, duration is time in ms; 65 * If zero, bounded by 'transactions' above. 66 */ 67 uint32_t duration; 68 69 /* If true, check for miscompares after a copy. */ 70 bool verify; 71 72 /* DMA directly to/from some memory address */ 73 uint64_t raw_target; 74 void *raw_vtarget; 75 bool raw_write; 76 bool raw_is_virtual; 77 78 bool zero_stats; 79 /* Configure coalesce period */ 80 uint16_t coalesce_period; 81 82 /* Internal usage -- not test inputs */ 83 TAILQ_HEAD(, test_transaction) free_q; 84 TAILQ_HEAD(, test_transaction) pend_q; 85 volatile bool too_late; 86 }; 87 88 #define IOAT_DMATEST _IOWR('i', 0, struct ioat_test) 89 90 #endif /* __IOAT_TEST_H__ */ 91