1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/conf.h> 32 #include <sys/ioccom.h> 33 #include <sys/kernel.h> 34 #include <sys/lock.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/rman.h> 39 #include <sys/sysctl.h> 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 #include <machine/stdarg.h> 45 #include <vm/vm.h> 46 #include <vm/vm_param.h> 47 #include <vm/pmap.h> 48 49 #include "ioat.h" 50 #include "ioat_hw.h" 51 #include "ioat_internal.h" 52 #include "ioat_test.h" 53 54 #ifndef time_after 55 #define time_after(a,b) ((long)(b) - (long)(a) < 0) 56 #endif 57 58 MALLOC_DEFINE(M_IOAT_TEST, "ioat_test", "ioat test allocations"); 59 60 #define IOAT_MAX_BUFS 256 61 62 struct test_transaction { 63 void *buf[IOAT_MAX_BUFS]; 64 uint32_t length; 65 uint32_t depth; 66 uint32_t crc[IOAT_MAX_BUFS]; 67 struct ioat_test *test; 68 TAILQ_ENTRY(test_transaction) entry; 69 }; 70 71 #define IT_LOCK() mtx_lock(&ioat_test_lk) 72 #define IT_UNLOCK() mtx_unlock(&ioat_test_lk) 73 #define IT_ASSERT() mtx_assert(&ioat_test_lk, MA_OWNED) 74 static struct mtx ioat_test_lk; 75 MTX_SYSINIT(ioat_test_lk, &ioat_test_lk, "test coordination mtx", MTX_DEF); 76 77 static int g_thread_index = 1; 78 static struct cdev *g_ioat_cdev = NULL; 79 80 #define ioat_test_log(v, ...) _ioat_test_log((v), "ioat_test: " __VA_ARGS__) 81 static void _ioat_test_log(int verbosity, const char *fmt, ...); 82 83 static void 84 ioat_test_transaction_destroy(struct test_transaction *tx) 85 { 86 struct ioat_test *test; 87 int i; 88 89 test = tx->test; 90 91 for (i = 0; i < IOAT_MAX_BUFS; i++) { 92 if (tx->buf[i] != NULL) { 93 if (test->testkind == IOAT_TEST_DMA_8K) 94 free(tx->buf[i], M_IOAT_TEST); 95 else 96 contigfree(tx->buf[i], tx->length, M_IOAT_TEST); 97 tx->buf[i] = NULL; 98 } 99 } 100 101 free(tx, M_IOAT_TEST); 102 } 103 104 static struct 105 test_transaction *ioat_test_transaction_create(struct ioat_test *test, 106 unsigned num_buffers) 107 { 108 struct test_transaction *tx; 109 unsigned i; 110 111 tx = malloc(sizeof(*tx), M_IOAT_TEST, M_NOWAIT | M_ZERO); 112 if (tx == NULL) 113 return (NULL); 114 115 tx->length = test->buffer_size; 116 117 for (i = 0; i < num_buffers; i++) { 118 if (test->testkind == IOAT_TEST_DMA_8K) 119 tx->buf[i] = malloc(test->buffer_size, M_IOAT_TEST, 120 M_NOWAIT); 121 else 122 tx->buf[i] = contigmalloc(test->buffer_size, 123 M_IOAT_TEST, M_NOWAIT, 0, BUS_SPACE_MAXADDR, 124 PAGE_SIZE, 0); 125 126 if (tx->buf[i] == NULL) { 127 ioat_test_transaction_destroy(tx); 128 return (NULL); 129 } 130 } 131 return (tx); 132 } 133 134 static void 135 dump_hex(void *p, size_t chunks) 136 { 137 size_t i, j; 138 139 for (i = 0; i < chunks; i++) { 140 for (j = 0; j < 8; j++) 141 printf("%08x ", ((uint32_t *)p)[i * 8 + j]); 142 printf("\n"); 143 } 144 } 145 146 static bool 147 ioat_compare_ok(struct test_transaction *tx) 148 { 149 struct ioat_test *test; 150 char *dst, *src; 151 uint32_t i, j; 152 153 test = tx->test; 154 155 for (i = 0; i < tx->depth; i++) { 156 dst = tx->buf[2 * i + 1]; 157 src = tx->buf[2 * i]; 158 159 if (test->testkind == IOAT_TEST_FILL) { 160 for (j = 0; j < tx->length; j += sizeof(uint64_t)) { 161 if (memcmp(src, &dst[j], 162 MIN(sizeof(uint64_t), tx->length - j)) 163 != 0) 164 return (false); 165 } 166 } else if (test->testkind == IOAT_TEST_DMA) { 167 if (memcmp(src, dst, tx->length) != 0) 168 return (false); 169 } else if (test->testkind == IOAT_TEST_RAW_DMA) { 170 if (test->raw_write) 171 dst = test->raw_vtarget; 172 dump_hex(dst, tx->length / 32); 173 } 174 } 175 return (true); 176 } 177 178 static void 179 ioat_dma_test_callback(void *arg, int error) 180 { 181 struct test_transaction *tx; 182 struct ioat_test *test; 183 184 if (error != 0) 185 ioat_test_log(0, "%s: Got error: %d\n", __func__, error); 186 187 tx = arg; 188 test = tx->test; 189 190 if (test->verify && !ioat_compare_ok(tx)) { 191 ioat_test_log(0, "miscompare found\n"); 192 atomic_add_32(&test->status[IOAT_TEST_MISCOMPARE], tx->depth); 193 } else if (!test->too_late) 194 atomic_add_32(&test->status[IOAT_TEST_OK], tx->depth); 195 196 IT_LOCK(); 197 TAILQ_REMOVE(&test->pend_q, tx, entry); 198 TAILQ_INSERT_TAIL(&test->free_q, tx, entry); 199 wakeup(&test->free_q); 200 IT_UNLOCK(); 201 } 202 203 static int 204 ioat_test_prealloc_memory(struct ioat_test *test, int index) 205 { 206 uint32_t i, j, k; 207 struct test_transaction *tx; 208 209 for (i = 0; i < test->transactions; i++) { 210 tx = ioat_test_transaction_create(test, test->chain_depth * 2); 211 if (tx == NULL) { 212 ioat_test_log(0, "tx == NULL - memory exhausted\n"); 213 test->status[IOAT_TEST_NO_MEMORY]++; 214 return (ENOMEM); 215 } 216 217 TAILQ_INSERT_HEAD(&test->free_q, tx, entry); 218 219 tx->test = test; 220 tx->depth = test->chain_depth; 221 222 /* fill in source buffers */ 223 for (j = 0; j < (tx->length / sizeof(uint32_t)); j++) { 224 uint32_t val = j + (index << 28); 225 226 for (k = 0; k < test->chain_depth; k++) { 227 ((uint32_t *)tx->buf[2*k])[j] = ~val; 228 ((uint32_t *)tx->buf[2*k+1])[j] = val; 229 } 230 } 231 } 232 return (0); 233 } 234 235 static void 236 ioat_test_release_memory(struct ioat_test *test) 237 { 238 struct test_transaction *tx, *s; 239 240 TAILQ_FOREACH_SAFE(tx, &test->free_q, entry, s) 241 ioat_test_transaction_destroy(tx); 242 TAILQ_INIT(&test->free_q); 243 244 TAILQ_FOREACH_SAFE(tx, &test->pend_q, entry, s) 245 ioat_test_transaction_destroy(tx); 246 TAILQ_INIT(&test->pend_q); 247 } 248 249 static void 250 ioat_test_submit_1_tx(struct ioat_test *test, bus_dmaengine_t dma) 251 { 252 struct test_transaction *tx; 253 struct bus_dmadesc *desc; 254 bus_dmaengine_callback_t cb; 255 bus_addr_t src, dest; 256 uint64_t fillpattern; 257 uint32_t i, flags; 258 259 desc = NULL; 260 261 IT_LOCK(); 262 while (TAILQ_EMPTY(&test->free_q)) 263 msleep(&test->free_q, &ioat_test_lk, 0, "test_submit", 0); 264 265 tx = TAILQ_FIRST(&test->free_q); 266 TAILQ_REMOVE(&test->free_q, tx, entry); 267 TAILQ_INSERT_HEAD(&test->pend_q, tx, entry); 268 IT_UNLOCK(); 269 270 if (test->testkind != IOAT_TEST_MEMCPY) 271 ioat_acquire(dma); 272 for (i = 0; i < tx->depth; i++) { 273 if (test->testkind == IOAT_TEST_MEMCPY) { 274 memcpy(tx->buf[2 * i + 1], tx->buf[2 * i], tx->length); 275 if (i == tx->depth - 1) 276 ioat_dma_test_callback(tx, 0); 277 continue; 278 } 279 280 src = vtophys((vm_offset_t)tx->buf[2*i]); 281 dest = vtophys((vm_offset_t)tx->buf[2*i+1]); 282 283 if (test->testkind == IOAT_TEST_RAW_DMA) { 284 if (test->raw_write) 285 dest = test->raw_target; 286 else 287 src = test->raw_target; 288 } 289 290 if (i == tx->depth - 1) { 291 cb = ioat_dma_test_callback; 292 flags = DMA_INT_EN; 293 } else { 294 cb = NULL; 295 flags = 0; 296 } 297 298 if (test->testkind == IOAT_TEST_DMA || 299 test->testkind == IOAT_TEST_RAW_DMA) 300 desc = ioat_copy(dma, dest, src, tx->length, cb, tx, 301 flags); 302 else if (test->testkind == IOAT_TEST_FILL) { 303 fillpattern = *(uint64_t *)tx->buf[2*i]; 304 desc = ioat_blockfill(dma, dest, fillpattern, 305 tx->length, cb, tx, flags); 306 } else if (test->testkind == IOAT_TEST_DMA_8K) { 307 bus_addr_t src2, dst2; 308 309 src2 = vtophys((vm_offset_t)tx->buf[2*i] + PAGE_SIZE); 310 dst2 = vtophys((vm_offset_t)tx->buf[2*i+1] + PAGE_SIZE); 311 312 desc = ioat_copy_8k_aligned(dma, dest, dst2, src, src2, 313 cb, tx, flags); 314 } else if (test->testkind == IOAT_TEST_DMA_8K_PB) { 315 bus_addr_t src2, dst2; 316 317 src2 = vtophys((vm_offset_t)tx->buf[2*i+1] + PAGE_SIZE); 318 dst2 = vtophys((vm_offset_t)tx->buf[2*i] + PAGE_SIZE); 319 320 desc = ioat_copy_8k_aligned(dma, dest, dst2, src, src2, 321 cb, tx, flags); 322 } else if (test->testkind == IOAT_TEST_DMA_CRC) { 323 bus_addr_t crc; 324 325 tx->crc[i] = 0; 326 crc = vtophys((vm_offset_t)&tx->crc[i]); 327 desc = ioat_crc(dma, src, tx->length, 328 NULL, crc, cb, tx, flags | DMA_CRC_STORE); 329 } else if (test->testkind == IOAT_TEST_DMA_CRC_COPY) { 330 bus_addr_t crc; 331 332 tx->crc[i] = 0; 333 crc = vtophys((vm_offset_t)&tx->crc[i]); 334 desc = ioat_copy_crc(dma, dest, src, tx->length, 335 NULL, crc, cb, tx, flags | DMA_CRC_STORE); 336 } 337 if (desc == NULL) 338 break; 339 } 340 if (test->testkind == IOAT_TEST_MEMCPY) 341 return; 342 ioat_release(dma); 343 344 /* 345 * We couldn't issue an IO -- either the device is being detached or 346 * the HW reset. Essentially spin until the device comes back up or 347 * our timer expires. 348 */ 349 if (desc == NULL && tx->depth > 0) { 350 atomic_add_32(&test->status[IOAT_TEST_NO_DMA_ENGINE], tx->depth); 351 IT_LOCK(); 352 TAILQ_REMOVE(&test->pend_q, tx, entry); 353 TAILQ_INSERT_HEAD(&test->free_q, tx, entry); 354 IT_UNLOCK(); 355 } 356 } 357 358 static void 359 ioat_dma_test(void *arg) 360 { 361 struct ioat_softc *ioat; 362 struct ioat_test *test; 363 bus_dmaengine_t dmaengine; 364 uint32_t loops; 365 int index, rc, start, end, error; 366 367 test = arg; 368 memset(__DEVOLATILE(void *, test->status), 0, sizeof(test->status)); 369 370 if ((test->testkind == IOAT_TEST_DMA_8K || 371 test->testkind == IOAT_TEST_DMA_8K_PB) && 372 test->buffer_size != 2 * PAGE_SIZE) { 373 ioat_test_log(0, "Asked for 8k test and buffer size isn't 8k\n"); 374 test->status[IOAT_TEST_INVALID_INPUT]++; 375 return; 376 } 377 378 if (test->buffer_size > 1024 * 1024) { 379 ioat_test_log(0, "Buffer size too large >1MB\n"); 380 test->status[IOAT_TEST_NO_MEMORY]++; 381 return; 382 } 383 384 if (test->chain_depth * 2 > IOAT_MAX_BUFS) { 385 ioat_test_log(0, "Depth too large (> %u)\n", 386 (unsigned)IOAT_MAX_BUFS / 2); 387 test->status[IOAT_TEST_NO_MEMORY]++; 388 return; 389 } 390 391 if (btoc((uint64_t)test->buffer_size * test->chain_depth * 392 test->transactions) > (physmem / 4)) { 393 ioat_test_log(0, "Sanity check failed -- test would " 394 "use more than 1/4 of phys mem.\n"); 395 test->status[IOAT_TEST_NO_MEMORY]++; 396 return; 397 } 398 399 if ((uint64_t)test->transactions * test->chain_depth > (1<<16)) { 400 ioat_test_log(0, "Sanity check failed -- test would " 401 "use more than available IOAT ring space.\n"); 402 test->status[IOAT_TEST_NO_MEMORY]++; 403 return; 404 } 405 406 if (test->testkind >= IOAT_NUM_TESTKINDS) { 407 ioat_test_log(0, "Invalid kind %u\n", 408 (unsigned)test->testkind); 409 test->status[IOAT_TEST_INVALID_INPUT]++; 410 return; 411 } 412 413 dmaengine = ioat_get_dmaengine(test->channel_index, M_NOWAIT); 414 if (dmaengine == NULL) { 415 ioat_test_log(0, "Couldn't acquire dmaengine\n"); 416 test->status[IOAT_TEST_NO_DMA_ENGINE]++; 417 return; 418 } 419 ioat = to_ioat_softc(dmaengine); 420 421 if (test->testkind == IOAT_TEST_FILL && 422 (ioat->capabilities & IOAT_DMACAP_BFILL) == 0) 423 { 424 ioat_test_log(0, 425 "Hardware doesn't support block fill, aborting test\n"); 426 test->status[IOAT_TEST_INVALID_INPUT]++; 427 goto out; 428 } 429 430 if (test->coalesce_period > ioat->intrdelay_max) { 431 ioat_test_log(0, 432 "Hardware doesn't support intrdelay of %u us.\n", 433 (unsigned)test->coalesce_period); 434 test->status[IOAT_TEST_INVALID_INPUT]++; 435 goto out; 436 } 437 error = ioat_set_interrupt_coalesce(dmaengine, test->coalesce_period); 438 if (error == ENODEV && test->coalesce_period == 0) 439 error = 0; 440 if (error != 0) { 441 ioat_test_log(0, "ioat_set_interrupt_coalesce: %d\n", error); 442 test->status[IOAT_TEST_INVALID_INPUT]++; 443 goto out; 444 } 445 446 if (test->zero_stats) 447 memset(&ioat->stats, 0, sizeof(ioat->stats)); 448 449 if (test->testkind == IOAT_TEST_RAW_DMA) { 450 if (test->raw_is_virtual) { 451 test->raw_vtarget = (void *)test->raw_target; 452 test->raw_target = vtophys(test->raw_vtarget); 453 } else { 454 test->raw_vtarget = pmap_mapdev(test->raw_target, 455 test->buffer_size); 456 } 457 } 458 459 index = g_thread_index++; 460 TAILQ_INIT(&test->free_q); 461 TAILQ_INIT(&test->pend_q); 462 463 if (test->duration == 0) 464 ioat_test_log(1, "Thread %d: num_loops remaining: 0x%08x\n", 465 index, test->transactions); 466 else 467 ioat_test_log(1, "Thread %d: starting\n", index); 468 469 rc = ioat_test_prealloc_memory(test, index); 470 if (rc != 0) { 471 ioat_test_log(0, "prealloc_memory: %d\n", rc); 472 goto out; 473 } 474 wmb(); 475 476 test->too_late = false; 477 start = ticks; 478 end = start + (((sbintime_t)test->duration * hz) / 1000); 479 480 for (loops = 0;; loops++) { 481 if (test->duration == 0 && loops >= test->transactions) 482 break; 483 else if (test->duration != 0 && time_after(ticks, end)) { 484 test->too_late = true; 485 break; 486 } 487 488 ioat_test_submit_1_tx(test, dmaengine); 489 } 490 491 ioat_test_log(1, "Test Elapsed: %d ticks (overrun %d), %d sec.\n", 492 ticks - start, ticks - end, (ticks - start) / hz); 493 494 IT_LOCK(); 495 while (!TAILQ_EMPTY(&test->pend_q)) 496 msleep(&test->free_q, &ioat_test_lk, 0, "ioattestcompl", hz); 497 IT_UNLOCK(); 498 499 ioat_test_log(1, "Test Elapsed2: %d ticks (overrun %d), %d sec.\n", 500 ticks - start, ticks - end, (ticks - start) / hz); 501 502 ioat_test_release_memory(test); 503 out: 504 if (test->testkind == IOAT_TEST_RAW_DMA && !test->raw_is_virtual) 505 pmap_unmapdev(test->raw_vtarget, test->buffer_size); 506 ioat_put_dmaengine(dmaengine); 507 } 508 509 static int 510 ioat_test_open(struct cdev *dev, int flags, int fmt, struct thread *td) 511 { 512 513 return (0); 514 } 515 516 static int 517 ioat_test_close(struct cdev *dev, int flags, int fmt, struct thread *td) 518 { 519 520 return (0); 521 } 522 523 static int 524 ioat_test_ioctl(struct cdev *dev, unsigned long cmd, caddr_t arg, int flag, 525 struct thread *td) 526 { 527 528 switch (cmd) { 529 case IOAT_DMATEST: 530 ioat_dma_test(arg); 531 break; 532 default: 533 return (EINVAL); 534 } 535 return (0); 536 } 537 538 static struct cdevsw ioat_cdevsw = { 539 .d_version = D_VERSION, 540 .d_flags = 0, 541 .d_open = ioat_test_open, 542 .d_close = ioat_test_close, 543 .d_ioctl = ioat_test_ioctl, 544 .d_name = "ioat_test", 545 }; 546 547 static int 548 enable_ioat_test(bool enable) 549 { 550 struct make_dev_args devargs; 551 int error = 0; 552 553 if (enable && g_ioat_cdev == NULL) { 554 make_dev_args_init(&devargs); 555 devargs.mda_devsw = &ioat_cdevsw; 556 devargs.mda_uid = UID_ROOT; 557 devargs.mda_gid = GID_WHEEL; 558 devargs.mda_mode = 0600; 559 error = make_dev_s(&devargs, &g_ioat_cdev, "ioat_test"); 560 } else if (!enable && g_ioat_cdev != NULL) { 561 destroy_dev(g_ioat_cdev); 562 g_ioat_cdev = NULL; 563 } 564 return (error); 565 } 566 567 static int 568 sysctl_enable_ioat_test(SYSCTL_HANDLER_ARGS) 569 { 570 int error, enabled; 571 572 enabled = (g_ioat_cdev != NULL); 573 error = sysctl_handle_int(oidp, &enabled, 0, req); 574 if (error != 0 || req->newptr == NULL) 575 return (error); 576 577 return (enable_ioat_test(enabled)); 578 } 579 SYSCTL_PROC(_hw_ioat, OID_AUTO, enable_ioat_test, 580 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 0, 581 sysctl_enable_ioat_test, "I", 582 "Non-zero: Enable the /dev/ioat_test device"); 583 584 void 585 ioat_test_attach(void) 586 { 587 char *val; 588 589 val = kern_getenv("hw.ioat.enable_ioat_test"); 590 if (val != NULL && strcmp(val, "0") != 0) 591 enable_ioat_test(true); 592 freeenv(val); 593 } 594 595 void 596 ioat_test_detach(void) 597 { 598 599 enable_ioat_test(false); 600 } 601 602 static void 603 _ioat_test_log(int verbosity, const char *fmt, ...) 604 { 605 va_list argp; 606 607 if (verbosity > g_ioat_debug_level) 608 return; 609 610 va_start(argp, fmt); 611 vprintf(fmt, argp); 612 va_end(argp); 613 } 614