1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/ioccom.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/sbuf.h> 42 #include <sys/sysctl.h> 43 #include <sys/time.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <machine/stdarg.h> 49 50 #include "ioat.h" 51 #include "ioat_hw.h" 52 #include "ioat_internal.h" 53 54 #define IOAT_INTR_TIMO (hz / 10) 55 #define IOAT_REFLK (&ioat->submit_lock) 56 57 static int ioat_probe(device_t device); 58 static int ioat_attach(device_t device); 59 static int ioat_detach(device_t device); 60 static int ioat_setup_intr(struct ioat_softc *ioat); 61 static int ioat_teardown_intr(struct ioat_softc *ioat); 62 static int ioat3_attach(device_t device); 63 static int ioat_start_channel(struct ioat_softc *ioat); 64 static int ioat_map_pci_bar(struct ioat_softc *ioat); 65 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 66 int error); 67 static void ioat_interrupt_handler(void *arg); 68 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 69 static int chanerr_to_errno(uint32_t); 70 static void ioat_process_events(struct ioat_softc *ioat); 71 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 72 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 73 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 74 struct ioat_descriptor **); 75 static void ioat_free_ring_entry(struct ioat_softc *ioat, 76 struct ioat_descriptor *desc); 77 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 78 int mflags); 79 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 80 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 81 uint32_t index); 82 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 83 uint32_t size, boolean_t need_dscr, int mflags); 84 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 85 struct ioat_descriptor **); 86 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 87 struct ioat_descriptor **); 88 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 89 static void ioat_timer_callback(void *arg); 90 static void dump_descriptor(void *hw_desc); 91 static void ioat_submit_single(struct ioat_softc *ioat); 92 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 93 int error); 94 static int ioat_reset_hw(struct ioat_softc *ioat); 95 static void ioat_setup_sysctl(device_t device); 96 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 97 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 98 enum ioat_ref_kind); 99 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 100 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 101 enum ioat_ref_kind, boolean_t); 102 static inline void ioat_putn(struct ioat_softc *, uint32_t, 103 enum ioat_ref_kind); 104 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 105 enum ioat_ref_kind); 106 static void ioat_drain_locked(struct ioat_softc *); 107 108 #define ioat_log_message(v, ...) do { \ 109 if ((v) <= g_ioat_debug_level) { \ 110 device_printf(ioat->device, __VA_ARGS__); \ 111 } \ 112 } while (0) 113 114 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 115 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 116 117 static int g_force_legacy_interrupts; 118 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 119 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 120 121 int g_ioat_debug_level = 0; 122 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 123 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 124 125 /* 126 * OS <-> Driver interface structures 127 */ 128 static device_method_t ioat_pci_methods[] = { 129 /* Device interface */ 130 DEVMETHOD(device_probe, ioat_probe), 131 DEVMETHOD(device_attach, ioat_attach), 132 DEVMETHOD(device_detach, ioat_detach), 133 { 0, 0 } 134 }; 135 136 static driver_t ioat_pci_driver = { 137 "ioat", 138 ioat_pci_methods, 139 sizeof(struct ioat_softc), 140 }; 141 142 static devclass_t ioat_devclass; 143 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 144 MODULE_VERSION(ioat, 1); 145 146 /* 147 * Private data structures 148 */ 149 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 150 static int ioat_channel_index = 0; 151 SYSCTL_INT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 152 "Number of IOAT channels attached"); 153 154 static struct _pcsid 155 { 156 u_int32_t type; 157 const char *desc; 158 } pci_ids[] = { 159 { 0x34308086, "TBG IOAT Ch0" }, 160 { 0x34318086, "TBG IOAT Ch1" }, 161 { 0x34328086, "TBG IOAT Ch2" }, 162 { 0x34338086, "TBG IOAT Ch3" }, 163 { 0x34298086, "TBG IOAT Ch4" }, 164 { 0x342a8086, "TBG IOAT Ch5" }, 165 { 0x342b8086, "TBG IOAT Ch6" }, 166 { 0x342c8086, "TBG IOAT Ch7" }, 167 168 { 0x37108086, "JSF IOAT Ch0" }, 169 { 0x37118086, "JSF IOAT Ch1" }, 170 { 0x37128086, "JSF IOAT Ch2" }, 171 { 0x37138086, "JSF IOAT Ch3" }, 172 { 0x37148086, "JSF IOAT Ch4" }, 173 { 0x37158086, "JSF IOAT Ch5" }, 174 { 0x37168086, "JSF IOAT Ch6" }, 175 { 0x37178086, "JSF IOAT Ch7" }, 176 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 177 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 178 179 { 0x3c208086, "SNB IOAT Ch0" }, 180 { 0x3c218086, "SNB IOAT Ch1" }, 181 { 0x3c228086, "SNB IOAT Ch2" }, 182 { 0x3c238086, "SNB IOAT Ch3" }, 183 { 0x3c248086, "SNB IOAT Ch4" }, 184 { 0x3c258086, "SNB IOAT Ch5" }, 185 { 0x3c268086, "SNB IOAT Ch6" }, 186 { 0x3c278086, "SNB IOAT Ch7" }, 187 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 188 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 189 190 { 0x0e208086, "IVB IOAT Ch0" }, 191 { 0x0e218086, "IVB IOAT Ch1" }, 192 { 0x0e228086, "IVB IOAT Ch2" }, 193 { 0x0e238086, "IVB IOAT Ch3" }, 194 { 0x0e248086, "IVB IOAT Ch4" }, 195 { 0x0e258086, "IVB IOAT Ch5" }, 196 { 0x0e268086, "IVB IOAT Ch6" }, 197 { 0x0e278086, "IVB IOAT Ch7" }, 198 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 199 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 200 201 { 0x2f208086, "HSW IOAT Ch0" }, 202 { 0x2f218086, "HSW IOAT Ch1" }, 203 { 0x2f228086, "HSW IOAT Ch2" }, 204 { 0x2f238086, "HSW IOAT Ch3" }, 205 { 0x2f248086, "HSW IOAT Ch4" }, 206 { 0x2f258086, "HSW IOAT Ch5" }, 207 { 0x2f268086, "HSW IOAT Ch6" }, 208 { 0x2f278086, "HSW IOAT Ch7" }, 209 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 210 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 211 212 { 0x0c508086, "BWD IOAT Ch0" }, 213 { 0x0c518086, "BWD IOAT Ch1" }, 214 { 0x0c528086, "BWD IOAT Ch2" }, 215 { 0x0c538086, "BWD IOAT Ch3" }, 216 217 { 0x6f508086, "BDXDE IOAT Ch0" }, 218 { 0x6f518086, "BDXDE IOAT Ch1" }, 219 { 0x6f528086, "BDXDE IOAT Ch2" }, 220 { 0x6f538086, "BDXDE IOAT Ch3" }, 221 222 { 0x00000000, NULL } 223 }; 224 225 /* 226 * OS <-> Driver linkage functions 227 */ 228 static int 229 ioat_probe(device_t device) 230 { 231 struct _pcsid *ep; 232 u_int32_t type; 233 234 type = pci_get_devid(device); 235 for (ep = pci_ids; ep->type; ep++) { 236 if (ep->type == type) { 237 device_set_desc(device, ep->desc); 238 return (0); 239 } 240 } 241 return (ENXIO); 242 } 243 244 static int 245 ioat_attach(device_t device) 246 { 247 struct ioat_softc *ioat; 248 int error; 249 250 ioat = DEVICE2SOFTC(device); 251 ioat->device = device; 252 253 error = ioat_map_pci_bar(ioat); 254 if (error != 0) 255 goto err; 256 257 ioat->version = ioat_read_cbver(ioat); 258 if (ioat->version < IOAT_VER_3_0) { 259 error = ENODEV; 260 goto err; 261 } 262 263 error = ioat3_attach(device); 264 if (error != 0) 265 goto err; 266 267 error = pci_enable_busmaster(device); 268 if (error != 0) 269 goto err; 270 271 error = ioat_setup_intr(ioat); 272 if (error != 0) 273 goto err; 274 275 error = ioat_reset_hw(ioat); 276 if (error != 0) 277 goto err; 278 279 ioat_process_events(ioat); 280 ioat_setup_sysctl(device); 281 282 ioat->chan_idx = ioat_channel_index; 283 ioat_channel[ioat_channel_index++] = ioat; 284 ioat_test_attach(); 285 286 err: 287 if (error != 0) 288 ioat_detach(device); 289 return (error); 290 } 291 292 static int 293 ioat_detach(device_t device) 294 { 295 struct ioat_softc *ioat; 296 297 ioat = DEVICE2SOFTC(device); 298 299 ioat_test_detach(); 300 301 mtx_lock(IOAT_REFLK); 302 ioat->quiescing = TRUE; 303 ioat_channel[ioat->chan_idx] = NULL; 304 305 ioat_drain_locked(ioat); 306 mtx_unlock(IOAT_REFLK); 307 308 ioat_teardown_intr(ioat); 309 callout_drain(&ioat->timer); 310 311 pci_disable_busmaster(device); 312 313 if (ioat->pci_resource != NULL) 314 bus_release_resource(device, SYS_RES_MEMORY, 315 ioat->pci_resource_id, ioat->pci_resource); 316 317 if (ioat->ring != NULL) 318 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 319 320 if (ioat->comp_update != NULL) { 321 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 322 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 323 ioat->comp_update_map); 324 bus_dma_tag_destroy(ioat->comp_update_tag); 325 } 326 327 bus_dma_tag_destroy(ioat->hw_desc_tag); 328 329 return (0); 330 } 331 332 static int 333 ioat_teardown_intr(struct ioat_softc *ioat) 334 { 335 336 if (ioat->tag != NULL) 337 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 338 339 if (ioat->res != NULL) 340 bus_release_resource(ioat->device, SYS_RES_IRQ, 341 rman_get_rid(ioat->res), ioat->res); 342 343 pci_release_msi(ioat->device); 344 return (0); 345 } 346 347 static int 348 ioat_start_channel(struct ioat_softc *ioat) 349 { 350 uint64_t status; 351 uint32_t chanerr; 352 int i; 353 354 ioat_acquire(&ioat->dmaengine); 355 ioat_null(&ioat->dmaengine, NULL, NULL, 0); 356 ioat_release(&ioat->dmaengine); 357 358 for (i = 0; i < 100; i++) { 359 DELAY(1); 360 status = ioat_get_chansts(ioat); 361 if (is_ioat_idle(status)) 362 return (0); 363 } 364 365 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 366 ioat_log_message(0, "could not start channel: " 367 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 368 IOAT_CHANERR_STR); 369 return (ENXIO); 370 } 371 372 /* 373 * Initialize Hardware 374 */ 375 static int 376 ioat3_attach(device_t device) 377 { 378 struct ioat_softc *ioat; 379 struct ioat_descriptor **ring; 380 struct ioat_descriptor *next; 381 struct ioat_dma_hw_descriptor *dma_hw_desc; 382 int i, num_descriptors; 383 int error; 384 uint8_t xfercap; 385 386 error = 0; 387 ioat = DEVICE2SOFTC(device); 388 ioat->capabilities = ioat_read_dmacapability(ioat); 389 390 ioat_log_message(1, "Capabilities: %b\n", (int)ioat->capabilities, 391 IOAT_DMACAP_STR); 392 393 xfercap = ioat_read_xfercap(ioat); 394 ioat->max_xfer_size = 1 << xfercap; 395 396 /* TODO: need to check DCA here if we ever do XOR/PQ */ 397 398 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 399 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 400 callout_init(&ioat->timer, 1); 401 402 /* Establish lock order for Witness */ 403 mtx_lock(&ioat->submit_lock); 404 mtx_lock(&ioat->cleanup_lock); 405 mtx_unlock(&ioat->cleanup_lock); 406 mtx_unlock(&ioat->submit_lock); 407 408 ioat->is_resize_pending = FALSE; 409 ioat->is_completion_pending = FALSE; 410 ioat->is_reset_pending = FALSE; 411 ioat->is_channel_running = FALSE; 412 413 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 414 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 415 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 416 &ioat->comp_update_tag); 417 418 error = bus_dmamem_alloc(ioat->comp_update_tag, 419 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 420 if (ioat->comp_update == NULL) 421 return (ENOMEM); 422 423 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 424 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 425 0); 426 if (error != 0) 427 return (error); 428 429 ioat->ring_size_order = IOAT_MIN_ORDER; 430 431 num_descriptors = 1 << ioat->ring_size_order; 432 433 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 434 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 435 sizeof(struct ioat_dma_hw_descriptor), 1, 436 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 437 &ioat->hw_desc_tag); 438 439 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 440 M_ZERO | M_WAITOK); 441 if (ioat->ring == NULL) 442 return (ENOMEM); 443 444 ring = ioat->ring; 445 for (i = 0; i < num_descriptors; i++) { 446 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 447 if (ring[i] == NULL) 448 return (ENOMEM); 449 450 ring[i]->id = i; 451 } 452 453 for (i = 0; i < num_descriptors - 1; i++) { 454 next = ring[i + 1]; 455 dma_hw_desc = ring[i]->u.dma; 456 457 dma_hw_desc->next = next->hw_desc_bus_addr; 458 } 459 460 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 461 462 ioat->head = ioat->hw_head = 0; 463 ioat->tail = 0; 464 ioat->last_seen = 0; 465 return (0); 466 } 467 468 static int 469 ioat_map_pci_bar(struct ioat_softc *ioat) 470 { 471 472 ioat->pci_resource_id = PCIR_BAR(0); 473 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 474 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 475 476 if (ioat->pci_resource == NULL) { 477 ioat_log_message(0, "unable to allocate pci resource\n"); 478 return (ENODEV); 479 } 480 481 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 482 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 483 return (0); 484 } 485 486 static void 487 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 488 { 489 struct ioat_softc *ioat = arg; 490 491 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 492 ioat->comp_update_bus_addr = seg[0].ds_addr; 493 } 494 495 static void 496 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 497 { 498 bus_addr_t *baddr; 499 500 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 501 baddr = arg; 502 *baddr = segs->ds_addr; 503 } 504 505 /* 506 * Interrupt setup and handlers 507 */ 508 static int 509 ioat_setup_intr(struct ioat_softc *ioat) 510 { 511 uint32_t num_vectors; 512 int error; 513 boolean_t use_msix; 514 boolean_t force_legacy_interrupts; 515 516 use_msix = FALSE; 517 force_legacy_interrupts = FALSE; 518 519 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 520 num_vectors = 1; 521 pci_alloc_msix(ioat->device, &num_vectors); 522 if (num_vectors == 1) 523 use_msix = TRUE; 524 } 525 526 if (use_msix) { 527 ioat->rid = 1; 528 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 529 &ioat->rid, RF_ACTIVE); 530 } else { 531 ioat->rid = 0; 532 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 533 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 534 } 535 if (ioat->res == NULL) { 536 ioat_log_message(0, "bus_alloc_resource failed\n"); 537 return (ENOMEM); 538 } 539 540 ioat->tag = NULL; 541 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 542 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 543 if (error != 0) { 544 ioat_log_message(0, "bus_setup_intr failed\n"); 545 return (error); 546 } 547 548 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 549 return (0); 550 } 551 552 static boolean_t 553 ioat_model_resets_msix(struct ioat_softc *ioat) 554 { 555 u_int32_t pciid; 556 557 pciid = pci_get_devid(ioat->device); 558 switch (pciid) { 559 /* BWD: */ 560 case 0x0c508086: 561 case 0x0c518086: 562 case 0x0c528086: 563 case 0x0c538086: 564 /* BDXDE: */ 565 case 0x6f508086: 566 case 0x6f518086: 567 case 0x6f528086: 568 case 0x6f538086: 569 return (TRUE); 570 } 571 572 return (FALSE); 573 } 574 575 static void 576 ioat_interrupt_handler(void *arg) 577 { 578 struct ioat_softc *ioat = arg; 579 580 ioat_process_events(ioat); 581 } 582 583 static int 584 chanerr_to_errno(uint32_t chanerr) 585 { 586 587 if (chanerr == 0) 588 return (0); 589 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 590 return (EFAULT); 591 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 592 return (EIO); 593 /* This one is probably our fault: */ 594 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 595 return (EIO); 596 return (EIO); 597 } 598 599 static void 600 ioat_process_events(struct ioat_softc *ioat) 601 { 602 struct ioat_descriptor *desc; 603 struct bus_dmadesc *dmadesc; 604 uint64_t comp_update, status; 605 uint32_t completed, chanerr; 606 int error; 607 608 mtx_lock(&ioat->cleanup_lock); 609 610 completed = 0; 611 comp_update = *ioat->comp_update; 612 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 613 614 CTR0(KTR_IOAT, __func__); 615 616 if (status == ioat->last_seen) 617 goto out; 618 619 while (1) { 620 desc = ioat_get_ring_entry(ioat, ioat->tail); 621 dmadesc = &desc->bus_dmadesc; 622 CTR1(KTR_IOAT, "completing desc %d", ioat->tail); 623 624 if (dmadesc->callback_fn != NULL) 625 dmadesc->callback_fn(dmadesc->callback_arg, 0); 626 627 completed++; 628 ioat->tail++; 629 if (desc->hw_desc_bus_addr == status) 630 break; 631 } 632 633 ioat->last_seen = desc->hw_desc_bus_addr; 634 635 if (ioat->head == ioat->tail) { 636 ioat->is_completion_pending = FALSE; 637 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 638 ioat_timer_callback, ioat); 639 } 640 641 out: 642 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 643 mtx_unlock(&ioat->cleanup_lock); 644 645 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 646 wakeup(&ioat->tail); 647 648 if (!is_ioat_halted(comp_update)) 649 return; 650 651 /* 652 * Fatal programming error on this DMA channel. Flush any outstanding 653 * work with error status and restart the engine. 654 */ 655 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 656 mtx_lock(&ioat->submit_lock); 657 mtx_lock(&ioat->cleanup_lock); 658 ioat->quiescing = TRUE; 659 660 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 661 ioat_halted_debug(ioat, chanerr); 662 663 while (ioat_get_active(ioat) > 0) { 664 desc = ioat_get_ring_entry(ioat, ioat->tail); 665 dmadesc = &desc->bus_dmadesc; 666 CTR1(KTR_IOAT, "completing err desc %d", ioat->tail); 667 668 if (dmadesc->callback_fn != NULL) 669 dmadesc->callback_fn(dmadesc->callback_arg, 670 chanerr_to_errno(chanerr)); 671 672 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 673 ioat->tail++; 674 } 675 676 /* Clear error status */ 677 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 678 679 mtx_unlock(&ioat->cleanup_lock); 680 mtx_unlock(&ioat->submit_lock); 681 682 ioat_log_message(0, "Resetting channel to recover from error\n"); 683 error = ioat_reset_hw(ioat); 684 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 685 } 686 687 /* 688 * User API functions 689 */ 690 bus_dmaengine_t 691 ioat_get_dmaengine(uint32_t index) 692 { 693 struct ioat_softc *sc; 694 695 if (index >= ioat_channel_index) 696 return (NULL); 697 698 sc = ioat_channel[index]; 699 if (sc == NULL || sc->quiescing) 700 return (NULL); 701 702 return (&ioat_get(sc, IOAT_DMAENGINE_REF)->dmaengine); 703 } 704 705 void 706 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 707 { 708 struct ioat_softc *ioat; 709 710 ioat = to_ioat_softc(dmaengine); 711 ioat_put(ioat, IOAT_DMAENGINE_REF); 712 } 713 714 void 715 ioat_acquire(bus_dmaengine_t dmaengine) 716 { 717 struct ioat_softc *ioat; 718 719 ioat = to_ioat_softc(dmaengine); 720 mtx_lock(&ioat->submit_lock); 721 CTR0(KTR_IOAT, __func__); 722 } 723 724 void 725 ioat_release(bus_dmaengine_t dmaengine) 726 { 727 struct ioat_softc *ioat; 728 729 ioat = to_ioat_softc(dmaengine); 730 CTR0(KTR_IOAT, __func__); 731 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 732 mtx_unlock(&ioat->submit_lock); 733 } 734 735 static struct ioat_descriptor * 736 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 737 uint32_t size, uint64_t src, uint64_t dst, 738 bus_dmaengine_callback_t callback_fn, void *callback_arg, 739 uint32_t flags) 740 { 741 struct ioat_generic_hw_descriptor *hw_desc; 742 struct ioat_descriptor *desc; 743 int mflags; 744 745 mtx_assert(&ioat->submit_lock, MA_OWNED); 746 747 KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x", 748 flags & ~DMA_ALL_FLAGS)); 749 if ((flags & DMA_NO_WAIT) != 0) 750 mflags = M_NOWAIT; 751 else 752 mflags = M_WAITOK; 753 754 if (size > ioat->max_xfer_size) { 755 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 756 __func__, ioat->max_xfer_size, (unsigned)size); 757 return (NULL); 758 } 759 760 if (ioat_reserve_space(ioat, 1, mflags) != 0) 761 return (NULL); 762 763 desc = ioat_get_ring_entry(ioat, ioat->head); 764 hw_desc = desc->u.generic; 765 766 hw_desc->u.control_raw = 0; 767 hw_desc->u.control_generic.op = op; 768 hw_desc->u.control_generic.completion_update = 1; 769 770 if ((flags & DMA_INT_EN) != 0) 771 hw_desc->u.control_generic.int_enable = 1; 772 773 hw_desc->size = size; 774 hw_desc->src_addr = src; 775 hw_desc->dest_addr = dst; 776 777 desc->bus_dmadesc.callback_fn = callback_fn; 778 desc->bus_dmadesc.callback_arg = callback_arg; 779 return (desc); 780 } 781 782 struct bus_dmadesc * 783 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 784 void *callback_arg, uint32_t flags) 785 { 786 struct ioat_dma_hw_descriptor *hw_desc; 787 struct ioat_descriptor *desc; 788 struct ioat_softc *ioat; 789 790 CTR0(KTR_IOAT, __func__); 791 ioat = to_ioat_softc(dmaengine); 792 793 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 794 callback_arg, flags); 795 if (desc == NULL) 796 return (NULL); 797 798 hw_desc = desc->u.dma; 799 hw_desc->u.control.null = 1; 800 ioat_submit_single(ioat); 801 return (&desc->bus_dmadesc); 802 } 803 804 struct bus_dmadesc * 805 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 806 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 807 void *callback_arg, uint32_t flags) 808 { 809 struct ioat_dma_hw_descriptor *hw_desc; 810 struct ioat_descriptor *desc; 811 struct ioat_softc *ioat; 812 813 CTR0(KTR_IOAT, __func__); 814 ioat = to_ioat_softc(dmaengine); 815 816 if (((src | dst) & (0xffffull << 48)) != 0) { 817 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 818 __func__); 819 return (NULL); 820 } 821 822 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 823 callback_arg, flags); 824 if (desc == NULL) 825 return (NULL); 826 827 hw_desc = desc->u.dma; 828 if (g_ioat_debug_level >= 3) 829 dump_descriptor(hw_desc); 830 831 ioat_submit_single(ioat); 832 return (&desc->bus_dmadesc); 833 } 834 835 struct bus_dmadesc * 836 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 837 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 838 uint32_t flags) 839 { 840 struct ioat_fill_hw_descriptor *hw_desc; 841 struct ioat_descriptor *desc; 842 struct ioat_softc *ioat; 843 844 CTR0(KTR_IOAT, __func__); 845 ioat = to_ioat_softc(dmaengine); 846 847 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 848 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 849 __func__); 850 return (NULL); 851 } 852 853 if ((dst & (0xffffull << 48)) != 0) { 854 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 855 __func__); 856 return (NULL); 857 } 858 859 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 860 callback_fn, callback_arg, flags); 861 if (desc == NULL) 862 return (NULL); 863 864 hw_desc = desc->u.fill; 865 if (g_ioat_debug_level >= 3) 866 dump_descriptor(hw_desc); 867 868 ioat_submit_single(ioat); 869 return (&desc->bus_dmadesc); 870 } 871 872 /* 873 * Ring Management 874 */ 875 static inline uint32_t 876 ioat_get_active(struct ioat_softc *ioat) 877 { 878 879 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 880 } 881 882 static inline uint32_t 883 ioat_get_ring_space(struct ioat_softc *ioat) 884 { 885 886 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 887 } 888 889 static struct ioat_descriptor * 890 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 891 { 892 struct ioat_generic_hw_descriptor *hw_desc; 893 struct ioat_descriptor *desc; 894 int error, busdmaflag; 895 896 error = ENOMEM; 897 hw_desc = NULL; 898 899 if ((mflags & M_WAITOK) != 0) 900 busdmaflag = BUS_DMA_WAITOK; 901 else 902 busdmaflag = BUS_DMA_NOWAIT; 903 904 desc = malloc(sizeof(*desc), M_IOAT, mflags); 905 if (desc == NULL) 906 goto out; 907 908 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 909 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 910 if (hw_desc == NULL) 911 goto out; 912 913 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 914 desc->u.generic = hw_desc; 915 916 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 917 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 918 busdmaflag); 919 if (error) 920 goto out; 921 922 out: 923 if (error) { 924 ioat_free_ring_entry(ioat, desc); 925 return (NULL); 926 } 927 return (desc); 928 } 929 930 static void 931 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 932 { 933 934 if (desc == NULL) 935 return; 936 937 if (desc->u.generic) 938 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 939 ioat->hw_desc_map); 940 free(desc, M_IOAT); 941 } 942 943 /* 944 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 945 * for 'num_descs'. 946 * 947 * If mflags contains M_WAITOK, blocks until enough space is available. 948 * 949 * Returns zero on success, or an errno on error. If num_descs is beyond the 950 * maximum ring size, returns EINVAl; if allocation would block and mflags 951 * contains M_NOWAIT, returns EAGAIN. 952 * 953 * Must be called with the submit_lock held; returns with the lock held. The 954 * lock may be dropped to allocate the ring. 955 * 956 * (The submit_lock is needed to add any entries to the ring, so callers are 957 * assured enough room is available.) 958 */ 959 static int 960 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 961 { 962 struct ioat_descriptor **new_ring; 963 uint32_t order; 964 int error; 965 966 mtx_assert(&ioat->submit_lock, MA_OWNED); 967 error = 0; 968 969 if (num_descs < 1 || num_descs > (1 << IOAT_MAX_ORDER)) { 970 error = EINVAL; 971 goto out; 972 } 973 if (ioat->quiescing) { 974 error = ENXIO; 975 goto out; 976 } 977 978 for (;;) { 979 if (ioat_get_ring_space(ioat) >= num_descs) 980 goto out; 981 982 order = ioat->ring_size_order; 983 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 984 if ((mflags & M_WAITOK) != 0) { 985 msleep(&ioat->tail, &ioat->submit_lock, 0, 986 "ioat_rsz", 0); 987 continue; 988 } 989 990 error = EAGAIN; 991 break; 992 } 993 994 ioat->is_resize_pending = TRUE; 995 for (;;) { 996 mtx_unlock(&ioat->submit_lock); 997 998 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 999 TRUE, mflags); 1000 1001 mtx_lock(&ioat->submit_lock); 1002 KASSERT(ioat->ring_size_order == order, 1003 ("is_resize_pending should protect order")); 1004 1005 if (new_ring == NULL) { 1006 KASSERT((mflags & M_WAITOK) == 0, 1007 ("allocation failed")); 1008 error = EAGAIN; 1009 break; 1010 } 1011 1012 error = ring_grow(ioat, order, new_ring); 1013 if (error == 0) 1014 break; 1015 } 1016 ioat->is_resize_pending = FALSE; 1017 wakeup(&ioat->tail); 1018 if (error) 1019 break; 1020 } 1021 1022 out: 1023 mtx_assert(&ioat->submit_lock, MA_OWNED); 1024 return (error); 1025 } 1026 1027 static struct ioat_descriptor ** 1028 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1029 int mflags) 1030 { 1031 struct ioat_descriptor **ring; 1032 uint32_t i; 1033 int error; 1034 1035 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1036 1037 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1038 if (ring == NULL) 1039 return (NULL); 1040 1041 if (need_dscr) { 1042 error = ENOMEM; 1043 for (i = size / 2; i < size; i++) { 1044 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1045 if (ring[i] == NULL) 1046 goto out; 1047 ring[i]->id = i; 1048 } 1049 } 1050 error = 0; 1051 1052 out: 1053 if (error != 0 && ring != NULL) { 1054 ioat_free_ring(ioat, size, ring); 1055 ring = NULL; 1056 } 1057 return (ring); 1058 } 1059 1060 static void 1061 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1062 struct ioat_descriptor **ring) 1063 { 1064 uint32_t i; 1065 1066 for (i = 0; i < size; i++) { 1067 if (ring[i] != NULL) 1068 ioat_free_ring_entry(ioat, ring[i]); 1069 } 1070 free(ring, M_IOAT); 1071 } 1072 1073 static struct ioat_descriptor * 1074 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1075 { 1076 1077 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1078 } 1079 1080 static int 1081 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1082 struct ioat_descriptor **newring) 1083 { 1084 struct ioat_descriptor *tmp, *next; 1085 struct ioat_dma_hw_descriptor *hw; 1086 uint32_t oldsize, newsize, head, tail, i, end; 1087 int error; 1088 1089 CTR0(KTR_IOAT, __func__); 1090 1091 mtx_assert(&ioat->submit_lock, MA_OWNED); 1092 1093 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1094 error = EINVAL; 1095 goto out; 1096 } 1097 1098 oldsize = (1 << oldorder); 1099 newsize = (1 << (oldorder + 1)); 1100 1101 mtx_lock(&ioat->cleanup_lock); 1102 1103 head = ioat->head & (oldsize - 1); 1104 tail = ioat->tail & (oldsize - 1); 1105 1106 /* Copy old descriptors to new ring */ 1107 for (i = 0; i < oldsize; i++) 1108 newring[i] = ioat->ring[i]; 1109 1110 /* 1111 * If head has wrapped but tail hasn't, we must swap some descriptors 1112 * around so that tail can increment directly to head. 1113 */ 1114 if (head < tail) { 1115 for (i = 0; i <= head; i++) { 1116 tmp = newring[oldsize + i]; 1117 1118 newring[oldsize + i] = newring[i]; 1119 newring[oldsize + i]->id = oldsize + i; 1120 1121 newring[i] = tmp; 1122 newring[i]->id = i; 1123 } 1124 head += oldsize; 1125 } 1126 1127 KASSERT(head >= tail, ("invariants")); 1128 1129 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1130 if (head < oldsize) { 1131 i = oldsize - 1; 1132 end = newsize; 1133 } else { 1134 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1135 i = head; 1136 end = newsize + (head - oldsize) + 1; 1137 } 1138 1139 /* 1140 * Fix up hardware ring, being careful not to trample the active 1141 * section (tail -> head). 1142 */ 1143 for (; i < end; i++) { 1144 KASSERT((i & (newsize - 1)) < tail || 1145 (i & (newsize - 1)) >= head, ("trampling snake")); 1146 1147 next = newring[(i + 1) & (newsize - 1)]; 1148 hw = newring[i & (newsize - 1)]->u.dma; 1149 hw->next = next->hw_desc_bus_addr; 1150 } 1151 1152 free(ioat->ring, M_IOAT); 1153 ioat->ring = newring; 1154 ioat->ring_size_order = oldorder + 1; 1155 ioat->tail = tail; 1156 ioat->head = head; 1157 error = 0; 1158 1159 mtx_unlock(&ioat->cleanup_lock); 1160 out: 1161 if (error) 1162 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1163 return (error); 1164 } 1165 1166 static int 1167 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1168 struct ioat_descriptor **newring) 1169 { 1170 struct ioat_dma_hw_descriptor *hw; 1171 struct ioat_descriptor *ent, *next; 1172 uint32_t oldsize, newsize, current_idx, new_idx, i; 1173 int error; 1174 1175 CTR0(KTR_IOAT, __func__); 1176 1177 mtx_assert(&ioat->submit_lock, MA_OWNED); 1178 1179 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1180 error = EINVAL; 1181 goto out_unlocked; 1182 } 1183 1184 oldsize = (1 << oldorder); 1185 newsize = (1 << (oldorder - 1)); 1186 1187 mtx_lock(&ioat->cleanup_lock); 1188 1189 /* Can't shrink below current active set! */ 1190 if (ioat_get_active(ioat) >= newsize) { 1191 error = ENOMEM; 1192 goto out; 1193 } 1194 1195 /* 1196 * Copy current descriptors to the new ring, dropping the removed 1197 * descriptors. 1198 */ 1199 for (i = 0; i < newsize; i++) { 1200 current_idx = (ioat->tail + i) & (oldsize - 1); 1201 new_idx = (ioat->tail + i) & (newsize - 1); 1202 1203 newring[new_idx] = ioat->ring[current_idx]; 1204 newring[new_idx]->id = new_idx; 1205 } 1206 1207 /* Free deleted descriptors */ 1208 for (i = newsize; i < oldsize; i++) { 1209 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1210 ioat_free_ring_entry(ioat, ent); 1211 } 1212 1213 /* Fix up hardware ring. */ 1214 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1215 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1216 hw->next = next->hw_desc_bus_addr; 1217 1218 free(ioat->ring, M_IOAT); 1219 ioat->ring = newring; 1220 ioat->ring_size_order = oldorder - 1; 1221 error = 0; 1222 1223 out: 1224 mtx_unlock(&ioat->cleanup_lock); 1225 out_unlocked: 1226 if (error) 1227 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1228 return (error); 1229 } 1230 1231 static void 1232 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1233 { 1234 struct ioat_descriptor *desc; 1235 1236 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1237 IOAT_CHANERR_STR); 1238 if (chanerr == 0) 1239 return; 1240 1241 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1242 1243 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1244 dump_descriptor(desc->u.raw); 1245 1246 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1247 dump_descriptor(desc->u.raw); 1248 } 1249 1250 static void 1251 ioat_timer_callback(void *arg) 1252 { 1253 struct ioat_descriptor **newring; 1254 struct ioat_softc *ioat; 1255 uint32_t order; 1256 1257 ioat = arg; 1258 ioat_log_message(1, "%s\n", __func__); 1259 1260 if (ioat->is_completion_pending) { 1261 ioat_process_events(ioat); 1262 return; 1263 } 1264 1265 /* Slowly scale the ring down if idle. */ 1266 mtx_lock(&ioat->submit_lock); 1267 order = ioat->ring_size_order; 1268 if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) { 1269 mtx_unlock(&ioat->submit_lock); 1270 goto out; 1271 } 1272 ioat->is_resize_pending = TRUE; 1273 mtx_unlock(&ioat->submit_lock); 1274 1275 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1276 M_NOWAIT); 1277 1278 mtx_lock(&ioat->submit_lock); 1279 KASSERT(ioat->ring_size_order == order, 1280 ("resize_pending protects order")); 1281 1282 if (newring != NULL) 1283 ring_shrink(ioat, order, newring); 1284 1285 ioat->is_resize_pending = FALSE; 1286 mtx_unlock(&ioat->submit_lock); 1287 1288 out: 1289 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1290 callout_reset(&ioat->timer, 10 * hz, 1291 ioat_timer_callback, ioat); 1292 } 1293 1294 /* 1295 * Support Functions 1296 */ 1297 static void 1298 ioat_submit_single(struct ioat_softc *ioat) 1299 { 1300 1301 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1302 atomic_add_rel_int(&ioat->head, 1); 1303 atomic_add_rel_int(&ioat->hw_head, 1); 1304 1305 if (!ioat->is_completion_pending) { 1306 ioat->is_completion_pending = TRUE; 1307 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 1308 ioat_timer_callback, ioat); 1309 } 1310 } 1311 1312 static int 1313 ioat_reset_hw(struct ioat_softc *ioat) 1314 { 1315 uint64_t status; 1316 uint32_t chanerr; 1317 unsigned timeout; 1318 int error; 1319 1320 mtx_lock(IOAT_REFLK); 1321 ioat->quiescing = TRUE; 1322 ioat_drain_locked(ioat); 1323 mtx_unlock(IOAT_REFLK); 1324 1325 status = ioat_get_chansts(ioat); 1326 if (is_ioat_active(status) || is_ioat_idle(status)) 1327 ioat_suspend(ioat); 1328 1329 /* Wait at most 20 ms */ 1330 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1331 timeout < 20; timeout++) { 1332 DELAY(1000); 1333 status = ioat_get_chansts(ioat); 1334 } 1335 if (timeout == 20) { 1336 error = ETIMEDOUT; 1337 goto out; 1338 } 1339 1340 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1341 1342 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1343 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1344 1345 /* 1346 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1347 * that can cause stability issues for IOAT v3. 1348 */ 1349 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1350 4); 1351 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1352 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1353 1354 /* 1355 * BDXDE and BWD models reset MSI-X registers on device reset. 1356 * Save/restore their contents manually. 1357 */ 1358 if (ioat_model_resets_msix(ioat)) { 1359 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1360 pci_save_state(ioat->device); 1361 } 1362 1363 ioat_reset(ioat); 1364 1365 /* Wait at most 20 ms */ 1366 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1367 DELAY(1000); 1368 if (timeout == 20) { 1369 error = ETIMEDOUT; 1370 goto out; 1371 } 1372 1373 if (ioat_model_resets_msix(ioat)) { 1374 ioat_log_message(1, "device resets registers; restored\n"); 1375 pci_restore_state(ioat->device); 1376 } 1377 1378 /* Reset attempts to return the hardware to "halted." */ 1379 status = ioat_get_chansts(ioat); 1380 if (is_ioat_active(status) || is_ioat_idle(status)) { 1381 /* So this really shouldn't happen... */ 1382 ioat_log_message(0, "Device is active after a reset?\n"); 1383 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1384 error = 0; 1385 goto out; 1386 } 1387 1388 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1389 if (chanerr != 0) { 1390 mtx_lock(&ioat->cleanup_lock); 1391 ioat_halted_debug(ioat, chanerr); 1392 mtx_unlock(&ioat->cleanup_lock); 1393 error = EIO; 1394 goto out; 1395 } 1396 1397 /* 1398 * Bring device back online after reset. Writing CHAINADDR brings the 1399 * device back to active. 1400 * 1401 * The internal ring counter resets to zero, so we have to start over 1402 * at zero as well. 1403 */ 1404 ioat->tail = ioat->head = ioat->hw_head = 0; 1405 ioat->last_seen = 0; 1406 1407 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1408 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1409 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1410 error = 0; 1411 1412 out: 1413 mtx_lock(IOAT_REFLK); 1414 ioat->quiescing = FALSE; 1415 mtx_unlock(IOAT_REFLK); 1416 1417 if (error == 0) 1418 error = ioat_start_channel(ioat); 1419 1420 return (error); 1421 } 1422 1423 static int 1424 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1425 { 1426 struct ioat_softc *ioat; 1427 struct sbuf sb; 1428 uint64_t status; 1429 int error; 1430 1431 ioat = arg1; 1432 1433 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1434 1435 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1436 switch (status) { 1437 case IOAT_CHANSTS_ACTIVE: 1438 sbuf_printf(&sb, "ACTIVE"); 1439 break; 1440 case IOAT_CHANSTS_IDLE: 1441 sbuf_printf(&sb, "IDLE"); 1442 break; 1443 case IOAT_CHANSTS_SUSPENDED: 1444 sbuf_printf(&sb, "SUSPENDED"); 1445 break; 1446 case IOAT_CHANSTS_HALTED: 1447 sbuf_printf(&sb, "HALTED"); 1448 break; 1449 case IOAT_CHANSTS_ARMED: 1450 sbuf_printf(&sb, "ARMED"); 1451 break; 1452 default: 1453 sbuf_printf(&sb, "UNKNOWN"); 1454 break; 1455 } 1456 error = sbuf_finish(&sb); 1457 sbuf_delete(&sb); 1458 1459 if (error != 0 || req->newptr == NULL) 1460 return (error); 1461 return (EINVAL); 1462 } 1463 1464 static int 1465 sysctl_handle_error(SYSCTL_HANDLER_ARGS) 1466 { 1467 struct ioat_descriptor *desc; 1468 struct ioat_softc *ioat; 1469 int error, arg; 1470 1471 ioat = arg1; 1472 1473 arg = 0; 1474 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1475 if (error != 0 || req->newptr == NULL) 1476 return (error); 1477 1478 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1479 if (error != 0) 1480 return (error); 1481 1482 if (arg != 0) { 1483 ioat_acquire(&ioat->dmaengine); 1484 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 1, 1485 0xffff000000000000ull, 0xffff000000000000ull, NULL, NULL, 1486 0); 1487 if (desc == NULL) 1488 error = ENOMEM; 1489 else 1490 ioat_submit_single(ioat); 1491 ioat_release(&ioat->dmaengine); 1492 } 1493 return (error); 1494 } 1495 1496 static int 1497 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1498 { 1499 struct ioat_softc *ioat; 1500 int error, arg; 1501 1502 ioat = arg1; 1503 1504 arg = 0; 1505 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1506 if (error != 0 || req->newptr == NULL) 1507 return (error); 1508 1509 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1510 if (error != 0) 1511 return (error); 1512 1513 if (arg != 0) 1514 error = ioat_reset_hw(ioat); 1515 1516 return (error); 1517 } 1518 1519 static void 1520 dump_descriptor(void *hw_desc) 1521 { 1522 int i, j; 1523 1524 for (i = 0; i < 2; i++) { 1525 for (j = 0; j < 8; j++) 1526 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1527 printf("\n"); 1528 } 1529 } 1530 1531 static void 1532 ioat_setup_sysctl(device_t device) 1533 { 1534 struct sysctl_oid_list *par; 1535 struct sysctl_ctx_list *ctx; 1536 struct sysctl_oid *tree; 1537 struct ioat_softc *ioat; 1538 1539 ioat = DEVICE2SOFTC(device); 1540 ctx = device_get_sysctl_ctx(device); 1541 tree = device_get_sysctl_tree(device); 1542 par = SYSCTL_CHILDREN(tree); 1543 1544 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1545 &ioat->version, 0, "HW version (0xMM form)"); 1546 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1547 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1548 1549 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1550 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1551 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 0, 1552 "SW descriptor head pointer index"); 1553 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 0, 1554 "SW descriptor tail pointer index"); 1555 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "hw_head", CTLFLAG_RD, 1556 &ioat->hw_head, 0, "HW DMACOUNT"); 1557 1558 SYSCTL_ADD_UQUAD(ctx, par, OID_AUTO, "last_completion", CTLFLAG_RD, 1559 ioat->comp_update, "HW addr of last completion"); 1560 1561 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 1562 &ioat->is_resize_pending, 0, "resize pending"); 1563 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_completion_pending", CTLFLAG_RD, 1564 &ioat->is_completion_pending, 0, "completion pending"); 1565 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1566 &ioat->is_reset_pending, 0, "reset pending"); 1567 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1568 &ioat->is_channel_running, 0, "channel running"); 1569 1570 SYSCTL_ADD_PROC(ctx, par, OID_AUTO, "force_hw_reset", 1571 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1572 "Set to non-zero to reset the hardware"); 1573 SYSCTL_ADD_PROC(ctx, par, OID_AUTO, "force_hw_error", 1574 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_error, "I", 1575 "Set to non-zero to inject a recoverable hardware error"); 1576 SYSCTL_ADD_PROC(ctx, par, OID_AUTO, "chansts", 1577 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1578 "String of the channel status"); 1579 } 1580 1581 static inline struct ioat_softc * 1582 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1583 { 1584 uint32_t old; 1585 1586 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1587 1588 old = atomic_fetchadd_32(&ioat->refcnt, 1); 1589 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 1590 1591 #ifdef INVARIANTS 1592 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 1593 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 1594 #endif 1595 1596 return (ioat); 1597 } 1598 1599 static inline void 1600 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1601 { 1602 1603 _ioat_putn(ioat, n, kind, FALSE); 1604 } 1605 1606 static inline void 1607 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1608 { 1609 1610 _ioat_putn(ioat, n, kind, TRUE); 1611 } 1612 1613 static inline void 1614 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 1615 boolean_t locked) 1616 { 1617 uint32_t old; 1618 1619 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1620 1621 if (n == 0) 1622 return; 1623 1624 #ifdef INVARIANTS 1625 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 1626 KASSERT(old >= n, ("refcnt kind underflow")); 1627 #endif 1628 1629 /* Skip acquiring the lock if resulting refcnt > 0. */ 1630 for (;;) { 1631 old = ioat->refcnt; 1632 if (old <= n) 1633 break; 1634 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 1635 return; 1636 } 1637 1638 if (locked) 1639 mtx_assert(IOAT_REFLK, MA_OWNED); 1640 else 1641 mtx_lock(IOAT_REFLK); 1642 1643 old = atomic_fetchadd_32(&ioat->refcnt, -n); 1644 KASSERT(old >= n, ("refcnt error")); 1645 1646 if (old == n) 1647 wakeup(IOAT_REFLK); 1648 if (!locked) 1649 mtx_unlock(IOAT_REFLK); 1650 } 1651 1652 static inline void 1653 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1654 { 1655 1656 ioat_putn(ioat, 1, kind); 1657 } 1658 1659 static void 1660 ioat_drain_locked(struct ioat_softc *ioat) 1661 { 1662 1663 mtx_assert(IOAT_REFLK, MA_OWNED); 1664 while (ioat->refcnt > 0) 1665 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 1666 } 1667