1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ddb.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/fail.h> 37 #include <sys/ioccom.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/sbuf.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 #include <sys/time.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <machine/stdarg.h> 53 54 #ifdef DDB 55 #include <ddb/ddb.h> 56 #endif 57 58 #include "ioat.h" 59 #include "ioat_hw.h" 60 #include "ioat_internal.h" 61 62 #ifndef BUS_SPACE_MAXADDR_40BIT 63 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 64 #endif 65 #define IOAT_REFLK (&ioat->submit_lock) 66 67 static int ioat_probe(device_t device); 68 static int ioat_attach(device_t device); 69 static int ioat_detach(device_t device); 70 static int ioat_setup_intr(struct ioat_softc *ioat); 71 static int ioat_teardown_intr(struct ioat_softc *ioat); 72 static int ioat3_attach(device_t device); 73 static int ioat_start_channel(struct ioat_softc *ioat); 74 static int ioat_map_pci_bar(struct ioat_softc *ioat); 75 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 76 int error); 77 static void ioat_interrupt_handler(void *arg); 78 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 79 static int chanerr_to_errno(uint32_t); 80 static void ioat_process_events(struct ioat_softc *ioat); 81 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 82 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 83 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 84 struct ioat_descriptor *); 85 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 86 static union ioat_hw_descriptor *ioat_get_descriptor(struct ioat_softc *, 87 uint32_t index); 88 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *, 89 uint32_t index); 90 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 91 static void ioat_poll_timer_callback(void *arg); 92 static void dump_descriptor(void *hw_desc); 93 static void ioat_submit_single(struct ioat_softc *ioat); 94 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 95 int error); 96 static int ioat_reset_hw(struct ioat_softc *ioat); 97 static void ioat_reset_hw_task(void *, int); 98 static void ioat_setup_sysctl(device_t device); 99 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 100 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 101 enum ioat_ref_kind); 102 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 103 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 104 enum ioat_ref_kind, boolean_t); 105 static inline void ioat_putn(struct ioat_softc *, uint32_t, 106 enum ioat_ref_kind); 107 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 108 enum ioat_ref_kind); 109 static void ioat_drain_locked(struct ioat_softc *); 110 111 #define ioat_log_message(v, ...) do { \ 112 if ((v) <= g_ioat_debug_level) { \ 113 device_printf(ioat->device, __VA_ARGS__); \ 114 } \ 115 } while (0) 116 117 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 118 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 119 120 static int g_force_legacy_interrupts; 121 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 122 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 123 124 int g_ioat_debug_level = 0; 125 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 126 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 127 128 unsigned g_ioat_ring_order = 13; 129 SYSCTL_UINT(_hw_ioat, OID_AUTO, ring_order, CTLFLAG_RDTUN, &g_ioat_ring_order, 130 0, "Set IOAT ring order. (1 << this) == ring size."); 131 132 /* 133 * OS <-> Driver interface structures 134 */ 135 static device_method_t ioat_pci_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, ioat_probe), 138 DEVMETHOD(device_attach, ioat_attach), 139 DEVMETHOD(device_detach, ioat_detach), 140 DEVMETHOD_END 141 }; 142 143 static driver_t ioat_pci_driver = { 144 "ioat", 145 ioat_pci_methods, 146 sizeof(struct ioat_softc), 147 }; 148 149 static devclass_t ioat_devclass; 150 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 151 MODULE_VERSION(ioat, 1); 152 153 /* 154 * Private data structures 155 */ 156 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 157 static unsigned ioat_channel_index = 0; 158 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 159 "Number of IOAT channels attached"); 160 161 static struct _pcsid 162 { 163 u_int32_t type; 164 const char *desc; 165 } pci_ids[] = { 166 { 0x34308086, "TBG IOAT Ch0" }, 167 { 0x34318086, "TBG IOAT Ch1" }, 168 { 0x34328086, "TBG IOAT Ch2" }, 169 { 0x34338086, "TBG IOAT Ch3" }, 170 { 0x34298086, "TBG IOAT Ch4" }, 171 { 0x342a8086, "TBG IOAT Ch5" }, 172 { 0x342b8086, "TBG IOAT Ch6" }, 173 { 0x342c8086, "TBG IOAT Ch7" }, 174 175 { 0x37108086, "JSF IOAT Ch0" }, 176 { 0x37118086, "JSF IOAT Ch1" }, 177 { 0x37128086, "JSF IOAT Ch2" }, 178 { 0x37138086, "JSF IOAT Ch3" }, 179 { 0x37148086, "JSF IOAT Ch4" }, 180 { 0x37158086, "JSF IOAT Ch5" }, 181 { 0x37168086, "JSF IOAT Ch6" }, 182 { 0x37178086, "JSF IOAT Ch7" }, 183 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 184 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 185 186 { 0x3c208086, "SNB IOAT Ch0" }, 187 { 0x3c218086, "SNB IOAT Ch1" }, 188 { 0x3c228086, "SNB IOAT Ch2" }, 189 { 0x3c238086, "SNB IOAT Ch3" }, 190 { 0x3c248086, "SNB IOAT Ch4" }, 191 { 0x3c258086, "SNB IOAT Ch5" }, 192 { 0x3c268086, "SNB IOAT Ch6" }, 193 { 0x3c278086, "SNB IOAT Ch7" }, 194 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 195 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 196 197 { 0x0e208086, "IVB IOAT Ch0" }, 198 { 0x0e218086, "IVB IOAT Ch1" }, 199 { 0x0e228086, "IVB IOAT Ch2" }, 200 { 0x0e238086, "IVB IOAT Ch3" }, 201 { 0x0e248086, "IVB IOAT Ch4" }, 202 { 0x0e258086, "IVB IOAT Ch5" }, 203 { 0x0e268086, "IVB IOAT Ch6" }, 204 { 0x0e278086, "IVB IOAT Ch7" }, 205 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 206 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 207 208 { 0x2f208086, "HSW IOAT Ch0" }, 209 { 0x2f218086, "HSW IOAT Ch1" }, 210 { 0x2f228086, "HSW IOAT Ch2" }, 211 { 0x2f238086, "HSW IOAT Ch3" }, 212 { 0x2f248086, "HSW IOAT Ch4" }, 213 { 0x2f258086, "HSW IOAT Ch5" }, 214 { 0x2f268086, "HSW IOAT Ch6" }, 215 { 0x2f278086, "HSW IOAT Ch7" }, 216 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 217 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 218 219 { 0x0c508086, "BWD IOAT Ch0" }, 220 { 0x0c518086, "BWD IOAT Ch1" }, 221 { 0x0c528086, "BWD IOAT Ch2" }, 222 { 0x0c538086, "BWD IOAT Ch3" }, 223 224 { 0x6f508086, "BDXDE IOAT Ch0" }, 225 { 0x6f518086, "BDXDE IOAT Ch1" }, 226 { 0x6f528086, "BDXDE IOAT Ch2" }, 227 { 0x6f538086, "BDXDE IOAT Ch3" }, 228 229 { 0x6f208086, "BDX IOAT Ch0" }, 230 { 0x6f218086, "BDX IOAT Ch1" }, 231 { 0x6f228086, "BDX IOAT Ch2" }, 232 { 0x6f238086, "BDX IOAT Ch3" }, 233 { 0x6f248086, "BDX IOAT Ch4" }, 234 { 0x6f258086, "BDX IOAT Ch5" }, 235 { 0x6f268086, "BDX IOAT Ch6" }, 236 { 0x6f278086, "BDX IOAT Ch7" }, 237 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 238 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 239 240 { 0x20218086, "SKX IOAT" }, 241 }; 242 243 MODULE_PNP_INFO("W32:vendor/device;D:human", pci, ioat, pci_ids, 244 sizeof(pci_ids[0]), nitems(pci_ids)); 245 246 /* 247 * OS <-> Driver linkage functions 248 */ 249 static int 250 ioat_probe(device_t device) 251 { 252 struct _pcsid *ep; 253 u_int32_t type; 254 255 type = pci_get_devid(device); 256 for (ep = pci_ids; ep < &pci_ids[nitems(pci_ids)]; ep++) { 257 if (ep->type == type) { 258 device_set_desc(device, ep->desc); 259 return (0); 260 } 261 } 262 return (ENXIO); 263 } 264 265 static int 266 ioat_attach(device_t device) 267 { 268 struct ioat_softc *ioat; 269 int error; 270 271 ioat = DEVICE2SOFTC(device); 272 ioat->device = device; 273 274 error = ioat_map_pci_bar(ioat); 275 if (error != 0) 276 goto err; 277 278 ioat->version = ioat_read_cbver(ioat); 279 if (ioat->version < IOAT_VER_3_0) { 280 error = ENODEV; 281 goto err; 282 } 283 284 error = ioat3_attach(device); 285 if (error != 0) 286 goto err; 287 288 error = pci_enable_busmaster(device); 289 if (error != 0) 290 goto err; 291 292 error = ioat_setup_intr(ioat); 293 if (error != 0) 294 goto err; 295 296 error = ioat_reset_hw(ioat); 297 if (error != 0) 298 goto err; 299 300 ioat_process_events(ioat); 301 ioat_setup_sysctl(device); 302 303 ioat->chan_idx = ioat_channel_index; 304 ioat_channel[ioat_channel_index++] = ioat; 305 ioat_test_attach(); 306 307 err: 308 if (error != 0) 309 ioat_detach(device); 310 return (error); 311 } 312 313 static int 314 ioat_detach(device_t device) 315 { 316 struct ioat_softc *ioat; 317 318 ioat = DEVICE2SOFTC(device); 319 320 ioat_test_detach(); 321 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 322 323 mtx_lock(IOAT_REFLK); 324 ioat->quiescing = TRUE; 325 ioat->destroying = TRUE; 326 wakeup(&ioat->quiescing); 327 wakeup(&ioat->resetting); 328 329 ioat_channel[ioat->chan_idx] = NULL; 330 331 ioat_drain_locked(ioat); 332 mtx_unlock(IOAT_REFLK); 333 334 ioat_teardown_intr(ioat); 335 callout_drain(&ioat->poll_timer); 336 337 pci_disable_busmaster(device); 338 339 if (ioat->pci_resource != NULL) 340 bus_release_resource(device, SYS_RES_MEMORY, 341 ioat->pci_resource_id, ioat->pci_resource); 342 343 if (ioat->ring != NULL) 344 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 345 346 if (ioat->comp_update != NULL) { 347 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 348 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 349 ioat->comp_update_map); 350 bus_dma_tag_destroy(ioat->comp_update_tag); 351 } 352 353 if (ioat->hw_desc_ring != NULL) { 354 bus_dmamap_unload(ioat->hw_desc_tag, ioat->hw_desc_map); 355 bus_dmamem_free(ioat->hw_desc_tag, ioat->hw_desc_ring, 356 ioat->hw_desc_map); 357 bus_dma_tag_destroy(ioat->hw_desc_tag); 358 } 359 360 return (0); 361 } 362 363 static int 364 ioat_teardown_intr(struct ioat_softc *ioat) 365 { 366 367 if (ioat->tag != NULL) 368 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 369 370 if (ioat->res != NULL) 371 bus_release_resource(ioat->device, SYS_RES_IRQ, 372 rman_get_rid(ioat->res), ioat->res); 373 374 pci_release_msi(ioat->device); 375 return (0); 376 } 377 378 static int 379 ioat_start_channel(struct ioat_softc *ioat) 380 { 381 struct ioat_dma_hw_descriptor *hw_desc; 382 struct ioat_descriptor *desc; 383 struct bus_dmadesc *dmadesc; 384 uint64_t status; 385 uint32_t chanerr; 386 int i; 387 388 ioat_acquire(&ioat->dmaengine); 389 390 /* Submit 'NULL' operation manually to avoid quiescing flag */ 391 desc = ioat_get_ring_entry(ioat, ioat->head); 392 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->dma; 393 dmadesc = &desc->bus_dmadesc; 394 395 dmadesc->callback_fn = NULL; 396 dmadesc->callback_arg = NULL; 397 398 hw_desc->u.control_raw = 0; 399 hw_desc->u.control_generic.op = IOAT_OP_COPY; 400 hw_desc->u.control_generic.completion_update = 1; 401 hw_desc->size = 8; 402 hw_desc->src_addr = 0; 403 hw_desc->dest_addr = 0; 404 hw_desc->u.control.null = 1; 405 406 ioat_submit_single(ioat); 407 ioat_release(&ioat->dmaengine); 408 409 for (i = 0; i < 100; i++) { 410 DELAY(1); 411 status = ioat_get_chansts(ioat); 412 if (is_ioat_idle(status)) 413 return (0); 414 } 415 416 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 417 ioat_log_message(0, "could not start channel: " 418 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 419 IOAT_CHANERR_STR); 420 return (ENXIO); 421 } 422 423 /* 424 * Initialize Hardware 425 */ 426 static int 427 ioat3_attach(device_t device) 428 { 429 struct ioat_softc *ioat; 430 struct ioat_descriptor *ring; 431 struct ioat_dma_hw_descriptor *dma_hw_desc; 432 void *hw_desc; 433 size_t ringsz; 434 int i, num_descriptors; 435 int error; 436 uint8_t xfercap; 437 438 error = 0; 439 ioat = DEVICE2SOFTC(device); 440 ioat->capabilities = ioat_read_dmacapability(ioat); 441 442 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 443 IOAT_DMACAP_STR); 444 445 xfercap = ioat_read_xfercap(ioat); 446 ioat->max_xfer_size = 1 << xfercap; 447 448 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 449 IOAT_INTRDELAY_SUPPORTED) != 0; 450 if (ioat->intrdelay_supported) 451 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 452 453 /* TODO: need to check DCA here if we ever do XOR/PQ */ 454 455 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 456 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 457 callout_init(&ioat->poll_timer, 1); 458 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 459 460 /* Establish lock order for Witness */ 461 mtx_lock(&ioat->submit_lock); 462 mtx_lock(&ioat->cleanup_lock); 463 mtx_unlock(&ioat->cleanup_lock); 464 mtx_unlock(&ioat->submit_lock); 465 466 ioat->is_submitter_processing = FALSE; 467 ioat->is_completion_pending = FALSE; 468 ioat->is_reset_pending = FALSE; 469 ioat->is_channel_running = FALSE; 470 471 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 472 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 473 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 474 &ioat->comp_update_tag); 475 476 error = bus_dmamem_alloc(ioat->comp_update_tag, 477 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 478 if (ioat->comp_update == NULL) 479 return (ENOMEM); 480 481 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 482 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 483 0); 484 if (error != 0) 485 return (error); 486 487 ioat->ring_size_order = g_ioat_ring_order; 488 num_descriptors = 1 << ioat->ring_size_order; 489 ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors; 490 491 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 492 2 * 1024 * 1024, 0x0, (bus_addr_t)BUS_SPACE_MAXADDR_40BIT, 493 BUS_SPACE_MAXADDR, NULL, NULL, ringsz, 1, ringsz, 0, NULL, NULL, 494 &ioat->hw_desc_tag); 495 if (error != 0) 496 return (error); 497 498 error = bus_dmamem_alloc(ioat->hw_desc_tag, &hw_desc, 499 BUS_DMA_ZERO | BUS_DMA_WAITOK, &ioat->hw_desc_map); 500 if (error != 0) 501 return (error); 502 503 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 504 ringsz, ioat_dmamap_cb, &ioat->hw_desc_bus_addr, BUS_DMA_WAITOK); 505 if (error) 506 return (error); 507 508 ioat->hw_desc_ring = hw_desc; 509 510 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 511 M_ZERO | M_WAITOK); 512 513 ring = ioat->ring; 514 for (i = 0; i < num_descriptors; i++) { 515 memset(&ring[i].bus_dmadesc, 0, sizeof(ring[i].bus_dmadesc)); 516 ring[i].id = i; 517 } 518 519 for (i = 0; i < num_descriptors; i++) { 520 dma_hw_desc = &ioat->hw_desc_ring[i].dma; 521 dma_hw_desc->next = RING_PHYS_ADDR(ioat, i + 1); 522 } 523 524 ioat->head = ioat->hw_head = 0; 525 ioat->tail = 0; 526 ioat->last_seen = 0; 527 *ioat->comp_update = 0; 528 return (0); 529 } 530 531 static int 532 ioat_map_pci_bar(struct ioat_softc *ioat) 533 { 534 535 ioat->pci_resource_id = PCIR_BAR(0); 536 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 537 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 538 539 if (ioat->pci_resource == NULL) { 540 ioat_log_message(0, "unable to allocate pci resource\n"); 541 return (ENODEV); 542 } 543 544 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 545 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 546 return (0); 547 } 548 549 static void 550 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 551 { 552 struct ioat_softc *ioat = arg; 553 554 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 555 ioat->comp_update_bus_addr = seg[0].ds_addr; 556 } 557 558 static void 559 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 560 { 561 bus_addr_t *baddr; 562 563 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 564 baddr = arg; 565 *baddr = segs->ds_addr; 566 } 567 568 /* 569 * Interrupt setup and handlers 570 */ 571 static int 572 ioat_setup_intr(struct ioat_softc *ioat) 573 { 574 uint32_t num_vectors; 575 int error; 576 boolean_t use_msix; 577 boolean_t force_legacy_interrupts; 578 579 use_msix = FALSE; 580 force_legacy_interrupts = FALSE; 581 582 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 583 num_vectors = 1; 584 pci_alloc_msix(ioat->device, &num_vectors); 585 if (num_vectors == 1) 586 use_msix = TRUE; 587 } 588 589 if (use_msix) { 590 ioat->rid = 1; 591 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 592 &ioat->rid, RF_ACTIVE); 593 } else { 594 ioat->rid = 0; 595 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 596 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 597 } 598 if (ioat->res == NULL) { 599 ioat_log_message(0, "bus_alloc_resource failed\n"); 600 return (ENOMEM); 601 } 602 603 ioat->tag = NULL; 604 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 605 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 606 if (error != 0) { 607 ioat_log_message(0, "bus_setup_intr failed\n"); 608 return (error); 609 } 610 611 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 612 return (0); 613 } 614 615 static boolean_t 616 ioat_model_resets_msix(struct ioat_softc *ioat) 617 { 618 u_int32_t pciid; 619 620 pciid = pci_get_devid(ioat->device); 621 switch (pciid) { 622 /* BWD: */ 623 case 0x0c508086: 624 case 0x0c518086: 625 case 0x0c528086: 626 case 0x0c538086: 627 /* BDXDE: */ 628 case 0x6f508086: 629 case 0x6f518086: 630 case 0x6f528086: 631 case 0x6f538086: 632 return (TRUE); 633 } 634 635 return (FALSE); 636 } 637 638 static void 639 ioat_interrupt_handler(void *arg) 640 { 641 struct ioat_softc *ioat = arg; 642 643 ioat->stats.interrupts++; 644 ioat_process_events(ioat); 645 } 646 647 static int 648 chanerr_to_errno(uint32_t chanerr) 649 { 650 651 if (chanerr == 0) 652 return (0); 653 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 654 return (EFAULT); 655 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 656 return (EIO); 657 /* This one is probably our fault: */ 658 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 659 return (EIO); 660 return (EIO); 661 } 662 663 static void 664 ioat_process_events(struct ioat_softc *ioat) 665 { 666 struct ioat_descriptor *desc; 667 struct bus_dmadesc *dmadesc; 668 uint64_t comp_update, status; 669 uint32_t completed, chanerr; 670 boolean_t pending; 671 int error; 672 673 mtx_lock(&ioat->cleanup_lock); 674 675 /* 676 * Don't run while the hardware is being reset. Reset is responsible 677 * for blocking new work and draining & completing existing work, so 678 * there is nothing to do until new work is queued after reset anyway. 679 */ 680 if (ioat->resetting_cleanup) { 681 mtx_unlock(&ioat->cleanup_lock); 682 return; 683 } 684 685 completed = 0; 686 comp_update = *ioat->comp_update; 687 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 688 689 if (status < ioat->hw_desc_bus_addr || 690 status >= ioat->hw_desc_bus_addr + (1 << ioat->ring_size_order) * 691 sizeof(struct ioat_generic_hw_descriptor)) 692 panic("Bogus completion address %jx (channel %u)", 693 (uintmax_t)status, ioat->chan_idx); 694 695 if (status == ioat->last_seen) { 696 /* 697 * If we landed in process_events and nothing has been 698 * completed, check for a timeout due to channel halt. 699 */ 700 goto out; 701 } 702 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx", 703 __func__, ioat->chan_idx, comp_update, ioat->last_seen); 704 705 while (RING_PHYS_ADDR(ioat, ioat->tail - 1) != status) { 706 desc = ioat_get_ring_entry(ioat, ioat->tail); 707 dmadesc = &desc->bus_dmadesc; 708 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) ok cb %p(%p)", 709 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 710 dmadesc->callback_arg); 711 712 if (dmadesc->callback_fn != NULL) 713 dmadesc->callback_fn(dmadesc->callback_arg, 0); 714 715 completed++; 716 ioat->tail++; 717 } 718 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 719 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 720 721 if (completed != 0) { 722 ioat->last_seen = RING_PHYS_ADDR(ioat, ioat->tail - 1); 723 ioat->stats.descriptors_processed += completed; 724 } 725 726 out: 727 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 728 729 /* Perform a racy check first; only take the locks if it passes. */ 730 pending = (ioat_get_active(ioat) != 0); 731 if (!pending && ioat->is_completion_pending) { 732 mtx_unlock(&ioat->cleanup_lock); 733 mtx_lock(&ioat->submit_lock); 734 mtx_lock(&ioat->cleanup_lock); 735 736 pending = (ioat_get_active(ioat) != 0); 737 if (!pending && ioat->is_completion_pending) { 738 ioat->is_completion_pending = FALSE; 739 callout_stop(&ioat->poll_timer); 740 } 741 mtx_unlock(&ioat->submit_lock); 742 } 743 mtx_unlock(&ioat->cleanup_lock); 744 745 if (pending) 746 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 747 ioat); 748 749 if (completed != 0) { 750 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 751 wakeup(&ioat->tail); 752 } 753 754 /* 755 * The device doesn't seem to reliably push suspend/halt statuses to 756 * the channel completion memory address, so poll the device register 757 * here. 758 */ 759 comp_update = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 760 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 761 return; 762 763 ioat->stats.channel_halts++; 764 765 /* 766 * Fatal programming error on this DMA channel. Flush any outstanding 767 * work with error status and restart the engine. 768 */ 769 mtx_lock(&ioat->submit_lock); 770 mtx_lock(&ioat->cleanup_lock); 771 ioat->quiescing = TRUE; 772 /* 773 * This is safe to do here because we have both locks and the submit 774 * queue is quiesced. We know that we will drain all outstanding 775 * events, so ioat_reset_hw can't deadlock. It is necessary to 776 * protect other ioat_process_event threads from racing ioat_reset_hw, 777 * reading an indeterminate hw state, and attempting to continue 778 * issuing completions. 779 */ 780 ioat->resetting_cleanup = TRUE; 781 782 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 783 if (1 <= g_ioat_debug_level) 784 ioat_halted_debug(ioat, chanerr); 785 ioat->stats.last_halt_chanerr = chanerr; 786 787 while (ioat_get_active(ioat) > 0) { 788 desc = ioat_get_ring_entry(ioat, ioat->tail); 789 dmadesc = &desc->bus_dmadesc; 790 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) err cb %p(%p)", 791 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 792 dmadesc->callback_arg); 793 794 if (dmadesc->callback_fn != NULL) 795 dmadesc->callback_fn(dmadesc->callback_arg, 796 chanerr_to_errno(chanerr)); 797 798 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 799 ioat->tail++; 800 ioat->stats.descriptors_processed++; 801 ioat->stats.descriptors_error++; 802 } 803 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 804 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 805 806 if (ioat->is_completion_pending) { 807 ioat->is_completion_pending = FALSE; 808 callout_stop(&ioat->poll_timer); 809 } 810 811 /* Clear error status */ 812 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 813 814 mtx_unlock(&ioat->cleanup_lock); 815 mtx_unlock(&ioat->submit_lock); 816 817 ioat_log_message(0, "Resetting channel to recover from error\n"); 818 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 819 KASSERT(error == 0, 820 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 821 } 822 823 static void 824 ioat_reset_hw_task(void *ctx, int pending __unused) 825 { 826 struct ioat_softc *ioat; 827 int error; 828 829 ioat = ctx; 830 ioat_log_message(1, "%s: Resetting channel\n", __func__); 831 832 error = ioat_reset_hw(ioat); 833 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 834 (void)error; 835 } 836 837 /* 838 * User API functions 839 */ 840 unsigned 841 ioat_get_nchannels(void) 842 { 843 844 return (ioat_channel_index); 845 } 846 847 bus_dmaengine_t 848 ioat_get_dmaengine(uint32_t index, int flags) 849 { 850 struct ioat_softc *ioat; 851 852 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 853 ("invalid flags: 0x%08x", flags)); 854 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 855 ("invalid wait | nowait")); 856 857 if (index >= ioat_channel_index) 858 return (NULL); 859 860 ioat = ioat_channel[index]; 861 if (ioat == NULL || ioat->destroying) 862 return (NULL); 863 864 if (ioat->quiescing) { 865 if ((flags & M_NOWAIT) != 0) 866 return (NULL); 867 868 mtx_lock(IOAT_REFLK); 869 while (ioat->quiescing && !ioat->destroying) 870 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 871 mtx_unlock(IOAT_REFLK); 872 873 if (ioat->destroying) 874 return (NULL); 875 } 876 877 /* 878 * There's a race here between the quiescing check and HW reset or 879 * module destroy. 880 */ 881 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 882 } 883 884 void 885 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 886 { 887 struct ioat_softc *ioat; 888 889 ioat = to_ioat_softc(dmaengine); 890 ioat_put(ioat, IOAT_DMAENGINE_REF); 891 } 892 893 int 894 ioat_get_hwversion(bus_dmaengine_t dmaengine) 895 { 896 struct ioat_softc *ioat; 897 898 ioat = to_ioat_softc(dmaengine); 899 return (ioat->version); 900 } 901 902 size_t 903 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 904 { 905 struct ioat_softc *ioat; 906 907 ioat = to_ioat_softc(dmaengine); 908 return (ioat->max_xfer_size); 909 } 910 911 uint32_t 912 ioat_get_capabilities(bus_dmaengine_t dmaengine) 913 { 914 struct ioat_softc *ioat; 915 916 ioat = to_ioat_softc(dmaengine); 917 return (ioat->capabilities); 918 } 919 920 int 921 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 922 { 923 struct ioat_softc *ioat; 924 925 ioat = to_ioat_softc(dmaengine); 926 if (!ioat->intrdelay_supported) 927 return (ENODEV); 928 if (delay > ioat->intrdelay_max) 929 return (ERANGE); 930 931 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 932 ioat->cached_intrdelay = 933 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 934 return (0); 935 } 936 937 uint16_t 938 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 939 { 940 struct ioat_softc *ioat; 941 942 ioat = to_ioat_softc(dmaengine); 943 return (ioat->intrdelay_max); 944 } 945 946 void 947 ioat_acquire(bus_dmaengine_t dmaengine) 948 { 949 struct ioat_softc *ioat; 950 951 ioat = to_ioat_softc(dmaengine); 952 mtx_lock(&ioat->submit_lock); 953 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 954 ioat->acq_head = ioat->head; 955 } 956 957 int 958 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 959 { 960 struct ioat_softc *ioat; 961 int error; 962 963 ioat = to_ioat_softc(dmaengine); 964 ioat_acquire(dmaengine); 965 966 error = ioat_reserve_space(ioat, n, mflags); 967 if (error != 0) 968 ioat_release(dmaengine); 969 return (error); 970 } 971 972 void 973 ioat_release(bus_dmaengine_t dmaengine) 974 { 975 struct ioat_softc *ioat; 976 977 ioat = to_ioat_softc(dmaengine); 978 CTR4(KTR_IOAT, "%s channel=%u dispatch1 hw_head=%u head=%u", __func__, 979 ioat->chan_idx, ioat->hw_head & UINT16_MAX, ioat->head); 980 KFAIL_POINT_CODE(DEBUG_FP, ioat_release, /* do nothing */); 981 CTR4(KTR_IOAT, "%s channel=%u dispatch2 hw_head=%u head=%u", __func__, 982 ioat->chan_idx, ioat->hw_head & UINT16_MAX, ioat->head); 983 984 if (ioat->acq_head != ioat->head) { 985 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, 986 (uint16_t)ioat->hw_head); 987 988 if (!ioat->is_completion_pending) { 989 ioat->is_completion_pending = TRUE; 990 callout_reset(&ioat->poll_timer, 1, 991 ioat_poll_timer_callback, ioat); 992 } 993 } 994 mtx_unlock(&ioat->submit_lock); 995 } 996 997 static struct ioat_descriptor * 998 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 999 uint32_t size, uint64_t src, uint64_t dst, 1000 bus_dmaengine_callback_t callback_fn, void *callback_arg, 1001 uint32_t flags) 1002 { 1003 struct ioat_generic_hw_descriptor *hw_desc; 1004 struct ioat_descriptor *desc; 1005 int mflags; 1006 1007 mtx_assert(&ioat->submit_lock, MA_OWNED); 1008 1009 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 1010 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 1011 if ((flags & DMA_NO_WAIT) != 0) 1012 mflags = M_NOWAIT; 1013 else 1014 mflags = M_WAITOK; 1015 1016 if (size > ioat->max_xfer_size) { 1017 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 1018 __func__, ioat->max_xfer_size, (unsigned)size); 1019 return (NULL); 1020 } 1021 1022 if (ioat_reserve_space(ioat, 1, mflags) != 0) 1023 return (NULL); 1024 1025 desc = ioat_get_ring_entry(ioat, ioat->head); 1026 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->generic; 1027 1028 hw_desc->u.control_raw = 0; 1029 hw_desc->u.control_generic.op = op; 1030 hw_desc->u.control_generic.completion_update = 1; 1031 1032 if ((flags & DMA_INT_EN) != 0) 1033 hw_desc->u.control_generic.int_enable = 1; 1034 if ((flags & DMA_FENCE) != 0) 1035 hw_desc->u.control_generic.fence = 1; 1036 1037 hw_desc->size = size; 1038 hw_desc->src_addr = src; 1039 hw_desc->dest_addr = dst; 1040 1041 desc->bus_dmadesc.callback_fn = callback_fn; 1042 desc->bus_dmadesc.callback_arg = callback_arg; 1043 return (desc); 1044 } 1045 1046 struct bus_dmadesc * 1047 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1048 void *callback_arg, uint32_t flags) 1049 { 1050 struct ioat_dma_hw_descriptor *hw_desc; 1051 struct ioat_descriptor *desc; 1052 struct ioat_softc *ioat; 1053 1054 ioat = to_ioat_softc(dmaengine); 1055 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1056 1057 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1058 callback_arg, flags); 1059 if (desc == NULL) 1060 return (NULL); 1061 1062 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1063 hw_desc->u.control.null = 1; 1064 ioat_submit_single(ioat); 1065 return (&desc->bus_dmadesc); 1066 } 1067 1068 struct bus_dmadesc * 1069 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1070 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1071 void *callback_arg, uint32_t flags) 1072 { 1073 struct ioat_dma_hw_descriptor *hw_desc; 1074 struct ioat_descriptor *desc; 1075 struct ioat_softc *ioat; 1076 1077 ioat = to_ioat_softc(dmaengine); 1078 1079 if (((src | dst) & (0xffffull << 48)) != 0) { 1080 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1081 __func__); 1082 return (NULL); 1083 } 1084 1085 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1086 callback_arg, flags); 1087 if (desc == NULL) 1088 return (NULL); 1089 1090 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1091 if (g_ioat_debug_level >= 3) 1092 dump_descriptor(hw_desc); 1093 1094 ioat_submit_single(ioat); 1095 CTR6(KTR_IOAT, "%s channel=%u desc=%p dest=%lx src=%lx len=%lx", 1096 __func__, ioat->chan_idx, &desc->bus_dmadesc, dst, src, len); 1097 return (&desc->bus_dmadesc); 1098 } 1099 1100 struct bus_dmadesc * 1101 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1102 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1103 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1104 { 1105 struct ioat_dma_hw_descriptor *hw_desc; 1106 struct ioat_descriptor *desc; 1107 struct ioat_softc *ioat; 1108 1109 ioat = to_ioat_softc(dmaengine); 1110 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1111 1112 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 1113 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1114 __func__); 1115 return (NULL); 1116 } 1117 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 1118 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 1119 __func__); 1120 return (NULL); 1121 } 1122 1123 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 1124 callback_fn, callback_arg, flags); 1125 if (desc == NULL) 1126 return (NULL); 1127 1128 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1129 if (src2 != src1 + PAGE_SIZE) { 1130 hw_desc->u.control.src_page_break = 1; 1131 hw_desc->next_src_addr = src2; 1132 } 1133 if (dst2 != dst1 + PAGE_SIZE) { 1134 hw_desc->u.control.dest_page_break = 1; 1135 hw_desc->next_dest_addr = dst2; 1136 } 1137 1138 if (g_ioat_debug_level >= 3) 1139 dump_descriptor(hw_desc); 1140 1141 ioat_submit_single(ioat); 1142 return (&desc->bus_dmadesc); 1143 } 1144 1145 struct bus_dmadesc * 1146 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1147 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1148 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1149 { 1150 struct ioat_crc32_hw_descriptor *hw_desc; 1151 struct ioat_descriptor *desc; 1152 struct ioat_softc *ioat; 1153 uint32_t teststore; 1154 uint8_t op; 1155 1156 ioat = to_ioat_softc(dmaengine); 1157 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1158 1159 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1160 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1161 __func__); 1162 return (NULL); 1163 } 1164 if (((src | dst) & (0xffffffull << 40)) != 0) { 1165 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1166 __func__); 1167 return (NULL); 1168 } 1169 teststore = (flags & _DMA_CRC_TESTSTORE); 1170 if (teststore == _DMA_CRC_TESTSTORE) { 1171 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1172 return (NULL); 1173 } 1174 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1175 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1176 __func__); 1177 return (NULL); 1178 } 1179 1180 switch (teststore) { 1181 case DMA_CRC_STORE: 1182 op = IOAT_OP_MOVECRC_STORE; 1183 break; 1184 case DMA_CRC_TEST: 1185 op = IOAT_OP_MOVECRC_TEST; 1186 break; 1187 default: 1188 KASSERT(teststore == 0, ("bogus")); 1189 op = IOAT_OP_MOVECRC; 1190 break; 1191 } 1192 1193 if ((flags & DMA_CRC_INLINE) == 0 && 1194 (crcptr & (0xffffffull << 40)) != 0) { 1195 ioat_log_message(0, 1196 "%s: High 24 bits of crcptr invalid\n", __func__); 1197 return (NULL); 1198 } 1199 1200 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1201 callback_arg, flags & ~_DMA_CRC_FLAGS); 1202 if (desc == NULL) 1203 return (NULL); 1204 1205 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1206 1207 if ((flags & DMA_CRC_INLINE) == 0) 1208 hw_desc->crc_address = crcptr; 1209 else 1210 hw_desc->u.control.crc_location = 1; 1211 1212 if (initialseed != NULL) { 1213 hw_desc->u.control.use_seed = 1; 1214 hw_desc->seed = *initialseed; 1215 } 1216 1217 if (g_ioat_debug_level >= 3) 1218 dump_descriptor(hw_desc); 1219 1220 ioat_submit_single(ioat); 1221 return (&desc->bus_dmadesc); 1222 } 1223 1224 struct bus_dmadesc * 1225 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1226 uint32_t *initialseed, bus_addr_t crcptr, 1227 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1228 { 1229 struct ioat_crc32_hw_descriptor *hw_desc; 1230 struct ioat_descriptor *desc; 1231 struct ioat_softc *ioat; 1232 uint32_t teststore; 1233 uint8_t op; 1234 1235 ioat = to_ioat_softc(dmaengine); 1236 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1237 1238 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1239 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1240 __func__); 1241 return (NULL); 1242 } 1243 if ((src & (0xffffffull << 40)) != 0) { 1244 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1245 __func__); 1246 return (NULL); 1247 } 1248 teststore = (flags & _DMA_CRC_TESTSTORE); 1249 if (teststore == _DMA_CRC_TESTSTORE) { 1250 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1251 return (NULL); 1252 } 1253 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1254 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1255 __func__); 1256 return (NULL); 1257 } 1258 1259 switch (teststore) { 1260 case DMA_CRC_STORE: 1261 op = IOAT_OP_CRC_STORE; 1262 break; 1263 case DMA_CRC_TEST: 1264 op = IOAT_OP_CRC_TEST; 1265 break; 1266 default: 1267 KASSERT(teststore == 0, ("bogus")); 1268 op = IOAT_OP_CRC; 1269 break; 1270 } 1271 1272 if ((flags & DMA_CRC_INLINE) == 0 && 1273 (crcptr & (0xffffffull << 40)) != 0) { 1274 ioat_log_message(0, 1275 "%s: High 24 bits of crcptr invalid\n", __func__); 1276 return (NULL); 1277 } 1278 1279 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1280 callback_arg, flags & ~_DMA_CRC_FLAGS); 1281 if (desc == NULL) 1282 return (NULL); 1283 1284 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1285 1286 if ((flags & DMA_CRC_INLINE) == 0) 1287 hw_desc->crc_address = crcptr; 1288 else 1289 hw_desc->u.control.crc_location = 1; 1290 1291 if (initialseed != NULL) { 1292 hw_desc->u.control.use_seed = 1; 1293 hw_desc->seed = *initialseed; 1294 } 1295 1296 if (g_ioat_debug_level >= 3) 1297 dump_descriptor(hw_desc); 1298 1299 ioat_submit_single(ioat); 1300 return (&desc->bus_dmadesc); 1301 } 1302 1303 struct bus_dmadesc * 1304 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1305 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1306 uint32_t flags) 1307 { 1308 struct ioat_fill_hw_descriptor *hw_desc; 1309 struct ioat_descriptor *desc; 1310 struct ioat_softc *ioat; 1311 1312 ioat = to_ioat_softc(dmaengine); 1313 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1314 1315 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1316 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1317 __func__); 1318 return (NULL); 1319 } 1320 1321 if ((dst & (0xffffull << 48)) != 0) { 1322 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1323 __func__); 1324 return (NULL); 1325 } 1326 1327 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1328 callback_fn, callback_arg, flags); 1329 if (desc == NULL) 1330 return (NULL); 1331 1332 hw_desc = &ioat_get_descriptor(ioat, desc->id)->fill; 1333 if (g_ioat_debug_level >= 3) 1334 dump_descriptor(hw_desc); 1335 1336 ioat_submit_single(ioat); 1337 return (&desc->bus_dmadesc); 1338 } 1339 1340 /* 1341 * Ring Management 1342 */ 1343 static inline uint32_t 1344 ioat_get_active(struct ioat_softc *ioat) 1345 { 1346 1347 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1348 } 1349 1350 static inline uint32_t 1351 ioat_get_ring_space(struct ioat_softc *ioat) 1352 { 1353 1354 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1355 } 1356 1357 /* 1358 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1359 * for 'num_descs'. 1360 * 1361 * If mflags contains M_WAITOK, blocks until enough space is available. 1362 * 1363 * Returns zero on success, or an errno on error. If num_descs is beyond the 1364 * maximum ring size, returns EINVAl; if allocation would block and mflags 1365 * contains M_NOWAIT, returns EAGAIN. 1366 * 1367 * Must be called with the submit_lock held; returns with the lock held. The 1368 * lock may be dropped to allocate the ring. 1369 * 1370 * (The submit_lock is needed to add any entries to the ring, so callers are 1371 * assured enough room is available.) 1372 */ 1373 static int 1374 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1375 { 1376 boolean_t dug; 1377 int error; 1378 1379 mtx_assert(&ioat->submit_lock, MA_OWNED); 1380 error = 0; 1381 dug = FALSE; 1382 1383 if (num_descs < 1 || num_descs >= (1 << ioat->ring_size_order)) { 1384 error = EINVAL; 1385 goto out; 1386 } 1387 1388 for (;;) { 1389 if (ioat->quiescing) { 1390 error = ENXIO; 1391 goto out; 1392 } 1393 1394 if (ioat_get_ring_space(ioat) >= num_descs) 1395 goto out; 1396 1397 CTR3(KTR_IOAT, "%s channel=%u starved (%u)", __func__, 1398 ioat->chan_idx, num_descs); 1399 1400 if (!dug && !ioat->is_submitter_processing) { 1401 ioat->is_submitter_processing = TRUE; 1402 mtx_unlock(&ioat->submit_lock); 1403 1404 CTR2(KTR_IOAT, "%s channel=%u attempting to process events", 1405 __func__, ioat->chan_idx); 1406 ioat_process_events(ioat); 1407 1408 mtx_lock(&ioat->submit_lock); 1409 dug = TRUE; 1410 KASSERT(ioat->is_submitter_processing == TRUE, 1411 ("is_submitter_processing")); 1412 ioat->is_submitter_processing = FALSE; 1413 wakeup(&ioat->tail); 1414 continue; 1415 } 1416 1417 if ((mflags & M_WAITOK) == 0) { 1418 error = EAGAIN; 1419 break; 1420 } 1421 CTR2(KTR_IOAT, "%s channel=%u blocking on completions", 1422 __func__, ioat->chan_idx); 1423 msleep(&ioat->tail, &ioat->submit_lock, 0, 1424 "ioat_full", 0); 1425 continue; 1426 } 1427 1428 out: 1429 mtx_assert(&ioat->submit_lock, MA_OWNED); 1430 KASSERT(!ioat->quiescing || error == ENXIO, 1431 ("reserved during quiesce")); 1432 return (error); 1433 } 1434 1435 static void 1436 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1437 struct ioat_descriptor *ring) 1438 { 1439 1440 free(ring, M_IOAT); 1441 } 1442 1443 static struct ioat_descriptor * 1444 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1445 { 1446 1447 return (&ioat->ring[index % (1 << ioat->ring_size_order)]); 1448 } 1449 1450 static union ioat_hw_descriptor * 1451 ioat_get_descriptor(struct ioat_softc *ioat, uint32_t index) 1452 { 1453 1454 return (&ioat->hw_desc_ring[index % (1 << ioat->ring_size_order)]); 1455 } 1456 1457 static void 1458 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1459 { 1460 union ioat_hw_descriptor *desc; 1461 1462 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1463 IOAT_CHANERR_STR); 1464 if (chanerr == 0) 1465 return; 1466 1467 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1468 1469 desc = ioat_get_descriptor(ioat, ioat->tail + 0); 1470 dump_descriptor(desc); 1471 1472 desc = ioat_get_descriptor(ioat, ioat->tail + 1); 1473 dump_descriptor(desc); 1474 } 1475 1476 static void 1477 ioat_poll_timer_callback(void *arg) 1478 { 1479 struct ioat_softc *ioat; 1480 1481 ioat = arg; 1482 ioat_log_message(3, "%s\n", __func__); 1483 1484 ioat_process_events(ioat); 1485 } 1486 1487 /* 1488 * Support Functions 1489 */ 1490 static void 1491 ioat_submit_single(struct ioat_softc *ioat) 1492 { 1493 1494 mtx_assert(&ioat->submit_lock, MA_OWNED); 1495 1496 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1497 atomic_add_rel_int(&ioat->head, 1); 1498 atomic_add_rel_int(&ioat->hw_head, 1); 1499 CTR5(KTR_IOAT, "%s channel=%u head=%u hw_head=%u tail=%u", __func__, 1500 ioat->chan_idx, ioat->head, ioat->hw_head & UINT16_MAX, 1501 ioat->tail); 1502 1503 ioat->stats.descriptors_submitted++; 1504 } 1505 1506 static int 1507 ioat_reset_hw(struct ioat_softc *ioat) 1508 { 1509 uint64_t status; 1510 uint32_t chanerr; 1511 unsigned timeout; 1512 int error; 1513 1514 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1515 1516 mtx_lock(IOAT_REFLK); 1517 while (ioat->resetting && !ioat->destroying) 1518 msleep(&ioat->resetting, IOAT_REFLK, 0, "IRH_drain", 0); 1519 if (ioat->destroying) { 1520 mtx_unlock(IOAT_REFLK); 1521 return (ENXIO); 1522 } 1523 ioat->resetting = TRUE; 1524 1525 ioat->quiescing = TRUE; 1526 ioat_drain_locked(ioat); 1527 mtx_unlock(IOAT_REFLK); 1528 1529 /* 1530 * Suspend ioat_process_events while the hardware and softc are in an 1531 * indeterminate state. 1532 */ 1533 mtx_lock(&ioat->cleanup_lock); 1534 ioat->resetting_cleanup = TRUE; 1535 mtx_unlock(&ioat->cleanup_lock); 1536 1537 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__, 1538 ioat->chan_idx); 1539 1540 status = ioat_get_chansts(ioat); 1541 if (is_ioat_active(status) || is_ioat_idle(status)) 1542 ioat_suspend(ioat); 1543 1544 /* Wait at most 20 ms */ 1545 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1546 timeout < 20; timeout++) { 1547 DELAY(1000); 1548 status = ioat_get_chansts(ioat); 1549 } 1550 if (timeout == 20) { 1551 error = ETIMEDOUT; 1552 goto out; 1553 } 1554 1555 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1556 1557 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1558 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1559 1560 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__, 1561 ioat->chan_idx); 1562 1563 /* 1564 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1565 * that can cause stability issues for IOAT v3. 1566 */ 1567 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1568 4); 1569 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1570 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1571 1572 /* 1573 * BDXDE and BWD models reset MSI-X registers on device reset. 1574 * Save/restore their contents manually. 1575 */ 1576 if (ioat_model_resets_msix(ioat)) { 1577 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1578 pci_save_state(ioat->device); 1579 } 1580 1581 ioat_reset(ioat); 1582 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__, 1583 ioat->chan_idx); 1584 1585 /* Wait at most 20 ms */ 1586 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1587 DELAY(1000); 1588 if (timeout == 20) { 1589 error = ETIMEDOUT; 1590 goto out; 1591 } 1592 1593 if (ioat_model_resets_msix(ioat)) { 1594 ioat_log_message(1, "device resets registers; restored\n"); 1595 pci_restore_state(ioat->device); 1596 } 1597 1598 /* Reset attempts to return the hardware to "halted." */ 1599 status = ioat_get_chansts(ioat); 1600 if (is_ioat_active(status) || is_ioat_idle(status)) { 1601 /* So this really shouldn't happen... */ 1602 ioat_log_message(0, "Device is active after a reset?\n"); 1603 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1604 error = 0; 1605 goto out; 1606 } 1607 1608 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1609 if (chanerr != 0) { 1610 mtx_lock(&ioat->cleanup_lock); 1611 ioat_halted_debug(ioat, chanerr); 1612 mtx_unlock(&ioat->cleanup_lock); 1613 error = EIO; 1614 goto out; 1615 } 1616 1617 /* 1618 * Bring device back online after reset. Writing CHAINADDR brings the 1619 * device back to active. 1620 * 1621 * The internal ring counter resets to zero, so we have to start over 1622 * at zero as well. 1623 */ 1624 ioat->tail = ioat->head = ioat->hw_head = 0; 1625 ioat->last_seen = 0; 1626 *ioat->comp_update = 0; 1627 KASSERT(!ioat->is_completion_pending, ("bogus completion_pending")); 1628 1629 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1630 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1631 ioat_write_chainaddr(ioat, RING_PHYS_ADDR(ioat, 0)); 1632 error = 0; 1633 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__, 1634 ioat->chan_idx); 1635 1636 out: 1637 /* Enqueues a null operation and ensures it completes. */ 1638 if (error == 0) { 1639 error = ioat_start_channel(ioat); 1640 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__, 1641 ioat->chan_idx); 1642 } 1643 1644 /* 1645 * Resume completions now that ring state is consistent. 1646 */ 1647 mtx_lock(&ioat->cleanup_lock); 1648 ioat->resetting_cleanup = FALSE; 1649 mtx_unlock(&ioat->cleanup_lock); 1650 1651 /* Unblock submission of new work */ 1652 mtx_lock(IOAT_REFLK); 1653 ioat->quiescing = FALSE; 1654 wakeup(&ioat->quiescing); 1655 1656 ioat->resetting = FALSE; 1657 wakeup(&ioat->resetting); 1658 1659 if (ioat->is_completion_pending) 1660 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 1661 ioat); 1662 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx); 1663 mtx_unlock(IOAT_REFLK); 1664 1665 return (error); 1666 } 1667 1668 static int 1669 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1670 { 1671 struct ioat_softc *ioat; 1672 struct sbuf sb; 1673 uint64_t status; 1674 int error; 1675 1676 ioat = arg1; 1677 1678 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1679 1680 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1681 switch (status) { 1682 case IOAT_CHANSTS_ACTIVE: 1683 sbuf_printf(&sb, "ACTIVE"); 1684 break; 1685 case IOAT_CHANSTS_IDLE: 1686 sbuf_printf(&sb, "IDLE"); 1687 break; 1688 case IOAT_CHANSTS_SUSPENDED: 1689 sbuf_printf(&sb, "SUSPENDED"); 1690 break; 1691 case IOAT_CHANSTS_HALTED: 1692 sbuf_printf(&sb, "HALTED"); 1693 break; 1694 case IOAT_CHANSTS_ARMED: 1695 sbuf_printf(&sb, "ARMED"); 1696 break; 1697 default: 1698 sbuf_printf(&sb, "UNKNOWN"); 1699 break; 1700 } 1701 error = sbuf_finish(&sb); 1702 sbuf_delete(&sb); 1703 1704 if (error != 0 || req->newptr == NULL) 1705 return (error); 1706 return (EINVAL); 1707 } 1708 1709 static int 1710 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1711 { 1712 struct ioat_softc *ioat; 1713 struct sbuf sb; 1714 #define PRECISION "1" 1715 const uintmax_t factor = 10; 1716 uintmax_t rate; 1717 int error; 1718 1719 ioat = arg1; 1720 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1721 1722 if (ioat->stats.interrupts == 0) { 1723 sbuf_printf(&sb, "NaN"); 1724 goto out; 1725 } 1726 rate = ioat->stats.descriptors_processed * factor / 1727 ioat->stats.interrupts; 1728 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1729 rate % factor); 1730 #undef PRECISION 1731 out: 1732 error = sbuf_finish(&sb); 1733 sbuf_delete(&sb); 1734 if (error != 0 || req->newptr == NULL) 1735 return (error); 1736 return (EINVAL); 1737 } 1738 1739 static int 1740 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1741 { 1742 struct ioat_softc *ioat; 1743 int error, arg; 1744 1745 ioat = arg1; 1746 1747 arg = 0; 1748 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1749 if (error != 0 || req->newptr == NULL) 1750 return (error); 1751 1752 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1753 if (error != 0) 1754 return (error); 1755 1756 if (arg != 0) 1757 error = ioat_reset_hw(ioat); 1758 1759 return (error); 1760 } 1761 1762 static void 1763 dump_descriptor(void *hw_desc) 1764 { 1765 int i, j; 1766 1767 for (i = 0; i < 2; i++) { 1768 for (j = 0; j < 8; j++) 1769 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1770 printf("\n"); 1771 } 1772 } 1773 1774 static void 1775 ioat_setup_sysctl(device_t device) 1776 { 1777 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1778 struct sysctl_ctx_list *ctx; 1779 struct sysctl_oid *tree, *tmp; 1780 struct ioat_softc *ioat; 1781 1782 ioat = DEVICE2SOFTC(device); 1783 ctx = device_get_sysctl_ctx(device); 1784 tree = device_get_sysctl_tree(device); 1785 par = SYSCTL_CHILDREN(tree); 1786 1787 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1788 &ioat->version, 0, "HW version (0xMM form)"); 1789 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1790 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1791 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1792 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1793 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1794 &ioat->intrdelay_max, 0, 1795 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1796 1797 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 1798 "IOAT channel internal state"); 1799 state = SYSCTL_CHILDREN(tmp); 1800 1801 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1802 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1803 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1804 0, "SW descriptor head pointer index"); 1805 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1806 0, "SW descriptor tail pointer index"); 1807 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 1808 &ioat->hw_head, 0, "HW DMACOUNT"); 1809 1810 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1811 ioat->comp_update, "HW addr of last completion"); 1812 1813 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 1814 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 1815 "submitter processing"); 1816 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 1817 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 1818 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1819 &ioat->is_reset_pending, 0, "reset pending"); 1820 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1821 &ioat->is_channel_running, 0, "channel running"); 1822 1823 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1824 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1825 "String of the channel status"); 1826 1827 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1828 &ioat->cached_intrdelay, 0, 1829 "Current INTRDELAY on this channel (cached, microseconds)"); 1830 1831 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 1832 "Big hammers (mostly for testing)"); 1833 hammer = SYSCTL_CHILDREN(tmp); 1834 1835 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1836 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1837 "Set to non-zero to reset the hardware"); 1838 1839 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 1840 "IOAT channel statistics"); 1841 statpar = SYSCTL_CHILDREN(tmp); 1842 1843 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 1844 &ioat->stats.interrupts, 1845 "Number of interrupts processed on this channel"); 1846 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 1847 &ioat->stats.descriptors_processed, 1848 "Number of descriptors processed on this channel"); 1849 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 1850 &ioat->stats.descriptors_submitted, 1851 "Number of descriptors submitted to this channel"); 1852 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 1853 &ioat->stats.descriptors_error, 1854 "Number of descriptors failed by channel errors"); 1855 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 1856 &ioat->stats.channel_halts, 0, 1857 "Number of times the channel has halted"); 1858 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 1859 &ioat->stats.last_halt_chanerr, 0, 1860 "The raw CHANERR when the channel was last halted"); 1861 1862 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 1863 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 1864 "Descriptors per interrupt"); 1865 } 1866 1867 static inline struct ioat_softc * 1868 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1869 { 1870 uint32_t old; 1871 1872 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1873 1874 old = atomic_fetchadd_32(&ioat->refcnt, 1); 1875 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 1876 1877 #ifdef INVARIANTS 1878 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 1879 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 1880 #endif 1881 1882 return (ioat); 1883 } 1884 1885 static inline void 1886 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1887 { 1888 1889 _ioat_putn(ioat, n, kind, FALSE); 1890 } 1891 1892 static inline void 1893 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1894 { 1895 1896 _ioat_putn(ioat, n, kind, TRUE); 1897 } 1898 1899 static inline void 1900 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 1901 boolean_t locked) 1902 { 1903 uint32_t old; 1904 1905 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1906 1907 if (n == 0) 1908 return; 1909 1910 #ifdef INVARIANTS 1911 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 1912 KASSERT(old >= n, ("refcnt kind underflow")); 1913 #endif 1914 1915 /* Skip acquiring the lock if resulting refcnt > 0. */ 1916 for (;;) { 1917 old = ioat->refcnt; 1918 if (old <= n) 1919 break; 1920 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 1921 return; 1922 } 1923 1924 if (locked) 1925 mtx_assert(IOAT_REFLK, MA_OWNED); 1926 else 1927 mtx_lock(IOAT_REFLK); 1928 1929 old = atomic_fetchadd_32(&ioat->refcnt, -n); 1930 KASSERT(old >= n, ("refcnt error")); 1931 1932 if (old == n) 1933 wakeup(IOAT_REFLK); 1934 if (!locked) 1935 mtx_unlock(IOAT_REFLK); 1936 } 1937 1938 static inline void 1939 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1940 { 1941 1942 ioat_putn(ioat, 1, kind); 1943 } 1944 1945 static void 1946 ioat_drain_locked(struct ioat_softc *ioat) 1947 { 1948 1949 mtx_assert(IOAT_REFLK, MA_OWNED); 1950 while (ioat->refcnt > 0) 1951 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 1952 } 1953 1954 #ifdef DDB 1955 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 1956 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 1957 DB_SHOW_COMMAND(ioat, db_show_ioat) 1958 { 1959 struct ioat_softc *sc; 1960 unsigned idx; 1961 1962 if (!have_addr) 1963 goto usage; 1964 idx = (unsigned)addr; 1965 if (idx >= ioat_channel_index) 1966 goto usage; 1967 1968 sc = ioat_channel[idx]; 1969 db_printf("ioat softc at %p\n", sc); 1970 if (sc == NULL) 1971 return; 1972 1973 db_printf(" version: %d\n", sc->version); 1974 db_printf(" chan_idx: %u\n", sc->chan_idx); 1975 db_printf(" submit_lock: "); 1976 db_show_lock(&sc->submit_lock); 1977 1978 db_printf(" capabilities: %b\n", (int)sc->capabilities, 1979 IOAT_DMACAP_STR); 1980 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 1981 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 1982 1983 db_printf(" poll_timer:\n"); 1984 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 1985 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 1986 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 1987 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 1988 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 1989 1990 db_printf(" quiescing: %d\n", (int)sc->quiescing); 1991 db_printf(" destroying: %d\n", (int)sc->destroying); 1992 db_printf(" is_submitter_processing: %d\n", 1993 (int)sc->is_submitter_processing); 1994 db_printf(" is_completion_pending: %d\n", (int)sc->is_completion_pending); 1995 db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending); 1996 db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running); 1997 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 1998 db_printf(" resetting: %d\n", (int)sc->resetting); 1999 2000 db_printf(" head: %u\n", sc->head); 2001 db_printf(" tail: %u\n", sc->tail); 2002 db_printf(" hw_head: %u\n", sc->hw_head); 2003 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2004 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2005 db_printf(" ring: %p\n", sc->ring); 2006 db_printf(" descriptors: %p\n", sc->hw_desc_ring); 2007 db_printf(" descriptors (phys): 0x%jx\n", 2008 (uintmax_t)sc->hw_desc_bus_addr); 2009 2010 db_printf(" ring[%u] (tail):\n", sc->tail % 2011 (1 << sc->ring_size_order)); 2012 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 2013 db_printf(" addr: 0x%lx\n", 2014 RING_PHYS_ADDR(sc, sc->tail)); 2015 db_printf(" next: 0x%lx\n", 2016 ioat_get_descriptor(sc, sc->tail)->generic.next); 2017 2018 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 2019 (1 << sc->ring_size_order)); 2020 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 2021 db_printf(" addr: 0x%lx\n", 2022 RING_PHYS_ADDR(sc, sc->head - 1)); 2023 db_printf(" next: 0x%lx\n", 2024 ioat_get_descriptor(sc, sc->head - 1)->generic.next); 2025 2026 db_printf(" ring[%u] (head):\n", (sc->head) % 2027 (1 << sc->ring_size_order)); 2028 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2029 db_printf(" addr: 0x%lx\n", 2030 RING_PHYS_ADDR(sc, sc->head)); 2031 db_printf(" next: 0x%lx\n", 2032 ioat_get_descriptor(sc, sc->head)->generic.next); 2033 2034 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2035 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2036 == RING_PHYS_ADDR(sc, idx)) 2037 db_printf(" ring[%u] == hardware tail\n", idx); 2038 2039 db_printf(" cleanup_lock: "); 2040 db_show_lock(&sc->cleanup_lock); 2041 2042 db_printf(" refcnt: %u\n", sc->refcnt); 2043 #ifdef INVARIANTS 2044 CTASSERT(IOAT_NUM_REF_KINDS == 2); 2045 db_printf(" refkinds: [ENG=%u, DESCR=%u]\n", sc->refkinds[0], 2046 sc->refkinds[1]); 2047 #endif 2048 db_printf(" stats:\n"); 2049 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2050 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2051 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2052 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2053 2054 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2055 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2056 2057 if (db_pager_quit) 2058 return; 2059 2060 db_printf(" hw status:\n"); 2061 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2062 db_printf(" chanctrl: 0x%x\n", 2063 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2064 db_printf(" chancmd: 0x%x\n", 2065 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2066 db_printf(" dmacount: 0x%x\n", 2067 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2068 db_printf(" chainaddr: 0x%lx\n", 2069 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2070 db_printf(" chancmp: 0x%lx\n", 2071 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2072 db_printf(" chanerr: %b\n", 2073 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2074 return; 2075 usage: 2076 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2077 return; 2078 } 2079 #endif /* DDB */ 2080