1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * Copyright (C) 2018 Alexander Motin <mav@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_ddb.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/domainset.h> 38 #include <sys/fail.h> 39 #include <sys/ioccom.h> 40 #include <sys/kernel.h> 41 #include <sys/ktr.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/sysctl.h> 50 #include <sys/taskqueue.h> 51 #include <sys/time.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 #include <machine/stdarg.h> 57 58 #ifdef DDB 59 #include <ddb/ddb.h> 60 #endif 61 62 #include "ioat.h" 63 #include "ioat_hw.h" 64 #include "ioat_internal.h" 65 66 #ifndef BUS_SPACE_MAXADDR_40BIT 67 #define BUS_SPACE_MAXADDR_40BIT MIN(BUS_SPACE_MAXADDR, 0xFFFFFFFFFFULL) 68 #endif 69 #ifndef BUS_SPACE_MAXADDR_46BIT 70 #define BUS_SPACE_MAXADDR_46BIT MIN(BUS_SPACE_MAXADDR, 0x3FFFFFFFFFFFULL) 71 #endif 72 73 static int ioat_modevent(module_t mod, int type, void *data); 74 static int ioat_probe(device_t device); 75 static int ioat_attach(device_t device); 76 static int ioat_detach(device_t device); 77 static int ioat_setup_intr(struct ioat_softc *ioat); 78 static int ioat_teardown_intr(struct ioat_softc *ioat); 79 static int ioat3_attach(device_t device); 80 static int ioat_start_channel(struct ioat_softc *ioat); 81 static int ioat_map_pci_bar(struct ioat_softc *ioat); 82 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 83 int error); 84 static void ioat_interrupt_handler(void *arg); 85 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 86 static int chanerr_to_errno(uint32_t); 87 static void ioat_process_events(struct ioat_softc *ioat, boolean_t intr); 88 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 89 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 90 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 91 struct ioat_descriptor *); 92 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 93 static union ioat_hw_descriptor *ioat_get_descriptor(struct ioat_softc *, 94 uint32_t index); 95 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *, 96 uint32_t index); 97 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 98 static void ioat_poll_timer_callback(void *arg); 99 static void dump_descriptor(void *hw_desc); 100 static void ioat_submit_single(struct ioat_softc *ioat); 101 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 102 int error); 103 static int ioat_reset_hw(struct ioat_softc *ioat); 104 static void ioat_reset_hw_task(void *, int); 105 static void ioat_setup_sysctl(device_t device); 106 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 107 static void ioat_get(struct ioat_softc *); 108 static void ioat_put(struct ioat_softc *); 109 static void ioat_drain_locked(struct ioat_softc *); 110 111 #define ioat_log_message(v, ...) do { \ 112 if ((v) <= g_ioat_debug_level) { \ 113 device_printf(ioat->device, __VA_ARGS__); \ 114 } \ 115 } while (0) 116 117 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 118 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 119 "ioat node"); 120 121 static int g_force_legacy_interrupts; 122 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 123 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 124 125 int g_ioat_debug_level = 0; 126 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 127 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 128 129 unsigned g_ioat_ring_order = 13; 130 SYSCTL_UINT(_hw_ioat, OID_AUTO, ring_order, CTLFLAG_RDTUN, &g_ioat_ring_order, 131 0, "Set IOAT ring order. (1 << this) == ring size."); 132 133 /* 134 * OS <-> Driver interface structures 135 */ 136 static device_method_t ioat_pci_methods[] = { 137 /* Device interface */ 138 DEVMETHOD(device_probe, ioat_probe), 139 DEVMETHOD(device_attach, ioat_attach), 140 DEVMETHOD(device_detach, ioat_detach), 141 DEVMETHOD_END 142 }; 143 144 static driver_t ioat_pci_driver = { 145 "ioat", 146 ioat_pci_methods, 147 sizeof(struct ioat_softc), 148 }; 149 150 static devclass_t ioat_devclass; 151 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, ioat_modevent, NULL); 152 MODULE_VERSION(ioat, 1); 153 154 /* 155 * Private data structures 156 */ 157 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 158 static unsigned ioat_channel_index = 0; 159 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 160 "Number of IOAT channels attached"); 161 static struct mtx ioat_list_mtx; 162 MTX_SYSINIT(ioat_list_mtx, &ioat_list_mtx, "ioat list mtx", MTX_DEF); 163 164 static struct _pcsid 165 { 166 u_int32_t type; 167 const char *desc; 168 } pci_ids[] = { 169 { 0x34308086, "TBG IOAT Ch0" }, 170 { 0x34318086, "TBG IOAT Ch1" }, 171 { 0x34328086, "TBG IOAT Ch2" }, 172 { 0x34338086, "TBG IOAT Ch3" }, 173 { 0x34298086, "TBG IOAT Ch4" }, 174 { 0x342a8086, "TBG IOAT Ch5" }, 175 { 0x342b8086, "TBG IOAT Ch6" }, 176 { 0x342c8086, "TBG IOAT Ch7" }, 177 178 { 0x37108086, "JSF IOAT Ch0" }, 179 { 0x37118086, "JSF IOAT Ch1" }, 180 { 0x37128086, "JSF IOAT Ch2" }, 181 { 0x37138086, "JSF IOAT Ch3" }, 182 { 0x37148086, "JSF IOAT Ch4" }, 183 { 0x37158086, "JSF IOAT Ch5" }, 184 { 0x37168086, "JSF IOAT Ch6" }, 185 { 0x37178086, "JSF IOAT Ch7" }, 186 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 187 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 188 189 { 0x3c208086, "SNB IOAT Ch0" }, 190 { 0x3c218086, "SNB IOAT Ch1" }, 191 { 0x3c228086, "SNB IOAT Ch2" }, 192 { 0x3c238086, "SNB IOAT Ch3" }, 193 { 0x3c248086, "SNB IOAT Ch4" }, 194 { 0x3c258086, "SNB IOAT Ch5" }, 195 { 0x3c268086, "SNB IOAT Ch6" }, 196 { 0x3c278086, "SNB IOAT Ch7" }, 197 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 198 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 199 200 { 0x0e208086, "IVB IOAT Ch0" }, 201 { 0x0e218086, "IVB IOAT Ch1" }, 202 { 0x0e228086, "IVB IOAT Ch2" }, 203 { 0x0e238086, "IVB IOAT Ch3" }, 204 { 0x0e248086, "IVB IOAT Ch4" }, 205 { 0x0e258086, "IVB IOAT Ch5" }, 206 { 0x0e268086, "IVB IOAT Ch6" }, 207 { 0x0e278086, "IVB IOAT Ch7" }, 208 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 209 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 210 211 { 0x2f208086, "HSW IOAT Ch0" }, 212 { 0x2f218086, "HSW IOAT Ch1" }, 213 { 0x2f228086, "HSW IOAT Ch2" }, 214 { 0x2f238086, "HSW IOAT Ch3" }, 215 { 0x2f248086, "HSW IOAT Ch4" }, 216 { 0x2f258086, "HSW IOAT Ch5" }, 217 { 0x2f268086, "HSW IOAT Ch6" }, 218 { 0x2f278086, "HSW IOAT Ch7" }, 219 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 220 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 221 222 { 0x0c508086, "BWD IOAT Ch0" }, 223 { 0x0c518086, "BWD IOAT Ch1" }, 224 { 0x0c528086, "BWD IOAT Ch2" }, 225 { 0x0c538086, "BWD IOAT Ch3" }, 226 227 { 0x6f508086, "BDXDE IOAT Ch0" }, 228 { 0x6f518086, "BDXDE IOAT Ch1" }, 229 { 0x6f528086, "BDXDE IOAT Ch2" }, 230 { 0x6f538086, "BDXDE IOAT Ch3" }, 231 232 { 0x6f208086, "BDX IOAT Ch0" }, 233 { 0x6f218086, "BDX IOAT Ch1" }, 234 { 0x6f228086, "BDX IOAT Ch2" }, 235 { 0x6f238086, "BDX IOAT Ch3" }, 236 { 0x6f248086, "BDX IOAT Ch4" }, 237 { 0x6f258086, "BDX IOAT Ch5" }, 238 { 0x6f268086, "BDX IOAT Ch6" }, 239 { 0x6f278086, "BDX IOAT Ch7" }, 240 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 241 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 242 243 { 0x20218086, "SKX IOAT" }, 244 }; 245 246 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, ioat, pci_ids, 247 nitems(pci_ids)); 248 249 /* 250 * OS <-> Driver linkage functions 251 */ 252 static int 253 ioat_modevent(module_t mod __unused, int type, void *data __unused) 254 { 255 switch(type) { 256 case MOD_LOAD: 257 break; 258 259 case MOD_UNLOAD: 260 ioat_test_detach(); 261 break; 262 263 case MOD_SHUTDOWN: 264 break; 265 266 default: 267 return (EOPNOTSUPP); 268 } 269 270 return (0); 271 } 272 273 static int 274 ioat_probe(device_t device) 275 { 276 struct _pcsid *ep; 277 u_int32_t type; 278 279 type = pci_get_devid(device); 280 for (ep = pci_ids; ep < &pci_ids[nitems(pci_ids)]; ep++) { 281 if (ep->type == type) { 282 device_set_desc(device, ep->desc); 283 return (0); 284 } 285 } 286 return (ENXIO); 287 } 288 289 static int 290 ioat_attach(device_t device) 291 { 292 struct ioat_softc *ioat; 293 int error, i; 294 295 ioat = DEVICE2SOFTC(device); 296 ioat->device = device; 297 if (bus_get_domain(device, &ioat->domain) != 0) 298 ioat->domain = 0; 299 ioat->cpu = CPU_FFS(&cpuset_domain[ioat->domain]) - 1; 300 if (ioat->cpu < 0) 301 ioat->cpu = CPU_FIRST(); 302 303 error = ioat_map_pci_bar(ioat); 304 if (error != 0) 305 goto err; 306 307 ioat->version = ioat_read_cbver(ioat); 308 if (ioat->version < IOAT_VER_3_0) { 309 error = ENODEV; 310 goto err; 311 } 312 313 error = ioat3_attach(device); 314 if (error != 0) 315 goto err; 316 317 error = pci_enable_busmaster(device); 318 if (error != 0) 319 goto err; 320 321 error = ioat_setup_intr(ioat); 322 if (error != 0) 323 goto err; 324 325 error = ioat_reset_hw(ioat); 326 if (error != 0) 327 goto err; 328 329 ioat_process_events(ioat, FALSE); 330 ioat_setup_sysctl(device); 331 332 mtx_lock(&ioat_list_mtx); 333 for (i = 0; i < IOAT_MAX_CHANNELS; i++) { 334 if (ioat_channel[i] == NULL) 335 break; 336 } 337 if (i >= IOAT_MAX_CHANNELS) { 338 mtx_unlock(&ioat_list_mtx); 339 device_printf(device, "Too many I/OAT devices in system\n"); 340 error = ENXIO; 341 goto err; 342 } 343 ioat->chan_idx = i; 344 ioat_channel[i] = ioat; 345 if (i >= ioat_channel_index) 346 ioat_channel_index = i + 1; 347 mtx_unlock(&ioat_list_mtx); 348 349 ioat_test_attach(); 350 351 err: 352 if (error != 0) 353 ioat_detach(device); 354 return (error); 355 } 356 357 static inline int 358 ioat_bus_dmamap_destroy(struct ioat_softc *ioat, const char *func, 359 bus_dma_tag_t dmat, bus_dmamap_t map) 360 { 361 int error; 362 363 error = bus_dmamap_destroy(dmat, map); 364 if (error != 0) { 365 ioat_log_message(0, 366 "%s: bus_dmamap_destroy failed %d\n", func, error); 367 } 368 369 return (error); 370 } 371 372 static int 373 ioat_detach(device_t device) 374 { 375 struct ioat_softc *ioat; 376 int i, error; 377 378 ioat = DEVICE2SOFTC(device); 379 380 mtx_lock(&ioat_list_mtx); 381 ioat_channel[ioat->chan_idx] = NULL; 382 while (ioat_channel_index > 0 && 383 ioat_channel[ioat_channel_index - 1] == NULL) 384 ioat_channel_index--; 385 mtx_unlock(&ioat_list_mtx); 386 387 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 388 389 mtx_lock(&ioat->submit_lock); 390 ioat->quiescing = TRUE; 391 ioat->destroying = TRUE; 392 wakeup(&ioat->quiescing); 393 wakeup(&ioat->resetting); 394 395 ioat_drain_locked(ioat); 396 mtx_unlock(&ioat->submit_lock); 397 mtx_lock(&ioat->cleanup_lock); 398 while (ioat_get_active(ioat) > 0) 399 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1); 400 mtx_unlock(&ioat->cleanup_lock); 401 402 ioat_teardown_intr(ioat); 403 callout_drain(&ioat->poll_timer); 404 405 pci_disable_busmaster(device); 406 407 if (ioat->pci_resource != NULL) 408 bus_release_resource(device, SYS_RES_MEMORY, 409 ioat->pci_resource_id, ioat->pci_resource); 410 411 if (ioat->data_tag != NULL) { 412 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 413 error = ioat_bus_dmamap_destroy(ioat, __func__, 414 ioat->data_tag, ioat->ring[i].src_dmamap); 415 if (error != 0) 416 return (error); 417 } 418 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 419 error = ioat_bus_dmamap_destroy(ioat, __func__, 420 ioat->data_tag, ioat->ring[i].dst_dmamap); 421 if (error != 0) 422 return (error); 423 } 424 425 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 426 error = ioat_bus_dmamap_destroy(ioat, __func__, 427 ioat->data_tag, ioat->ring[i].src2_dmamap); 428 if (error != 0) 429 return (error); 430 } 431 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 432 error = ioat_bus_dmamap_destroy(ioat, __func__, 433 ioat->data_tag, ioat->ring[i].dst2_dmamap); 434 if (error != 0) 435 return (error); 436 } 437 438 bus_dma_tag_destroy(ioat->data_tag); 439 } 440 441 if (ioat->ring != NULL) 442 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 443 444 if (ioat->comp_update != NULL) { 445 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 446 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 447 ioat->comp_update_map); 448 bus_dma_tag_destroy(ioat->comp_update_tag); 449 } 450 451 if (ioat->hw_desc_ring != NULL) { 452 bus_dmamap_unload(ioat->hw_desc_tag, ioat->hw_desc_map); 453 bus_dmamem_free(ioat->hw_desc_tag, ioat->hw_desc_ring, 454 ioat->hw_desc_map); 455 bus_dma_tag_destroy(ioat->hw_desc_tag); 456 } 457 458 return (0); 459 } 460 461 static int 462 ioat_teardown_intr(struct ioat_softc *ioat) 463 { 464 465 if (ioat->tag != NULL) 466 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 467 468 if (ioat->res != NULL) 469 bus_release_resource(ioat->device, SYS_RES_IRQ, 470 rman_get_rid(ioat->res), ioat->res); 471 472 pci_release_msi(ioat->device); 473 return (0); 474 } 475 476 static int 477 ioat_start_channel(struct ioat_softc *ioat) 478 { 479 struct ioat_dma_hw_descriptor *hw_desc; 480 struct ioat_descriptor *desc; 481 struct bus_dmadesc *dmadesc; 482 uint64_t status; 483 uint32_t chanerr; 484 int i; 485 486 ioat_acquire(&ioat->dmaengine); 487 488 /* Submit 'NULL' operation manually to avoid quiescing flag */ 489 desc = ioat_get_ring_entry(ioat, ioat->head); 490 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->dma; 491 dmadesc = &desc->bus_dmadesc; 492 493 dmadesc->callback_fn = NULL; 494 dmadesc->callback_arg = NULL; 495 496 hw_desc->u.control_raw = 0; 497 hw_desc->u.control_generic.op = IOAT_OP_COPY; 498 hw_desc->u.control_generic.completion_update = 1; 499 hw_desc->size = 8; 500 hw_desc->src_addr = 0; 501 hw_desc->dest_addr = 0; 502 hw_desc->u.control.null = 1; 503 504 ioat_submit_single(ioat); 505 ioat_release(&ioat->dmaengine); 506 507 for (i = 0; i < 100; i++) { 508 DELAY(1); 509 status = ioat_get_chansts(ioat); 510 if (is_ioat_idle(status)) 511 return (0); 512 } 513 514 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 515 ioat_log_message(0, "could not start channel: " 516 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 517 IOAT_CHANERR_STR); 518 return (ENXIO); 519 } 520 521 /* 522 * Initialize Hardware 523 */ 524 static int 525 ioat3_attach(device_t device) 526 { 527 struct ioat_softc *ioat; 528 struct ioat_descriptor *ring; 529 struct ioat_dma_hw_descriptor *dma_hw_desc; 530 void *hw_desc; 531 bus_addr_t lowaddr; 532 size_t ringsz; 533 int i, num_descriptors; 534 int error; 535 uint8_t xfercap; 536 537 error = 0; 538 ioat = DEVICE2SOFTC(device); 539 ioat->capabilities = ioat_read_dmacapability(ioat); 540 541 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 542 IOAT_DMACAP_STR); 543 544 xfercap = ioat_read_xfercap(ioat); 545 ioat->max_xfer_size = 1 << xfercap; 546 547 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 548 IOAT_INTRDELAY_SUPPORTED) != 0; 549 if (ioat->intrdelay_supported) 550 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 551 552 /* TODO: need to check DCA here if we ever do XOR/PQ */ 553 554 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 555 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 556 callout_init(&ioat->poll_timer, 1); 557 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 558 559 /* Establish lock order for Witness */ 560 mtx_lock(&ioat->cleanup_lock); 561 mtx_lock(&ioat->submit_lock); 562 mtx_unlock(&ioat->submit_lock); 563 mtx_unlock(&ioat->cleanup_lock); 564 565 ioat->is_submitter_processing = FALSE; 566 567 if (ioat->version >= IOAT_VER_3_3) 568 lowaddr = BUS_SPACE_MAXADDR_48BIT; 569 else if (ioat->version >= IOAT_VER_3_2) 570 lowaddr = BUS_SPACE_MAXADDR_46BIT; 571 else 572 lowaddr = BUS_SPACE_MAXADDR_40BIT; 573 574 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 575 sizeof(uint64_t), 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 576 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 577 &ioat->comp_update_tag); 578 if (error != 0) 579 return (error); 580 581 error = bus_dmamem_alloc(ioat->comp_update_tag, 582 (void **)&ioat->comp_update, BUS_DMA_ZERO | BUS_DMA_WAITOK, 583 &ioat->comp_update_map); 584 if (error != 0) 585 return (error); 586 587 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 588 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 589 BUS_DMA_NOWAIT); 590 if (error != 0) 591 return (error); 592 593 ioat->ring_size_order = g_ioat_ring_order; 594 num_descriptors = 1 << ioat->ring_size_order; 595 ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors; 596 597 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 598 2 * 1024 * 1024, 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 599 ringsz, 1, ringsz, 0, NULL, NULL, &ioat->hw_desc_tag); 600 if (error != 0) 601 return (error); 602 603 error = bus_dmamem_alloc(ioat->hw_desc_tag, &hw_desc, 604 BUS_DMA_ZERO | BUS_DMA_WAITOK, &ioat->hw_desc_map); 605 if (error != 0) 606 return (error); 607 608 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 609 ringsz, ioat_dmamap_cb, &ioat->hw_desc_bus_addr, BUS_DMA_NOWAIT); 610 if (error) 611 return (error); 612 613 ioat->hw_desc_ring = hw_desc; 614 615 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 616 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 617 ioat->max_xfer_size, 1, ioat->max_xfer_size, 0, NULL, NULL, 618 &ioat->data_tag); 619 if (error != 0) 620 return (error); 621 ioat->ring = malloc_domainset(num_descriptors * sizeof(*ring), M_IOAT, 622 DOMAINSET_PREF(ioat->domain), M_ZERO | M_WAITOK); 623 624 ring = ioat->ring; 625 for (i = 0; i < num_descriptors; i++) { 626 memset(&ring[i].bus_dmadesc, 0, sizeof(ring[i].bus_dmadesc)); 627 ring[i].id = i; 628 error = bus_dmamap_create(ioat->data_tag, 0, 629 &ring[i].src_dmamap); 630 if (error != 0) { 631 ioat_log_message(0, 632 "%s: bus_dmamap_create failed %d\n", __func__, 633 error); 634 return (error); 635 } 636 error = bus_dmamap_create(ioat->data_tag, 0, 637 &ring[i].dst_dmamap); 638 if (error != 0) { 639 ioat_log_message(0, 640 "%s: bus_dmamap_create failed %d\n", __func__, 641 error); 642 return (error); 643 } 644 error = bus_dmamap_create(ioat->data_tag, 0, 645 &ring[i].src2_dmamap); 646 if (error != 0) { 647 ioat_log_message(0, 648 "%s: bus_dmamap_create failed %d\n", __func__, 649 error); 650 return (error); 651 } 652 error = bus_dmamap_create(ioat->data_tag, 0, 653 &ring[i].dst2_dmamap); 654 if (error != 0) { 655 ioat_log_message(0, 656 "%s: bus_dmamap_create failed %d\n", __func__, 657 error); 658 return (error); 659 } 660 } 661 662 for (i = 0; i < num_descriptors; i++) { 663 dma_hw_desc = &ioat->hw_desc_ring[i].dma; 664 dma_hw_desc->next = RING_PHYS_ADDR(ioat, i + 1); 665 } 666 667 ioat->tail = ioat->head = 0; 668 *ioat->comp_update = ioat->last_seen = 669 RING_PHYS_ADDR(ioat, ioat->tail - 1); 670 return (0); 671 } 672 673 static int 674 ioat_map_pci_bar(struct ioat_softc *ioat) 675 { 676 677 ioat->pci_resource_id = PCIR_BAR(0); 678 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 679 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 680 681 if (ioat->pci_resource == NULL) { 682 ioat_log_message(0, "unable to allocate pci resource\n"); 683 return (ENODEV); 684 } 685 686 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 687 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 688 return (0); 689 } 690 691 static void 692 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 693 { 694 struct ioat_softc *ioat = arg; 695 696 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 697 ioat->comp_update_bus_addr = seg[0].ds_addr; 698 } 699 700 static void 701 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 702 { 703 bus_addr_t *baddr; 704 705 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 706 baddr = arg; 707 *baddr = segs->ds_addr; 708 } 709 710 /* 711 * Interrupt setup and handlers 712 */ 713 static int 714 ioat_setup_intr(struct ioat_softc *ioat) 715 { 716 uint32_t num_vectors; 717 int error; 718 boolean_t use_msix; 719 720 use_msix = FALSE; 721 722 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 723 num_vectors = 1; 724 pci_alloc_msix(ioat->device, &num_vectors); 725 if (num_vectors == 1) 726 use_msix = TRUE; 727 } 728 729 if (use_msix) { 730 ioat->rid = 1; 731 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 732 &ioat->rid, RF_ACTIVE); 733 } else { 734 ioat->rid = 0; 735 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 736 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 737 } 738 if (ioat->res == NULL) { 739 ioat_log_message(0, "bus_alloc_resource failed\n"); 740 return (ENOMEM); 741 } 742 743 ioat->tag = NULL; 744 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 745 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 746 if (error != 0) { 747 ioat_log_message(0, "bus_setup_intr failed\n"); 748 return (error); 749 } 750 751 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 752 return (0); 753 } 754 755 static boolean_t 756 ioat_model_resets_msix(struct ioat_softc *ioat) 757 { 758 u_int32_t pciid; 759 760 pciid = pci_get_devid(ioat->device); 761 switch (pciid) { 762 /* BWD: */ 763 case 0x0c508086: 764 case 0x0c518086: 765 case 0x0c528086: 766 case 0x0c538086: 767 /* BDXDE: */ 768 case 0x6f508086: 769 case 0x6f518086: 770 case 0x6f528086: 771 case 0x6f538086: 772 return (TRUE); 773 } 774 775 return (FALSE); 776 } 777 778 static void 779 ioat_interrupt_handler(void *arg) 780 { 781 struct ioat_softc *ioat = arg; 782 783 ioat->stats.interrupts++; 784 ioat_process_events(ioat, TRUE); 785 } 786 787 static int 788 chanerr_to_errno(uint32_t chanerr) 789 { 790 791 if (chanerr == 0) 792 return (0); 793 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 794 return (EFAULT); 795 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 796 return (EIO); 797 /* This one is probably our fault: */ 798 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 799 return (EIO); 800 return (EIO); 801 } 802 803 static void 804 ioat_process_events(struct ioat_softc *ioat, boolean_t intr) 805 { 806 struct ioat_descriptor *desc; 807 struct bus_dmadesc *dmadesc; 808 uint64_t comp_update, status; 809 uint32_t completed, chanerr; 810 int error __diagused; 811 812 if (intr) { 813 mtx_lock(&ioat->cleanup_lock); 814 } else { 815 if (!mtx_trylock(&ioat->cleanup_lock)) 816 return; 817 } 818 819 /* 820 * Don't run while the hardware is being reset. Reset is responsible 821 * for blocking new work and draining & completing existing work, so 822 * there is nothing to do until new work is queued after reset anyway. 823 */ 824 if (ioat->resetting_cleanup) { 825 mtx_unlock(&ioat->cleanup_lock); 826 return; 827 } 828 829 completed = 0; 830 comp_update = *ioat->comp_update; 831 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 832 833 if (status < ioat->hw_desc_bus_addr || 834 status >= ioat->hw_desc_bus_addr + (1 << ioat->ring_size_order) * 835 sizeof(struct ioat_generic_hw_descriptor)) 836 panic("Bogus completion address %jx (channel %u)", 837 (uintmax_t)status, ioat->chan_idx); 838 839 if (status == ioat->last_seen) { 840 /* 841 * If we landed in process_events and nothing has been 842 * completed, check for a timeout due to channel halt. 843 */ 844 goto out; 845 } 846 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx", 847 __func__, ioat->chan_idx, comp_update, ioat->last_seen); 848 849 while (RING_PHYS_ADDR(ioat, ioat->tail - 1) != status) { 850 desc = ioat_get_ring_entry(ioat, ioat->tail); 851 dmadesc = &desc->bus_dmadesc; 852 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) ok cb %p(%p)", 853 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 854 dmadesc->callback_arg); 855 856 bus_dmamap_unload(ioat->data_tag, desc->src_dmamap); 857 bus_dmamap_unload(ioat->data_tag, desc->dst_dmamap); 858 bus_dmamap_unload(ioat->data_tag, desc->src2_dmamap); 859 bus_dmamap_unload(ioat->data_tag, desc->dst2_dmamap); 860 861 if (dmadesc->callback_fn != NULL) 862 dmadesc->callback_fn(dmadesc->callback_arg, 0); 863 864 completed++; 865 ioat->tail++; 866 } 867 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 868 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 869 870 if (completed != 0) { 871 ioat->last_seen = RING_PHYS_ADDR(ioat, ioat->tail - 1); 872 ioat->stats.descriptors_processed += completed; 873 wakeup(&ioat->tail); 874 } 875 876 out: 877 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 878 mtx_unlock(&ioat->cleanup_lock); 879 880 /* 881 * The device doesn't seem to reliably push suspend/halt statuses to 882 * the channel completion memory address, so poll the device register 883 * here. For performance reasons skip it on interrupts, do it only 884 * on much more rare polling events. 885 */ 886 if (!intr) 887 comp_update = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 888 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 889 return; 890 891 ioat->stats.channel_halts++; 892 893 /* 894 * Fatal programming error on this DMA channel. Flush any outstanding 895 * work with error status and restart the engine. 896 */ 897 mtx_lock(&ioat->submit_lock); 898 ioat->quiescing = TRUE; 899 mtx_unlock(&ioat->submit_lock); 900 901 /* 902 * This is safe to do here because the submit queue is quiesced. We 903 * know that we will drain all outstanding events, so ioat_reset_hw 904 * can't deadlock. It is necessary to protect other ioat_process_event 905 * threads from racing ioat_reset_hw, reading an indeterminate hw 906 * state, and attempting to continue issuing completions. 907 */ 908 mtx_lock(&ioat->cleanup_lock); 909 ioat->resetting_cleanup = TRUE; 910 911 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 912 if (1 <= g_ioat_debug_level) 913 ioat_halted_debug(ioat, chanerr); 914 ioat->stats.last_halt_chanerr = chanerr; 915 916 while (ioat_get_active(ioat) > 0) { 917 desc = ioat_get_ring_entry(ioat, ioat->tail); 918 dmadesc = &desc->bus_dmadesc; 919 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) err cb %p(%p)", 920 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 921 dmadesc->callback_arg); 922 923 if (dmadesc->callback_fn != NULL) 924 dmadesc->callback_fn(dmadesc->callback_arg, 925 chanerr_to_errno(chanerr)); 926 927 ioat->tail++; 928 ioat->stats.descriptors_processed++; 929 ioat->stats.descriptors_error++; 930 } 931 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 932 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 933 934 /* Clear error status */ 935 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 936 937 mtx_unlock(&ioat->cleanup_lock); 938 939 ioat_log_message(0, "Resetting channel to recover from error\n"); 940 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 941 KASSERT(error == 0, 942 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 943 } 944 945 static void 946 ioat_reset_hw_task(void *ctx, int pending __unused) 947 { 948 struct ioat_softc *ioat; 949 int error __diagused; 950 951 ioat = ctx; 952 ioat_log_message(1, "%s: Resetting channel\n", __func__); 953 954 error = ioat_reset_hw(ioat); 955 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 956 } 957 958 /* 959 * User API functions 960 */ 961 unsigned 962 ioat_get_nchannels(void) 963 { 964 965 return (ioat_channel_index); 966 } 967 968 bus_dmaengine_t 969 ioat_get_dmaengine(uint32_t index, int flags) 970 { 971 struct ioat_softc *ioat; 972 973 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 974 ("invalid flags: 0x%08x", flags)); 975 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 976 ("invalid wait | nowait")); 977 978 mtx_lock(&ioat_list_mtx); 979 if (index >= ioat_channel_index || 980 (ioat = ioat_channel[index]) == NULL) { 981 mtx_unlock(&ioat_list_mtx); 982 return (NULL); 983 } 984 mtx_lock(&ioat->submit_lock); 985 mtx_unlock(&ioat_list_mtx); 986 987 if (ioat->destroying) { 988 mtx_unlock(&ioat->submit_lock); 989 return (NULL); 990 } 991 992 ioat_get(ioat); 993 if (ioat->quiescing) { 994 if ((flags & M_NOWAIT) != 0) { 995 ioat_put(ioat); 996 mtx_unlock(&ioat->submit_lock); 997 return (NULL); 998 } 999 1000 while (ioat->quiescing && !ioat->destroying) 1001 msleep(&ioat->quiescing, &ioat->submit_lock, 0, "getdma", 0); 1002 1003 if (ioat->destroying) { 1004 ioat_put(ioat); 1005 mtx_unlock(&ioat->submit_lock); 1006 return (NULL); 1007 } 1008 } 1009 mtx_unlock(&ioat->submit_lock); 1010 return (&ioat->dmaengine); 1011 } 1012 1013 void 1014 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 1015 { 1016 struct ioat_softc *ioat; 1017 1018 ioat = to_ioat_softc(dmaengine); 1019 mtx_lock(&ioat->submit_lock); 1020 ioat_put(ioat); 1021 mtx_unlock(&ioat->submit_lock); 1022 } 1023 1024 int 1025 ioat_get_hwversion(bus_dmaengine_t dmaengine) 1026 { 1027 struct ioat_softc *ioat; 1028 1029 ioat = to_ioat_softc(dmaengine); 1030 return (ioat->version); 1031 } 1032 1033 size_t 1034 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 1035 { 1036 struct ioat_softc *ioat; 1037 1038 ioat = to_ioat_softc(dmaengine); 1039 return (ioat->max_xfer_size); 1040 } 1041 1042 uint32_t 1043 ioat_get_capabilities(bus_dmaengine_t dmaengine) 1044 { 1045 struct ioat_softc *ioat; 1046 1047 ioat = to_ioat_softc(dmaengine); 1048 return (ioat->capabilities); 1049 } 1050 1051 int 1052 ioat_get_domain(bus_dmaengine_t dmaengine, int *domain) 1053 { 1054 struct ioat_softc *ioat; 1055 1056 ioat = to_ioat_softc(dmaengine); 1057 return (bus_get_domain(ioat->device, domain)); 1058 } 1059 1060 int 1061 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 1062 { 1063 struct ioat_softc *ioat; 1064 1065 ioat = to_ioat_softc(dmaengine); 1066 if (!ioat->intrdelay_supported) 1067 return (ENODEV); 1068 if (delay > ioat->intrdelay_max) 1069 return (ERANGE); 1070 1071 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 1072 ioat->cached_intrdelay = 1073 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 1074 return (0); 1075 } 1076 1077 uint16_t 1078 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 1079 { 1080 struct ioat_softc *ioat; 1081 1082 ioat = to_ioat_softc(dmaengine); 1083 return (ioat->intrdelay_max); 1084 } 1085 1086 void 1087 ioat_acquire(bus_dmaengine_t dmaengine) 1088 { 1089 struct ioat_softc *ioat; 1090 1091 ioat = to_ioat_softc(dmaengine); 1092 mtx_lock(&ioat->submit_lock); 1093 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1094 ioat->acq_head = ioat->head; 1095 } 1096 1097 int 1098 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 1099 { 1100 struct ioat_softc *ioat; 1101 int error; 1102 1103 ioat = to_ioat_softc(dmaengine); 1104 ioat_acquire(dmaengine); 1105 1106 error = ioat_reserve_space(ioat, n, mflags); 1107 if (error != 0) 1108 ioat_release(dmaengine); 1109 return (error); 1110 } 1111 1112 void 1113 ioat_release(bus_dmaengine_t dmaengine) 1114 { 1115 struct ioat_softc *ioat; 1116 1117 ioat = to_ioat_softc(dmaengine); 1118 CTR3(KTR_IOAT, "%s channel=%u dispatch1 head=%u", __func__, 1119 ioat->chan_idx, ioat->head); 1120 KFAIL_POINT_CODE(DEBUG_FP, ioat_release, /* do nothing */); 1121 CTR3(KTR_IOAT, "%s channel=%u dispatch2 head=%u", __func__, 1122 ioat->chan_idx, ioat->head); 1123 1124 if (ioat->acq_head != ioat->head) { 1125 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, 1126 (uint16_t)ioat->head); 1127 1128 if (!callout_pending(&ioat->poll_timer)) { 1129 callout_reset_on(&ioat->poll_timer, 1, 1130 ioat_poll_timer_callback, ioat, ioat->cpu); 1131 } 1132 } 1133 mtx_unlock(&ioat->submit_lock); 1134 } 1135 1136 static struct ioat_descriptor * 1137 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 1138 uint32_t size, uint64_t src, uint64_t dst, 1139 bus_dmaengine_callback_t callback_fn, void *callback_arg, 1140 uint32_t flags) 1141 { 1142 struct ioat_generic_hw_descriptor *hw_desc; 1143 struct ioat_descriptor *desc; 1144 bus_dma_segment_t seg; 1145 int mflags, nseg, error; 1146 1147 mtx_assert(&ioat->submit_lock, MA_OWNED); 1148 1149 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 1150 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 1151 KASSERT(size <= ioat->max_xfer_size, ("%s: size too big (%u > %u)", 1152 __func__, (unsigned)size, ioat->max_xfer_size)); 1153 1154 if ((flags & DMA_NO_WAIT) != 0) 1155 mflags = M_NOWAIT; 1156 else 1157 mflags = M_WAITOK; 1158 1159 if (ioat_reserve_space(ioat, 1, mflags) != 0) 1160 return (NULL); 1161 1162 desc = ioat_get_ring_entry(ioat, ioat->head); 1163 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->generic; 1164 1165 hw_desc->u.control_raw = 0; 1166 hw_desc->u.control_generic.op = op; 1167 hw_desc->u.control_generic.completion_update = 1; 1168 1169 if ((flags & DMA_INT_EN) != 0) 1170 hw_desc->u.control_generic.int_enable = 1; 1171 if ((flags & DMA_FENCE) != 0) 1172 hw_desc->u.control_generic.fence = 1; 1173 1174 hw_desc->size = size; 1175 1176 if (src != 0) { 1177 nseg = -1; 1178 error = _bus_dmamap_load_phys(ioat->data_tag, desc->src_dmamap, 1179 src, size, 0, &seg, &nseg); 1180 if (error != 0) { 1181 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1182 " failed %d\n", __func__, error); 1183 return (NULL); 1184 } 1185 hw_desc->src_addr = seg.ds_addr; 1186 } 1187 1188 if (dst != 0) { 1189 nseg = -1; 1190 error = _bus_dmamap_load_phys(ioat->data_tag, desc->dst_dmamap, 1191 dst, size, 0, &seg, &nseg); 1192 if (error != 0) { 1193 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1194 " failed %d\n", __func__, error); 1195 return (NULL); 1196 } 1197 hw_desc->dest_addr = seg.ds_addr; 1198 } 1199 1200 desc->bus_dmadesc.callback_fn = callback_fn; 1201 desc->bus_dmadesc.callback_arg = callback_arg; 1202 return (desc); 1203 } 1204 1205 struct bus_dmadesc * 1206 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1207 void *callback_arg, uint32_t flags) 1208 { 1209 struct ioat_dma_hw_descriptor *hw_desc; 1210 struct ioat_descriptor *desc; 1211 struct ioat_softc *ioat; 1212 1213 ioat = to_ioat_softc(dmaengine); 1214 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1215 1216 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1217 callback_arg, flags); 1218 if (desc == NULL) 1219 return (NULL); 1220 1221 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1222 hw_desc->u.control.null = 1; 1223 ioat_submit_single(ioat); 1224 return (&desc->bus_dmadesc); 1225 } 1226 1227 struct bus_dmadesc * 1228 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1229 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1230 void *callback_arg, uint32_t flags) 1231 { 1232 struct ioat_dma_hw_descriptor *hw_desc; 1233 struct ioat_descriptor *desc; 1234 struct ioat_softc *ioat; 1235 1236 ioat = to_ioat_softc(dmaengine); 1237 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1238 callback_arg, flags); 1239 if (desc == NULL) 1240 return (NULL); 1241 1242 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1243 if (g_ioat_debug_level >= 3) 1244 dump_descriptor(hw_desc); 1245 1246 ioat_submit_single(ioat); 1247 CTR6(KTR_IOAT, "%s channel=%u desc=%p dest=%lx src=%lx len=%lx", 1248 __func__, ioat->chan_idx, &desc->bus_dmadesc, dst, src, len); 1249 return (&desc->bus_dmadesc); 1250 } 1251 1252 struct bus_dmadesc * 1253 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1254 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1255 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1256 { 1257 struct ioat_dma_hw_descriptor *hw_desc; 1258 struct ioat_descriptor *desc; 1259 struct ioat_softc *ioat; 1260 bus_size_t src1_len, dst1_len; 1261 bus_dma_segment_t seg; 1262 int nseg, error; 1263 1264 ioat = to_ioat_softc(dmaengine); 1265 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1266 1267 KASSERT(((src1 | src2 | dst1 | dst2) & PAGE_MASK) == 0, 1268 ("%s: addresses are not page-aligned", __func__)); 1269 1270 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, 0, 0, 1271 callback_fn, callback_arg, flags); 1272 if (desc == NULL) 1273 return (NULL); 1274 1275 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1276 1277 src1_len = (src2 != src1 + PAGE_SIZE) ? PAGE_SIZE : 2 * PAGE_SIZE; 1278 nseg = -1; 1279 error = _bus_dmamap_load_phys(ioat->data_tag, 1280 desc->src_dmamap, src1, src1_len, 0, &seg, &nseg); 1281 if (error != 0) { 1282 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1283 " failed %d\n", __func__, error); 1284 return (NULL); 1285 } 1286 hw_desc->src_addr = seg.ds_addr; 1287 if (src1_len != 2 * PAGE_SIZE) { 1288 hw_desc->u.control.src_page_break = 1; 1289 nseg = -1; 1290 error = _bus_dmamap_load_phys(ioat->data_tag, 1291 desc->src2_dmamap, src2, PAGE_SIZE, 0, &seg, &nseg); 1292 if (error != 0) { 1293 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1294 " failed %d\n", __func__, error); 1295 return (NULL); 1296 } 1297 hw_desc->next_src_addr = seg.ds_addr; 1298 } 1299 1300 dst1_len = (dst2 != dst1 + PAGE_SIZE) ? PAGE_SIZE : 2 * PAGE_SIZE; 1301 nseg = -1; 1302 error = _bus_dmamap_load_phys(ioat->data_tag, 1303 desc->dst_dmamap, dst1, dst1_len, 0, &seg, &nseg); 1304 if (error != 0) { 1305 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1306 " failed %d\n", __func__, error); 1307 return (NULL); 1308 } 1309 hw_desc->dest_addr = seg.ds_addr; 1310 if (dst1_len != 2 * PAGE_SIZE) { 1311 hw_desc->u.control.dest_page_break = 1; 1312 nseg = -1; 1313 error = _bus_dmamap_load_phys(ioat->data_tag, 1314 desc->dst2_dmamap, dst2, PAGE_SIZE, 0, &seg, &nseg); 1315 if (error != 0) { 1316 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1317 " failed %d\n", __func__, error); 1318 return (NULL); 1319 } 1320 hw_desc->next_dest_addr = seg.ds_addr; 1321 } 1322 1323 if (g_ioat_debug_level >= 3) 1324 dump_descriptor(hw_desc); 1325 1326 ioat_submit_single(ioat); 1327 return (&desc->bus_dmadesc); 1328 } 1329 1330 struct bus_dmadesc * 1331 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1332 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1333 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1334 { 1335 struct ioat_crc32_hw_descriptor *hw_desc; 1336 struct ioat_descriptor *desc; 1337 struct ioat_softc *ioat; 1338 uint32_t teststore; 1339 uint8_t op; 1340 bus_dma_segment_t seg; 1341 int nseg, error; 1342 1343 ioat = to_ioat_softc(dmaengine); 1344 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1345 1346 KASSERT((ioat->capabilities & IOAT_DMACAP_MOVECRC) != 0, 1347 ("%s: device lacks MOVECRC capability", __func__)); 1348 teststore = (flags & _DMA_CRC_TESTSTORE); 1349 KASSERT(teststore != _DMA_CRC_TESTSTORE, 1350 ("%s: TEST and STORE invalid", __func__)); 1351 KASSERT(teststore != 0 || (flags & DMA_CRC_INLINE) == 0, 1352 ("%s: INLINE invalid without TEST or STORE", __func__)); 1353 1354 switch (teststore) { 1355 case DMA_CRC_STORE: 1356 op = IOAT_OP_MOVECRC_STORE; 1357 break; 1358 case DMA_CRC_TEST: 1359 op = IOAT_OP_MOVECRC_TEST; 1360 break; 1361 default: 1362 KASSERT(teststore == 0, ("bogus")); 1363 op = IOAT_OP_MOVECRC; 1364 break; 1365 } 1366 1367 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1368 callback_arg, flags & ~_DMA_CRC_FLAGS); 1369 if (desc == NULL) 1370 return (NULL); 1371 1372 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1373 1374 if ((flags & DMA_CRC_INLINE) == 0) { 1375 nseg = -1; 1376 error = _bus_dmamap_load_phys(ioat->data_tag, 1377 desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0, 1378 &seg, &nseg); 1379 if (error != 0) { 1380 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1381 " failed %d\n", __func__, error); 1382 return (NULL); 1383 } 1384 hw_desc->crc_address = seg.ds_addr; 1385 } else 1386 hw_desc->u.control.crc_location = 1; 1387 1388 if (initialseed != NULL) { 1389 hw_desc->u.control.use_seed = 1; 1390 hw_desc->seed = *initialseed; 1391 } 1392 1393 if (g_ioat_debug_level >= 3) 1394 dump_descriptor(hw_desc); 1395 1396 ioat_submit_single(ioat); 1397 return (&desc->bus_dmadesc); 1398 } 1399 1400 struct bus_dmadesc * 1401 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1402 uint32_t *initialseed, bus_addr_t crcptr, 1403 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1404 { 1405 struct ioat_crc32_hw_descriptor *hw_desc; 1406 struct ioat_descriptor *desc; 1407 struct ioat_softc *ioat; 1408 uint32_t teststore; 1409 uint8_t op; 1410 bus_dma_segment_t seg; 1411 int nseg, error; 1412 1413 ioat = to_ioat_softc(dmaengine); 1414 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1415 1416 KASSERT((ioat->capabilities & IOAT_DMACAP_CRC) != 0, 1417 ("%s: device lacks CRC capability", __func__)); 1418 teststore = (flags & _DMA_CRC_TESTSTORE); 1419 KASSERT(teststore != _DMA_CRC_TESTSTORE, 1420 ("%s: TEST and STORE invalid", __func__)); 1421 KASSERT(teststore != 0 || (flags & DMA_CRC_INLINE) == 0, 1422 ("%s: INLINE invalid without TEST or STORE", __func__)); 1423 1424 switch (teststore) { 1425 case DMA_CRC_STORE: 1426 op = IOAT_OP_CRC_STORE; 1427 break; 1428 case DMA_CRC_TEST: 1429 op = IOAT_OP_CRC_TEST; 1430 break; 1431 default: 1432 KASSERT(teststore == 0, ("bogus")); 1433 op = IOAT_OP_CRC; 1434 break; 1435 } 1436 1437 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1438 callback_arg, flags & ~_DMA_CRC_FLAGS); 1439 if (desc == NULL) 1440 return (NULL); 1441 1442 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1443 1444 if ((flags & DMA_CRC_INLINE) == 0) { 1445 nseg = -1; 1446 error = _bus_dmamap_load_phys(ioat->data_tag, 1447 desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0, 1448 &seg, &nseg); 1449 if (error != 0) { 1450 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1451 " failed %d\n", __func__, error); 1452 return (NULL); 1453 } 1454 hw_desc->crc_address = seg.ds_addr; 1455 } else 1456 hw_desc->u.control.crc_location = 1; 1457 1458 if (initialseed != NULL) { 1459 hw_desc->u.control.use_seed = 1; 1460 hw_desc->seed = *initialseed; 1461 } 1462 1463 if (g_ioat_debug_level >= 3) 1464 dump_descriptor(hw_desc); 1465 1466 ioat_submit_single(ioat); 1467 return (&desc->bus_dmadesc); 1468 } 1469 1470 struct bus_dmadesc * 1471 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1472 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1473 uint32_t flags) 1474 { 1475 struct ioat_fill_hw_descriptor *hw_desc; 1476 struct ioat_descriptor *desc; 1477 struct ioat_softc *ioat; 1478 1479 ioat = to_ioat_softc(dmaengine); 1480 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1481 1482 KASSERT((ioat->capabilities & IOAT_DMACAP_BFILL) != 0, 1483 ("%s: device lacks BFILL capability", __func__)); 1484 1485 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, 0, dst, 1486 callback_fn, callback_arg, flags); 1487 if (desc == NULL) 1488 return (NULL); 1489 1490 hw_desc = &ioat_get_descriptor(ioat, desc->id)->fill; 1491 hw_desc->src_data = fillpattern; 1492 if (g_ioat_debug_level >= 3) 1493 dump_descriptor(hw_desc); 1494 1495 ioat_submit_single(ioat); 1496 return (&desc->bus_dmadesc); 1497 } 1498 1499 /* 1500 * Ring Management 1501 */ 1502 static inline uint32_t 1503 ioat_get_active(struct ioat_softc *ioat) 1504 { 1505 1506 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1507 } 1508 1509 static inline uint32_t 1510 ioat_get_ring_space(struct ioat_softc *ioat) 1511 { 1512 1513 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1514 } 1515 1516 /* 1517 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1518 * for 'num_descs'. 1519 * 1520 * If mflags contains M_WAITOK, blocks until enough space is available. 1521 * 1522 * Returns zero on success, or an errno on error. If num_descs is beyond the 1523 * maximum ring size, returns EINVAl; if allocation would block and mflags 1524 * contains M_NOWAIT, returns EAGAIN. 1525 * 1526 * Must be called with the submit_lock held; returns with the lock held. The 1527 * lock may be dropped to allocate the ring. 1528 * 1529 * (The submit_lock is needed to add any entries to the ring, so callers are 1530 * assured enough room is available.) 1531 */ 1532 static int 1533 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1534 { 1535 boolean_t dug; 1536 int error; 1537 1538 mtx_assert(&ioat->submit_lock, MA_OWNED); 1539 error = 0; 1540 dug = FALSE; 1541 1542 if (num_descs < 1 || num_descs >= (1 << ioat->ring_size_order)) { 1543 error = EINVAL; 1544 goto out; 1545 } 1546 1547 for (;;) { 1548 if (ioat->quiescing) { 1549 error = ENXIO; 1550 goto out; 1551 } 1552 1553 if (ioat_get_ring_space(ioat) >= num_descs) 1554 goto out; 1555 1556 CTR3(KTR_IOAT, "%s channel=%u starved (%u)", __func__, 1557 ioat->chan_idx, num_descs); 1558 1559 if (!dug && !ioat->is_submitter_processing) { 1560 ioat->is_submitter_processing = TRUE; 1561 mtx_unlock(&ioat->submit_lock); 1562 1563 CTR2(KTR_IOAT, "%s channel=%u attempting to process events", 1564 __func__, ioat->chan_idx); 1565 ioat_process_events(ioat, FALSE); 1566 1567 mtx_lock(&ioat->submit_lock); 1568 dug = TRUE; 1569 KASSERT(ioat->is_submitter_processing == TRUE, 1570 ("is_submitter_processing")); 1571 ioat->is_submitter_processing = FALSE; 1572 wakeup(&ioat->tail); 1573 continue; 1574 } 1575 1576 if ((mflags & M_WAITOK) == 0) { 1577 error = EAGAIN; 1578 break; 1579 } 1580 CTR2(KTR_IOAT, "%s channel=%u blocking on completions", 1581 __func__, ioat->chan_idx); 1582 msleep(&ioat->tail, &ioat->submit_lock, 0, 1583 "ioat_full", 0); 1584 continue; 1585 } 1586 1587 out: 1588 mtx_assert(&ioat->submit_lock, MA_OWNED); 1589 KASSERT(!ioat->quiescing || error == ENXIO, 1590 ("reserved during quiesce")); 1591 return (error); 1592 } 1593 1594 static void 1595 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1596 struct ioat_descriptor *ring) 1597 { 1598 1599 free(ring, M_IOAT); 1600 } 1601 1602 static struct ioat_descriptor * 1603 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1604 { 1605 1606 return (&ioat->ring[index % (1 << ioat->ring_size_order)]); 1607 } 1608 1609 static union ioat_hw_descriptor * 1610 ioat_get_descriptor(struct ioat_softc *ioat, uint32_t index) 1611 { 1612 1613 return (&ioat->hw_desc_ring[index % (1 << ioat->ring_size_order)]); 1614 } 1615 1616 static void 1617 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1618 { 1619 union ioat_hw_descriptor *desc; 1620 1621 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1622 IOAT_CHANERR_STR); 1623 if (chanerr == 0) 1624 return; 1625 1626 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1627 1628 desc = ioat_get_descriptor(ioat, ioat->tail + 0); 1629 dump_descriptor(desc); 1630 1631 desc = ioat_get_descriptor(ioat, ioat->tail + 1); 1632 dump_descriptor(desc); 1633 } 1634 1635 static void 1636 ioat_poll_timer_callback(void *arg) 1637 { 1638 struct ioat_softc *ioat; 1639 1640 ioat = arg; 1641 CTR1(KTR_IOAT, "%s", __func__); 1642 1643 ioat_process_events(ioat, FALSE); 1644 1645 mtx_lock(&ioat->submit_lock); 1646 if (ioat_get_active(ioat) > 0) 1647 callout_schedule(&ioat->poll_timer, 1); 1648 mtx_unlock(&ioat->submit_lock); 1649 } 1650 1651 /* 1652 * Support Functions 1653 */ 1654 static void 1655 ioat_submit_single(struct ioat_softc *ioat) 1656 { 1657 1658 mtx_assert(&ioat->submit_lock, MA_OWNED); 1659 1660 ioat->head++; 1661 CTR4(KTR_IOAT, "%s channel=%u head=%u tail=%u", __func__, 1662 ioat->chan_idx, ioat->head, ioat->tail); 1663 1664 ioat->stats.descriptors_submitted++; 1665 } 1666 1667 static int 1668 ioat_reset_hw(struct ioat_softc *ioat) 1669 { 1670 uint64_t status; 1671 uint32_t chanerr; 1672 unsigned timeout; 1673 int error; 1674 1675 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1676 1677 mtx_lock(&ioat->submit_lock); 1678 while (ioat->resetting && !ioat->destroying) 1679 msleep(&ioat->resetting, &ioat->submit_lock, 0, "IRH_drain", 0); 1680 if (ioat->destroying) { 1681 mtx_unlock(&ioat->submit_lock); 1682 return (ENXIO); 1683 } 1684 ioat->resetting = TRUE; 1685 ioat->quiescing = TRUE; 1686 mtx_unlock(&ioat->submit_lock); 1687 mtx_lock(&ioat->cleanup_lock); 1688 while (ioat_get_active(ioat) > 0) 1689 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1); 1690 1691 /* 1692 * Suspend ioat_process_events while the hardware and softc are in an 1693 * indeterminate state. 1694 */ 1695 ioat->resetting_cleanup = TRUE; 1696 mtx_unlock(&ioat->cleanup_lock); 1697 1698 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__, 1699 ioat->chan_idx); 1700 1701 status = ioat_get_chansts(ioat); 1702 if (is_ioat_active(status) || is_ioat_idle(status)) 1703 ioat_suspend(ioat); 1704 1705 /* Wait at most 20 ms */ 1706 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1707 timeout < 20; timeout++) { 1708 DELAY(1000); 1709 status = ioat_get_chansts(ioat); 1710 } 1711 if (timeout == 20) { 1712 error = ETIMEDOUT; 1713 goto out; 1714 } 1715 1716 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1717 1718 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1719 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1720 1721 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__, 1722 ioat->chan_idx); 1723 1724 /* 1725 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1726 * that can cause stability issues for IOAT v3. 1727 */ 1728 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1729 4); 1730 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1731 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1732 1733 /* 1734 * BDXDE and BWD models reset MSI-X registers on device reset. 1735 * Save/restore their contents manually. 1736 */ 1737 if (ioat_model_resets_msix(ioat)) { 1738 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1739 pci_save_state(ioat->device); 1740 } 1741 1742 ioat_reset(ioat); 1743 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__, 1744 ioat->chan_idx); 1745 1746 /* Wait at most 20 ms */ 1747 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1748 DELAY(1000); 1749 if (timeout == 20) { 1750 error = ETIMEDOUT; 1751 goto out; 1752 } 1753 1754 if (ioat_model_resets_msix(ioat)) { 1755 ioat_log_message(1, "device resets registers; restored\n"); 1756 pci_restore_state(ioat->device); 1757 } 1758 1759 /* Reset attempts to return the hardware to "halted." */ 1760 status = ioat_get_chansts(ioat); 1761 if (is_ioat_active(status) || is_ioat_idle(status)) { 1762 /* So this really shouldn't happen... */ 1763 ioat_log_message(0, "Device is active after a reset?\n"); 1764 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1765 error = 0; 1766 goto out; 1767 } 1768 1769 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1770 if (chanerr != 0) { 1771 mtx_lock(&ioat->cleanup_lock); 1772 ioat_halted_debug(ioat, chanerr); 1773 mtx_unlock(&ioat->cleanup_lock); 1774 error = EIO; 1775 goto out; 1776 } 1777 1778 /* 1779 * Bring device back online after reset. Writing CHAINADDR brings the 1780 * device back to active. 1781 * 1782 * The internal ring counter resets to zero, so we have to start over 1783 * at zero as well. 1784 */ 1785 ioat->tail = ioat->head = 0; 1786 *ioat->comp_update = ioat->last_seen = 1787 RING_PHYS_ADDR(ioat, ioat->tail - 1); 1788 1789 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1790 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1791 ioat_write_chainaddr(ioat, RING_PHYS_ADDR(ioat, 0)); 1792 error = 0; 1793 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__, 1794 ioat->chan_idx); 1795 1796 out: 1797 /* Enqueues a null operation and ensures it completes. */ 1798 if (error == 0) { 1799 error = ioat_start_channel(ioat); 1800 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__, 1801 ioat->chan_idx); 1802 } 1803 1804 /* 1805 * Resume completions now that ring state is consistent. 1806 */ 1807 mtx_lock(&ioat->cleanup_lock); 1808 ioat->resetting_cleanup = FALSE; 1809 mtx_unlock(&ioat->cleanup_lock); 1810 1811 /* Unblock submission of new work */ 1812 mtx_lock(&ioat->submit_lock); 1813 ioat->quiescing = FALSE; 1814 wakeup(&ioat->quiescing); 1815 1816 ioat->resetting = FALSE; 1817 wakeup(&ioat->resetting); 1818 1819 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx); 1820 mtx_unlock(&ioat->submit_lock); 1821 1822 return (error); 1823 } 1824 1825 static int 1826 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1827 { 1828 struct ioat_softc *ioat; 1829 struct sbuf sb; 1830 uint64_t status; 1831 int error; 1832 1833 ioat = arg1; 1834 1835 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1836 1837 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1838 switch (status) { 1839 case IOAT_CHANSTS_ACTIVE: 1840 sbuf_printf(&sb, "ACTIVE"); 1841 break; 1842 case IOAT_CHANSTS_IDLE: 1843 sbuf_printf(&sb, "IDLE"); 1844 break; 1845 case IOAT_CHANSTS_SUSPENDED: 1846 sbuf_printf(&sb, "SUSPENDED"); 1847 break; 1848 case IOAT_CHANSTS_HALTED: 1849 sbuf_printf(&sb, "HALTED"); 1850 break; 1851 case IOAT_CHANSTS_ARMED: 1852 sbuf_printf(&sb, "ARMED"); 1853 break; 1854 default: 1855 sbuf_printf(&sb, "UNKNOWN"); 1856 break; 1857 } 1858 error = sbuf_finish(&sb); 1859 sbuf_delete(&sb); 1860 1861 if (error != 0 || req->newptr == NULL) 1862 return (error); 1863 return (EINVAL); 1864 } 1865 1866 static int 1867 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1868 { 1869 struct ioat_softc *ioat; 1870 struct sbuf sb; 1871 #define PRECISION "1" 1872 const uintmax_t factor = 10; 1873 uintmax_t rate; 1874 int error; 1875 1876 ioat = arg1; 1877 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1878 1879 if (ioat->stats.interrupts == 0) { 1880 sbuf_printf(&sb, "NaN"); 1881 goto out; 1882 } 1883 rate = ioat->stats.descriptors_processed * factor / 1884 ioat->stats.interrupts; 1885 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1886 rate % factor); 1887 #undef PRECISION 1888 out: 1889 error = sbuf_finish(&sb); 1890 sbuf_delete(&sb); 1891 if (error != 0 || req->newptr == NULL) 1892 return (error); 1893 return (EINVAL); 1894 } 1895 1896 static int 1897 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1898 { 1899 struct ioat_softc *ioat; 1900 int error, arg; 1901 1902 ioat = arg1; 1903 1904 arg = 0; 1905 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1906 if (error != 0 || req->newptr == NULL) 1907 return (error); 1908 1909 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1910 if (error != 0) 1911 return (error); 1912 1913 if (arg != 0) 1914 error = ioat_reset_hw(ioat); 1915 1916 return (error); 1917 } 1918 1919 static void 1920 dump_descriptor(void *hw_desc) 1921 { 1922 int i, j; 1923 1924 for (i = 0; i < 2; i++) { 1925 for (j = 0; j < 8; j++) 1926 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1927 printf("\n"); 1928 } 1929 } 1930 1931 static void 1932 ioat_setup_sysctl(device_t device) 1933 { 1934 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1935 struct sysctl_ctx_list *ctx; 1936 struct sysctl_oid *tree, *tmp; 1937 struct ioat_softc *ioat; 1938 1939 ioat = DEVICE2SOFTC(device); 1940 ctx = device_get_sysctl_ctx(device); 1941 tree = device_get_sysctl_tree(device); 1942 par = SYSCTL_CHILDREN(tree); 1943 1944 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1945 &ioat->version, 0, "HW version (0xMM form)"); 1946 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1947 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1948 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1949 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1950 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1951 &ioat->intrdelay_max, 0, 1952 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1953 1954 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", 1955 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IOAT channel internal state"); 1956 state = SYSCTL_CHILDREN(tmp); 1957 1958 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1959 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1960 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1961 0, "SW descriptor head pointer index"); 1962 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1963 0, "SW descriptor tail pointer index"); 1964 1965 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1966 ioat->comp_update, "HW addr of last completion"); 1967 1968 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 1969 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 1970 "submitter processing"); 1971 1972 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1973 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, ioat, 0, 1974 sysctl_handle_chansts, "A", "String of the channel status"); 1975 1976 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1977 &ioat->cached_intrdelay, 0, 1978 "Current INTRDELAY on this channel (cached, microseconds)"); 1979 1980 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", 1981 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1982 "Big hammers (mostly for testing)"); 1983 hammer = SYSCTL_CHILDREN(tmp); 1984 1985 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1986 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, ioat, 0, 1987 sysctl_handle_reset, "I", "Set to non-zero to reset the hardware"); 1988 1989 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", 1990 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IOAT channel statistics"); 1991 statpar = SYSCTL_CHILDREN(tmp); 1992 1993 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", 1994 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.interrupts, 1995 "Number of interrupts processed on this channel"); 1996 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", 1997 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_processed, 1998 "Number of descriptors processed on this channel"); 1999 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", 2000 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_submitted, 2001 "Number of descriptors submitted to this channel"); 2002 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", 2003 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_error, 2004 "Number of descriptors failed by channel errors"); 2005 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", 2006 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.channel_halts, 0, 2007 "Number of times the channel has halted"); 2008 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", 2009 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.last_halt_chanerr, 0, 2010 "The raw CHANERR when the channel was last halted"); 2011 2012 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 2013 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, ioat, 0, 2014 sysctl_handle_dpi, "A", "Descriptors per interrupt"); 2015 } 2016 2017 static void 2018 ioat_get(struct ioat_softc *ioat) 2019 { 2020 2021 mtx_assert(&ioat->submit_lock, MA_OWNED); 2022 KASSERT(ioat->refcnt < UINT32_MAX, ("refcnt overflow")); 2023 2024 ioat->refcnt++; 2025 } 2026 2027 static void 2028 ioat_put(struct ioat_softc *ioat) 2029 { 2030 2031 mtx_assert(&ioat->submit_lock, MA_OWNED); 2032 KASSERT(ioat->refcnt >= 1, ("refcnt error")); 2033 2034 if (--ioat->refcnt == 0) 2035 wakeup(&ioat->refcnt); 2036 } 2037 2038 static void 2039 ioat_drain_locked(struct ioat_softc *ioat) 2040 { 2041 2042 mtx_assert(&ioat->submit_lock, MA_OWNED); 2043 2044 while (ioat->refcnt > 0) 2045 msleep(&ioat->refcnt, &ioat->submit_lock, 0, "ioat_drain", 0); 2046 } 2047 2048 #ifdef DDB 2049 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 2050 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 2051 DB_SHOW_COMMAND(ioat, db_show_ioat) 2052 { 2053 struct ioat_softc *sc; 2054 unsigned idx; 2055 2056 if (!have_addr) 2057 goto usage; 2058 idx = (unsigned)addr; 2059 if (idx >= ioat_channel_index) 2060 goto usage; 2061 2062 sc = ioat_channel[idx]; 2063 db_printf("ioat softc at %p\n", sc); 2064 if (sc == NULL) 2065 return; 2066 2067 db_printf(" version: %d\n", sc->version); 2068 db_printf(" chan_idx: %u\n", sc->chan_idx); 2069 db_printf(" submit_lock: "); 2070 db_show_lock(&sc->submit_lock); 2071 2072 db_printf(" capabilities: %b\n", (int)sc->capabilities, 2073 IOAT_DMACAP_STR); 2074 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 2075 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 2076 2077 db_printf(" poll_timer:\n"); 2078 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 2079 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 2080 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 2081 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 2082 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 2083 2084 db_printf(" quiescing: %d\n", (int)sc->quiescing); 2085 db_printf(" destroying: %d\n", (int)sc->destroying); 2086 db_printf(" is_submitter_processing: %d\n", 2087 (int)sc->is_submitter_processing); 2088 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 2089 db_printf(" resetting: %d\n", (int)sc->resetting); 2090 2091 db_printf(" head: %u\n", sc->head); 2092 db_printf(" tail: %u\n", sc->tail); 2093 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2094 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2095 db_printf(" ring: %p\n", sc->ring); 2096 db_printf(" descriptors: %p\n", sc->hw_desc_ring); 2097 db_printf(" descriptors (phys): 0x%jx\n", 2098 (uintmax_t)sc->hw_desc_bus_addr); 2099 2100 db_printf(" ring[%u] (tail):\n", sc->tail % 2101 (1 << sc->ring_size_order)); 2102 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 2103 db_printf(" addr: 0x%lx\n", 2104 RING_PHYS_ADDR(sc, sc->tail)); 2105 db_printf(" next: 0x%lx\n", 2106 ioat_get_descriptor(sc, sc->tail)->generic.next); 2107 2108 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 2109 (1 << sc->ring_size_order)); 2110 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 2111 db_printf(" addr: 0x%lx\n", 2112 RING_PHYS_ADDR(sc, sc->head - 1)); 2113 db_printf(" next: 0x%lx\n", 2114 ioat_get_descriptor(sc, sc->head - 1)->generic.next); 2115 2116 db_printf(" ring[%u] (head):\n", (sc->head) % 2117 (1 << sc->ring_size_order)); 2118 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2119 db_printf(" addr: 0x%lx\n", 2120 RING_PHYS_ADDR(sc, sc->head)); 2121 db_printf(" next: 0x%lx\n", 2122 ioat_get_descriptor(sc, sc->head)->generic.next); 2123 2124 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2125 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2126 == RING_PHYS_ADDR(sc, idx)) 2127 db_printf(" ring[%u] == hardware tail\n", idx); 2128 2129 db_printf(" cleanup_lock: "); 2130 db_show_lock(&sc->cleanup_lock); 2131 2132 db_printf(" refcnt: %u\n", sc->refcnt); 2133 db_printf(" stats:\n"); 2134 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2135 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2136 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2137 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2138 2139 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2140 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2141 2142 if (db_pager_quit) 2143 return; 2144 2145 db_printf(" hw status:\n"); 2146 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2147 db_printf(" chanctrl: 0x%x\n", 2148 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2149 db_printf(" chancmd: 0x%x\n", 2150 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2151 db_printf(" dmacount: 0x%x\n", 2152 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2153 db_printf(" chainaddr: 0x%lx\n", 2154 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2155 db_printf(" chancmp: 0x%lx\n", 2156 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2157 db_printf(" chanerr: %b\n", 2158 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2159 return; 2160 usage: 2161 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2162 return; 2163 } 2164 #endif /* DDB */ 2165