1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * Copyright (C) 2018 Alexander Motin <mav@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_ddb.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/domainset.h> 38 #include <sys/fail.h> 39 #include <sys/ioccom.h> 40 #include <sys/kernel.h> 41 #include <sys/ktr.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/sysctl.h> 50 #include <sys/taskqueue.h> 51 #include <sys/time.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 #include <machine/stdarg.h> 57 58 #ifdef DDB 59 #include <ddb/ddb.h> 60 #endif 61 62 #include "ioat.h" 63 #include "ioat_hw.h" 64 #include "ioat_internal.h" 65 66 #ifndef BUS_SPACE_MAXADDR_40BIT 67 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 68 #endif 69 70 static int ioat_probe(device_t device); 71 static int ioat_attach(device_t device); 72 static int ioat_detach(device_t device); 73 static int ioat_setup_intr(struct ioat_softc *ioat); 74 static int ioat_teardown_intr(struct ioat_softc *ioat); 75 static int ioat3_attach(device_t device); 76 static int ioat_start_channel(struct ioat_softc *ioat); 77 static int ioat_map_pci_bar(struct ioat_softc *ioat); 78 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 79 int error); 80 static void ioat_interrupt_handler(void *arg); 81 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 82 static int chanerr_to_errno(uint32_t); 83 static void ioat_process_events(struct ioat_softc *ioat, boolean_t intr); 84 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 85 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 86 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 87 struct ioat_descriptor *); 88 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 89 static union ioat_hw_descriptor *ioat_get_descriptor(struct ioat_softc *, 90 uint32_t index); 91 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *, 92 uint32_t index); 93 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 94 static void ioat_poll_timer_callback(void *arg); 95 static void dump_descriptor(void *hw_desc); 96 static void ioat_submit_single(struct ioat_softc *ioat); 97 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 98 int error); 99 static int ioat_reset_hw(struct ioat_softc *ioat); 100 static void ioat_reset_hw_task(void *, int); 101 static void ioat_setup_sysctl(device_t device); 102 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 103 static void ioat_get(struct ioat_softc *); 104 static void ioat_put(struct ioat_softc *); 105 static void ioat_drain_locked(struct ioat_softc *); 106 107 #define ioat_log_message(v, ...) do { \ 108 if ((v) <= g_ioat_debug_level) { \ 109 device_printf(ioat->device, __VA_ARGS__); \ 110 } \ 111 } while (0) 112 113 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 114 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 115 116 static int g_force_legacy_interrupts; 117 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 118 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 119 120 int g_ioat_debug_level = 0; 121 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 122 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 123 124 unsigned g_ioat_ring_order = 13; 125 SYSCTL_UINT(_hw_ioat, OID_AUTO, ring_order, CTLFLAG_RDTUN, &g_ioat_ring_order, 126 0, "Set IOAT ring order. (1 << this) == ring size."); 127 128 /* 129 * OS <-> Driver interface structures 130 */ 131 static device_method_t ioat_pci_methods[] = { 132 /* Device interface */ 133 DEVMETHOD(device_probe, ioat_probe), 134 DEVMETHOD(device_attach, ioat_attach), 135 DEVMETHOD(device_detach, ioat_detach), 136 DEVMETHOD_END 137 }; 138 139 static driver_t ioat_pci_driver = { 140 "ioat", 141 ioat_pci_methods, 142 sizeof(struct ioat_softc), 143 }; 144 145 static devclass_t ioat_devclass; 146 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 147 MODULE_VERSION(ioat, 1); 148 149 /* 150 * Private data structures 151 */ 152 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 153 static unsigned ioat_channel_index = 0; 154 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 155 "Number of IOAT channels attached"); 156 static struct mtx ioat_list_mtx; 157 MTX_SYSINIT(ioat_list_mtx, &ioat_list_mtx, "ioat list mtx", MTX_DEF); 158 159 static struct _pcsid 160 { 161 u_int32_t type; 162 const char *desc; 163 } pci_ids[] = { 164 { 0x34308086, "TBG IOAT Ch0" }, 165 { 0x34318086, "TBG IOAT Ch1" }, 166 { 0x34328086, "TBG IOAT Ch2" }, 167 { 0x34338086, "TBG IOAT Ch3" }, 168 { 0x34298086, "TBG IOAT Ch4" }, 169 { 0x342a8086, "TBG IOAT Ch5" }, 170 { 0x342b8086, "TBG IOAT Ch6" }, 171 { 0x342c8086, "TBG IOAT Ch7" }, 172 173 { 0x37108086, "JSF IOAT Ch0" }, 174 { 0x37118086, "JSF IOAT Ch1" }, 175 { 0x37128086, "JSF IOAT Ch2" }, 176 { 0x37138086, "JSF IOAT Ch3" }, 177 { 0x37148086, "JSF IOAT Ch4" }, 178 { 0x37158086, "JSF IOAT Ch5" }, 179 { 0x37168086, "JSF IOAT Ch6" }, 180 { 0x37178086, "JSF IOAT Ch7" }, 181 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 182 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 183 184 { 0x3c208086, "SNB IOAT Ch0" }, 185 { 0x3c218086, "SNB IOAT Ch1" }, 186 { 0x3c228086, "SNB IOAT Ch2" }, 187 { 0x3c238086, "SNB IOAT Ch3" }, 188 { 0x3c248086, "SNB IOAT Ch4" }, 189 { 0x3c258086, "SNB IOAT Ch5" }, 190 { 0x3c268086, "SNB IOAT Ch6" }, 191 { 0x3c278086, "SNB IOAT Ch7" }, 192 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 193 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 194 195 { 0x0e208086, "IVB IOAT Ch0" }, 196 { 0x0e218086, "IVB IOAT Ch1" }, 197 { 0x0e228086, "IVB IOAT Ch2" }, 198 { 0x0e238086, "IVB IOAT Ch3" }, 199 { 0x0e248086, "IVB IOAT Ch4" }, 200 { 0x0e258086, "IVB IOAT Ch5" }, 201 { 0x0e268086, "IVB IOAT Ch6" }, 202 { 0x0e278086, "IVB IOAT Ch7" }, 203 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 204 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 205 206 { 0x2f208086, "HSW IOAT Ch0" }, 207 { 0x2f218086, "HSW IOAT Ch1" }, 208 { 0x2f228086, "HSW IOAT Ch2" }, 209 { 0x2f238086, "HSW IOAT Ch3" }, 210 { 0x2f248086, "HSW IOAT Ch4" }, 211 { 0x2f258086, "HSW IOAT Ch5" }, 212 { 0x2f268086, "HSW IOAT Ch6" }, 213 { 0x2f278086, "HSW IOAT Ch7" }, 214 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 215 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 216 217 { 0x0c508086, "BWD IOAT Ch0" }, 218 { 0x0c518086, "BWD IOAT Ch1" }, 219 { 0x0c528086, "BWD IOAT Ch2" }, 220 { 0x0c538086, "BWD IOAT Ch3" }, 221 222 { 0x6f508086, "BDXDE IOAT Ch0" }, 223 { 0x6f518086, "BDXDE IOAT Ch1" }, 224 { 0x6f528086, "BDXDE IOAT Ch2" }, 225 { 0x6f538086, "BDXDE IOAT Ch3" }, 226 227 { 0x6f208086, "BDX IOAT Ch0" }, 228 { 0x6f218086, "BDX IOAT Ch1" }, 229 { 0x6f228086, "BDX IOAT Ch2" }, 230 { 0x6f238086, "BDX IOAT Ch3" }, 231 { 0x6f248086, "BDX IOAT Ch4" }, 232 { 0x6f258086, "BDX IOAT Ch5" }, 233 { 0x6f268086, "BDX IOAT Ch6" }, 234 { 0x6f278086, "BDX IOAT Ch7" }, 235 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 236 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 237 238 { 0x20218086, "SKX IOAT" }, 239 }; 240 241 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, ioat, pci_ids, 242 nitems(pci_ids)); 243 244 /* 245 * OS <-> Driver linkage functions 246 */ 247 static int 248 ioat_probe(device_t device) 249 { 250 struct _pcsid *ep; 251 u_int32_t type; 252 253 type = pci_get_devid(device); 254 for (ep = pci_ids; ep < &pci_ids[nitems(pci_ids)]; ep++) { 255 if (ep->type == type) { 256 device_set_desc(device, ep->desc); 257 return (0); 258 } 259 } 260 return (ENXIO); 261 } 262 263 static int 264 ioat_attach(device_t device) 265 { 266 struct ioat_softc *ioat; 267 int error, i; 268 269 ioat = DEVICE2SOFTC(device); 270 ioat->device = device; 271 if (bus_get_domain(device, &ioat->domain) != 0) 272 ioat->domain = 0; 273 ioat->cpu = CPU_FFS(&cpuset_domain[ioat->domain]) - 1; 274 if (ioat->cpu < 0) 275 ioat->cpu = CPU_FIRST(); 276 277 error = ioat_map_pci_bar(ioat); 278 if (error != 0) 279 goto err; 280 281 ioat->version = ioat_read_cbver(ioat); 282 if (ioat->version < IOAT_VER_3_0) { 283 error = ENODEV; 284 goto err; 285 } 286 287 error = ioat3_attach(device); 288 if (error != 0) 289 goto err; 290 291 error = pci_enable_busmaster(device); 292 if (error != 0) 293 goto err; 294 295 error = ioat_setup_intr(ioat); 296 if (error != 0) 297 goto err; 298 299 error = ioat_reset_hw(ioat); 300 if (error != 0) 301 goto err; 302 303 ioat_process_events(ioat, FALSE); 304 ioat_setup_sysctl(device); 305 306 mtx_lock(&ioat_list_mtx); 307 for (i = 0; i < IOAT_MAX_CHANNELS; i++) { 308 if (ioat_channel[i] == NULL) 309 break; 310 } 311 if (i >= IOAT_MAX_CHANNELS) { 312 mtx_unlock(&ioat_list_mtx); 313 device_printf(device, "Too many I/OAT devices in system\n"); 314 error = ENXIO; 315 goto err; 316 } 317 ioat->chan_idx = i; 318 ioat_channel[i] = ioat; 319 if (i >= ioat_channel_index) 320 ioat_channel_index = i + 1; 321 mtx_unlock(&ioat_list_mtx); 322 323 ioat_test_attach(); 324 325 err: 326 if (error != 0) 327 ioat_detach(device); 328 return (error); 329 } 330 331 static inline int 332 ioat_bus_dmamap_destroy(struct ioat_softc *ioat, const char *func, 333 bus_dma_tag_t dmat, bus_dmamap_t map) 334 { 335 int error; 336 337 error = bus_dmamap_destroy(dmat, map); 338 if (error != 0) { 339 ioat_log_message(0, 340 "%s: bus_dmamap_destroy failed %d\n", func, error); 341 } 342 343 return (error); 344 } 345 346 static int 347 ioat_detach(device_t device) 348 { 349 struct ioat_softc *ioat; 350 int i, error; 351 352 ioat = DEVICE2SOFTC(device); 353 354 mtx_lock(&ioat_list_mtx); 355 ioat_channel[ioat->chan_idx] = NULL; 356 while (ioat_channel_index > 0 && 357 ioat_channel[ioat_channel_index - 1] == NULL) 358 ioat_channel_index--; 359 mtx_unlock(&ioat_list_mtx); 360 361 ioat_test_detach(); 362 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 363 364 mtx_lock(&ioat->submit_lock); 365 ioat->quiescing = TRUE; 366 ioat->destroying = TRUE; 367 wakeup(&ioat->quiescing); 368 wakeup(&ioat->resetting); 369 370 ioat_drain_locked(ioat); 371 mtx_unlock(&ioat->submit_lock); 372 mtx_lock(&ioat->cleanup_lock); 373 while (ioat_get_active(ioat) > 0) 374 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1); 375 mtx_unlock(&ioat->cleanup_lock); 376 377 ioat_teardown_intr(ioat); 378 callout_drain(&ioat->poll_timer); 379 380 pci_disable_busmaster(device); 381 382 if (ioat->pci_resource != NULL) 383 bus_release_resource(device, SYS_RES_MEMORY, 384 ioat->pci_resource_id, ioat->pci_resource); 385 386 if (ioat->data_tag != NULL) { 387 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 388 error = ioat_bus_dmamap_destroy(ioat, __func__, 389 ioat->data_tag, ioat->ring[i].src_dmamap); 390 if (error != 0) 391 return (error); 392 } 393 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 394 error = ioat_bus_dmamap_destroy(ioat, __func__, 395 ioat->data_tag, ioat->ring[i].dst_dmamap); 396 if (error != 0) 397 return (error); 398 } 399 400 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 401 error = ioat_bus_dmamap_destroy(ioat, __func__, 402 ioat->data_tag, ioat->ring[i].src2_dmamap); 403 if (error != 0) 404 return (error); 405 } 406 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 407 error = ioat_bus_dmamap_destroy(ioat, __func__, 408 ioat->data_tag, ioat->ring[i].dst2_dmamap); 409 if (error != 0) 410 return (error); 411 } 412 413 bus_dma_tag_destroy(ioat->data_tag); 414 } 415 416 if (ioat->data_crc_tag != NULL) { 417 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 418 error = ioat_bus_dmamap_destroy(ioat, __func__, 419 ioat->data_crc_tag, ioat->ring[i].crc_dmamap); 420 if (error != 0) 421 return (error); 422 } 423 424 bus_dma_tag_destroy(ioat->data_crc_tag); 425 } 426 427 if (ioat->ring != NULL) 428 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 429 430 if (ioat->comp_update != NULL) { 431 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 432 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 433 ioat->comp_update_map); 434 bus_dma_tag_destroy(ioat->comp_update_tag); 435 } 436 437 if (ioat->hw_desc_ring != NULL) { 438 bus_dmamap_unload(ioat->hw_desc_tag, ioat->hw_desc_map); 439 bus_dmamem_free(ioat->hw_desc_tag, ioat->hw_desc_ring, 440 ioat->hw_desc_map); 441 bus_dma_tag_destroy(ioat->hw_desc_tag); 442 } 443 444 return (0); 445 } 446 447 static int 448 ioat_teardown_intr(struct ioat_softc *ioat) 449 { 450 451 if (ioat->tag != NULL) 452 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 453 454 if (ioat->res != NULL) 455 bus_release_resource(ioat->device, SYS_RES_IRQ, 456 rman_get_rid(ioat->res), ioat->res); 457 458 pci_release_msi(ioat->device); 459 return (0); 460 } 461 462 static int 463 ioat_start_channel(struct ioat_softc *ioat) 464 { 465 struct ioat_dma_hw_descriptor *hw_desc; 466 struct ioat_descriptor *desc; 467 struct bus_dmadesc *dmadesc; 468 uint64_t status; 469 uint32_t chanerr; 470 int i; 471 472 ioat_acquire(&ioat->dmaengine); 473 474 /* Submit 'NULL' operation manually to avoid quiescing flag */ 475 desc = ioat_get_ring_entry(ioat, ioat->head); 476 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->dma; 477 dmadesc = &desc->bus_dmadesc; 478 479 dmadesc->callback_fn = NULL; 480 dmadesc->callback_arg = NULL; 481 482 hw_desc->u.control_raw = 0; 483 hw_desc->u.control_generic.op = IOAT_OP_COPY; 484 hw_desc->u.control_generic.completion_update = 1; 485 hw_desc->size = 8; 486 hw_desc->src_addr = 0; 487 hw_desc->dest_addr = 0; 488 hw_desc->u.control.null = 1; 489 490 ioat_submit_single(ioat); 491 ioat_release(&ioat->dmaengine); 492 493 for (i = 0; i < 100; i++) { 494 DELAY(1); 495 status = ioat_get_chansts(ioat); 496 if (is_ioat_idle(status)) 497 return (0); 498 } 499 500 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 501 ioat_log_message(0, "could not start channel: " 502 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 503 IOAT_CHANERR_STR); 504 return (ENXIO); 505 } 506 507 /* 508 * Initialize Hardware 509 */ 510 static int 511 ioat3_attach(device_t device) 512 { 513 struct ioat_softc *ioat; 514 struct ioat_descriptor *ring; 515 struct ioat_dma_hw_descriptor *dma_hw_desc; 516 void *hw_desc; 517 size_t ringsz; 518 int i, num_descriptors; 519 int error; 520 uint8_t xfercap; 521 522 error = 0; 523 ioat = DEVICE2SOFTC(device); 524 ioat->capabilities = ioat_read_dmacapability(ioat); 525 526 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 527 IOAT_DMACAP_STR); 528 529 xfercap = ioat_read_xfercap(ioat); 530 ioat->max_xfer_size = 1 << xfercap; 531 532 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 533 IOAT_INTRDELAY_SUPPORTED) != 0; 534 if (ioat->intrdelay_supported) 535 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 536 537 /* TODO: need to check DCA here if we ever do XOR/PQ */ 538 539 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 540 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 541 callout_init(&ioat->poll_timer, 1); 542 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 543 544 /* Establish lock order for Witness */ 545 mtx_lock(&ioat->cleanup_lock); 546 mtx_lock(&ioat->submit_lock); 547 mtx_unlock(&ioat->submit_lock); 548 mtx_unlock(&ioat->cleanup_lock); 549 550 ioat->is_submitter_processing = FALSE; 551 552 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 553 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 554 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 555 &ioat->comp_update_tag); 556 557 error = bus_dmamem_alloc(ioat->comp_update_tag, 558 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 559 if (ioat->comp_update == NULL) 560 return (ENOMEM); 561 562 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 563 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 564 0); 565 if (error != 0) 566 return (error); 567 568 ioat->ring_size_order = g_ioat_ring_order; 569 num_descriptors = 1 << ioat->ring_size_order; 570 ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors; 571 572 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 573 2 * 1024 * 1024, 0x0, (bus_addr_t)BUS_SPACE_MAXADDR_40BIT, 574 BUS_SPACE_MAXADDR, NULL, NULL, ringsz, 1, ringsz, 0, NULL, NULL, 575 &ioat->hw_desc_tag); 576 if (error != 0) 577 return (error); 578 579 error = bus_dmamem_alloc(ioat->hw_desc_tag, &hw_desc, 580 BUS_DMA_ZERO | BUS_DMA_WAITOK, &ioat->hw_desc_map); 581 if (error != 0) 582 return (error); 583 584 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 585 ringsz, ioat_dmamap_cb, &ioat->hw_desc_bus_addr, BUS_DMA_WAITOK); 586 if (error) 587 return (error); 588 589 ioat->hw_desc_ring = hw_desc; 590 591 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 592 1, 0, BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL, 593 ioat->max_xfer_size, 1, ioat->max_xfer_size, 0, NULL, NULL, 594 &ioat->data_crc_tag); 595 if (error != 0) { 596 ioat_log_message(0, "%s: bus_dma_tag_create failed %d\n", 597 __func__, error); 598 return (error); 599 } 600 601 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 602 1, 0, BUS_SPACE_MAXADDR_48BIT, BUS_SPACE_MAXADDR, NULL, NULL, 603 ioat->max_xfer_size, 1, ioat->max_xfer_size, 0, NULL, NULL, 604 &ioat->data_tag); 605 if (error != 0) { 606 ioat_log_message(0, "%s: bus_dma_tag_create failed %d\n", 607 __func__, error); 608 return (error); 609 } 610 ioat->ring = malloc_domainset(num_descriptors * sizeof(*ring), M_IOAT, 611 DOMAINSET_PREF(ioat->domain), M_ZERO | M_WAITOK); 612 613 ring = ioat->ring; 614 for (i = 0; i < num_descriptors; i++) { 615 memset(&ring[i].bus_dmadesc, 0, sizeof(ring[i].bus_dmadesc)); 616 ring[i].id = i; 617 error = bus_dmamap_create(ioat->data_tag, 0, 618 &ring[i].src_dmamap); 619 if (error != 0) { 620 ioat_log_message(0, 621 "%s: bus_dmamap_create failed %d\n", __func__, 622 error); 623 return (error); 624 } 625 error = bus_dmamap_create(ioat->data_tag, 0, 626 &ring[i].dst_dmamap); 627 if (error != 0) { 628 ioat_log_message(0, 629 "%s: bus_dmamap_create failed %d\n", __func__, 630 error); 631 return (error); 632 } 633 error = bus_dmamap_create(ioat->data_tag, 0, 634 &ring[i].src2_dmamap); 635 if (error != 0) { 636 ioat_log_message(0, 637 "%s: bus_dmamap_create failed %d\n", __func__, 638 error); 639 return (error); 640 } 641 error = bus_dmamap_create(ioat->data_tag, 0, 642 &ring[i].dst2_dmamap); 643 if (error != 0) { 644 ioat_log_message(0, 645 "%s: bus_dmamap_create failed %d\n", __func__, 646 error); 647 return (error); 648 } 649 error = bus_dmamap_create(ioat->data_crc_tag, 0, 650 &ring[i].crc_dmamap); 651 if (error != 0) { 652 ioat_log_message(0, 653 "%s: bus_dmamap_create failed %d\n", __func__, 654 error); 655 return (error); 656 } 657 } 658 659 for (i = 0; i < num_descriptors; i++) { 660 dma_hw_desc = &ioat->hw_desc_ring[i].dma; 661 dma_hw_desc->next = RING_PHYS_ADDR(ioat, i + 1); 662 } 663 664 ioat->head = 0; 665 ioat->tail = 0; 666 ioat->last_seen = 0; 667 *ioat->comp_update = 0; 668 return (0); 669 } 670 671 static int 672 ioat_map_pci_bar(struct ioat_softc *ioat) 673 { 674 675 ioat->pci_resource_id = PCIR_BAR(0); 676 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 677 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 678 679 if (ioat->pci_resource == NULL) { 680 ioat_log_message(0, "unable to allocate pci resource\n"); 681 return (ENODEV); 682 } 683 684 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 685 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 686 return (0); 687 } 688 689 static void 690 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 691 { 692 struct ioat_softc *ioat = arg; 693 694 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 695 ioat->comp_update_bus_addr = seg[0].ds_addr; 696 } 697 698 static void 699 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 700 { 701 bus_addr_t *baddr; 702 703 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 704 baddr = arg; 705 *baddr = segs->ds_addr; 706 } 707 708 /* 709 * Interrupt setup and handlers 710 */ 711 static int 712 ioat_setup_intr(struct ioat_softc *ioat) 713 { 714 uint32_t num_vectors; 715 int error; 716 boolean_t use_msix; 717 boolean_t force_legacy_interrupts; 718 719 use_msix = FALSE; 720 force_legacy_interrupts = FALSE; 721 722 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 723 num_vectors = 1; 724 pci_alloc_msix(ioat->device, &num_vectors); 725 if (num_vectors == 1) 726 use_msix = TRUE; 727 } 728 729 if (use_msix) { 730 ioat->rid = 1; 731 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 732 &ioat->rid, RF_ACTIVE); 733 } else { 734 ioat->rid = 0; 735 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 736 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 737 } 738 if (ioat->res == NULL) { 739 ioat_log_message(0, "bus_alloc_resource failed\n"); 740 return (ENOMEM); 741 } 742 743 ioat->tag = NULL; 744 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 745 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 746 if (error != 0) { 747 ioat_log_message(0, "bus_setup_intr failed\n"); 748 return (error); 749 } 750 751 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 752 return (0); 753 } 754 755 static boolean_t 756 ioat_model_resets_msix(struct ioat_softc *ioat) 757 { 758 u_int32_t pciid; 759 760 pciid = pci_get_devid(ioat->device); 761 switch (pciid) { 762 /* BWD: */ 763 case 0x0c508086: 764 case 0x0c518086: 765 case 0x0c528086: 766 case 0x0c538086: 767 /* BDXDE: */ 768 case 0x6f508086: 769 case 0x6f518086: 770 case 0x6f528086: 771 case 0x6f538086: 772 return (TRUE); 773 } 774 775 return (FALSE); 776 } 777 778 static void 779 ioat_interrupt_handler(void *arg) 780 { 781 struct ioat_softc *ioat = arg; 782 783 ioat->stats.interrupts++; 784 ioat_process_events(ioat, TRUE); 785 } 786 787 static int 788 chanerr_to_errno(uint32_t chanerr) 789 { 790 791 if (chanerr == 0) 792 return (0); 793 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 794 return (EFAULT); 795 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 796 return (EIO); 797 /* This one is probably our fault: */ 798 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 799 return (EIO); 800 return (EIO); 801 } 802 803 static void 804 ioat_process_events(struct ioat_softc *ioat, boolean_t intr) 805 { 806 struct ioat_descriptor *desc; 807 struct bus_dmadesc *dmadesc; 808 uint64_t comp_update, status; 809 uint32_t completed, chanerr; 810 int error; 811 812 mtx_lock(&ioat->cleanup_lock); 813 814 /* 815 * Don't run while the hardware is being reset. Reset is responsible 816 * for blocking new work and draining & completing existing work, so 817 * there is nothing to do until new work is queued after reset anyway. 818 */ 819 if (ioat->resetting_cleanup) { 820 mtx_unlock(&ioat->cleanup_lock); 821 return; 822 } 823 824 completed = 0; 825 comp_update = *ioat->comp_update; 826 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 827 828 if (status < ioat->hw_desc_bus_addr || 829 status >= ioat->hw_desc_bus_addr + (1 << ioat->ring_size_order) * 830 sizeof(struct ioat_generic_hw_descriptor)) 831 panic("Bogus completion address %jx (channel %u)", 832 (uintmax_t)status, ioat->chan_idx); 833 834 if (status == ioat->last_seen) { 835 /* 836 * If we landed in process_events and nothing has been 837 * completed, check for a timeout due to channel halt. 838 */ 839 goto out; 840 } 841 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx", 842 __func__, ioat->chan_idx, comp_update, ioat->last_seen); 843 844 while (RING_PHYS_ADDR(ioat, ioat->tail - 1) != status) { 845 desc = ioat_get_ring_entry(ioat, ioat->tail); 846 dmadesc = &desc->bus_dmadesc; 847 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) ok cb %p(%p)", 848 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 849 dmadesc->callback_arg); 850 851 bus_dmamap_unload(ioat->data_tag, desc->src_dmamap); 852 bus_dmamap_unload(ioat->data_tag, desc->dst_dmamap); 853 bus_dmamap_unload(ioat->data_tag, desc->src2_dmamap); 854 bus_dmamap_unload(ioat->data_tag, desc->dst2_dmamap); 855 bus_dmamap_unload(ioat->data_crc_tag, desc->crc_dmamap); 856 857 if (dmadesc->callback_fn != NULL) 858 dmadesc->callback_fn(dmadesc->callback_arg, 0); 859 860 completed++; 861 ioat->tail++; 862 } 863 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 864 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 865 866 if (completed != 0) { 867 ioat->last_seen = RING_PHYS_ADDR(ioat, ioat->tail - 1); 868 ioat->stats.descriptors_processed += completed; 869 wakeup(&ioat->tail); 870 } 871 872 out: 873 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 874 mtx_unlock(&ioat->cleanup_lock); 875 876 /* 877 * The device doesn't seem to reliably push suspend/halt statuses to 878 * the channel completion memory address, so poll the device register 879 * here. For performance reasons skip it on interrupts, do it only 880 * on much more rare polling events. 881 */ 882 if (!intr) 883 comp_update = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 884 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 885 return; 886 887 ioat->stats.channel_halts++; 888 889 /* 890 * Fatal programming error on this DMA channel. Flush any outstanding 891 * work with error status and restart the engine. 892 */ 893 mtx_lock(&ioat->submit_lock); 894 ioat->quiescing = TRUE; 895 mtx_unlock(&ioat->submit_lock); 896 897 /* 898 * This is safe to do here because the submit queue is quiesced. We 899 * know that we will drain all outstanding events, so ioat_reset_hw 900 * can't deadlock. It is necessary to protect other ioat_process_event 901 * threads from racing ioat_reset_hw, reading an indeterminate hw 902 * state, and attempting to continue issuing completions. 903 */ 904 mtx_lock(&ioat->cleanup_lock); 905 ioat->resetting_cleanup = TRUE; 906 907 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 908 if (1 <= g_ioat_debug_level) 909 ioat_halted_debug(ioat, chanerr); 910 ioat->stats.last_halt_chanerr = chanerr; 911 912 while (ioat_get_active(ioat) > 0) { 913 desc = ioat_get_ring_entry(ioat, ioat->tail); 914 dmadesc = &desc->bus_dmadesc; 915 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) err cb %p(%p)", 916 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 917 dmadesc->callback_arg); 918 919 if (dmadesc->callback_fn != NULL) 920 dmadesc->callback_fn(dmadesc->callback_arg, 921 chanerr_to_errno(chanerr)); 922 923 ioat->tail++; 924 ioat->stats.descriptors_processed++; 925 ioat->stats.descriptors_error++; 926 } 927 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 928 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 929 930 /* Clear error status */ 931 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 932 933 mtx_unlock(&ioat->cleanup_lock); 934 935 ioat_log_message(0, "Resetting channel to recover from error\n"); 936 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 937 KASSERT(error == 0, 938 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 939 } 940 941 static void 942 ioat_reset_hw_task(void *ctx, int pending __unused) 943 { 944 struct ioat_softc *ioat; 945 int error; 946 947 ioat = ctx; 948 ioat_log_message(1, "%s: Resetting channel\n", __func__); 949 950 error = ioat_reset_hw(ioat); 951 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 952 (void)error; 953 } 954 955 /* 956 * User API functions 957 */ 958 unsigned 959 ioat_get_nchannels(void) 960 { 961 962 return (ioat_channel_index); 963 } 964 965 bus_dmaengine_t 966 ioat_get_dmaengine(uint32_t index, int flags) 967 { 968 struct ioat_softc *ioat; 969 970 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 971 ("invalid flags: 0x%08x", flags)); 972 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 973 ("invalid wait | nowait")); 974 975 mtx_lock(&ioat_list_mtx); 976 if (index >= ioat_channel_index || 977 (ioat = ioat_channel[index]) == NULL) { 978 mtx_unlock(&ioat_list_mtx); 979 return (NULL); 980 } 981 mtx_lock(&ioat->submit_lock); 982 mtx_unlock(&ioat_list_mtx); 983 984 if (ioat->destroying) { 985 mtx_unlock(&ioat->submit_lock); 986 return (NULL); 987 } 988 989 ioat_get(ioat); 990 if (ioat->quiescing) { 991 if ((flags & M_NOWAIT) != 0) { 992 ioat_put(ioat); 993 mtx_unlock(&ioat->submit_lock); 994 return (NULL); 995 } 996 997 while (ioat->quiescing && !ioat->destroying) 998 msleep(&ioat->quiescing, &ioat->submit_lock, 0, "getdma", 0); 999 1000 if (ioat->destroying) { 1001 ioat_put(ioat); 1002 mtx_unlock(&ioat->submit_lock); 1003 return (NULL); 1004 } 1005 } 1006 mtx_unlock(&ioat->submit_lock); 1007 return (&ioat->dmaengine); 1008 } 1009 1010 void 1011 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 1012 { 1013 struct ioat_softc *ioat; 1014 1015 ioat = to_ioat_softc(dmaengine); 1016 mtx_lock(&ioat->submit_lock); 1017 ioat_put(ioat); 1018 mtx_unlock(&ioat->submit_lock); 1019 } 1020 1021 int 1022 ioat_get_hwversion(bus_dmaengine_t dmaengine) 1023 { 1024 struct ioat_softc *ioat; 1025 1026 ioat = to_ioat_softc(dmaengine); 1027 return (ioat->version); 1028 } 1029 1030 size_t 1031 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 1032 { 1033 struct ioat_softc *ioat; 1034 1035 ioat = to_ioat_softc(dmaengine); 1036 return (ioat->max_xfer_size); 1037 } 1038 1039 uint32_t 1040 ioat_get_capabilities(bus_dmaengine_t dmaengine) 1041 { 1042 struct ioat_softc *ioat; 1043 1044 ioat = to_ioat_softc(dmaengine); 1045 return (ioat->capabilities); 1046 } 1047 1048 int 1049 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 1050 { 1051 struct ioat_softc *ioat; 1052 1053 ioat = to_ioat_softc(dmaengine); 1054 if (!ioat->intrdelay_supported) 1055 return (ENODEV); 1056 if (delay > ioat->intrdelay_max) 1057 return (ERANGE); 1058 1059 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 1060 ioat->cached_intrdelay = 1061 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 1062 return (0); 1063 } 1064 1065 uint16_t 1066 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 1067 { 1068 struct ioat_softc *ioat; 1069 1070 ioat = to_ioat_softc(dmaengine); 1071 return (ioat->intrdelay_max); 1072 } 1073 1074 void 1075 ioat_acquire(bus_dmaengine_t dmaengine) 1076 { 1077 struct ioat_softc *ioat; 1078 1079 ioat = to_ioat_softc(dmaengine); 1080 mtx_lock(&ioat->submit_lock); 1081 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1082 ioat->acq_head = ioat->head; 1083 } 1084 1085 int 1086 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 1087 { 1088 struct ioat_softc *ioat; 1089 int error; 1090 1091 ioat = to_ioat_softc(dmaengine); 1092 ioat_acquire(dmaengine); 1093 1094 error = ioat_reserve_space(ioat, n, mflags); 1095 if (error != 0) 1096 ioat_release(dmaengine); 1097 return (error); 1098 } 1099 1100 void 1101 ioat_release(bus_dmaengine_t dmaengine) 1102 { 1103 struct ioat_softc *ioat; 1104 1105 ioat = to_ioat_softc(dmaengine); 1106 CTR3(KTR_IOAT, "%s channel=%u dispatch1 head=%u", __func__, 1107 ioat->chan_idx, ioat->head); 1108 KFAIL_POINT_CODE(DEBUG_FP, ioat_release, /* do nothing */); 1109 CTR3(KTR_IOAT, "%s channel=%u dispatch2 head=%u", __func__, 1110 ioat->chan_idx, ioat->head); 1111 1112 if (ioat->acq_head != ioat->head) { 1113 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, 1114 (uint16_t)ioat->head); 1115 1116 if (!callout_pending(&ioat->poll_timer)) { 1117 callout_reset_on(&ioat->poll_timer, 1, 1118 ioat_poll_timer_callback, ioat, ioat->cpu); 1119 } 1120 } 1121 mtx_unlock(&ioat->submit_lock); 1122 } 1123 1124 static struct ioat_descriptor * 1125 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 1126 uint32_t size, uint64_t src, uint64_t dst, 1127 bus_dmaengine_callback_t callback_fn, void *callback_arg, 1128 uint32_t flags) 1129 { 1130 struct ioat_generic_hw_descriptor *hw_desc; 1131 struct ioat_descriptor *desc; 1132 bus_dma_segment_t seg; 1133 int mflags, nseg, error; 1134 1135 mtx_assert(&ioat->submit_lock, MA_OWNED); 1136 1137 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 1138 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 1139 if ((flags & DMA_NO_WAIT) != 0) 1140 mflags = M_NOWAIT; 1141 else 1142 mflags = M_WAITOK; 1143 1144 if (size > ioat->max_xfer_size) { 1145 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 1146 __func__, ioat->max_xfer_size, (unsigned)size); 1147 return (NULL); 1148 } 1149 1150 if (ioat_reserve_space(ioat, 1, mflags) != 0) 1151 return (NULL); 1152 1153 desc = ioat_get_ring_entry(ioat, ioat->head); 1154 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->generic; 1155 1156 hw_desc->u.control_raw = 0; 1157 hw_desc->u.control_generic.op = op; 1158 hw_desc->u.control_generic.completion_update = 1; 1159 1160 if ((flags & DMA_INT_EN) != 0) 1161 hw_desc->u.control_generic.int_enable = 1; 1162 if ((flags & DMA_FENCE) != 0) 1163 hw_desc->u.control_generic.fence = 1; 1164 1165 hw_desc->size = size; 1166 1167 if (src != 0) { 1168 nseg = -1; 1169 error = _bus_dmamap_load_phys(ioat->data_tag, desc->src_dmamap, 1170 src, size, 0, &seg, &nseg); 1171 if (error != 0) { 1172 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1173 " failed %d\n", __func__, error); 1174 return (NULL); 1175 } 1176 hw_desc->src_addr = seg.ds_addr; 1177 } 1178 1179 if (dst != 0) { 1180 nseg = -1; 1181 error = _bus_dmamap_load_phys(ioat->data_tag, desc->dst_dmamap, 1182 dst, size, 0, &seg, &nseg); 1183 if (error != 0) { 1184 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1185 " failed %d\n", __func__, error); 1186 return (NULL); 1187 } 1188 hw_desc->dest_addr = seg.ds_addr; 1189 } 1190 1191 desc->bus_dmadesc.callback_fn = callback_fn; 1192 desc->bus_dmadesc.callback_arg = callback_arg; 1193 return (desc); 1194 } 1195 1196 struct bus_dmadesc * 1197 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1198 void *callback_arg, uint32_t flags) 1199 { 1200 struct ioat_dma_hw_descriptor *hw_desc; 1201 struct ioat_descriptor *desc; 1202 struct ioat_softc *ioat; 1203 1204 ioat = to_ioat_softc(dmaengine); 1205 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1206 1207 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1208 callback_arg, flags); 1209 if (desc == NULL) 1210 return (NULL); 1211 1212 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1213 hw_desc->u.control.null = 1; 1214 ioat_submit_single(ioat); 1215 return (&desc->bus_dmadesc); 1216 } 1217 1218 struct bus_dmadesc * 1219 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1220 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1221 void *callback_arg, uint32_t flags) 1222 { 1223 struct ioat_dma_hw_descriptor *hw_desc; 1224 struct ioat_descriptor *desc; 1225 struct ioat_softc *ioat; 1226 1227 ioat = to_ioat_softc(dmaengine); 1228 1229 if (((src | dst) & (0xffffull << 48)) != 0) { 1230 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1231 __func__); 1232 return (NULL); 1233 } 1234 1235 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1236 callback_arg, flags); 1237 if (desc == NULL) 1238 return (NULL); 1239 1240 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1241 if (g_ioat_debug_level >= 3) 1242 dump_descriptor(hw_desc); 1243 1244 ioat_submit_single(ioat); 1245 CTR6(KTR_IOAT, "%s channel=%u desc=%p dest=%lx src=%lx len=%lx", 1246 __func__, ioat->chan_idx, &desc->bus_dmadesc, dst, src, len); 1247 return (&desc->bus_dmadesc); 1248 } 1249 1250 struct bus_dmadesc * 1251 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1252 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1253 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1254 { 1255 struct ioat_dma_hw_descriptor *hw_desc; 1256 struct ioat_descriptor *desc; 1257 struct ioat_softc *ioat; 1258 bus_size_t src1_len, dst1_len; 1259 bus_dma_segment_t seg; 1260 int nseg, error; 1261 1262 ioat = to_ioat_softc(dmaengine); 1263 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1264 1265 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 1266 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1267 __func__); 1268 return (NULL); 1269 } 1270 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 1271 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 1272 __func__); 1273 return (NULL); 1274 } 1275 1276 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, 0, 0, 1277 callback_fn, callback_arg, flags); 1278 if (desc == NULL) 1279 return (NULL); 1280 1281 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1282 1283 src1_len = (src2 != src1 + PAGE_SIZE) ? PAGE_SIZE : 2 * PAGE_SIZE; 1284 nseg = -1; 1285 error = _bus_dmamap_load_phys(ioat->data_tag, 1286 desc->src_dmamap, src1, src1_len, 0, &seg, &nseg); 1287 if (error != 0) { 1288 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1289 " failed %d\n", __func__, error); 1290 return (NULL); 1291 } 1292 hw_desc->src_addr = seg.ds_addr; 1293 if (src1_len != 2 * PAGE_SIZE) { 1294 hw_desc->u.control.src_page_break = 1; 1295 nseg = -1; 1296 error = _bus_dmamap_load_phys(ioat->data_tag, 1297 desc->src2_dmamap, src2, PAGE_SIZE, 0, &seg, &nseg); 1298 if (error != 0) { 1299 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1300 " failed %d\n", __func__, error); 1301 return (NULL); 1302 } 1303 hw_desc->next_src_addr = seg.ds_addr; 1304 } 1305 1306 dst1_len = (dst2 != dst1 + PAGE_SIZE) ? PAGE_SIZE : 2 * PAGE_SIZE; 1307 nseg = -1; 1308 error = _bus_dmamap_load_phys(ioat->data_tag, 1309 desc->dst_dmamap, dst1, dst1_len, 0, &seg, &nseg); 1310 if (error != 0) { 1311 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1312 " failed %d\n", __func__, error); 1313 return (NULL); 1314 } 1315 hw_desc->dest_addr = seg.ds_addr; 1316 if (dst1_len != 2 * PAGE_SIZE) { 1317 hw_desc->u.control.dest_page_break = 1; 1318 nseg = -1; 1319 error = _bus_dmamap_load_phys(ioat->data_tag, 1320 desc->dst2_dmamap, dst2, PAGE_SIZE, 0, &seg, &nseg); 1321 if (error != 0) { 1322 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1323 " failed %d\n", __func__, error); 1324 return (NULL); 1325 } 1326 hw_desc->next_dest_addr = seg.ds_addr; 1327 } 1328 1329 if (g_ioat_debug_level >= 3) 1330 dump_descriptor(hw_desc); 1331 1332 ioat_submit_single(ioat); 1333 return (&desc->bus_dmadesc); 1334 } 1335 1336 struct bus_dmadesc * 1337 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1338 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1339 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1340 { 1341 struct ioat_crc32_hw_descriptor *hw_desc; 1342 struct ioat_descriptor *desc; 1343 struct ioat_softc *ioat; 1344 uint32_t teststore; 1345 uint8_t op; 1346 bus_dma_segment_t seg; 1347 int nseg, error; 1348 1349 ioat = to_ioat_softc(dmaengine); 1350 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1351 1352 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1353 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1354 __func__); 1355 return (NULL); 1356 } 1357 if (((src | dst) & (0xffffffull << 40)) != 0) { 1358 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1359 __func__); 1360 return (NULL); 1361 } 1362 teststore = (flags & _DMA_CRC_TESTSTORE); 1363 if (teststore == _DMA_CRC_TESTSTORE) { 1364 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1365 return (NULL); 1366 } 1367 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1368 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1369 __func__); 1370 return (NULL); 1371 } 1372 1373 switch (teststore) { 1374 case DMA_CRC_STORE: 1375 op = IOAT_OP_MOVECRC_STORE; 1376 break; 1377 case DMA_CRC_TEST: 1378 op = IOAT_OP_MOVECRC_TEST; 1379 break; 1380 default: 1381 KASSERT(teststore == 0, ("bogus")); 1382 op = IOAT_OP_MOVECRC; 1383 break; 1384 } 1385 1386 if ((flags & DMA_CRC_INLINE) == 0 && 1387 (crcptr & (0xffffffull << 40)) != 0) { 1388 ioat_log_message(0, 1389 "%s: High 24 bits of crcptr invalid\n", __func__); 1390 return (NULL); 1391 } 1392 1393 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1394 callback_arg, flags & ~_DMA_CRC_FLAGS); 1395 if (desc == NULL) 1396 return (NULL); 1397 1398 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1399 1400 if ((flags & DMA_CRC_INLINE) == 0) { 1401 nseg = -1; 1402 error = _bus_dmamap_load_phys(ioat->data_crc_tag, 1403 desc->crc_dmamap, crcptr, sizeof(uint32_t), 0, 1404 &seg, &nseg); 1405 if (error != 0) { 1406 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1407 " failed %d\n", __func__, error); 1408 return (NULL); 1409 } 1410 hw_desc->crc_address = seg.ds_addr; 1411 } else 1412 hw_desc->u.control.crc_location = 1; 1413 1414 if (initialseed != NULL) { 1415 hw_desc->u.control.use_seed = 1; 1416 hw_desc->seed = *initialseed; 1417 } 1418 1419 if (g_ioat_debug_level >= 3) 1420 dump_descriptor(hw_desc); 1421 1422 ioat_submit_single(ioat); 1423 return (&desc->bus_dmadesc); 1424 } 1425 1426 struct bus_dmadesc * 1427 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1428 uint32_t *initialseed, bus_addr_t crcptr, 1429 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1430 { 1431 struct ioat_crc32_hw_descriptor *hw_desc; 1432 struct ioat_descriptor *desc; 1433 struct ioat_softc *ioat; 1434 uint32_t teststore; 1435 uint8_t op; 1436 bus_dma_segment_t seg; 1437 int nseg, error; 1438 1439 ioat = to_ioat_softc(dmaengine); 1440 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1441 1442 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1443 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1444 __func__); 1445 return (NULL); 1446 } 1447 if ((src & (0xffffffull << 40)) != 0) { 1448 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1449 __func__); 1450 return (NULL); 1451 } 1452 teststore = (flags & _DMA_CRC_TESTSTORE); 1453 if (teststore == _DMA_CRC_TESTSTORE) { 1454 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1455 return (NULL); 1456 } 1457 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1458 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1459 __func__); 1460 return (NULL); 1461 } 1462 1463 switch (teststore) { 1464 case DMA_CRC_STORE: 1465 op = IOAT_OP_CRC_STORE; 1466 break; 1467 case DMA_CRC_TEST: 1468 op = IOAT_OP_CRC_TEST; 1469 break; 1470 default: 1471 KASSERT(teststore == 0, ("bogus")); 1472 op = IOAT_OP_CRC; 1473 break; 1474 } 1475 1476 if ((flags & DMA_CRC_INLINE) == 0 && 1477 (crcptr & (0xffffffull << 40)) != 0) { 1478 ioat_log_message(0, 1479 "%s: High 24 bits of crcptr invalid\n", __func__); 1480 return (NULL); 1481 } 1482 1483 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1484 callback_arg, flags & ~_DMA_CRC_FLAGS); 1485 if (desc == NULL) 1486 return (NULL); 1487 1488 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1489 1490 if ((flags & DMA_CRC_INLINE) == 0) { 1491 nseg = -1; 1492 error = _bus_dmamap_load_phys(ioat->data_crc_tag, 1493 desc->crc_dmamap, crcptr, sizeof(uint32_t), 0, 1494 &seg, &nseg); 1495 if (error != 0) { 1496 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1497 " failed %d\n", __func__, error); 1498 return (NULL); 1499 } 1500 hw_desc->crc_address = seg.ds_addr; 1501 } else 1502 hw_desc->u.control.crc_location = 1; 1503 1504 if (initialseed != NULL) { 1505 hw_desc->u.control.use_seed = 1; 1506 hw_desc->seed = *initialseed; 1507 } 1508 1509 if (g_ioat_debug_level >= 3) 1510 dump_descriptor(hw_desc); 1511 1512 ioat_submit_single(ioat); 1513 return (&desc->bus_dmadesc); 1514 } 1515 1516 struct bus_dmadesc * 1517 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1518 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1519 uint32_t flags) 1520 { 1521 struct ioat_fill_hw_descriptor *hw_desc; 1522 struct ioat_descriptor *desc; 1523 struct ioat_softc *ioat; 1524 1525 ioat = to_ioat_softc(dmaengine); 1526 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1527 1528 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1529 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1530 __func__); 1531 return (NULL); 1532 } 1533 1534 if ((dst & (0xffffull << 48)) != 0) { 1535 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1536 __func__); 1537 return (NULL); 1538 } 1539 1540 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, 0, dst, 1541 callback_fn, callback_arg, flags); 1542 if (desc == NULL) 1543 return (NULL); 1544 1545 hw_desc = &ioat_get_descriptor(ioat, desc->id)->fill; 1546 hw_desc->src_data = fillpattern; 1547 if (g_ioat_debug_level >= 3) 1548 dump_descriptor(hw_desc); 1549 1550 ioat_submit_single(ioat); 1551 return (&desc->bus_dmadesc); 1552 } 1553 1554 /* 1555 * Ring Management 1556 */ 1557 static inline uint32_t 1558 ioat_get_active(struct ioat_softc *ioat) 1559 { 1560 1561 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1562 } 1563 1564 static inline uint32_t 1565 ioat_get_ring_space(struct ioat_softc *ioat) 1566 { 1567 1568 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1569 } 1570 1571 /* 1572 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1573 * for 'num_descs'. 1574 * 1575 * If mflags contains M_WAITOK, blocks until enough space is available. 1576 * 1577 * Returns zero on success, or an errno on error. If num_descs is beyond the 1578 * maximum ring size, returns EINVAl; if allocation would block and mflags 1579 * contains M_NOWAIT, returns EAGAIN. 1580 * 1581 * Must be called with the submit_lock held; returns with the lock held. The 1582 * lock may be dropped to allocate the ring. 1583 * 1584 * (The submit_lock is needed to add any entries to the ring, so callers are 1585 * assured enough room is available.) 1586 */ 1587 static int 1588 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1589 { 1590 boolean_t dug; 1591 int error; 1592 1593 mtx_assert(&ioat->submit_lock, MA_OWNED); 1594 error = 0; 1595 dug = FALSE; 1596 1597 if (num_descs < 1 || num_descs >= (1 << ioat->ring_size_order)) { 1598 error = EINVAL; 1599 goto out; 1600 } 1601 1602 for (;;) { 1603 if (ioat->quiescing) { 1604 error = ENXIO; 1605 goto out; 1606 } 1607 1608 if (ioat_get_ring_space(ioat) >= num_descs) 1609 goto out; 1610 1611 CTR3(KTR_IOAT, "%s channel=%u starved (%u)", __func__, 1612 ioat->chan_idx, num_descs); 1613 1614 if (!dug && !ioat->is_submitter_processing) { 1615 ioat->is_submitter_processing = TRUE; 1616 mtx_unlock(&ioat->submit_lock); 1617 1618 CTR2(KTR_IOAT, "%s channel=%u attempting to process events", 1619 __func__, ioat->chan_idx); 1620 ioat_process_events(ioat, FALSE); 1621 1622 mtx_lock(&ioat->submit_lock); 1623 dug = TRUE; 1624 KASSERT(ioat->is_submitter_processing == TRUE, 1625 ("is_submitter_processing")); 1626 ioat->is_submitter_processing = FALSE; 1627 wakeup(&ioat->tail); 1628 continue; 1629 } 1630 1631 if ((mflags & M_WAITOK) == 0) { 1632 error = EAGAIN; 1633 break; 1634 } 1635 CTR2(KTR_IOAT, "%s channel=%u blocking on completions", 1636 __func__, ioat->chan_idx); 1637 msleep(&ioat->tail, &ioat->submit_lock, 0, 1638 "ioat_full", 0); 1639 continue; 1640 } 1641 1642 out: 1643 mtx_assert(&ioat->submit_lock, MA_OWNED); 1644 KASSERT(!ioat->quiescing || error == ENXIO, 1645 ("reserved during quiesce")); 1646 return (error); 1647 } 1648 1649 static void 1650 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1651 struct ioat_descriptor *ring) 1652 { 1653 1654 free_domain(ring, M_IOAT); 1655 } 1656 1657 static struct ioat_descriptor * 1658 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1659 { 1660 1661 return (&ioat->ring[index % (1 << ioat->ring_size_order)]); 1662 } 1663 1664 static union ioat_hw_descriptor * 1665 ioat_get_descriptor(struct ioat_softc *ioat, uint32_t index) 1666 { 1667 1668 return (&ioat->hw_desc_ring[index % (1 << ioat->ring_size_order)]); 1669 } 1670 1671 static void 1672 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1673 { 1674 union ioat_hw_descriptor *desc; 1675 1676 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1677 IOAT_CHANERR_STR); 1678 if (chanerr == 0) 1679 return; 1680 1681 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1682 1683 desc = ioat_get_descriptor(ioat, ioat->tail + 0); 1684 dump_descriptor(desc); 1685 1686 desc = ioat_get_descriptor(ioat, ioat->tail + 1); 1687 dump_descriptor(desc); 1688 } 1689 1690 static void 1691 ioat_poll_timer_callback(void *arg) 1692 { 1693 struct ioat_softc *ioat; 1694 1695 ioat = arg; 1696 ioat_log_message(3, "%s\n", __func__); 1697 1698 ioat_process_events(ioat, FALSE); 1699 1700 mtx_lock(&ioat->submit_lock); 1701 if (ioat_get_active(ioat) > 0) 1702 callout_schedule(&ioat->poll_timer, 1); 1703 mtx_unlock(&ioat->submit_lock); 1704 } 1705 1706 /* 1707 * Support Functions 1708 */ 1709 static void 1710 ioat_submit_single(struct ioat_softc *ioat) 1711 { 1712 1713 mtx_assert(&ioat->submit_lock, MA_OWNED); 1714 1715 ioat->head++; 1716 CTR4(KTR_IOAT, "%s channel=%u head=%u tail=%u", __func__, 1717 ioat->chan_idx, ioat->head, ioat->tail); 1718 1719 ioat->stats.descriptors_submitted++; 1720 } 1721 1722 static int 1723 ioat_reset_hw(struct ioat_softc *ioat) 1724 { 1725 uint64_t status; 1726 uint32_t chanerr; 1727 unsigned timeout; 1728 int error; 1729 1730 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1731 1732 mtx_lock(&ioat->submit_lock); 1733 while (ioat->resetting && !ioat->destroying) 1734 msleep(&ioat->resetting, &ioat->submit_lock, 0, "IRH_drain", 0); 1735 if (ioat->destroying) { 1736 mtx_unlock(&ioat->submit_lock); 1737 return (ENXIO); 1738 } 1739 ioat->resetting = TRUE; 1740 ioat->quiescing = TRUE; 1741 mtx_unlock(&ioat->submit_lock); 1742 mtx_lock(&ioat->cleanup_lock); 1743 while (ioat_get_active(ioat) > 0) 1744 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1); 1745 1746 /* 1747 * Suspend ioat_process_events while the hardware and softc are in an 1748 * indeterminate state. 1749 */ 1750 ioat->resetting_cleanup = TRUE; 1751 mtx_unlock(&ioat->cleanup_lock); 1752 1753 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__, 1754 ioat->chan_idx); 1755 1756 status = ioat_get_chansts(ioat); 1757 if (is_ioat_active(status) || is_ioat_idle(status)) 1758 ioat_suspend(ioat); 1759 1760 /* Wait at most 20 ms */ 1761 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1762 timeout < 20; timeout++) { 1763 DELAY(1000); 1764 status = ioat_get_chansts(ioat); 1765 } 1766 if (timeout == 20) { 1767 error = ETIMEDOUT; 1768 goto out; 1769 } 1770 1771 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1772 1773 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1774 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1775 1776 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__, 1777 ioat->chan_idx); 1778 1779 /* 1780 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1781 * that can cause stability issues for IOAT v3. 1782 */ 1783 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1784 4); 1785 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1786 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1787 1788 /* 1789 * BDXDE and BWD models reset MSI-X registers on device reset. 1790 * Save/restore their contents manually. 1791 */ 1792 if (ioat_model_resets_msix(ioat)) { 1793 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1794 pci_save_state(ioat->device); 1795 } 1796 1797 ioat_reset(ioat); 1798 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__, 1799 ioat->chan_idx); 1800 1801 /* Wait at most 20 ms */ 1802 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1803 DELAY(1000); 1804 if (timeout == 20) { 1805 error = ETIMEDOUT; 1806 goto out; 1807 } 1808 1809 if (ioat_model_resets_msix(ioat)) { 1810 ioat_log_message(1, "device resets registers; restored\n"); 1811 pci_restore_state(ioat->device); 1812 } 1813 1814 /* Reset attempts to return the hardware to "halted." */ 1815 status = ioat_get_chansts(ioat); 1816 if (is_ioat_active(status) || is_ioat_idle(status)) { 1817 /* So this really shouldn't happen... */ 1818 ioat_log_message(0, "Device is active after a reset?\n"); 1819 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1820 error = 0; 1821 goto out; 1822 } 1823 1824 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1825 if (chanerr != 0) { 1826 mtx_lock(&ioat->cleanup_lock); 1827 ioat_halted_debug(ioat, chanerr); 1828 mtx_unlock(&ioat->cleanup_lock); 1829 error = EIO; 1830 goto out; 1831 } 1832 1833 /* 1834 * Bring device back online after reset. Writing CHAINADDR brings the 1835 * device back to active. 1836 * 1837 * The internal ring counter resets to zero, so we have to start over 1838 * at zero as well. 1839 */ 1840 ioat->tail = ioat->head = 0; 1841 ioat->last_seen = 0; 1842 *ioat->comp_update = 0; 1843 1844 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1845 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1846 ioat_write_chainaddr(ioat, RING_PHYS_ADDR(ioat, 0)); 1847 error = 0; 1848 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__, 1849 ioat->chan_idx); 1850 1851 out: 1852 /* Enqueues a null operation and ensures it completes. */ 1853 if (error == 0) { 1854 error = ioat_start_channel(ioat); 1855 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__, 1856 ioat->chan_idx); 1857 } 1858 1859 /* 1860 * Resume completions now that ring state is consistent. 1861 */ 1862 mtx_lock(&ioat->cleanup_lock); 1863 ioat->resetting_cleanup = FALSE; 1864 mtx_unlock(&ioat->cleanup_lock); 1865 1866 /* Unblock submission of new work */ 1867 mtx_lock(&ioat->submit_lock); 1868 ioat->quiescing = FALSE; 1869 wakeup(&ioat->quiescing); 1870 1871 ioat->resetting = FALSE; 1872 wakeup(&ioat->resetting); 1873 1874 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx); 1875 mtx_unlock(&ioat->submit_lock); 1876 1877 return (error); 1878 } 1879 1880 static int 1881 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1882 { 1883 struct ioat_softc *ioat; 1884 struct sbuf sb; 1885 uint64_t status; 1886 int error; 1887 1888 ioat = arg1; 1889 1890 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1891 1892 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1893 switch (status) { 1894 case IOAT_CHANSTS_ACTIVE: 1895 sbuf_printf(&sb, "ACTIVE"); 1896 break; 1897 case IOAT_CHANSTS_IDLE: 1898 sbuf_printf(&sb, "IDLE"); 1899 break; 1900 case IOAT_CHANSTS_SUSPENDED: 1901 sbuf_printf(&sb, "SUSPENDED"); 1902 break; 1903 case IOAT_CHANSTS_HALTED: 1904 sbuf_printf(&sb, "HALTED"); 1905 break; 1906 case IOAT_CHANSTS_ARMED: 1907 sbuf_printf(&sb, "ARMED"); 1908 break; 1909 default: 1910 sbuf_printf(&sb, "UNKNOWN"); 1911 break; 1912 } 1913 error = sbuf_finish(&sb); 1914 sbuf_delete(&sb); 1915 1916 if (error != 0 || req->newptr == NULL) 1917 return (error); 1918 return (EINVAL); 1919 } 1920 1921 static int 1922 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1923 { 1924 struct ioat_softc *ioat; 1925 struct sbuf sb; 1926 #define PRECISION "1" 1927 const uintmax_t factor = 10; 1928 uintmax_t rate; 1929 int error; 1930 1931 ioat = arg1; 1932 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1933 1934 if (ioat->stats.interrupts == 0) { 1935 sbuf_printf(&sb, "NaN"); 1936 goto out; 1937 } 1938 rate = ioat->stats.descriptors_processed * factor / 1939 ioat->stats.interrupts; 1940 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1941 rate % factor); 1942 #undef PRECISION 1943 out: 1944 error = sbuf_finish(&sb); 1945 sbuf_delete(&sb); 1946 if (error != 0 || req->newptr == NULL) 1947 return (error); 1948 return (EINVAL); 1949 } 1950 1951 static int 1952 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1953 { 1954 struct ioat_softc *ioat; 1955 int error, arg; 1956 1957 ioat = arg1; 1958 1959 arg = 0; 1960 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1961 if (error != 0 || req->newptr == NULL) 1962 return (error); 1963 1964 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1965 if (error != 0) 1966 return (error); 1967 1968 if (arg != 0) 1969 error = ioat_reset_hw(ioat); 1970 1971 return (error); 1972 } 1973 1974 static void 1975 dump_descriptor(void *hw_desc) 1976 { 1977 int i, j; 1978 1979 for (i = 0; i < 2; i++) { 1980 for (j = 0; j < 8; j++) 1981 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1982 printf("\n"); 1983 } 1984 } 1985 1986 static void 1987 ioat_setup_sysctl(device_t device) 1988 { 1989 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1990 struct sysctl_ctx_list *ctx; 1991 struct sysctl_oid *tree, *tmp; 1992 struct ioat_softc *ioat; 1993 1994 ioat = DEVICE2SOFTC(device); 1995 ctx = device_get_sysctl_ctx(device); 1996 tree = device_get_sysctl_tree(device); 1997 par = SYSCTL_CHILDREN(tree); 1998 1999 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 2000 &ioat->version, 0, "HW version (0xMM form)"); 2001 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 2002 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 2003 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 2004 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 2005 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 2006 &ioat->intrdelay_max, 0, 2007 "Maximum configurable INTRDELAY on this channel (microseconds)"); 2008 2009 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 2010 "IOAT channel internal state"); 2011 state = SYSCTL_CHILDREN(tmp); 2012 2013 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 2014 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 2015 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 2016 0, "SW descriptor head pointer index"); 2017 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 2018 0, "SW descriptor tail pointer index"); 2019 2020 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 2021 ioat->comp_update, "HW addr of last completion"); 2022 2023 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 2024 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 2025 "submitter processing"); 2026 2027 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 2028 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 2029 "String of the channel status"); 2030 2031 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 2032 &ioat->cached_intrdelay, 0, 2033 "Current INTRDELAY on this channel (cached, microseconds)"); 2034 2035 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 2036 "Big hammers (mostly for testing)"); 2037 hammer = SYSCTL_CHILDREN(tmp); 2038 2039 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 2040 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 2041 "Set to non-zero to reset the hardware"); 2042 2043 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 2044 "IOAT channel statistics"); 2045 statpar = SYSCTL_CHILDREN(tmp); 2046 2047 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 2048 &ioat->stats.interrupts, 2049 "Number of interrupts processed on this channel"); 2050 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 2051 &ioat->stats.descriptors_processed, 2052 "Number of descriptors processed on this channel"); 2053 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 2054 &ioat->stats.descriptors_submitted, 2055 "Number of descriptors submitted to this channel"); 2056 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 2057 &ioat->stats.descriptors_error, 2058 "Number of descriptors failed by channel errors"); 2059 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 2060 &ioat->stats.channel_halts, 0, 2061 "Number of times the channel has halted"); 2062 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 2063 &ioat->stats.last_halt_chanerr, 0, 2064 "The raw CHANERR when the channel was last halted"); 2065 2066 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 2067 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 2068 "Descriptors per interrupt"); 2069 } 2070 2071 static void 2072 ioat_get(struct ioat_softc *ioat) 2073 { 2074 2075 mtx_assert(&ioat->submit_lock, MA_OWNED); 2076 KASSERT(ioat->refcnt < UINT32_MAX, ("refcnt overflow")); 2077 2078 ioat->refcnt++; 2079 } 2080 2081 static void 2082 ioat_put(struct ioat_softc *ioat) 2083 { 2084 2085 mtx_assert(&ioat->submit_lock, MA_OWNED); 2086 KASSERT(ioat->refcnt >= 1, ("refcnt error")); 2087 2088 if (--ioat->refcnt == 0) 2089 wakeup(&ioat->refcnt); 2090 } 2091 2092 static void 2093 ioat_drain_locked(struct ioat_softc *ioat) 2094 { 2095 2096 mtx_assert(&ioat->submit_lock, MA_OWNED); 2097 2098 while (ioat->refcnt > 0) 2099 msleep(&ioat->refcnt, &ioat->submit_lock, 0, "ioat_drain", 0); 2100 } 2101 2102 #ifdef DDB 2103 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 2104 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 2105 DB_SHOW_COMMAND(ioat, db_show_ioat) 2106 { 2107 struct ioat_softc *sc; 2108 unsigned idx; 2109 2110 if (!have_addr) 2111 goto usage; 2112 idx = (unsigned)addr; 2113 if (idx >= ioat_channel_index) 2114 goto usage; 2115 2116 sc = ioat_channel[idx]; 2117 db_printf("ioat softc at %p\n", sc); 2118 if (sc == NULL) 2119 return; 2120 2121 db_printf(" version: %d\n", sc->version); 2122 db_printf(" chan_idx: %u\n", sc->chan_idx); 2123 db_printf(" submit_lock: "); 2124 db_show_lock(&sc->submit_lock); 2125 2126 db_printf(" capabilities: %b\n", (int)sc->capabilities, 2127 IOAT_DMACAP_STR); 2128 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 2129 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 2130 2131 db_printf(" poll_timer:\n"); 2132 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 2133 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 2134 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 2135 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 2136 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 2137 2138 db_printf(" quiescing: %d\n", (int)sc->quiescing); 2139 db_printf(" destroying: %d\n", (int)sc->destroying); 2140 db_printf(" is_submitter_processing: %d\n", 2141 (int)sc->is_submitter_processing); 2142 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 2143 db_printf(" resetting: %d\n", (int)sc->resetting); 2144 2145 db_printf(" head: %u\n", sc->head); 2146 db_printf(" tail: %u\n", sc->tail); 2147 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2148 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2149 db_printf(" ring: %p\n", sc->ring); 2150 db_printf(" descriptors: %p\n", sc->hw_desc_ring); 2151 db_printf(" descriptors (phys): 0x%jx\n", 2152 (uintmax_t)sc->hw_desc_bus_addr); 2153 2154 db_printf(" ring[%u] (tail):\n", sc->tail % 2155 (1 << sc->ring_size_order)); 2156 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 2157 db_printf(" addr: 0x%lx\n", 2158 RING_PHYS_ADDR(sc, sc->tail)); 2159 db_printf(" next: 0x%lx\n", 2160 ioat_get_descriptor(sc, sc->tail)->generic.next); 2161 2162 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 2163 (1 << sc->ring_size_order)); 2164 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 2165 db_printf(" addr: 0x%lx\n", 2166 RING_PHYS_ADDR(sc, sc->head - 1)); 2167 db_printf(" next: 0x%lx\n", 2168 ioat_get_descriptor(sc, sc->head - 1)->generic.next); 2169 2170 db_printf(" ring[%u] (head):\n", (sc->head) % 2171 (1 << sc->ring_size_order)); 2172 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2173 db_printf(" addr: 0x%lx\n", 2174 RING_PHYS_ADDR(sc, sc->head)); 2175 db_printf(" next: 0x%lx\n", 2176 ioat_get_descriptor(sc, sc->head)->generic.next); 2177 2178 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2179 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2180 == RING_PHYS_ADDR(sc, idx)) 2181 db_printf(" ring[%u] == hardware tail\n", idx); 2182 2183 db_printf(" cleanup_lock: "); 2184 db_show_lock(&sc->cleanup_lock); 2185 2186 db_printf(" refcnt: %u\n", sc->refcnt); 2187 db_printf(" stats:\n"); 2188 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2189 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2190 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2191 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2192 2193 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2194 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2195 2196 if (db_pager_quit) 2197 return; 2198 2199 db_printf(" hw status:\n"); 2200 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2201 db_printf(" chanctrl: 0x%x\n", 2202 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2203 db_printf(" chancmd: 0x%x\n", 2204 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2205 db_printf(" dmacount: 0x%x\n", 2206 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2207 db_printf(" chainaddr: 0x%lx\n", 2208 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2209 db_printf(" chancmp: 0x%lx\n", 2210 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2211 db_printf(" chanerr: %b\n", 2212 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2213 return; 2214 usage: 2215 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2216 return; 2217 } 2218 #endif /* DDB */ 2219