1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ddb.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/fail.h> 37 #include <sys/ioccom.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/sbuf.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 #include <sys/time.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <machine/stdarg.h> 53 54 #ifdef DDB 55 #include <ddb/ddb.h> 56 #endif 57 58 #include "ioat.h" 59 #include "ioat_hw.h" 60 #include "ioat_internal.h" 61 62 #ifndef BUS_SPACE_MAXADDR_40BIT 63 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 64 #endif 65 #define IOAT_REFLK (&ioat->submit_lock) 66 67 static int ioat_probe(device_t device); 68 static int ioat_attach(device_t device); 69 static int ioat_detach(device_t device); 70 static int ioat_setup_intr(struct ioat_softc *ioat); 71 static int ioat_teardown_intr(struct ioat_softc *ioat); 72 static int ioat3_attach(device_t device); 73 static int ioat_start_channel(struct ioat_softc *ioat); 74 static int ioat_map_pci_bar(struct ioat_softc *ioat); 75 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 76 int error); 77 static void ioat_interrupt_handler(void *arg); 78 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 79 static int chanerr_to_errno(uint32_t); 80 static void ioat_process_events(struct ioat_softc *ioat); 81 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 82 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 83 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 84 struct ioat_descriptor *); 85 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 86 static union ioat_hw_descriptor *ioat_get_descriptor(struct ioat_softc *, 87 uint32_t index); 88 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *, 89 uint32_t index); 90 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 91 static void ioat_poll_timer_callback(void *arg); 92 static void dump_descriptor(void *hw_desc); 93 static void ioat_submit_single(struct ioat_softc *ioat); 94 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 95 int error); 96 static int ioat_reset_hw(struct ioat_softc *ioat); 97 static void ioat_reset_hw_task(void *, int); 98 static void ioat_setup_sysctl(device_t device); 99 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 100 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 101 enum ioat_ref_kind); 102 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 103 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 104 enum ioat_ref_kind, boolean_t); 105 static inline void ioat_putn(struct ioat_softc *, uint32_t, 106 enum ioat_ref_kind); 107 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 108 enum ioat_ref_kind); 109 static void ioat_drain_locked(struct ioat_softc *); 110 111 #define ioat_log_message(v, ...) do { \ 112 if ((v) <= g_ioat_debug_level) { \ 113 device_printf(ioat->device, __VA_ARGS__); \ 114 } \ 115 } while (0) 116 117 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 118 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 119 120 static int g_force_legacy_interrupts; 121 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 122 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 123 124 int g_ioat_debug_level = 0; 125 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 126 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 127 128 unsigned g_ioat_ring_order = 13; 129 SYSCTL_UINT(_hw_ioat, OID_AUTO, ring_order, CTLFLAG_RDTUN, &g_ioat_ring_order, 130 0, "Set IOAT ring order. (1 << this) == ring size."); 131 132 /* 133 * OS <-> Driver interface structures 134 */ 135 static device_method_t ioat_pci_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, ioat_probe), 138 DEVMETHOD(device_attach, ioat_attach), 139 DEVMETHOD(device_detach, ioat_detach), 140 DEVMETHOD_END 141 }; 142 143 static driver_t ioat_pci_driver = { 144 "ioat", 145 ioat_pci_methods, 146 sizeof(struct ioat_softc), 147 }; 148 149 static devclass_t ioat_devclass; 150 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 151 MODULE_VERSION(ioat, 1); 152 153 /* 154 * Private data structures 155 */ 156 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 157 static unsigned ioat_channel_index = 0; 158 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 159 "Number of IOAT channels attached"); 160 161 static struct _pcsid 162 { 163 u_int32_t type; 164 const char *desc; 165 } pci_ids[] = { 166 { 0x34308086, "TBG IOAT Ch0" }, 167 { 0x34318086, "TBG IOAT Ch1" }, 168 { 0x34328086, "TBG IOAT Ch2" }, 169 { 0x34338086, "TBG IOAT Ch3" }, 170 { 0x34298086, "TBG IOAT Ch4" }, 171 { 0x342a8086, "TBG IOAT Ch5" }, 172 { 0x342b8086, "TBG IOAT Ch6" }, 173 { 0x342c8086, "TBG IOAT Ch7" }, 174 175 { 0x37108086, "JSF IOAT Ch0" }, 176 { 0x37118086, "JSF IOAT Ch1" }, 177 { 0x37128086, "JSF IOAT Ch2" }, 178 { 0x37138086, "JSF IOAT Ch3" }, 179 { 0x37148086, "JSF IOAT Ch4" }, 180 { 0x37158086, "JSF IOAT Ch5" }, 181 { 0x37168086, "JSF IOAT Ch6" }, 182 { 0x37178086, "JSF IOAT Ch7" }, 183 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 184 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 185 186 { 0x3c208086, "SNB IOAT Ch0" }, 187 { 0x3c218086, "SNB IOAT Ch1" }, 188 { 0x3c228086, "SNB IOAT Ch2" }, 189 { 0x3c238086, "SNB IOAT Ch3" }, 190 { 0x3c248086, "SNB IOAT Ch4" }, 191 { 0x3c258086, "SNB IOAT Ch5" }, 192 { 0x3c268086, "SNB IOAT Ch6" }, 193 { 0x3c278086, "SNB IOAT Ch7" }, 194 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 195 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 196 197 { 0x0e208086, "IVB IOAT Ch0" }, 198 { 0x0e218086, "IVB IOAT Ch1" }, 199 { 0x0e228086, "IVB IOAT Ch2" }, 200 { 0x0e238086, "IVB IOAT Ch3" }, 201 { 0x0e248086, "IVB IOAT Ch4" }, 202 { 0x0e258086, "IVB IOAT Ch5" }, 203 { 0x0e268086, "IVB IOAT Ch6" }, 204 { 0x0e278086, "IVB IOAT Ch7" }, 205 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 206 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 207 208 { 0x2f208086, "HSW IOAT Ch0" }, 209 { 0x2f218086, "HSW IOAT Ch1" }, 210 { 0x2f228086, "HSW IOAT Ch2" }, 211 { 0x2f238086, "HSW IOAT Ch3" }, 212 { 0x2f248086, "HSW IOAT Ch4" }, 213 { 0x2f258086, "HSW IOAT Ch5" }, 214 { 0x2f268086, "HSW IOAT Ch6" }, 215 { 0x2f278086, "HSW IOAT Ch7" }, 216 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 217 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 218 219 { 0x0c508086, "BWD IOAT Ch0" }, 220 { 0x0c518086, "BWD IOAT Ch1" }, 221 { 0x0c528086, "BWD IOAT Ch2" }, 222 { 0x0c538086, "BWD IOAT Ch3" }, 223 224 { 0x6f508086, "BDXDE IOAT Ch0" }, 225 { 0x6f518086, "BDXDE IOAT Ch1" }, 226 { 0x6f528086, "BDXDE IOAT Ch2" }, 227 { 0x6f538086, "BDXDE IOAT Ch3" }, 228 229 { 0x6f208086, "BDX IOAT Ch0" }, 230 { 0x6f218086, "BDX IOAT Ch1" }, 231 { 0x6f228086, "BDX IOAT Ch2" }, 232 { 0x6f238086, "BDX IOAT Ch3" }, 233 { 0x6f248086, "BDX IOAT Ch4" }, 234 { 0x6f258086, "BDX IOAT Ch5" }, 235 { 0x6f268086, "BDX IOAT Ch6" }, 236 { 0x6f278086, "BDX IOAT Ch7" }, 237 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 238 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 239 240 { 0x00000000, NULL } 241 }; 242 243 /* 244 * OS <-> Driver linkage functions 245 */ 246 static int 247 ioat_probe(device_t device) 248 { 249 struct _pcsid *ep; 250 u_int32_t type; 251 252 type = pci_get_devid(device); 253 for (ep = pci_ids; ep->type; ep++) { 254 if (ep->type == type) { 255 device_set_desc(device, ep->desc); 256 return (0); 257 } 258 } 259 return (ENXIO); 260 } 261 262 static int 263 ioat_attach(device_t device) 264 { 265 struct ioat_softc *ioat; 266 int error; 267 268 ioat = DEVICE2SOFTC(device); 269 ioat->device = device; 270 271 error = ioat_map_pci_bar(ioat); 272 if (error != 0) 273 goto err; 274 275 ioat->version = ioat_read_cbver(ioat); 276 if (ioat->version < IOAT_VER_3_0) { 277 error = ENODEV; 278 goto err; 279 } 280 281 error = ioat3_attach(device); 282 if (error != 0) 283 goto err; 284 285 error = pci_enable_busmaster(device); 286 if (error != 0) 287 goto err; 288 289 error = ioat_setup_intr(ioat); 290 if (error != 0) 291 goto err; 292 293 error = ioat_reset_hw(ioat); 294 if (error != 0) 295 goto err; 296 297 ioat_process_events(ioat); 298 ioat_setup_sysctl(device); 299 300 ioat->chan_idx = ioat_channel_index; 301 ioat_channel[ioat_channel_index++] = ioat; 302 ioat_test_attach(); 303 304 err: 305 if (error != 0) 306 ioat_detach(device); 307 return (error); 308 } 309 310 static int 311 ioat_detach(device_t device) 312 { 313 struct ioat_softc *ioat; 314 315 ioat = DEVICE2SOFTC(device); 316 317 ioat_test_detach(); 318 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 319 320 mtx_lock(IOAT_REFLK); 321 ioat->quiescing = TRUE; 322 ioat->destroying = TRUE; 323 wakeup(&ioat->quiescing); 324 wakeup(&ioat->resetting); 325 326 ioat_channel[ioat->chan_idx] = NULL; 327 328 ioat_drain_locked(ioat); 329 mtx_unlock(IOAT_REFLK); 330 331 ioat_teardown_intr(ioat); 332 callout_drain(&ioat->poll_timer); 333 334 pci_disable_busmaster(device); 335 336 if (ioat->pci_resource != NULL) 337 bus_release_resource(device, SYS_RES_MEMORY, 338 ioat->pci_resource_id, ioat->pci_resource); 339 340 if (ioat->ring != NULL) 341 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 342 343 if (ioat->comp_update != NULL) { 344 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 345 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 346 ioat->comp_update_map); 347 bus_dma_tag_destroy(ioat->comp_update_tag); 348 } 349 350 if (ioat->hw_desc_ring != NULL) { 351 bus_dmamap_unload(ioat->hw_desc_tag, ioat->hw_desc_map); 352 bus_dmamem_free(ioat->hw_desc_tag, ioat->hw_desc_ring, 353 ioat->hw_desc_map); 354 bus_dma_tag_destroy(ioat->hw_desc_tag); 355 } 356 357 return (0); 358 } 359 360 static int 361 ioat_teardown_intr(struct ioat_softc *ioat) 362 { 363 364 if (ioat->tag != NULL) 365 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 366 367 if (ioat->res != NULL) 368 bus_release_resource(ioat->device, SYS_RES_IRQ, 369 rman_get_rid(ioat->res), ioat->res); 370 371 pci_release_msi(ioat->device); 372 return (0); 373 } 374 375 static int 376 ioat_start_channel(struct ioat_softc *ioat) 377 { 378 struct ioat_dma_hw_descriptor *hw_desc; 379 struct ioat_descriptor *desc; 380 struct bus_dmadesc *dmadesc; 381 uint64_t status; 382 uint32_t chanerr; 383 int i; 384 385 ioat_acquire(&ioat->dmaengine); 386 387 /* Submit 'NULL' operation manually to avoid quiescing flag */ 388 desc = ioat_get_ring_entry(ioat, ioat->head); 389 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->dma; 390 dmadesc = &desc->bus_dmadesc; 391 392 dmadesc->callback_fn = NULL; 393 dmadesc->callback_arg = NULL; 394 395 hw_desc->u.control_raw = 0; 396 hw_desc->u.control_generic.op = IOAT_OP_COPY; 397 hw_desc->u.control_generic.completion_update = 1; 398 hw_desc->size = 8; 399 hw_desc->src_addr = 0; 400 hw_desc->dest_addr = 0; 401 hw_desc->u.control.null = 1; 402 403 ioat_submit_single(ioat); 404 ioat_release(&ioat->dmaengine); 405 406 for (i = 0; i < 100; i++) { 407 DELAY(1); 408 status = ioat_get_chansts(ioat); 409 if (is_ioat_idle(status)) 410 return (0); 411 } 412 413 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 414 ioat_log_message(0, "could not start channel: " 415 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 416 IOAT_CHANERR_STR); 417 return (ENXIO); 418 } 419 420 /* 421 * Initialize Hardware 422 */ 423 static int 424 ioat3_attach(device_t device) 425 { 426 struct ioat_softc *ioat; 427 struct ioat_descriptor *ring; 428 struct ioat_dma_hw_descriptor *dma_hw_desc; 429 void *hw_desc; 430 size_t ringsz; 431 int i, num_descriptors; 432 int error; 433 uint8_t xfercap; 434 435 error = 0; 436 ioat = DEVICE2SOFTC(device); 437 ioat->capabilities = ioat_read_dmacapability(ioat); 438 439 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 440 IOAT_DMACAP_STR); 441 442 xfercap = ioat_read_xfercap(ioat); 443 ioat->max_xfer_size = 1 << xfercap; 444 445 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 446 IOAT_INTRDELAY_SUPPORTED) != 0; 447 if (ioat->intrdelay_supported) 448 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 449 450 /* TODO: need to check DCA here if we ever do XOR/PQ */ 451 452 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 453 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 454 callout_init(&ioat->poll_timer, 1); 455 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 456 457 /* Establish lock order for Witness */ 458 mtx_lock(&ioat->submit_lock); 459 mtx_lock(&ioat->cleanup_lock); 460 mtx_unlock(&ioat->cleanup_lock); 461 mtx_unlock(&ioat->submit_lock); 462 463 ioat->is_submitter_processing = FALSE; 464 ioat->is_completion_pending = FALSE; 465 ioat->is_reset_pending = FALSE; 466 ioat->is_channel_running = FALSE; 467 468 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 469 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 470 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 471 &ioat->comp_update_tag); 472 473 error = bus_dmamem_alloc(ioat->comp_update_tag, 474 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 475 if (ioat->comp_update == NULL) 476 return (ENOMEM); 477 478 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 479 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 480 0); 481 if (error != 0) 482 return (error); 483 484 ioat->ring_size_order = g_ioat_ring_order; 485 num_descriptors = 1 << ioat->ring_size_order; 486 ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors; 487 488 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 489 2 * 1024 * 1024, 0x0, (bus_addr_t)BUS_SPACE_MAXADDR_40BIT, 490 BUS_SPACE_MAXADDR, NULL, NULL, ringsz, 1, ringsz, 0, NULL, NULL, 491 &ioat->hw_desc_tag); 492 if (error != 0) 493 return (error); 494 495 error = bus_dmamem_alloc(ioat->hw_desc_tag, &hw_desc, 496 BUS_DMA_ZERO | BUS_DMA_WAITOK, &ioat->hw_desc_map); 497 if (error != 0) 498 return (error); 499 500 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 501 ringsz, ioat_dmamap_cb, &ioat->hw_desc_bus_addr, BUS_DMA_WAITOK); 502 if (error) 503 return (error); 504 505 ioat->hw_desc_ring = hw_desc; 506 507 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 508 M_ZERO | M_WAITOK); 509 510 ring = ioat->ring; 511 for (i = 0; i < num_descriptors; i++) { 512 memset(&ring[i].bus_dmadesc, 0, sizeof(ring[i].bus_dmadesc)); 513 ring[i].id = i; 514 } 515 516 for (i = 0; i < num_descriptors; i++) { 517 dma_hw_desc = &ioat->hw_desc_ring[i].dma; 518 dma_hw_desc->next = RING_PHYS_ADDR(ioat, i + 1); 519 } 520 521 ioat->head = ioat->hw_head = 0; 522 ioat->tail = 0; 523 ioat->last_seen = 0; 524 *ioat->comp_update = 0; 525 return (0); 526 } 527 528 static int 529 ioat_map_pci_bar(struct ioat_softc *ioat) 530 { 531 532 ioat->pci_resource_id = PCIR_BAR(0); 533 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 534 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 535 536 if (ioat->pci_resource == NULL) { 537 ioat_log_message(0, "unable to allocate pci resource\n"); 538 return (ENODEV); 539 } 540 541 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 542 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 543 return (0); 544 } 545 546 static void 547 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 548 { 549 struct ioat_softc *ioat = arg; 550 551 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 552 ioat->comp_update_bus_addr = seg[0].ds_addr; 553 } 554 555 static void 556 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 557 { 558 bus_addr_t *baddr; 559 560 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 561 baddr = arg; 562 *baddr = segs->ds_addr; 563 } 564 565 /* 566 * Interrupt setup and handlers 567 */ 568 static int 569 ioat_setup_intr(struct ioat_softc *ioat) 570 { 571 uint32_t num_vectors; 572 int error; 573 boolean_t use_msix; 574 boolean_t force_legacy_interrupts; 575 576 use_msix = FALSE; 577 force_legacy_interrupts = FALSE; 578 579 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 580 num_vectors = 1; 581 pci_alloc_msix(ioat->device, &num_vectors); 582 if (num_vectors == 1) 583 use_msix = TRUE; 584 } 585 586 if (use_msix) { 587 ioat->rid = 1; 588 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 589 &ioat->rid, RF_ACTIVE); 590 } else { 591 ioat->rid = 0; 592 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 593 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 594 } 595 if (ioat->res == NULL) { 596 ioat_log_message(0, "bus_alloc_resource failed\n"); 597 return (ENOMEM); 598 } 599 600 ioat->tag = NULL; 601 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 602 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 603 if (error != 0) { 604 ioat_log_message(0, "bus_setup_intr failed\n"); 605 return (error); 606 } 607 608 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 609 return (0); 610 } 611 612 static boolean_t 613 ioat_model_resets_msix(struct ioat_softc *ioat) 614 { 615 u_int32_t pciid; 616 617 pciid = pci_get_devid(ioat->device); 618 switch (pciid) { 619 /* BWD: */ 620 case 0x0c508086: 621 case 0x0c518086: 622 case 0x0c528086: 623 case 0x0c538086: 624 /* BDXDE: */ 625 case 0x6f508086: 626 case 0x6f518086: 627 case 0x6f528086: 628 case 0x6f538086: 629 return (TRUE); 630 } 631 632 return (FALSE); 633 } 634 635 static void 636 ioat_interrupt_handler(void *arg) 637 { 638 struct ioat_softc *ioat = arg; 639 640 ioat->stats.interrupts++; 641 ioat_process_events(ioat); 642 } 643 644 static int 645 chanerr_to_errno(uint32_t chanerr) 646 { 647 648 if (chanerr == 0) 649 return (0); 650 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 651 return (EFAULT); 652 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 653 return (EIO); 654 /* This one is probably our fault: */ 655 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 656 return (EIO); 657 return (EIO); 658 } 659 660 static void 661 ioat_process_events(struct ioat_softc *ioat) 662 { 663 struct ioat_descriptor *desc; 664 struct bus_dmadesc *dmadesc; 665 uint64_t comp_update, status; 666 uint32_t completed, chanerr; 667 boolean_t pending; 668 int error; 669 670 mtx_lock(&ioat->cleanup_lock); 671 672 /* 673 * Don't run while the hardware is being reset. Reset is responsible 674 * for blocking new work and draining & completing existing work, so 675 * there is nothing to do until new work is queued after reset anyway. 676 */ 677 if (ioat->resetting_cleanup) { 678 mtx_unlock(&ioat->cleanup_lock); 679 return; 680 } 681 682 completed = 0; 683 comp_update = *ioat->comp_update; 684 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 685 686 if (status < ioat->hw_desc_bus_addr || 687 status >= ioat->hw_desc_bus_addr + (1 << ioat->ring_size_order) * 688 sizeof(struct ioat_generic_hw_descriptor)) 689 panic("Bogus completion address %jx (channel %u)", 690 (uintmax_t)status, ioat->chan_idx); 691 692 if (status == ioat->last_seen) { 693 /* 694 * If we landed in process_events and nothing has been 695 * completed, check for a timeout due to channel halt. 696 */ 697 goto out; 698 } 699 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx", 700 __func__, ioat->chan_idx, comp_update, ioat->last_seen); 701 702 while (RING_PHYS_ADDR(ioat, ioat->tail - 1) != status) { 703 desc = ioat_get_ring_entry(ioat, ioat->tail); 704 dmadesc = &desc->bus_dmadesc; 705 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) ok cb %p(%p)", 706 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 707 dmadesc->callback_arg); 708 709 if (dmadesc->callback_fn != NULL) 710 dmadesc->callback_fn(dmadesc->callback_arg, 0); 711 712 completed++; 713 ioat->tail++; 714 } 715 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 716 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 717 718 if (completed != 0) { 719 ioat->last_seen = RING_PHYS_ADDR(ioat, ioat->tail - 1); 720 ioat->stats.descriptors_processed += completed; 721 } 722 723 out: 724 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 725 726 /* Perform a racy check first; only take the locks if it passes. */ 727 pending = (ioat_get_active(ioat) != 0); 728 if (!pending && ioat->is_completion_pending) { 729 mtx_unlock(&ioat->cleanup_lock); 730 mtx_lock(&ioat->submit_lock); 731 mtx_lock(&ioat->cleanup_lock); 732 733 pending = (ioat_get_active(ioat) != 0); 734 if (!pending && ioat->is_completion_pending) { 735 ioat->is_completion_pending = FALSE; 736 callout_stop(&ioat->poll_timer); 737 } 738 mtx_unlock(&ioat->submit_lock); 739 } 740 mtx_unlock(&ioat->cleanup_lock); 741 742 if (pending) 743 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 744 ioat); 745 746 if (completed != 0) { 747 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 748 wakeup(&ioat->tail); 749 } 750 751 /* 752 * The device doesn't seem to reliably push suspend/halt statuses to 753 * the channel completion memory address, so poll the device register 754 * here. 755 */ 756 comp_update = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 757 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 758 return; 759 760 ioat->stats.channel_halts++; 761 762 /* 763 * Fatal programming error on this DMA channel. Flush any outstanding 764 * work with error status and restart the engine. 765 */ 766 mtx_lock(&ioat->submit_lock); 767 mtx_lock(&ioat->cleanup_lock); 768 ioat->quiescing = TRUE; 769 /* 770 * This is safe to do here because we have both locks and the submit 771 * queue is quiesced. We know that we will drain all outstanding 772 * events, so ioat_reset_hw can't deadlock. It is necessary to 773 * protect other ioat_process_event threads from racing ioat_reset_hw, 774 * reading an indeterminate hw state, and attempting to continue 775 * issuing completions. 776 */ 777 ioat->resetting_cleanup = TRUE; 778 779 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 780 if (1 <= g_ioat_debug_level) 781 ioat_halted_debug(ioat, chanerr); 782 ioat->stats.last_halt_chanerr = chanerr; 783 784 while (ioat_get_active(ioat) > 0) { 785 desc = ioat_get_ring_entry(ioat, ioat->tail); 786 dmadesc = &desc->bus_dmadesc; 787 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) err cb %p(%p)", 788 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 789 dmadesc->callback_arg); 790 791 if (dmadesc->callback_fn != NULL) 792 dmadesc->callback_fn(dmadesc->callback_arg, 793 chanerr_to_errno(chanerr)); 794 795 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 796 ioat->tail++; 797 ioat->stats.descriptors_processed++; 798 ioat->stats.descriptors_error++; 799 } 800 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 801 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 802 803 if (ioat->is_completion_pending) { 804 ioat->is_completion_pending = FALSE; 805 callout_stop(&ioat->poll_timer); 806 } 807 808 /* Clear error status */ 809 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 810 811 mtx_unlock(&ioat->cleanup_lock); 812 mtx_unlock(&ioat->submit_lock); 813 814 ioat_log_message(0, "Resetting channel to recover from error\n"); 815 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 816 KASSERT(error == 0, 817 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 818 } 819 820 static void 821 ioat_reset_hw_task(void *ctx, int pending __unused) 822 { 823 struct ioat_softc *ioat; 824 int error; 825 826 ioat = ctx; 827 ioat_log_message(1, "%s: Resetting channel\n", __func__); 828 829 error = ioat_reset_hw(ioat); 830 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 831 (void)error; 832 } 833 834 /* 835 * User API functions 836 */ 837 unsigned 838 ioat_get_nchannels(void) 839 { 840 841 return (ioat_channel_index); 842 } 843 844 bus_dmaengine_t 845 ioat_get_dmaengine(uint32_t index, int flags) 846 { 847 struct ioat_softc *ioat; 848 849 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 850 ("invalid flags: 0x%08x", flags)); 851 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 852 ("invalid wait | nowait")); 853 854 if (index >= ioat_channel_index) 855 return (NULL); 856 857 ioat = ioat_channel[index]; 858 if (ioat == NULL || ioat->destroying) 859 return (NULL); 860 861 if (ioat->quiescing) { 862 if ((flags & M_NOWAIT) != 0) 863 return (NULL); 864 865 mtx_lock(IOAT_REFLK); 866 while (ioat->quiescing && !ioat->destroying) 867 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 868 mtx_unlock(IOAT_REFLK); 869 870 if (ioat->destroying) 871 return (NULL); 872 } 873 874 /* 875 * There's a race here between the quiescing check and HW reset or 876 * module destroy. 877 */ 878 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 879 } 880 881 void 882 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 883 { 884 struct ioat_softc *ioat; 885 886 ioat = to_ioat_softc(dmaengine); 887 ioat_put(ioat, IOAT_DMAENGINE_REF); 888 } 889 890 int 891 ioat_get_hwversion(bus_dmaengine_t dmaengine) 892 { 893 struct ioat_softc *ioat; 894 895 ioat = to_ioat_softc(dmaengine); 896 return (ioat->version); 897 } 898 899 size_t 900 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 901 { 902 struct ioat_softc *ioat; 903 904 ioat = to_ioat_softc(dmaengine); 905 return (ioat->max_xfer_size); 906 } 907 908 uint32_t 909 ioat_get_capabilities(bus_dmaengine_t dmaengine) 910 { 911 struct ioat_softc *ioat; 912 913 ioat = to_ioat_softc(dmaengine); 914 return (ioat->capabilities); 915 } 916 917 int 918 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 919 { 920 struct ioat_softc *ioat; 921 922 ioat = to_ioat_softc(dmaengine); 923 if (!ioat->intrdelay_supported) 924 return (ENODEV); 925 if (delay > ioat->intrdelay_max) 926 return (ERANGE); 927 928 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 929 ioat->cached_intrdelay = 930 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 931 return (0); 932 } 933 934 uint16_t 935 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 936 { 937 struct ioat_softc *ioat; 938 939 ioat = to_ioat_softc(dmaengine); 940 return (ioat->intrdelay_max); 941 } 942 943 void 944 ioat_acquire(bus_dmaengine_t dmaengine) 945 { 946 struct ioat_softc *ioat; 947 948 ioat = to_ioat_softc(dmaengine); 949 mtx_lock(&ioat->submit_lock); 950 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 951 ioat->acq_head = ioat->head; 952 } 953 954 int 955 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 956 { 957 struct ioat_softc *ioat; 958 int error; 959 960 ioat = to_ioat_softc(dmaengine); 961 ioat_acquire(dmaengine); 962 963 error = ioat_reserve_space(ioat, n, mflags); 964 if (error != 0) 965 ioat_release(dmaengine); 966 return (error); 967 } 968 969 void 970 ioat_release(bus_dmaengine_t dmaengine) 971 { 972 struct ioat_softc *ioat; 973 974 ioat = to_ioat_softc(dmaengine); 975 CTR4(KTR_IOAT, "%s channel=%u dispatch1 hw_head=%u head=%u", __func__, 976 ioat->chan_idx, ioat->hw_head & UINT16_MAX, ioat->head); 977 KFAIL_POINT_CODE(DEBUG_FP, ioat_release, /* do nothing */); 978 CTR4(KTR_IOAT, "%s channel=%u dispatch2 hw_head=%u head=%u", __func__, 979 ioat->chan_idx, ioat->hw_head & UINT16_MAX, ioat->head); 980 981 if (ioat->acq_head != ioat->head) { 982 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, 983 (uint16_t)ioat->hw_head); 984 985 if (!ioat->is_completion_pending) { 986 ioat->is_completion_pending = TRUE; 987 callout_reset(&ioat->poll_timer, 1, 988 ioat_poll_timer_callback, ioat); 989 } 990 } 991 mtx_unlock(&ioat->submit_lock); 992 } 993 994 static struct ioat_descriptor * 995 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 996 uint32_t size, uint64_t src, uint64_t dst, 997 bus_dmaengine_callback_t callback_fn, void *callback_arg, 998 uint32_t flags) 999 { 1000 struct ioat_generic_hw_descriptor *hw_desc; 1001 struct ioat_descriptor *desc; 1002 int mflags; 1003 1004 mtx_assert(&ioat->submit_lock, MA_OWNED); 1005 1006 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 1007 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 1008 if ((flags & DMA_NO_WAIT) != 0) 1009 mflags = M_NOWAIT; 1010 else 1011 mflags = M_WAITOK; 1012 1013 if (size > ioat->max_xfer_size) { 1014 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 1015 __func__, ioat->max_xfer_size, (unsigned)size); 1016 return (NULL); 1017 } 1018 1019 if (ioat_reserve_space(ioat, 1, mflags) != 0) 1020 return (NULL); 1021 1022 desc = ioat_get_ring_entry(ioat, ioat->head); 1023 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->generic; 1024 1025 hw_desc->u.control_raw = 0; 1026 hw_desc->u.control_generic.op = op; 1027 hw_desc->u.control_generic.completion_update = 1; 1028 1029 if ((flags & DMA_INT_EN) != 0) 1030 hw_desc->u.control_generic.int_enable = 1; 1031 if ((flags & DMA_FENCE) != 0) 1032 hw_desc->u.control_generic.fence = 1; 1033 1034 hw_desc->size = size; 1035 hw_desc->src_addr = src; 1036 hw_desc->dest_addr = dst; 1037 1038 desc->bus_dmadesc.callback_fn = callback_fn; 1039 desc->bus_dmadesc.callback_arg = callback_arg; 1040 return (desc); 1041 } 1042 1043 struct bus_dmadesc * 1044 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1045 void *callback_arg, uint32_t flags) 1046 { 1047 struct ioat_dma_hw_descriptor *hw_desc; 1048 struct ioat_descriptor *desc; 1049 struct ioat_softc *ioat; 1050 1051 ioat = to_ioat_softc(dmaengine); 1052 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1053 1054 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1055 callback_arg, flags); 1056 if (desc == NULL) 1057 return (NULL); 1058 1059 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1060 hw_desc->u.control.null = 1; 1061 ioat_submit_single(ioat); 1062 return (&desc->bus_dmadesc); 1063 } 1064 1065 struct bus_dmadesc * 1066 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1067 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1068 void *callback_arg, uint32_t flags) 1069 { 1070 struct ioat_dma_hw_descriptor *hw_desc; 1071 struct ioat_descriptor *desc; 1072 struct ioat_softc *ioat; 1073 1074 ioat = to_ioat_softc(dmaengine); 1075 1076 if (((src | dst) & (0xffffull << 48)) != 0) { 1077 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1078 __func__); 1079 return (NULL); 1080 } 1081 1082 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1083 callback_arg, flags); 1084 if (desc == NULL) 1085 return (NULL); 1086 1087 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1088 if (g_ioat_debug_level >= 3) 1089 dump_descriptor(hw_desc); 1090 1091 ioat_submit_single(ioat); 1092 CTR6(KTR_IOAT, "%s channel=%u desc=%p dest=%lx src=%lx len=%lx", 1093 __func__, ioat->chan_idx, &desc->bus_dmadesc, dst, src, len); 1094 return (&desc->bus_dmadesc); 1095 } 1096 1097 struct bus_dmadesc * 1098 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1099 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1100 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1101 { 1102 struct ioat_dma_hw_descriptor *hw_desc; 1103 struct ioat_descriptor *desc; 1104 struct ioat_softc *ioat; 1105 1106 ioat = to_ioat_softc(dmaengine); 1107 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1108 1109 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 1110 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1111 __func__); 1112 return (NULL); 1113 } 1114 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 1115 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 1116 __func__); 1117 return (NULL); 1118 } 1119 1120 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 1121 callback_fn, callback_arg, flags); 1122 if (desc == NULL) 1123 return (NULL); 1124 1125 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1126 if (src2 != src1 + PAGE_SIZE) { 1127 hw_desc->u.control.src_page_break = 1; 1128 hw_desc->next_src_addr = src2; 1129 } 1130 if (dst2 != dst1 + PAGE_SIZE) { 1131 hw_desc->u.control.dest_page_break = 1; 1132 hw_desc->next_dest_addr = dst2; 1133 } 1134 1135 if (g_ioat_debug_level >= 3) 1136 dump_descriptor(hw_desc); 1137 1138 ioat_submit_single(ioat); 1139 return (&desc->bus_dmadesc); 1140 } 1141 1142 struct bus_dmadesc * 1143 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1144 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1145 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1146 { 1147 struct ioat_crc32_hw_descriptor *hw_desc; 1148 struct ioat_descriptor *desc; 1149 struct ioat_softc *ioat; 1150 uint32_t teststore; 1151 uint8_t op; 1152 1153 ioat = to_ioat_softc(dmaengine); 1154 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1155 1156 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1157 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1158 __func__); 1159 return (NULL); 1160 } 1161 if (((src | dst) & (0xffffffull << 40)) != 0) { 1162 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1163 __func__); 1164 return (NULL); 1165 } 1166 teststore = (flags & _DMA_CRC_TESTSTORE); 1167 if (teststore == _DMA_CRC_TESTSTORE) { 1168 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1169 return (NULL); 1170 } 1171 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1172 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1173 __func__); 1174 return (NULL); 1175 } 1176 1177 switch (teststore) { 1178 case DMA_CRC_STORE: 1179 op = IOAT_OP_MOVECRC_STORE; 1180 break; 1181 case DMA_CRC_TEST: 1182 op = IOAT_OP_MOVECRC_TEST; 1183 break; 1184 default: 1185 KASSERT(teststore == 0, ("bogus")); 1186 op = IOAT_OP_MOVECRC; 1187 break; 1188 } 1189 1190 if ((flags & DMA_CRC_INLINE) == 0 && 1191 (crcptr & (0xffffffull << 40)) != 0) { 1192 ioat_log_message(0, 1193 "%s: High 24 bits of crcptr invalid\n", __func__); 1194 return (NULL); 1195 } 1196 1197 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1198 callback_arg, flags & ~_DMA_CRC_FLAGS); 1199 if (desc == NULL) 1200 return (NULL); 1201 1202 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1203 1204 if ((flags & DMA_CRC_INLINE) == 0) 1205 hw_desc->crc_address = crcptr; 1206 else 1207 hw_desc->u.control.crc_location = 1; 1208 1209 if (initialseed != NULL) { 1210 hw_desc->u.control.use_seed = 1; 1211 hw_desc->seed = *initialseed; 1212 } 1213 1214 if (g_ioat_debug_level >= 3) 1215 dump_descriptor(hw_desc); 1216 1217 ioat_submit_single(ioat); 1218 return (&desc->bus_dmadesc); 1219 } 1220 1221 struct bus_dmadesc * 1222 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1223 uint32_t *initialseed, bus_addr_t crcptr, 1224 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1225 { 1226 struct ioat_crc32_hw_descriptor *hw_desc; 1227 struct ioat_descriptor *desc; 1228 struct ioat_softc *ioat; 1229 uint32_t teststore; 1230 uint8_t op; 1231 1232 ioat = to_ioat_softc(dmaengine); 1233 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1234 1235 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1236 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1237 __func__); 1238 return (NULL); 1239 } 1240 if ((src & (0xffffffull << 40)) != 0) { 1241 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1242 __func__); 1243 return (NULL); 1244 } 1245 teststore = (flags & _DMA_CRC_TESTSTORE); 1246 if (teststore == _DMA_CRC_TESTSTORE) { 1247 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1248 return (NULL); 1249 } 1250 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1251 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1252 __func__); 1253 return (NULL); 1254 } 1255 1256 switch (teststore) { 1257 case DMA_CRC_STORE: 1258 op = IOAT_OP_CRC_STORE; 1259 break; 1260 case DMA_CRC_TEST: 1261 op = IOAT_OP_CRC_TEST; 1262 break; 1263 default: 1264 KASSERT(teststore == 0, ("bogus")); 1265 op = IOAT_OP_CRC; 1266 break; 1267 } 1268 1269 if ((flags & DMA_CRC_INLINE) == 0 && 1270 (crcptr & (0xffffffull << 40)) != 0) { 1271 ioat_log_message(0, 1272 "%s: High 24 bits of crcptr invalid\n", __func__); 1273 return (NULL); 1274 } 1275 1276 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1277 callback_arg, flags & ~_DMA_CRC_FLAGS); 1278 if (desc == NULL) 1279 return (NULL); 1280 1281 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1282 1283 if ((flags & DMA_CRC_INLINE) == 0) 1284 hw_desc->crc_address = crcptr; 1285 else 1286 hw_desc->u.control.crc_location = 1; 1287 1288 if (initialseed != NULL) { 1289 hw_desc->u.control.use_seed = 1; 1290 hw_desc->seed = *initialseed; 1291 } 1292 1293 if (g_ioat_debug_level >= 3) 1294 dump_descriptor(hw_desc); 1295 1296 ioat_submit_single(ioat); 1297 return (&desc->bus_dmadesc); 1298 } 1299 1300 struct bus_dmadesc * 1301 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1302 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1303 uint32_t flags) 1304 { 1305 struct ioat_fill_hw_descriptor *hw_desc; 1306 struct ioat_descriptor *desc; 1307 struct ioat_softc *ioat; 1308 1309 ioat = to_ioat_softc(dmaengine); 1310 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1311 1312 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1313 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1314 __func__); 1315 return (NULL); 1316 } 1317 1318 if ((dst & (0xffffull << 48)) != 0) { 1319 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1320 __func__); 1321 return (NULL); 1322 } 1323 1324 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1325 callback_fn, callback_arg, flags); 1326 if (desc == NULL) 1327 return (NULL); 1328 1329 hw_desc = &ioat_get_descriptor(ioat, desc->id)->fill; 1330 if (g_ioat_debug_level >= 3) 1331 dump_descriptor(hw_desc); 1332 1333 ioat_submit_single(ioat); 1334 return (&desc->bus_dmadesc); 1335 } 1336 1337 /* 1338 * Ring Management 1339 */ 1340 static inline uint32_t 1341 ioat_get_active(struct ioat_softc *ioat) 1342 { 1343 1344 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1345 } 1346 1347 static inline uint32_t 1348 ioat_get_ring_space(struct ioat_softc *ioat) 1349 { 1350 1351 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1352 } 1353 1354 /* 1355 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1356 * for 'num_descs'. 1357 * 1358 * If mflags contains M_WAITOK, blocks until enough space is available. 1359 * 1360 * Returns zero on success, or an errno on error. If num_descs is beyond the 1361 * maximum ring size, returns EINVAl; if allocation would block and mflags 1362 * contains M_NOWAIT, returns EAGAIN. 1363 * 1364 * Must be called with the submit_lock held; returns with the lock held. The 1365 * lock may be dropped to allocate the ring. 1366 * 1367 * (The submit_lock is needed to add any entries to the ring, so callers are 1368 * assured enough room is available.) 1369 */ 1370 static int 1371 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1372 { 1373 boolean_t dug; 1374 int error; 1375 1376 mtx_assert(&ioat->submit_lock, MA_OWNED); 1377 error = 0; 1378 dug = FALSE; 1379 1380 if (num_descs < 1 || num_descs >= (1 << ioat->ring_size_order)) { 1381 error = EINVAL; 1382 goto out; 1383 } 1384 1385 for (;;) { 1386 if (ioat->quiescing) { 1387 error = ENXIO; 1388 goto out; 1389 } 1390 1391 if (ioat_get_ring_space(ioat) >= num_descs) 1392 goto out; 1393 1394 CTR3(KTR_IOAT, "%s channel=%u starved (%u)", __func__, 1395 ioat->chan_idx, num_descs); 1396 1397 if (!dug && !ioat->is_submitter_processing) { 1398 ioat->is_submitter_processing = TRUE; 1399 mtx_unlock(&ioat->submit_lock); 1400 1401 CTR2(KTR_IOAT, "%s channel=%u attempting to process events", 1402 __func__, ioat->chan_idx); 1403 ioat_process_events(ioat); 1404 1405 mtx_lock(&ioat->submit_lock); 1406 dug = TRUE; 1407 KASSERT(ioat->is_submitter_processing == TRUE, 1408 ("is_submitter_processing")); 1409 ioat->is_submitter_processing = FALSE; 1410 wakeup(&ioat->tail); 1411 continue; 1412 } 1413 1414 if ((mflags & M_WAITOK) == 0) { 1415 error = EAGAIN; 1416 break; 1417 } 1418 CTR2(KTR_IOAT, "%s channel=%u blocking on completions", 1419 __func__, ioat->chan_idx); 1420 msleep(&ioat->tail, &ioat->submit_lock, 0, 1421 "ioat_full", 0); 1422 continue; 1423 } 1424 1425 out: 1426 mtx_assert(&ioat->submit_lock, MA_OWNED); 1427 KASSERT(!ioat->quiescing || error == ENXIO, 1428 ("reserved during quiesce")); 1429 return (error); 1430 } 1431 1432 static void 1433 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1434 struct ioat_descriptor *ring) 1435 { 1436 1437 free(ring, M_IOAT); 1438 } 1439 1440 static struct ioat_descriptor * 1441 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1442 { 1443 1444 return (&ioat->ring[index % (1 << ioat->ring_size_order)]); 1445 } 1446 1447 static union ioat_hw_descriptor * 1448 ioat_get_descriptor(struct ioat_softc *ioat, uint32_t index) 1449 { 1450 1451 return (&ioat->hw_desc_ring[index % (1 << ioat->ring_size_order)]); 1452 } 1453 1454 static void 1455 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1456 { 1457 union ioat_hw_descriptor *desc; 1458 1459 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1460 IOAT_CHANERR_STR); 1461 if (chanerr == 0) 1462 return; 1463 1464 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1465 1466 desc = ioat_get_descriptor(ioat, ioat->tail + 0); 1467 dump_descriptor(desc); 1468 1469 desc = ioat_get_descriptor(ioat, ioat->tail + 1); 1470 dump_descriptor(desc); 1471 } 1472 1473 static void 1474 ioat_poll_timer_callback(void *arg) 1475 { 1476 struct ioat_softc *ioat; 1477 1478 ioat = arg; 1479 ioat_log_message(3, "%s\n", __func__); 1480 1481 ioat_process_events(ioat); 1482 } 1483 1484 /* 1485 * Support Functions 1486 */ 1487 static void 1488 ioat_submit_single(struct ioat_softc *ioat) 1489 { 1490 1491 mtx_assert(&ioat->submit_lock, MA_OWNED); 1492 1493 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1494 atomic_add_rel_int(&ioat->head, 1); 1495 atomic_add_rel_int(&ioat->hw_head, 1); 1496 CTR5(KTR_IOAT, "%s channel=%u head=%u hw_head=%u tail=%u", __func__, 1497 ioat->chan_idx, ioat->head, ioat->hw_head & UINT16_MAX, 1498 ioat->tail); 1499 1500 ioat->stats.descriptors_submitted++; 1501 } 1502 1503 static int 1504 ioat_reset_hw(struct ioat_softc *ioat) 1505 { 1506 uint64_t status; 1507 uint32_t chanerr; 1508 unsigned timeout; 1509 int error; 1510 1511 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1512 1513 mtx_lock(IOAT_REFLK); 1514 while (ioat->resetting && !ioat->destroying) 1515 msleep(&ioat->resetting, IOAT_REFLK, 0, "IRH_drain", 0); 1516 if (ioat->destroying) { 1517 mtx_unlock(IOAT_REFLK); 1518 return (ENXIO); 1519 } 1520 ioat->resetting = TRUE; 1521 1522 ioat->quiescing = TRUE; 1523 ioat_drain_locked(ioat); 1524 mtx_unlock(IOAT_REFLK); 1525 1526 /* 1527 * Suspend ioat_process_events while the hardware and softc are in an 1528 * indeterminate state. 1529 */ 1530 mtx_lock(&ioat->cleanup_lock); 1531 ioat->resetting_cleanup = TRUE; 1532 mtx_unlock(&ioat->cleanup_lock); 1533 1534 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__, 1535 ioat->chan_idx); 1536 1537 status = ioat_get_chansts(ioat); 1538 if (is_ioat_active(status) || is_ioat_idle(status)) 1539 ioat_suspend(ioat); 1540 1541 /* Wait at most 20 ms */ 1542 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1543 timeout < 20; timeout++) { 1544 DELAY(1000); 1545 status = ioat_get_chansts(ioat); 1546 } 1547 if (timeout == 20) { 1548 error = ETIMEDOUT; 1549 goto out; 1550 } 1551 1552 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1553 1554 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1555 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1556 1557 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__, 1558 ioat->chan_idx); 1559 1560 /* 1561 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1562 * that can cause stability issues for IOAT v3. 1563 */ 1564 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1565 4); 1566 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1567 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1568 1569 /* 1570 * BDXDE and BWD models reset MSI-X registers on device reset. 1571 * Save/restore their contents manually. 1572 */ 1573 if (ioat_model_resets_msix(ioat)) { 1574 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1575 pci_save_state(ioat->device); 1576 } 1577 1578 ioat_reset(ioat); 1579 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__, 1580 ioat->chan_idx); 1581 1582 /* Wait at most 20 ms */ 1583 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1584 DELAY(1000); 1585 if (timeout == 20) { 1586 error = ETIMEDOUT; 1587 goto out; 1588 } 1589 1590 if (ioat_model_resets_msix(ioat)) { 1591 ioat_log_message(1, "device resets registers; restored\n"); 1592 pci_restore_state(ioat->device); 1593 } 1594 1595 /* Reset attempts to return the hardware to "halted." */ 1596 status = ioat_get_chansts(ioat); 1597 if (is_ioat_active(status) || is_ioat_idle(status)) { 1598 /* So this really shouldn't happen... */ 1599 ioat_log_message(0, "Device is active after a reset?\n"); 1600 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1601 error = 0; 1602 goto out; 1603 } 1604 1605 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1606 if (chanerr != 0) { 1607 mtx_lock(&ioat->cleanup_lock); 1608 ioat_halted_debug(ioat, chanerr); 1609 mtx_unlock(&ioat->cleanup_lock); 1610 error = EIO; 1611 goto out; 1612 } 1613 1614 /* 1615 * Bring device back online after reset. Writing CHAINADDR brings the 1616 * device back to active. 1617 * 1618 * The internal ring counter resets to zero, so we have to start over 1619 * at zero as well. 1620 */ 1621 ioat->tail = ioat->head = ioat->hw_head = 0; 1622 ioat->last_seen = 0; 1623 *ioat->comp_update = 0; 1624 KASSERT(!ioat->is_completion_pending, ("bogus completion_pending")); 1625 1626 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1627 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1628 ioat_write_chainaddr(ioat, RING_PHYS_ADDR(ioat, 0)); 1629 error = 0; 1630 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__, 1631 ioat->chan_idx); 1632 1633 out: 1634 /* Enqueues a null operation and ensures it completes. */ 1635 if (error == 0) { 1636 error = ioat_start_channel(ioat); 1637 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__, 1638 ioat->chan_idx); 1639 } 1640 1641 /* 1642 * Resume completions now that ring state is consistent. 1643 */ 1644 mtx_lock(&ioat->cleanup_lock); 1645 ioat->resetting_cleanup = FALSE; 1646 mtx_unlock(&ioat->cleanup_lock); 1647 1648 /* Unblock submission of new work */ 1649 mtx_lock(IOAT_REFLK); 1650 ioat->quiescing = FALSE; 1651 wakeup(&ioat->quiescing); 1652 1653 ioat->resetting = FALSE; 1654 wakeup(&ioat->resetting); 1655 1656 if (ioat->is_completion_pending) 1657 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 1658 ioat); 1659 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx); 1660 mtx_unlock(IOAT_REFLK); 1661 1662 return (error); 1663 } 1664 1665 static int 1666 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1667 { 1668 struct ioat_softc *ioat; 1669 struct sbuf sb; 1670 uint64_t status; 1671 int error; 1672 1673 ioat = arg1; 1674 1675 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1676 1677 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1678 switch (status) { 1679 case IOAT_CHANSTS_ACTIVE: 1680 sbuf_printf(&sb, "ACTIVE"); 1681 break; 1682 case IOAT_CHANSTS_IDLE: 1683 sbuf_printf(&sb, "IDLE"); 1684 break; 1685 case IOAT_CHANSTS_SUSPENDED: 1686 sbuf_printf(&sb, "SUSPENDED"); 1687 break; 1688 case IOAT_CHANSTS_HALTED: 1689 sbuf_printf(&sb, "HALTED"); 1690 break; 1691 case IOAT_CHANSTS_ARMED: 1692 sbuf_printf(&sb, "ARMED"); 1693 break; 1694 default: 1695 sbuf_printf(&sb, "UNKNOWN"); 1696 break; 1697 } 1698 error = sbuf_finish(&sb); 1699 sbuf_delete(&sb); 1700 1701 if (error != 0 || req->newptr == NULL) 1702 return (error); 1703 return (EINVAL); 1704 } 1705 1706 static int 1707 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1708 { 1709 struct ioat_softc *ioat; 1710 struct sbuf sb; 1711 #define PRECISION "1" 1712 const uintmax_t factor = 10; 1713 uintmax_t rate; 1714 int error; 1715 1716 ioat = arg1; 1717 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1718 1719 if (ioat->stats.interrupts == 0) { 1720 sbuf_printf(&sb, "NaN"); 1721 goto out; 1722 } 1723 rate = ioat->stats.descriptors_processed * factor / 1724 ioat->stats.interrupts; 1725 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1726 rate % factor); 1727 #undef PRECISION 1728 out: 1729 error = sbuf_finish(&sb); 1730 sbuf_delete(&sb); 1731 if (error != 0 || req->newptr == NULL) 1732 return (error); 1733 return (EINVAL); 1734 } 1735 1736 static int 1737 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1738 { 1739 struct ioat_softc *ioat; 1740 int error, arg; 1741 1742 ioat = arg1; 1743 1744 arg = 0; 1745 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1746 if (error != 0 || req->newptr == NULL) 1747 return (error); 1748 1749 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1750 if (error != 0) 1751 return (error); 1752 1753 if (arg != 0) 1754 error = ioat_reset_hw(ioat); 1755 1756 return (error); 1757 } 1758 1759 static void 1760 dump_descriptor(void *hw_desc) 1761 { 1762 int i, j; 1763 1764 for (i = 0; i < 2; i++) { 1765 for (j = 0; j < 8; j++) 1766 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1767 printf("\n"); 1768 } 1769 } 1770 1771 static void 1772 ioat_setup_sysctl(device_t device) 1773 { 1774 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1775 struct sysctl_ctx_list *ctx; 1776 struct sysctl_oid *tree, *tmp; 1777 struct ioat_softc *ioat; 1778 1779 ioat = DEVICE2SOFTC(device); 1780 ctx = device_get_sysctl_ctx(device); 1781 tree = device_get_sysctl_tree(device); 1782 par = SYSCTL_CHILDREN(tree); 1783 1784 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1785 &ioat->version, 0, "HW version (0xMM form)"); 1786 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1787 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1788 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1789 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1790 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1791 &ioat->intrdelay_max, 0, 1792 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1793 1794 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 1795 "IOAT channel internal state"); 1796 state = SYSCTL_CHILDREN(tmp); 1797 1798 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1799 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1800 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1801 0, "SW descriptor head pointer index"); 1802 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1803 0, "SW descriptor tail pointer index"); 1804 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 1805 &ioat->hw_head, 0, "HW DMACOUNT"); 1806 1807 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1808 ioat->comp_update, "HW addr of last completion"); 1809 1810 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 1811 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 1812 "submitter processing"); 1813 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 1814 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 1815 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1816 &ioat->is_reset_pending, 0, "reset pending"); 1817 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1818 &ioat->is_channel_running, 0, "channel running"); 1819 1820 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1821 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1822 "String of the channel status"); 1823 1824 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1825 &ioat->cached_intrdelay, 0, 1826 "Current INTRDELAY on this channel (cached, microseconds)"); 1827 1828 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 1829 "Big hammers (mostly for testing)"); 1830 hammer = SYSCTL_CHILDREN(tmp); 1831 1832 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1833 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1834 "Set to non-zero to reset the hardware"); 1835 1836 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 1837 "IOAT channel statistics"); 1838 statpar = SYSCTL_CHILDREN(tmp); 1839 1840 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 1841 &ioat->stats.interrupts, 1842 "Number of interrupts processed on this channel"); 1843 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 1844 &ioat->stats.descriptors_processed, 1845 "Number of descriptors processed on this channel"); 1846 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 1847 &ioat->stats.descriptors_submitted, 1848 "Number of descriptors submitted to this channel"); 1849 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 1850 &ioat->stats.descriptors_error, 1851 "Number of descriptors failed by channel errors"); 1852 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 1853 &ioat->stats.channel_halts, 0, 1854 "Number of times the channel has halted"); 1855 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 1856 &ioat->stats.last_halt_chanerr, 0, 1857 "The raw CHANERR when the channel was last halted"); 1858 1859 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 1860 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 1861 "Descriptors per interrupt"); 1862 } 1863 1864 static inline struct ioat_softc * 1865 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1866 { 1867 uint32_t old; 1868 1869 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1870 1871 old = atomic_fetchadd_32(&ioat->refcnt, 1); 1872 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 1873 1874 #ifdef INVARIANTS 1875 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 1876 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 1877 #endif 1878 1879 return (ioat); 1880 } 1881 1882 static inline void 1883 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1884 { 1885 1886 _ioat_putn(ioat, n, kind, FALSE); 1887 } 1888 1889 static inline void 1890 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1891 { 1892 1893 _ioat_putn(ioat, n, kind, TRUE); 1894 } 1895 1896 static inline void 1897 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 1898 boolean_t locked) 1899 { 1900 uint32_t old; 1901 1902 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1903 1904 if (n == 0) 1905 return; 1906 1907 #ifdef INVARIANTS 1908 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 1909 KASSERT(old >= n, ("refcnt kind underflow")); 1910 #endif 1911 1912 /* Skip acquiring the lock if resulting refcnt > 0. */ 1913 for (;;) { 1914 old = ioat->refcnt; 1915 if (old <= n) 1916 break; 1917 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 1918 return; 1919 } 1920 1921 if (locked) 1922 mtx_assert(IOAT_REFLK, MA_OWNED); 1923 else 1924 mtx_lock(IOAT_REFLK); 1925 1926 old = atomic_fetchadd_32(&ioat->refcnt, -n); 1927 KASSERT(old >= n, ("refcnt error")); 1928 1929 if (old == n) 1930 wakeup(IOAT_REFLK); 1931 if (!locked) 1932 mtx_unlock(IOAT_REFLK); 1933 } 1934 1935 static inline void 1936 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1937 { 1938 1939 ioat_putn(ioat, 1, kind); 1940 } 1941 1942 static void 1943 ioat_drain_locked(struct ioat_softc *ioat) 1944 { 1945 1946 mtx_assert(IOAT_REFLK, MA_OWNED); 1947 while (ioat->refcnt > 0) 1948 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 1949 } 1950 1951 #ifdef DDB 1952 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 1953 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 1954 DB_SHOW_COMMAND(ioat, db_show_ioat) 1955 { 1956 struct ioat_softc *sc; 1957 unsigned idx; 1958 1959 if (!have_addr) 1960 goto usage; 1961 idx = (unsigned)addr; 1962 if (idx >= ioat_channel_index) 1963 goto usage; 1964 1965 sc = ioat_channel[idx]; 1966 db_printf("ioat softc at %p\n", sc); 1967 if (sc == NULL) 1968 return; 1969 1970 db_printf(" version: %d\n", sc->version); 1971 db_printf(" chan_idx: %u\n", sc->chan_idx); 1972 db_printf(" submit_lock: "); 1973 db_show_lock(&sc->submit_lock); 1974 1975 db_printf(" capabilities: %b\n", (int)sc->capabilities, 1976 IOAT_DMACAP_STR); 1977 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 1978 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 1979 1980 db_printf(" poll_timer:\n"); 1981 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 1982 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 1983 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 1984 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 1985 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 1986 1987 db_printf(" quiescing: %d\n", (int)sc->quiescing); 1988 db_printf(" destroying: %d\n", (int)sc->destroying); 1989 db_printf(" is_submitter_processing: %d\n", 1990 (int)sc->is_submitter_processing); 1991 db_printf(" is_completion_pending: %d\n", (int)sc->is_completion_pending); 1992 db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending); 1993 db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running); 1994 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 1995 db_printf(" resetting: %d\n", (int)sc->resetting); 1996 1997 db_printf(" head: %u\n", sc->head); 1998 db_printf(" tail: %u\n", sc->tail); 1999 db_printf(" hw_head: %u\n", sc->hw_head); 2000 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2001 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2002 db_printf(" ring: %p\n", sc->ring); 2003 db_printf(" descriptors: %p\n", sc->hw_desc_ring); 2004 db_printf(" descriptors (phys): 0x%jx\n", 2005 (uintmax_t)sc->hw_desc_bus_addr); 2006 2007 db_printf(" ring[%u] (tail):\n", sc->tail % 2008 (1 << sc->ring_size_order)); 2009 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 2010 db_printf(" addr: 0x%lx\n", 2011 RING_PHYS_ADDR(sc, sc->tail)); 2012 db_printf(" next: 0x%lx\n", 2013 ioat_get_descriptor(sc, sc->tail)->generic.next); 2014 2015 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 2016 (1 << sc->ring_size_order)); 2017 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 2018 db_printf(" addr: 0x%lx\n", 2019 RING_PHYS_ADDR(sc, sc->head - 1)); 2020 db_printf(" next: 0x%lx\n", 2021 ioat_get_descriptor(sc, sc->head - 1)->generic.next); 2022 2023 db_printf(" ring[%u] (head):\n", (sc->head) % 2024 (1 << sc->ring_size_order)); 2025 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2026 db_printf(" addr: 0x%lx\n", 2027 RING_PHYS_ADDR(sc, sc->head)); 2028 db_printf(" next: 0x%lx\n", 2029 ioat_get_descriptor(sc, sc->head)->generic.next); 2030 2031 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2032 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2033 == RING_PHYS_ADDR(sc, idx)) 2034 db_printf(" ring[%u] == hardware tail\n", idx); 2035 2036 db_printf(" cleanup_lock: "); 2037 db_show_lock(&sc->cleanup_lock); 2038 2039 db_printf(" refcnt: %u\n", sc->refcnt); 2040 #ifdef INVARIANTS 2041 CTASSERT(IOAT_NUM_REF_KINDS == 2); 2042 db_printf(" refkinds: [ENG=%u, DESCR=%u]\n", sc->refkinds[0], 2043 sc->refkinds[1]); 2044 #endif 2045 db_printf(" stats:\n"); 2046 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2047 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2048 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2049 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2050 2051 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2052 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2053 2054 if (db_pager_quit) 2055 return; 2056 2057 db_printf(" hw status:\n"); 2058 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2059 db_printf(" chanctrl: 0x%x\n", 2060 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2061 db_printf(" chancmd: 0x%x\n", 2062 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2063 db_printf(" dmacount: 0x%x\n", 2064 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2065 db_printf(" chainaddr: 0x%lx\n", 2066 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2067 db_printf(" chancmp: 0x%lx\n", 2068 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2069 db_printf(" chanerr: %b\n", 2070 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2071 return; 2072 usage: 2073 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2074 return; 2075 } 2076 #endif /* DDB */ 2077