1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ddb.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/ioccom.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/sbuf.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #include <machine/stdarg.h> 52 53 #ifdef DDB 54 #include <ddb/ddb.h> 55 #endif 56 57 #include "ioat.h" 58 #include "ioat_hw.h" 59 #include "ioat_internal.h" 60 61 #ifndef BUS_SPACE_MAXADDR_40BIT 62 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 63 #endif 64 #define IOAT_REFLK (&ioat->submit_lock) 65 #define IOAT_SHRINK_PERIOD (10 * hz) 66 67 static int ioat_probe(device_t device); 68 static int ioat_attach(device_t device); 69 static int ioat_detach(device_t device); 70 static int ioat_setup_intr(struct ioat_softc *ioat); 71 static int ioat_teardown_intr(struct ioat_softc *ioat); 72 static int ioat3_attach(device_t device); 73 static int ioat_start_channel(struct ioat_softc *ioat); 74 static int ioat_map_pci_bar(struct ioat_softc *ioat); 75 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 76 int error); 77 static void ioat_interrupt_handler(void *arg); 78 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 79 static int chanerr_to_errno(uint32_t); 80 static void ioat_process_events(struct ioat_softc *ioat); 81 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 82 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 83 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 84 struct ioat_descriptor **); 85 static void ioat_free_ring_entry(struct ioat_softc *ioat, 86 struct ioat_descriptor *desc); 87 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 88 int mflags); 89 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 90 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 91 uint32_t index); 92 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 93 uint32_t size, boolean_t need_dscr, int mflags); 94 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 95 struct ioat_descriptor **); 96 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 97 struct ioat_descriptor **); 98 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 99 static void ioat_poll_timer_callback(void *arg); 100 static void ioat_shrink_timer_callback(void *arg); 101 static void dump_descriptor(void *hw_desc); 102 static void ioat_submit_single(struct ioat_softc *ioat); 103 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 104 int error); 105 static int ioat_reset_hw(struct ioat_softc *ioat); 106 static void ioat_reset_hw_task(void *, int); 107 static void ioat_setup_sysctl(device_t device); 108 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 109 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 110 enum ioat_ref_kind); 111 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 112 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 113 enum ioat_ref_kind, boolean_t); 114 static inline void ioat_putn(struct ioat_softc *, uint32_t, 115 enum ioat_ref_kind); 116 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 117 enum ioat_ref_kind); 118 static void ioat_drain_locked(struct ioat_softc *); 119 120 #define ioat_log_message(v, ...) do { \ 121 if ((v) <= g_ioat_debug_level) { \ 122 device_printf(ioat->device, __VA_ARGS__); \ 123 } \ 124 } while (0) 125 126 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 127 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 128 129 static int g_force_legacy_interrupts; 130 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 131 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 132 133 int g_ioat_debug_level = 0; 134 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 135 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 136 137 /* 138 * OS <-> Driver interface structures 139 */ 140 static device_method_t ioat_pci_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, ioat_probe), 143 DEVMETHOD(device_attach, ioat_attach), 144 DEVMETHOD(device_detach, ioat_detach), 145 DEVMETHOD_END 146 }; 147 148 static driver_t ioat_pci_driver = { 149 "ioat", 150 ioat_pci_methods, 151 sizeof(struct ioat_softc), 152 }; 153 154 static devclass_t ioat_devclass; 155 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 156 MODULE_VERSION(ioat, 1); 157 158 /* 159 * Private data structures 160 */ 161 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 162 static unsigned ioat_channel_index = 0; 163 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 164 "Number of IOAT channels attached"); 165 166 static struct _pcsid 167 { 168 u_int32_t type; 169 const char *desc; 170 } pci_ids[] = { 171 { 0x34308086, "TBG IOAT Ch0" }, 172 { 0x34318086, "TBG IOAT Ch1" }, 173 { 0x34328086, "TBG IOAT Ch2" }, 174 { 0x34338086, "TBG IOAT Ch3" }, 175 { 0x34298086, "TBG IOAT Ch4" }, 176 { 0x342a8086, "TBG IOAT Ch5" }, 177 { 0x342b8086, "TBG IOAT Ch6" }, 178 { 0x342c8086, "TBG IOAT Ch7" }, 179 180 { 0x37108086, "JSF IOAT Ch0" }, 181 { 0x37118086, "JSF IOAT Ch1" }, 182 { 0x37128086, "JSF IOAT Ch2" }, 183 { 0x37138086, "JSF IOAT Ch3" }, 184 { 0x37148086, "JSF IOAT Ch4" }, 185 { 0x37158086, "JSF IOAT Ch5" }, 186 { 0x37168086, "JSF IOAT Ch6" }, 187 { 0x37178086, "JSF IOAT Ch7" }, 188 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 189 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 190 191 { 0x3c208086, "SNB IOAT Ch0" }, 192 { 0x3c218086, "SNB IOAT Ch1" }, 193 { 0x3c228086, "SNB IOAT Ch2" }, 194 { 0x3c238086, "SNB IOAT Ch3" }, 195 { 0x3c248086, "SNB IOAT Ch4" }, 196 { 0x3c258086, "SNB IOAT Ch5" }, 197 { 0x3c268086, "SNB IOAT Ch6" }, 198 { 0x3c278086, "SNB IOAT Ch7" }, 199 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 200 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 201 202 { 0x0e208086, "IVB IOAT Ch0" }, 203 { 0x0e218086, "IVB IOAT Ch1" }, 204 { 0x0e228086, "IVB IOAT Ch2" }, 205 { 0x0e238086, "IVB IOAT Ch3" }, 206 { 0x0e248086, "IVB IOAT Ch4" }, 207 { 0x0e258086, "IVB IOAT Ch5" }, 208 { 0x0e268086, "IVB IOAT Ch6" }, 209 { 0x0e278086, "IVB IOAT Ch7" }, 210 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 211 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 212 213 { 0x2f208086, "HSW IOAT Ch0" }, 214 { 0x2f218086, "HSW IOAT Ch1" }, 215 { 0x2f228086, "HSW IOAT Ch2" }, 216 { 0x2f238086, "HSW IOAT Ch3" }, 217 { 0x2f248086, "HSW IOAT Ch4" }, 218 { 0x2f258086, "HSW IOAT Ch5" }, 219 { 0x2f268086, "HSW IOAT Ch6" }, 220 { 0x2f278086, "HSW IOAT Ch7" }, 221 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 222 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 223 224 { 0x0c508086, "BWD IOAT Ch0" }, 225 { 0x0c518086, "BWD IOAT Ch1" }, 226 { 0x0c528086, "BWD IOAT Ch2" }, 227 { 0x0c538086, "BWD IOAT Ch3" }, 228 229 { 0x6f508086, "BDXDE IOAT Ch0" }, 230 { 0x6f518086, "BDXDE IOAT Ch1" }, 231 { 0x6f528086, "BDXDE IOAT Ch2" }, 232 { 0x6f538086, "BDXDE IOAT Ch3" }, 233 234 { 0x6f208086, "BDX IOAT Ch0" }, 235 { 0x6f218086, "BDX IOAT Ch1" }, 236 { 0x6f228086, "BDX IOAT Ch2" }, 237 { 0x6f238086, "BDX IOAT Ch3" }, 238 { 0x6f248086, "BDX IOAT Ch4" }, 239 { 0x6f258086, "BDX IOAT Ch5" }, 240 { 0x6f268086, "BDX IOAT Ch6" }, 241 { 0x6f278086, "BDX IOAT Ch7" }, 242 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 243 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 244 245 { 0x00000000, NULL } 246 }; 247 248 /* 249 * OS <-> Driver linkage functions 250 */ 251 static int 252 ioat_probe(device_t device) 253 { 254 struct _pcsid *ep; 255 u_int32_t type; 256 257 type = pci_get_devid(device); 258 for (ep = pci_ids; ep->type; ep++) { 259 if (ep->type == type) { 260 device_set_desc(device, ep->desc); 261 return (0); 262 } 263 } 264 return (ENXIO); 265 } 266 267 static int 268 ioat_attach(device_t device) 269 { 270 struct ioat_softc *ioat; 271 int error; 272 273 ioat = DEVICE2SOFTC(device); 274 ioat->device = device; 275 276 error = ioat_map_pci_bar(ioat); 277 if (error != 0) 278 goto err; 279 280 ioat->version = ioat_read_cbver(ioat); 281 if (ioat->version < IOAT_VER_3_0) { 282 error = ENODEV; 283 goto err; 284 } 285 286 error = ioat3_attach(device); 287 if (error != 0) 288 goto err; 289 290 error = pci_enable_busmaster(device); 291 if (error != 0) 292 goto err; 293 294 error = ioat_setup_intr(ioat); 295 if (error != 0) 296 goto err; 297 298 error = ioat_reset_hw(ioat); 299 if (error != 0) 300 goto err; 301 302 ioat_process_events(ioat); 303 ioat_setup_sysctl(device); 304 305 ioat->chan_idx = ioat_channel_index; 306 ioat_channel[ioat_channel_index++] = ioat; 307 ioat_test_attach(); 308 309 err: 310 if (error != 0) 311 ioat_detach(device); 312 return (error); 313 } 314 315 static int 316 ioat_detach(device_t device) 317 { 318 struct ioat_softc *ioat; 319 320 ioat = DEVICE2SOFTC(device); 321 322 ioat_test_detach(); 323 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 324 325 mtx_lock(IOAT_REFLK); 326 ioat->quiescing = TRUE; 327 ioat->destroying = TRUE; 328 wakeup(&ioat->quiescing); 329 wakeup(&ioat->resetting); 330 331 ioat_channel[ioat->chan_idx] = NULL; 332 333 ioat_drain_locked(ioat); 334 mtx_unlock(IOAT_REFLK); 335 336 ioat_teardown_intr(ioat); 337 callout_drain(&ioat->poll_timer); 338 callout_drain(&ioat->shrink_timer); 339 340 pci_disable_busmaster(device); 341 342 if (ioat->pci_resource != NULL) 343 bus_release_resource(device, SYS_RES_MEMORY, 344 ioat->pci_resource_id, ioat->pci_resource); 345 346 if (ioat->ring != NULL) 347 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 348 349 if (ioat->comp_update != NULL) { 350 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 351 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 352 ioat->comp_update_map); 353 bus_dma_tag_destroy(ioat->comp_update_tag); 354 } 355 356 bus_dma_tag_destroy(ioat->hw_desc_tag); 357 358 return (0); 359 } 360 361 static int 362 ioat_teardown_intr(struct ioat_softc *ioat) 363 { 364 365 if (ioat->tag != NULL) 366 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 367 368 if (ioat->res != NULL) 369 bus_release_resource(ioat->device, SYS_RES_IRQ, 370 rman_get_rid(ioat->res), ioat->res); 371 372 pci_release_msi(ioat->device); 373 return (0); 374 } 375 376 static int 377 ioat_start_channel(struct ioat_softc *ioat) 378 { 379 struct ioat_dma_hw_descriptor *hw_desc; 380 struct ioat_descriptor *desc; 381 struct bus_dmadesc *dmadesc; 382 uint64_t status; 383 uint32_t chanerr; 384 int i; 385 386 ioat_acquire(&ioat->dmaengine); 387 388 /* Submit 'NULL' operation manually to avoid quiescing flag */ 389 desc = ioat_get_ring_entry(ioat, ioat->head); 390 dmadesc = &desc->bus_dmadesc; 391 hw_desc = desc->u.dma; 392 393 dmadesc->callback_fn = NULL; 394 dmadesc->callback_arg = NULL; 395 396 hw_desc->u.control_raw = 0; 397 hw_desc->u.control_generic.op = IOAT_OP_COPY; 398 hw_desc->u.control_generic.completion_update = 1; 399 hw_desc->size = 8; 400 hw_desc->src_addr = 0; 401 hw_desc->dest_addr = 0; 402 hw_desc->u.control.null = 1; 403 404 ioat_submit_single(ioat); 405 ioat_release(&ioat->dmaengine); 406 407 for (i = 0; i < 100; i++) { 408 DELAY(1); 409 status = ioat_get_chansts(ioat); 410 if (is_ioat_idle(status)) 411 return (0); 412 } 413 414 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 415 ioat_log_message(0, "could not start channel: " 416 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 417 IOAT_CHANERR_STR); 418 return (ENXIO); 419 } 420 421 /* 422 * Initialize Hardware 423 */ 424 static int 425 ioat3_attach(device_t device) 426 { 427 struct ioat_softc *ioat; 428 struct ioat_descriptor **ring; 429 struct ioat_descriptor *next; 430 struct ioat_dma_hw_descriptor *dma_hw_desc; 431 int i, num_descriptors; 432 int error; 433 uint8_t xfercap; 434 435 error = 0; 436 ioat = DEVICE2SOFTC(device); 437 ioat->capabilities = ioat_read_dmacapability(ioat); 438 439 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 440 IOAT_DMACAP_STR); 441 442 xfercap = ioat_read_xfercap(ioat); 443 ioat->max_xfer_size = 1 << xfercap; 444 445 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 446 IOAT_INTRDELAY_SUPPORTED) != 0; 447 if (ioat->intrdelay_supported) 448 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 449 450 /* TODO: need to check DCA here if we ever do XOR/PQ */ 451 452 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 453 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 454 callout_init(&ioat->poll_timer, 1); 455 callout_init(&ioat->shrink_timer, 1); 456 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 457 458 /* Establish lock order for Witness */ 459 mtx_lock(&ioat->submit_lock); 460 mtx_lock(&ioat->cleanup_lock); 461 mtx_unlock(&ioat->cleanup_lock); 462 mtx_unlock(&ioat->submit_lock); 463 464 ioat->is_resize_pending = FALSE; 465 ioat->is_submitter_processing = FALSE; 466 ioat->is_completion_pending = FALSE; 467 ioat->is_reset_pending = FALSE; 468 ioat->is_channel_running = FALSE; 469 470 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 471 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 472 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 473 &ioat->comp_update_tag); 474 475 error = bus_dmamem_alloc(ioat->comp_update_tag, 476 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 477 if (ioat->comp_update == NULL) 478 return (ENOMEM); 479 480 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 481 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 482 0); 483 if (error != 0) 484 return (error); 485 486 ioat->ring_size_order = IOAT_MIN_ORDER; 487 488 num_descriptors = 1 << ioat->ring_size_order; 489 490 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 491 BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL, 492 sizeof(struct ioat_dma_hw_descriptor), 1, 493 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 494 &ioat->hw_desc_tag); 495 496 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 497 M_ZERO | M_WAITOK); 498 499 ring = ioat->ring; 500 for (i = 0; i < num_descriptors; i++) { 501 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 502 if (ring[i] == NULL) 503 return (ENOMEM); 504 505 ring[i]->id = i; 506 } 507 508 for (i = 0; i < num_descriptors - 1; i++) { 509 next = ring[i + 1]; 510 dma_hw_desc = ring[i]->u.dma; 511 512 dma_hw_desc->next = next->hw_desc_bus_addr; 513 } 514 515 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 516 517 ioat->head = ioat->hw_head = 0; 518 ioat->tail = 0; 519 ioat->last_seen = 0; 520 *ioat->comp_update = 0; 521 return (0); 522 } 523 524 static int 525 ioat_map_pci_bar(struct ioat_softc *ioat) 526 { 527 528 ioat->pci_resource_id = PCIR_BAR(0); 529 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 530 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 531 532 if (ioat->pci_resource == NULL) { 533 ioat_log_message(0, "unable to allocate pci resource\n"); 534 return (ENODEV); 535 } 536 537 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 538 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 539 return (0); 540 } 541 542 static void 543 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 544 { 545 struct ioat_softc *ioat = arg; 546 547 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 548 ioat->comp_update_bus_addr = seg[0].ds_addr; 549 } 550 551 static void 552 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 553 { 554 bus_addr_t *baddr; 555 556 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 557 baddr = arg; 558 *baddr = segs->ds_addr; 559 } 560 561 /* 562 * Interrupt setup and handlers 563 */ 564 static int 565 ioat_setup_intr(struct ioat_softc *ioat) 566 { 567 uint32_t num_vectors; 568 int error; 569 boolean_t use_msix; 570 boolean_t force_legacy_interrupts; 571 572 use_msix = FALSE; 573 force_legacy_interrupts = FALSE; 574 575 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 576 num_vectors = 1; 577 pci_alloc_msix(ioat->device, &num_vectors); 578 if (num_vectors == 1) 579 use_msix = TRUE; 580 } 581 582 if (use_msix) { 583 ioat->rid = 1; 584 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 585 &ioat->rid, RF_ACTIVE); 586 } else { 587 ioat->rid = 0; 588 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 589 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 590 } 591 if (ioat->res == NULL) { 592 ioat_log_message(0, "bus_alloc_resource failed\n"); 593 return (ENOMEM); 594 } 595 596 ioat->tag = NULL; 597 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 598 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 599 if (error != 0) { 600 ioat_log_message(0, "bus_setup_intr failed\n"); 601 return (error); 602 } 603 604 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 605 return (0); 606 } 607 608 static boolean_t 609 ioat_model_resets_msix(struct ioat_softc *ioat) 610 { 611 u_int32_t pciid; 612 613 pciid = pci_get_devid(ioat->device); 614 switch (pciid) { 615 /* BWD: */ 616 case 0x0c508086: 617 case 0x0c518086: 618 case 0x0c528086: 619 case 0x0c538086: 620 /* BDXDE: */ 621 case 0x6f508086: 622 case 0x6f518086: 623 case 0x6f528086: 624 case 0x6f538086: 625 return (TRUE); 626 } 627 628 return (FALSE); 629 } 630 631 static void 632 ioat_interrupt_handler(void *arg) 633 { 634 struct ioat_softc *ioat = arg; 635 636 ioat->stats.interrupts++; 637 ioat_process_events(ioat); 638 } 639 640 static int 641 chanerr_to_errno(uint32_t chanerr) 642 { 643 644 if (chanerr == 0) 645 return (0); 646 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 647 return (EFAULT); 648 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 649 return (EIO); 650 /* This one is probably our fault: */ 651 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 652 return (EIO); 653 return (EIO); 654 } 655 656 static void 657 ioat_process_events(struct ioat_softc *ioat) 658 { 659 struct ioat_descriptor *desc; 660 struct bus_dmadesc *dmadesc; 661 uint64_t comp_update, status; 662 uint32_t completed, chanerr; 663 boolean_t pending; 664 int error; 665 666 mtx_lock(&ioat->cleanup_lock); 667 668 /* 669 * Don't run while the hardware is being reset. Reset is responsible 670 * for blocking new work and draining & completing existing work, so 671 * there is nothing to do until new work is queued after reset anyway. 672 */ 673 if (ioat->resetting_cleanup) { 674 mtx_unlock(&ioat->cleanup_lock); 675 return; 676 } 677 678 completed = 0; 679 comp_update = ioat_get_chansts(ioat); 680 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 681 682 if (status == ioat->last_seen) { 683 /* 684 * If we landed in process_events and nothing has been 685 * completed, check for a timeout due to channel halt. 686 */ 687 goto out; 688 } 689 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx", 690 __func__, ioat->chan_idx, comp_update, ioat->last_seen); 691 692 desc = ioat_get_ring_entry(ioat, ioat->tail - 1); 693 while (desc->hw_desc_bus_addr != status && ioat_get_active(ioat) > 0) { 694 desc = ioat_get_ring_entry(ioat, ioat->tail); 695 dmadesc = &desc->bus_dmadesc; 696 CTR4(KTR_IOAT, "channel=%u completing desc %u ok cb %p(%p)", 697 ioat->chan_idx, ioat->tail, dmadesc->callback_fn, 698 dmadesc->callback_arg); 699 700 if (dmadesc->callback_fn != NULL) 701 dmadesc->callback_fn(dmadesc->callback_arg, 0); 702 703 completed++; 704 ioat->tail++; 705 } 706 707 if (completed != 0) { 708 ioat->last_seen = desc->hw_desc_bus_addr; 709 ioat->stats.descriptors_processed += completed; 710 } 711 712 out: 713 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 714 715 /* Perform a racy check first; only take the locks if it passes. */ 716 pending = (ioat_get_active(ioat) != 0); 717 if (!pending && ioat->is_completion_pending) { 718 mtx_unlock(&ioat->cleanup_lock); 719 mtx_lock(&ioat->submit_lock); 720 mtx_lock(&ioat->cleanup_lock); 721 722 pending = (ioat_get_active(ioat) != 0); 723 if (!pending && ioat->is_completion_pending) { 724 ioat->is_completion_pending = FALSE; 725 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 726 ioat_shrink_timer_callback, ioat); 727 callout_stop(&ioat->poll_timer); 728 } 729 mtx_unlock(&ioat->submit_lock); 730 } 731 mtx_unlock(&ioat->cleanup_lock); 732 733 if (pending) 734 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 735 ioat); 736 737 if (completed != 0) { 738 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 739 wakeup(&ioat->tail); 740 } 741 742 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 743 return; 744 745 ioat->stats.channel_halts++; 746 747 /* 748 * Fatal programming error on this DMA channel. Flush any outstanding 749 * work with error status and restart the engine. 750 */ 751 mtx_lock(&ioat->submit_lock); 752 mtx_lock(&ioat->cleanup_lock); 753 ioat->quiescing = TRUE; 754 755 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 756 if (1 <= g_ioat_debug_level) 757 ioat_halted_debug(ioat, chanerr); 758 ioat->stats.last_halt_chanerr = chanerr; 759 760 while (ioat_get_active(ioat) > 0) { 761 desc = ioat_get_ring_entry(ioat, ioat->tail); 762 dmadesc = &desc->bus_dmadesc; 763 CTR4(KTR_IOAT, "channel=%u completing desc %u err cb %p(%p)", 764 ioat->chan_idx, ioat->tail, dmadesc->callback_fn, 765 dmadesc->callback_arg); 766 767 if (dmadesc->callback_fn != NULL) 768 dmadesc->callback_fn(dmadesc->callback_arg, 769 chanerr_to_errno(chanerr)); 770 771 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 772 ioat->tail++; 773 ioat->stats.descriptors_processed++; 774 ioat->stats.descriptors_error++; 775 } 776 777 if (ioat->is_completion_pending) { 778 ioat->is_completion_pending = FALSE; 779 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 780 ioat_shrink_timer_callback, ioat); 781 callout_stop(&ioat->poll_timer); 782 } 783 784 /* Clear error status */ 785 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 786 787 mtx_unlock(&ioat->cleanup_lock); 788 mtx_unlock(&ioat->submit_lock); 789 790 ioat_log_message(0, "Resetting channel to recover from error\n"); 791 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 792 KASSERT(error == 0, 793 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 794 } 795 796 static void 797 ioat_reset_hw_task(void *ctx, int pending __unused) 798 { 799 struct ioat_softc *ioat; 800 int error; 801 802 ioat = ctx; 803 ioat_log_message(1, "%s: Resetting channel\n", __func__); 804 805 error = ioat_reset_hw(ioat); 806 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 807 (void)error; 808 } 809 810 /* 811 * User API functions 812 */ 813 unsigned 814 ioat_get_nchannels(void) 815 { 816 817 return (ioat_channel_index); 818 } 819 820 bus_dmaengine_t 821 ioat_get_dmaengine(uint32_t index, int flags) 822 { 823 struct ioat_softc *ioat; 824 825 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 826 ("invalid flags: 0x%08x", flags)); 827 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 828 ("invalid wait | nowait")); 829 830 if (index >= ioat_channel_index) 831 return (NULL); 832 833 ioat = ioat_channel[index]; 834 if (ioat == NULL || ioat->destroying) 835 return (NULL); 836 837 if (ioat->quiescing) { 838 if ((flags & M_NOWAIT) != 0) 839 return (NULL); 840 841 mtx_lock(IOAT_REFLK); 842 while (ioat->quiescing && !ioat->destroying) 843 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 844 mtx_unlock(IOAT_REFLK); 845 846 if (ioat->destroying) 847 return (NULL); 848 } 849 850 /* 851 * There's a race here between the quiescing check and HW reset or 852 * module destroy. 853 */ 854 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 855 } 856 857 void 858 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 859 { 860 struct ioat_softc *ioat; 861 862 ioat = to_ioat_softc(dmaengine); 863 ioat_put(ioat, IOAT_DMAENGINE_REF); 864 } 865 866 int 867 ioat_get_hwversion(bus_dmaengine_t dmaengine) 868 { 869 struct ioat_softc *ioat; 870 871 ioat = to_ioat_softc(dmaengine); 872 return (ioat->version); 873 } 874 875 size_t 876 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 877 { 878 struct ioat_softc *ioat; 879 880 ioat = to_ioat_softc(dmaengine); 881 return (ioat->max_xfer_size); 882 } 883 884 uint32_t 885 ioat_get_capabilities(bus_dmaengine_t dmaengine) 886 { 887 struct ioat_softc *ioat; 888 889 ioat = to_ioat_softc(dmaengine); 890 return (ioat->capabilities); 891 } 892 893 int 894 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 895 { 896 struct ioat_softc *ioat; 897 898 ioat = to_ioat_softc(dmaengine); 899 if (!ioat->intrdelay_supported) 900 return (ENODEV); 901 if (delay > ioat->intrdelay_max) 902 return (ERANGE); 903 904 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 905 ioat->cached_intrdelay = 906 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 907 return (0); 908 } 909 910 uint16_t 911 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 912 { 913 struct ioat_softc *ioat; 914 915 ioat = to_ioat_softc(dmaengine); 916 return (ioat->intrdelay_max); 917 } 918 919 void 920 ioat_acquire(bus_dmaengine_t dmaengine) 921 { 922 struct ioat_softc *ioat; 923 924 ioat = to_ioat_softc(dmaengine); 925 mtx_lock(&ioat->submit_lock); 926 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 927 } 928 929 int 930 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 931 { 932 struct ioat_softc *ioat; 933 int error; 934 935 ioat = to_ioat_softc(dmaengine); 936 ioat_acquire(dmaengine); 937 938 error = ioat_reserve_space(ioat, n, mflags); 939 if (error != 0) 940 ioat_release(dmaengine); 941 return (error); 942 } 943 944 void 945 ioat_release(bus_dmaengine_t dmaengine) 946 { 947 struct ioat_softc *ioat; 948 949 ioat = to_ioat_softc(dmaengine); 950 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 951 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 952 953 if (!ioat->is_completion_pending) { 954 ioat->is_completion_pending = TRUE; 955 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 956 ioat); 957 callout_stop(&ioat->shrink_timer); 958 } 959 mtx_unlock(&ioat->submit_lock); 960 } 961 962 static struct ioat_descriptor * 963 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 964 uint32_t size, uint64_t src, uint64_t dst, 965 bus_dmaengine_callback_t callback_fn, void *callback_arg, 966 uint32_t flags) 967 { 968 struct ioat_generic_hw_descriptor *hw_desc; 969 struct ioat_descriptor *desc; 970 int mflags; 971 972 mtx_assert(&ioat->submit_lock, MA_OWNED); 973 974 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 975 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 976 if ((flags & DMA_NO_WAIT) != 0) 977 mflags = M_NOWAIT; 978 else 979 mflags = M_WAITOK; 980 981 if (size > ioat->max_xfer_size) { 982 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 983 __func__, ioat->max_xfer_size, (unsigned)size); 984 return (NULL); 985 } 986 987 if (ioat_reserve_space(ioat, 1, mflags) != 0) 988 return (NULL); 989 990 desc = ioat_get_ring_entry(ioat, ioat->head); 991 hw_desc = desc->u.generic; 992 993 hw_desc->u.control_raw = 0; 994 hw_desc->u.control_generic.op = op; 995 hw_desc->u.control_generic.completion_update = 1; 996 997 if ((flags & DMA_INT_EN) != 0) 998 hw_desc->u.control_generic.int_enable = 1; 999 if ((flags & DMA_FENCE) != 0) 1000 hw_desc->u.control_generic.fence = 1; 1001 1002 hw_desc->size = size; 1003 hw_desc->src_addr = src; 1004 hw_desc->dest_addr = dst; 1005 1006 desc->bus_dmadesc.callback_fn = callback_fn; 1007 desc->bus_dmadesc.callback_arg = callback_arg; 1008 return (desc); 1009 } 1010 1011 struct bus_dmadesc * 1012 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1013 void *callback_arg, uint32_t flags) 1014 { 1015 struct ioat_dma_hw_descriptor *hw_desc; 1016 struct ioat_descriptor *desc; 1017 struct ioat_softc *ioat; 1018 1019 ioat = to_ioat_softc(dmaengine); 1020 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1021 1022 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1023 callback_arg, flags); 1024 if (desc == NULL) 1025 return (NULL); 1026 1027 hw_desc = desc->u.dma; 1028 hw_desc->u.control.null = 1; 1029 ioat_submit_single(ioat); 1030 return (&desc->bus_dmadesc); 1031 } 1032 1033 struct bus_dmadesc * 1034 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1035 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1036 void *callback_arg, uint32_t flags) 1037 { 1038 struct ioat_dma_hw_descriptor *hw_desc; 1039 struct ioat_descriptor *desc; 1040 struct ioat_softc *ioat; 1041 1042 ioat = to_ioat_softc(dmaengine); 1043 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1044 1045 if (((src | dst) & (0xffffull << 48)) != 0) { 1046 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1047 __func__); 1048 return (NULL); 1049 } 1050 1051 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1052 callback_arg, flags); 1053 if (desc == NULL) 1054 return (NULL); 1055 1056 hw_desc = desc->u.dma; 1057 if (g_ioat_debug_level >= 3) 1058 dump_descriptor(hw_desc); 1059 1060 ioat_submit_single(ioat); 1061 return (&desc->bus_dmadesc); 1062 } 1063 1064 struct bus_dmadesc * 1065 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1066 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1067 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1068 { 1069 struct ioat_dma_hw_descriptor *hw_desc; 1070 struct ioat_descriptor *desc; 1071 struct ioat_softc *ioat; 1072 1073 ioat = to_ioat_softc(dmaengine); 1074 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1075 1076 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 1077 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1078 __func__); 1079 return (NULL); 1080 } 1081 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 1082 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 1083 __func__); 1084 return (NULL); 1085 } 1086 1087 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 1088 callback_fn, callback_arg, flags); 1089 if (desc == NULL) 1090 return (NULL); 1091 1092 hw_desc = desc->u.dma; 1093 if (src2 != src1 + PAGE_SIZE) { 1094 hw_desc->u.control.src_page_break = 1; 1095 hw_desc->next_src_addr = src2; 1096 } 1097 if (dst2 != dst1 + PAGE_SIZE) { 1098 hw_desc->u.control.dest_page_break = 1; 1099 hw_desc->next_dest_addr = dst2; 1100 } 1101 1102 if (g_ioat_debug_level >= 3) 1103 dump_descriptor(hw_desc); 1104 1105 ioat_submit_single(ioat); 1106 return (&desc->bus_dmadesc); 1107 } 1108 1109 struct bus_dmadesc * 1110 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1111 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1112 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1113 { 1114 struct ioat_crc32_hw_descriptor *hw_desc; 1115 struct ioat_descriptor *desc; 1116 struct ioat_softc *ioat; 1117 uint32_t teststore; 1118 uint8_t op; 1119 1120 ioat = to_ioat_softc(dmaengine); 1121 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1122 1123 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1124 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1125 __func__); 1126 return (NULL); 1127 } 1128 if (((src | dst) & (0xffffffull << 40)) != 0) { 1129 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1130 __func__); 1131 return (NULL); 1132 } 1133 teststore = (flags & _DMA_CRC_TESTSTORE); 1134 if (teststore == _DMA_CRC_TESTSTORE) { 1135 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1136 return (NULL); 1137 } 1138 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1139 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1140 __func__); 1141 return (NULL); 1142 } 1143 1144 switch (teststore) { 1145 case DMA_CRC_STORE: 1146 op = IOAT_OP_MOVECRC_STORE; 1147 break; 1148 case DMA_CRC_TEST: 1149 op = IOAT_OP_MOVECRC_TEST; 1150 break; 1151 default: 1152 KASSERT(teststore == 0, ("bogus")); 1153 op = IOAT_OP_MOVECRC; 1154 break; 1155 } 1156 1157 if ((flags & DMA_CRC_INLINE) == 0 && 1158 (crcptr & (0xffffffull << 40)) != 0) { 1159 ioat_log_message(0, 1160 "%s: High 24 bits of crcptr invalid\n", __func__); 1161 return (NULL); 1162 } 1163 1164 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1165 callback_arg, flags & ~_DMA_CRC_FLAGS); 1166 if (desc == NULL) 1167 return (NULL); 1168 1169 hw_desc = desc->u.crc32; 1170 1171 if ((flags & DMA_CRC_INLINE) == 0) 1172 hw_desc->crc_address = crcptr; 1173 else 1174 hw_desc->u.control.crc_location = 1; 1175 1176 if (initialseed != NULL) { 1177 hw_desc->u.control.use_seed = 1; 1178 hw_desc->seed = *initialseed; 1179 } 1180 1181 if (g_ioat_debug_level >= 3) 1182 dump_descriptor(hw_desc); 1183 1184 ioat_submit_single(ioat); 1185 return (&desc->bus_dmadesc); 1186 } 1187 1188 struct bus_dmadesc * 1189 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1190 uint32_t *initialseed, bus_addr_t crcptr, 1191 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1192 { 1193 struct ioat_crc32_hw_descriptor *hw_desc; 1194 struct ioat_descriptor *desc; 1195 struct ioat_softc *ioat; 1196 uint32_t teststore; 1197 uint8_t op; 1198 1199 ioat = to_ioat_softc(dmaengine); 1200 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1201 1202 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1203 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1204 __func__); 1205 return (NULL); 1206 } 1207 if ((src & (0xffffffull << 40)) != 0) { 1208 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1209 __func__); 1210 return (NULL); 1211 } 1212 teststore = (flags & _DMA_CRC_TESTSTORE); 1213 if (teststore == _DMA_CRC_TESTSTORE) { 1214 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1215 return (NULL); 1216 } 1217 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1218 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1219 __func__); 1220 return (NULL); 1221 } 1222 1223 switch (teststore) { 1224 case DMA_CRC_STORE: 1225 op = IOAT_OP_CRC_STORE; 1226 break; 1227 case DMA_CRC_TEST: 1228 op = IOAT_OP_CRC_TEST; 1229 break; 1230 default: 1231 KASSERT(teststore == 0, ("bogus")); 1232 op = IOAT_OP_CRC; 1233 break; 1234 } 1235 1236 if ((flags & DMA_CRC_INLINE) == 0 && 1237 (crcptr & (0xffffffull << 40)) != 0) { 1238 ioat_log_message(0, 1239 "%s: High 24 bits of crcptr invalid\n", __func__); 1240 return (NULL); 1241 } 1242 1243 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1244 callback_arg, flags & ~_DMA_CRC_FLAGS); 1245 if (desc == NULL) 1246 return (NULL); 1247 1248 hw_desc = desc->u.crc32; 1249 1250 if ((flags & DMA_CRC_INLINE) == 0) 1251 hw_desc->crc_address = crcptr; 1252 else 1253 hw_desc->u.control.crc_location = 1; 1254 1255 if (initialseed != NULL) { 1256 hw_desc->u.control.use_seed = 1; 1257 hw_desc->seed = *initialseed; 1258 } 1259 1260 if (g_ioat_debug_level >= 3) 1261 dump_descriptor(hw_desc); 1262 1263 ioat_submit_single(ioat); 1264 return (&desc->bus_dmadesc); 1265 } 1266 1267 struct bus_dmadesc * 1268 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1269 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1270 uint32_t flags) 1271 { 1272 struct ioat_fill_hw_descriptor *hw_desc; 1273 struct ioat_descriptor *desc; 1274 struct ioat_softc *ioat; 1275 1276 ioat = to_ioat_softc(dmaengine); 1277 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1278 1279 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1280 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1281 __func__); 1282 return (NULL); 1283 } 1284 1285 if ((dst & (0xffffull << 48)) != 0) { 1286 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1287 __func__); 1288 return (NULL); 1289 } 1290 1291 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1292 callback_fn, callback_arg, flags); 1293 if (desc == NULL) 1294 return (NULL); 1295 1296 hw_desc = desc->u.fill; 1297 if (g_ioat_debug_level >= 3) 1298 dump_descriptor(hw_desc); 1299 1300 ioat_submit_single(ioat); 1301 return (&desc->bus_dmadesc); 1302 } 1303 1304 /* 1305 * Ring Management 1306 */ 1307 static inline uint32_t 1308 ioat_get_active(struct ioat_softc *ioat) 1309 { 1310 1311 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1312 } 1313 1314 static inline uint32_t 1315 ioat_get_ring_space(struct ioat_softc *ioat) 1316 { 1317 1318 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1319 } 1320 1321 static struct ioat_descriptor * 1322 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 1323 { 1324 struct ioat_generic_hw_descriptor *hw_desc; 1325 struct ioat_descriptor *desc; 1326 int error, busdmaflag; 1327 1328 error = ENOMEM; 1329 hw_desc = NULL; 1330 1331 if ((mflags & M_WAITOK) != 0) 1332 busdmaflag = BUS_DMA_WAITOK; 1333 else 1334 busdmaflag = BUS_DMA_NOWAIT; 1335 1336 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1337 if (desc == NULL) 1338 goto out; 1339 1340 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1341 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1342 if (hw_desc == NULL) 1343 goto out; 1344 1345 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1346 desc->u.generic = hw_desc; 1347 1348 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1349 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1350 busdmaflag); 1351 if (error) 1352 goto out; 1353 1354 out: 1355 if (error) { 1356 ioat_free_ring_entry(ioat, desc); 1357 return (NULL); 1358 } 1359 return (desc); 1360 } 1361 1362 static void 1363 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1364 { 1365 1366 if (desc == NULL) 1367 return; 1368 1369 if (desc->u.generic) 1370 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1371 ioat->hw_desc_map); 1372 free(desc, M_IOAT); 1373 } 1374 1375 /* 1376 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1377 * for 'num_descs'. 1378 * 1379 * If mflags contains M_WAITOK, blocks until enough space is available. 1380 * 1381 * Returns zero on success, or an errno on error. If num_descs is beyond the 1382 * maximum ring size, returns EINVAl; if allocation would block and mflags 1383 * contains M_NOWAIT, returns EAGAIN. 1384 * 1385 * Must be called with the submit_lock held; returns with the lock held. The 1386 * lock may be dropped to allocate the ring. 1387 * 1388 * (The submit_lock is needed to add any entries to the ring, so callers are 1389 * assured enough room is available.) 1390 */ 1391 static int 1392 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1393 { 1394 struct ioat_descriptor **new_ring; 1395 uint32_t order; 1396 boolean_t dug; 1397 int error; 1398 1399 mtx_assert(&ioat->submit_lock, MA_OWNED); 1400 error = 0; 1401 dug = FALSE; 1402 1403 if (num_descs < 1 || num_descs >= (1 << IOAT_MAX_ORDER)) { 1404 error = EINVAL; 1405 goto out; 1406 } 1407 1408 for (;;) { 1409 if (ioat->quiescing) { 1410 error = ENXIO; 1411 goto out; 1412 } 1413 1414 if (ioat_get_ring_space(ioat) >= num_descs) 1415 goto out; 1416 1417 if (!dug && !ioat->is_submitter_processing && 1418 (1 << ioat->ring_size_order) > num_descs) { 1419 ioat->is_submitter_processing = TRUE; 1420 mtx_unlock(&ioat->submit_lock); 1421 1422 ioat_process_events(ioat); 1423 1424 mtx_lock(&ioat->submit_lock); 1425 dug = TRUE; 1426 KASSERT(ioat->is_submitter_processing == TRUE, 1427 ("is_submitter_processing")); 1428 ioat->is_submitter_processing = FALSE; 1429 wakeup(&ioat->tail); 1430 continue; 1431 } 1432 1433 order = ioat->ring_size_order; 1434 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1435 if ((mflags & M_WAITOK) != 0) { 1436 msleep(&ioat->tail, &ioat->submit_lock, 0, 1437 "ioat_rsz", 0); 1438 continue; 1439 } 1440 1441 error = EAGAIN; 1442 break; 1443 } 1444 1445 ioat->is_resize_pending = TRUE; 1446 for (;;) { 1447 mtx_unlock(&ioat->submit_lock); 1448 1449 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1450 TRUE, mflags); 1451 1452 mtx_lock(&ioat->submit_lock); 1453 KASSERT(ioat->ring_size_order == order, 1454 ("is_resize_pending should protect order")); 1455 1456 if (new_ring == NULL) { 1457 KASSERT((mflags & M_WAITOK) == 0, 1458 ("allocation failed")); 1459 error = EAGAIN; 1460 break; 1461 } 1462 1463 error = ring_grow(ioat, order, new_ring); 1464 if (error == 0) 1465 break; 1466 } 1467 ioat->is_resize_pending = FALSE; 1468 wakeup(&ioat->tail); 1469 if (error) 1470 break; 1471 } 1472 1473 out: 1474 mtx_assert(&ioat->submit_lock, MA_OWNED); 1475 KASSERT(!ioat->quiescing || error == ENXIO, 1476 ("reserved during quiesce")); 1477 return (error); 1478 } 1479 1480 static struct ioat_descriptor ** 1481 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1482 int mflags) 1483 { 1484 struct ioat_descriptor **ring; 1485 uint32_t i; 1486 int error; 1487 1488 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1489 1490 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1491 if (ring == NULL) 1492 return (NULL); 1493 1494 if (need_dscr) { 1495 error = ENOMEM; 1496 for (i = size / 2; i < size; i++) { 1497 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1498 if (ring[i] == NULL) 1499 goto out; 1500 ring[i]->id = i; 1501 } 1502 } 1503 error = 0; 1504 1505 out: 1506 if (error != 0 && ring != NULL) { 1507 ioat_free_ring(ioat, size, ring); 1508 ring = NULL; 1509 } 1510 return (ring); 1511 } 1512 1513 static void 1514 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1515 struct ioat_descriptor **ring) 1516 { 1517 uint32_t i; 1518 1519 for (i = 0; i < size; i++) { 1520 if (ring[i] != NULL) 1521 ioat_free_ring_entry(ioat, ring[i]); 1522 } 1523 free(ring, M_IOAT); 1524 } 1525 1526 static struct ioat_descriptor * 1527 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1528 { 1529 1530 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1531 } 1532 1533 static int 1534 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1535 struct ioat_descriptor **newring) 1536 { 1537 struct ioat_descriptor *tmp, *next; 1538 struct ioat_dma_hw_descriptor *hw; 1539 uint32_t oldsize, newsize, head, tail, i, end; 1540 int error; 1541 1542 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1543 1544 mtx_assert(&ioat->submit_lock, MA_OWNED); 1545 1546 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1547 error = EINVAL; 1548 goto out; 1549 } 1550 1551 oldsize = (1 << oldorder); 1552 newsize = (1 << (oldorder + 1)); 1553 1554 mtx_lock(&ioat->cleanup_lock); 1555 1556 head = ioat->head & (oldsize - 1); 1557 tail = ioat->tail & (oldsize - 1); 1558 1559 /* Copy old descriptors to new ring */ 1560 for (i = 0; i < oldsize; i++) 1561 newring[i] = ioat->ring[i]; 1562 1563 /* 1564 * If head has wrapped but tail hasn't, we must swap some descriptors 1565 * around so that tail can increment directly to head. 1566 */ 1567 if (head < tail) { 1568 for (i = 0; i <= head; i++) { 1569 tmp = newring[oldsize + i]; 1570 1571 newring[oldsize + i] = newring[i]; 1572 newring[oldsize + i]->id = oldsize + i; 1573 1574 newring[i] = tmp; 1575 newring[i]->id = i; 1576 } 1577 head += oldsize; 1578 } 1579 1580 KASSERT(head >= tail, ("invariants")); 1581 1582 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1583 if (head < oldsize) { 1584 i = oldsize - 1; 1585 end = newsize; 1586 } else { 1587 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1588 i = head; 1589 end = newsize + (head - oldsize) + 1; 1590 } 1591 1592 /* 1593 * Fix up hardware ring, being careful not to trample the active 1594 * section (tail -> head). 1595 */ 1596 for (; i < end; i++) { 1597 KASSERT((i & (newsize - 1)) < tail || 1598 (i & (newsize - 1)) >= head, ("trampling snake")); 1599 1600 next = newring[(i + 1) & (newsize - 1)]; 1601 hw = newring[i & (newsize - 1)]->u.dma; 1602 hw->next = next->hw_desc_bus_addr; 1603 } 1604 1605 #ifdef INVARIANTS 1606 for (i = 0; i < newsize; i++) { 1607 next = newring[(i + 1) & (newsize - 1)]; 1608 hw = newring[i & (newsize - 1)]->u.dma; 1609 1610 KASSERT(hw->next == next->hw_desc_bus_addr, 1611 ("mismatch at i:%u (oldsize:%u); next=%p nextaddr=0x%lx" 1612 " (tail:%u)", i, oldsize, next, next->hw_desc_bus_addr, 1613 tail)); 1614 } 1615 #endif 1616 1617 free(ioat->ring, M_IOAT); 1618 ioat->ring = newring; 1619 ioat->ring_size_order = oldorder + 1; 1620 ioat->tail = tail; 1621 ioat->head = head; 1622 error = 0; 1623 1624 mtx_unlock(&ioat->cleanup_lock); 1625 out: 1626 if (error) 1627 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1628 return (error); 1629 } 1630 1631 static int 1632 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1633 struct ioat_descriptor **newring) 1634 { 1635 struct ioat_dma_hw_descriptor *hw; 1636 struct ioat_descriptor *ent, *next; 1637 uint32_t oldsize, newsize, current_idx, new_idx, i; 1638 int error; 1639 1640 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1641 1642 mtx_assert(&ioat->submit_lock, MA_OWNED); 1643 1644 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1645 error = EINVAL; 1646 goto out_unlocked; 1647 } 1648 1649 oldsize = (1 << oldorder); 1650 newsize = (1 << (oldorder - 1)); 1651 1652 mtx_lock(&ioat->cleanup_lock); 1653 1654 /* Can't shrink below current active set! */ 1655 if (ioat_get_active(ioat) >= newsize) { 1656 error = ENOMEM; 1657 goto out; 1658 } 1659 1660 /* 1661 * Copy current descriptors to the new ring, dropping the removed 1662 * descriptors. 1663 */ 1664 for (i = 0; i < newsize; i++) { 1665 current_idx = (ioat->tail + i) & (oldsize - 1); 1666 new_idx = (ioat->tail + i) & (newsize - 1); 1667 1668 newring[new_idx] = ioat->ring[current_idx]; 1669 newring[new_idx]->id = new_idx; 1670 } 1671 1672 /* Free deleted descriptors */ 1673 for (i = newsize; i < oldsize; i++) { 1674 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1675 ioat_free_ring_entry(ioat, ent); 1676 } 1677 1678 /* Fix up hardware ring. */ 1679 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1680 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1681 hw->next = next->hw_desc_bus_addr; 1682 1683 #ifdef INVARIANTS 1684 for (i = 0; i < newsize; i++) { 1685 next = newring[(i + 1) & (newsize - 1)]; 1686 hw = newring[i & (newsize - 1)]->u.dma; 1687 1688 KASSERT(hw->next == next->hw_desc_bus_addr, 1689 ("mismatch at i:%u (newsize:%u); next=%p nextaddr=0x%lx " 1690 "(tail:%u)", i, newsize, next, next->hw_desc_bus_addr, 1691 ioat->tail)); 1692 } 1693 #endif 1694 1695 free(ioat->ring, M_IOAT); 1696 ioat->ring = newring; 1697 ioat->ring_size_order = oldorder - 1; 1698 error = 0; 1699 1700 out: 1701 mtx_unlock(&ioat->cleanup_lock); 1702 out_unlocked: 1703 if (error) 1704 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1705 return (error); 1706 } 1707 1708 static void 1709 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1710 { 1711 struct ioat_descriptor *desc; 1712 1713 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1714 IOAT_CHANERR_STR); 1715 if (chanerr == 0) 1716 return; 1717 1718 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1719 1720 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1721 dump_descriptor(desc->u.raw); 1722 1723 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1724 dump_descriptor(desc->u.raw); 1725 } 1726 1727 static void 1728 ioat_poll_timer_callback(void *arg) 1729 { 1730 struct ioat_softc *ioat; 1731 1732 ioat = arg; 1733 ioat_log_message(3, "%s\n", __func__); 1734 1735 ioat_process_events(ioat); 1736 } 1737 1738 static void 1739 ioat_shrink_timer_callback(void *arg) 1740 { 1741 struct ioat_descriptor **newring; 1742 struct ioat_softc *ioat; 1743 uint32_t order; 1744 1745 ioat = arg; 1746 ioat_log_message(1, "%s\n", __func__); 1747 1748 /* Slowly scale the ring down if idle. */ 1749 mtx_lock(&ioat->submit_lock); 1750 1751 /* Don't run while the hardware is being reset. */ 1752 if (ioat->resetting) { 1753 mtx_unlock(&ioat->submit_lock); 1754 return; 1755 } 1756 1757 order = ioat->ring_size_order; 1758 if (ioat->is_completion_pending || ioat->is_resize_pending || 1759 order == IOAT_MIN_ORDER) { 1760 mtx_unlock(&ioat->submit_lock); 1761 goto out; 1762 } 1763 ioat->is_resize_pending = TRUE; 1764 mtx_unlock(&ioat->submit_lock); 1765 1766 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1767 M_NOWAIT); 1768 1769 mtx_lock(&ioat->submit_lock); 1770 KASSERT(ioat->ring_size_order == order, 1771 ("resize_pending protects order")); 1772 1773 if (newring != NULL && !ioat->is_completion_pending) 1774 ring_shrink(ioat, order, newring); 1775 else if (newring != NULL) 1776 ioat_free_ring(ioat, (1 << (order - 1)), newring); 1777 1778 ioat->is_resize_pending = FALSE; 1779 mtx_unlock(&ioat->submit_lock); 1780 1781 out: 1782 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1783 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 1784 ioat_shrink_timer_callback, ioat); 1785 } 1786 1787 /* 1788 * Support Functions 1789 */ 1790 static void 1791 ioat_submit_single(struct ioat_softc *ioat) 1792 { 1793 1794 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1795 atomic_add_rel_int(&ioat->head, 1); 1796 atomic_add_rel_int(&ioat->hw_head, 1); 1797 1798 ioat->stats.descriptors_submitted++; 1799 } 1800 1801 static int 1802 ioat_reset_hw(struct ioat_softc *ioat) 1803 { 1804 uint64_t status; 1805 uint32_t chanerr; 1806 unsigned timeout; 1807 int error; 1808 1809 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1810 1811 mtx_lock(IOAT_REFLK); 1812 while (ioat->resetting && !ioat->destroying) 1813 msleep(&ioat->resetting, IOAT_REFLK, 0, "IRH_drain", 0); 1814 if (ioat->destroying) { 1815 mtx_unlock(IOAT_REFLK); 1816 return (ENXIO); 1817 } 1818 ioat->resetting = TRUE; 1819 1820 ioat->quiescing = TRUE; 1821 ioat_drain_locked(ioat); 1822 mtx_unlock(IOAT_REFLK); 1823 1824 /* 1825 * Suspend ioat_process_events while the hardware and softc are in an 1826 * indeterminate state. 1827 */ 1828 mtx_lock(&ioat->cleanup_lock); 1829 ioat->resetting_cleanup = TRUE; 1830 mtx_unlock(&ioat->cleanup_lock); 1831 1832 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__, 1833 ioat->chan_idx); 1834 1835 status = ioat_get_chansts(ioat); 1836 if (is_ioat_active(status) || is_ioat_idle(status)) 1837 ioat_suspend(ioat); 1838 1839 /* Wait at most 20 ms */ 1840 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1841 timeout < 20; timeout++) { 1842 DELAY(1000); 1843 status = ioat_get_chansts(ioat); 1844 } 1845 if (timeout == 20) { 1846 error = ETIMEDOUT; 1847 goto out; 1848 } 1849 1850 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1851 1852 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1853 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1854 1855 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__, 1856 ioat->chan_idx); 1857 1858 /* 1859 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1860 * that can cause stability issues for IOAT v3. 1861 */ 1862 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1863 4); 1864 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1865 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1866 1867 /* 1868 * BDXDE and BWD models reset MSI-X registers on device reset. 1869 * Save/restore their contents manually. 1870 */ 1871 if (ioat_model_resets_msix(ioat)) { 1872 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1873 pci_save_state(ioat->device); 1874 } 1875 1876 ioat_reset(ioat); 1877 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__, 1878 ioat->chan_idx); 1879 1880 /* Wait at most 20 ms */ 1881 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1882 DELAY(1000); 1883 if (timeout == 20) { 1884 error = ETIMEDOUT; 1885 goto out; 1886 } 1887 1888 if (ioat_model_resets_msix(ioat)) { 1889 ioat_log_message(1, "device resets registers; restored\n"); 1890 pci_restore_state(ioat->device); 1891 } 1892 1893 /* Reset attempts to return the hardware to "halted." */ 1894 status = ioat_get_chansts(ioat); 1895 if (is_ioat_active(status) || is_ioat_idle(status)) { 1896 /* So this really shouldn't happen... */ 1897 ioat_log_message(0, "Device is active after a reset?\n"); 1898 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1899 error = 0; 1900 goto out; 1901 } 1902 1903 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1904 if (chanerr != 0) { 1905 mtx_lock(&ioat->cleanup_lock); 1906 ioat_halted_debug(ioat, chanerr); 1907 mtx_unlock(&ioat->cleanup_lock); 1908 error = EIO; 1909 goto out; 1910 } 1911 1912 /* 1913 * Bring device back online after reset. Writing CHAINADDR brings the 1914 * device back to active. 1915 * 1916 * The internal ring counter resets to zero, so we have to start over 1917 * at zero as well. 1918 */ 1919 ioat->tail = ioat->head = ioat->hw_head = 0; 1920 ioat->last_seen = 0; 1921 *ioat->comp_update = 0; 1922 KASSERT(!ioat->is_completion_pending, ("bogus completion_pending")); 1923 1924 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1925 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1926 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1927 error = 0; 1928 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__, 1929 ioat->chan_idx); 1930 1931 out: 1932 /* Enqueues a null operation and ensures it completes. */ 1933 if (error == 0) { 1934 error = ioat_start_channel(ioat); 1935 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__, 1936 ioat->chan_idx); 1937 } 1938 1939 /* 1940 * Resume completions now that ring state is consistent. 1941 */ 1942 mtx_lock(&ioat->cleanup_lock); 1943 ioat->resetting_cleanup = FALSE; 1944 mtx_unlock(&ioat->cleanup_lock); 1945 1946 /* Unblock submission of new work */ 1947 mtx_lock(IOAT_REFLK); 1948 ioat->quiescing = FALSE; 1949 wakeup(&ioat->quiescing); 1950 1951 ioat->resetting = FALSE; 1952 wakeup(&ioat->resetting); 1953 1954 if (ioat->is_completion_pending) 1955 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 1956 ioat); 1957 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx); 1958 mtx_unlock(IOAT_REFLK); 1959 1960 return (error); 1961 } 1962 1963 static int 1964 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1965 { 1966 struct ioat_softc *ioat; 1967 struct sbuf sb; 1968 uint64_t status; 1969 int error; 1970 1971 ioat = arg1; 1972 1973 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1974 1975 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1976 switch (status) { 1977 case IOAT_CHANSTS_ACTIVE: 1978 sbuf_printf(&sb, "ACTIVE"); 1979 break; 1980 case IOAT_CHANSTS_IDLE: 1981 sbuf_printf(&sb, "IDLE"); 1982 break; 1983 case IOAT_CHANSTS_SUSPENDED: 1984 sbuf_printf(&sb, "SUSPENDED"); 1985 break; 1986 case IOAT_CHANSTS_HALTED: 1987 sbuf_printf(&sb, "HALTED"); 1988 break; 1989 case IOAT_CHANSTS_ARMED: 1990 sbuf_printf(&sb, "ARMED"); 1991 break; 1992 default: 1993 sbuf_printf(&sb, "UNKNOWN"); 1994 break; 1995 } 1996 error = sbuf_finish(&sb); 1997 sbuf_delete(&sb); 1998 1999 if (error != 0 || req->newptr == NULL) 2000 return (error); 2001 return (EINVAL); 2002 } 2003 2004 static int 2005 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 2006 { 2007 struct ioat_softc *ioat; 2008 struct sbuf sb; 2009 #define PRECISION "1" 2010 const uintmax_t factor = 10; 2011 uintmax_t rate; 2012 int error; 2013 2014 ioat = arg1; 2015 sbuf_new_for_sysctl(&sb, NULL, 16, req); 2016 2017 if (ioat->stats.interrupts == 0) { 2018 sbuf_printf(&sb, "NaN"); 2019 goto out; 2020 } 2021 rate = ioat->stats.descriptors_processed * factor / 2022 ioat->stats.interrupts; 2023 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 2024 rate % factor); 2025 #undef PRECISION 2026 out: 2027 error = sbuf_finish(&sb); 2028 sbuf_delete(&sb); 2029 if (error != 0 || req->newptr == NULL) 2030 return (error); 2031 return (EINVAL); 2032 } 2033 2034 static int 2035 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 2036 { 2037 struct ioat_softc *ioat; 2038 int error, arg; 2039 2040 ioat = arg1; 2041 2042 arg = 0; 2043 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 2044 if (error != 0 || req->newptr == NULL) 2045 return (error); 2046 2047 error = SYSCTL_IN(req, &arg, sizeof(arg)); 2048 if (error != 0) 2049 return (error); 2050 2051 if (arg != 0) 2052 error = ioat_reset_hw(ioat); 2053 2054 return (error); 2055 } 2056 2057 static void 2058 dump_descriptor(void *hw_desc) 2059 { 2060 int i, j; 2061 2062 for (i = 0; i < 2; i++) { 2063 for (j = 0; j < 8; j++) 2064 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 2065 printf("\n"); 2066 } 2067 } 2068 2069 static void 2070 ioat_setup_sysctl(device_t device) 2071 { 2072 struct sysctl_oid_list *par, *statpar, *state, *hammer; 2073 struct sysctl_ctx_list *ctx; 2074 struct sysctl_oid *tree, *tmp; 2075 struct ioat_softc *ioat; 2076 2077 ioat = DEVICE2SOFTC(device); 2078 ctx = device_get_sysctl_ctx(device); 2079 tree = device_get_sysctl_tree(device); 2080 par = SYSCTL_CHILDREN(tree); 2081 2082 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 2083 &ioat->version, 0, "HW version (0xMM form)"); 2084 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 2085 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 2086 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 2087 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 2088 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 2089 &ioat->intrdelay_max, 0, 2090 "Maximum configurable INTRDELAY on this channel (microseconds)"); 2091 2092 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 2093 "IOAT channel internal state"); 2094 state = SYSCTL_CHILDREN(tmp); 2095 2096 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 2097 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 2098 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 2099 0, "SW descriptor head pointer index"); 2100 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 2101 0, "SW descriptor tail pointer index"); 2102 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 2103 &ioat->hw_head, 0, "HW DMACOUNT"); 2104 2105 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 2106 ioat->comp_update, "HW addr of last completion"); 2107 2108 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 2109 &ioat->is_resize_pending, 0, "resize pending"); 2110 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 2111 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 2112 "submitter processing"); 2113 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 2114 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 2115 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 2116 &ioat->is_reset_pending, 0, "reset pending"); 2117 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 2118 &ioat->is_channel_running, 0, "channel running"); 2119 2120 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 2121 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 2122 "String of the channel status"); 2123 2124 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 2125 &ioat->cached_intrdelay, 0, 2126 "Current INTRDELAY on this channel (cached, microseconds)"); 2127 2128 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 2129 "Big hammers (mostly for testing)"); 2130 hammer = SYSCTL_CHILDREN(tmp); 2131 2132 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 2133 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 2134 "Set to non-zero to reset the hardware"); 2135 2136 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 2137 "IOAT channel statistics"); 2138 statpar = SYSCTL_CHILDREN(tmp); 2139 2140 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 2141 &ioat->stats.interrupts, 2142 "Number of interrupts processed on this channel"); 2143 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 2144 &ioat->stats.descriptors_processed, 2145 "Number of descriptors processed on this channel"); 2146 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 2147 &ioat->stats.descriptors_submitted, 2148 "Number of descriptors submitted to this channel"); 2149 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 2150 &ioat->stats.descriptors_error, 2151 "Number of descriptors failed by channel errors"); 2152 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 2153 &ioat->stats.channel_halts, 0, 2154 "Number of times the channel has halted"); 2155 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 2156 &ioat->stats.last_halt_chanerr, 0, 2157 "The raw CHANERR when the channel was last halted"); 2158 2159 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 2160 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 2161 "Descriptors per interrupt"); 2162 } 2163 2164 static inline struct ioat_softc * 2165 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2166 { 2167 uint32_t old; 2168 2169 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2170 2171 old = atomic_fetchadd_32(&ioat->refcnt, 1); 2172 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 2173 2174 #ifdef INVARIANTS 2175 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 2176 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 2177 #endif 2178 2179 return (ioat); 2180 } 2181 2182 static inline void 2183 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2184 { 2185 2186 _ioat_putn(ioat, n, kind, FALSE); 2187 } 2188 2189 static inline void 2190 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2191 { 2192 2193 _ioat_putn(ioat, n, kind, TRUE); 2194 } 2195 2196 static inline void 2197 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 2198 boolean_t locked) 2199 { 2200 uint32_t old; 2201 2202 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2203 2204 if (n == 0) 2205 return; 2206 2207 #ifdef INVARIANTS 2208 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 2209 KASSERT(old >= n, ("refcnt kind underflow")); 2210 #endif 2211 2212 /* Skip acquiring the lock if resulting refcnt > 0. */ 2213 for (;;) { 2214 old = ioat->refcnt; 2215 if (old <= n) 2216 break; 2217 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 2218 return; 2219 } 2220 2221 if (locked) 2222 mtx_assert(IOAT_REFLK, MA_OWNED); 2223 else 2224 mtx_lock(IOAT_REFLK); 2225 2226 old = atomic_fetchadd_32(&ioat->refcnt, -n); 2227 KASSERT(old >= n, ("refcnt error")); 2228 2229 if (old == n) 2230 wakeup(IOAT_REFLK); 2231 if (!locked) 2232 mtx_unlock(IOAT_REFLK); 2233 } 2234 2235 static inline void 2236 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2237 { 2238 2239 ioat_putn(ioat, 1, kind); 2240 } 2241 2242 static void 2243 ioat_drain_locked(struct ioat_softc *ioat) 2244 { 2245 2246 mtx_assert(IOAT_REFLK, MA_OWNED); 2247 while (ioat->refcnt > 0) 2248 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 2249 } 2250 2251 #ifdef DDB 2252 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 2253 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 2254 DB_SHOW_COMMAND(ioat, db_show_ioat) 2255 { 2256 struct ioat_softc *sc; 2257 unsigned idx; 2258 2259 if (!have_addr) 2260 goto usage; 2261 idx = (unsigned)addr; 2262 if (idx >= ioat_channel_index) 2263 goto usage; 2264 2265 sc = ioat_channel[idx]; 2266 db_printf("ioat softc at %p\n", sc); 2267 if (sc == NULL) 2268 return; 2269 2270 db_printf(" version: %d\n", sc->version); 2271 db_printf(" chan_idx: %u\n", sc->chan_idx); 2272 db_printf(" submit_lock: "); 2273 db_show_lock(&sc->submit_lock); 2274 2275 db_printf(" capabilities: %b\n", (int)sc->capabilities, 2276 IOAT_DMACAP_STR); 2277 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 2278 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 2279 2280 db_printf(" poll_timer:\n"); 2281 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 2282 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 2283 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 2284 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 2285 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 2286 2287 db_printf(" shrink_timer:\n"); 2288 db_printf(" c_time: %ju\n", (uintmax_t)sc->shrink_timer.c_time); 2289 db_printf(" c_arg: %p\n", sc->shrink_timer.c_arg); 2290 db_printf(" c_func: %p\n", sc->shrink_timer.c_func); 2291 db_printf(" c_lock: %p\n", sc->shrink_timer.c_lock); 2292 db_printf(" c_flags: 0x%x\n", (unsigned)sc->shrink_timer.c_flags); 2293 2294 db_printf(" quiescing: %d\n", (int)sc->quiescing); 2295 db_printf(" destroying: %d\n", (int)sc->destroying); 2296 db_printf(" is_resize_pending: %d\n", (int)sc->is_resize_pending); 2297 db_printf(" is_submitter_processing: %d\n", 2298 (int)sc->is_submitter_processing); 2299 db_printf(" is_completion_pending: %d\n", (int)sc->is_completion_pending); 2300 db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending); 2301 db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running); 2302 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 2303 db_printf(" resetting: %d\n", (int)sc->resetting); 2304 2305 db_printf(" head: %u\n", sc->head); 2306 db_printf(" tail: %u\n", sc->tail); 2307 db_printf(" hw_head: %u\n", sc->hw_head); 2308 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2309 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2310 db_printf(" ring: %p\n", sc->ring); 2311 2312 db_printf(" ring[%u] (tail):\n", sc->tail % 2313 (1 << sc->ring_size_order)); 2314 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 2315 db_printf(" addr: 0x%lx\n", 2316 ioat_get_ring_entry(sc, sc->tail)->hw_desc_bus_addr); 2317 db_printf(" next: 0x%lx\n", 2318 ioat_get_ring_entry(sc, sc->tail)->u.generic->next); 2319 2320 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 2321 (1 << sc->ring_size_order)); 2322 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 2323 db_printf(" addr: 0x%lx\n", 2324 ioat_get_ring_entry(sc, sc->head - 1)->hw_desc_bus_addr); 2325 db_printf(" next: 0x%lx\n", 2326 ioat_get_ring_entry(sc, sc->head - 1)->u.generic->next); 2327 2328 db_printf(" ring[%u] (head):\n", (sc->head) % 2329 (1 << sc->ring_size_order)); 2330 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2331 db_printf(" addr: 0x%lx\n", 2332 ioat_get_ring_entry(sc, sc->head)->hw_desc_bus_addr); 2333 db_printf(" next: 0x%lx\n", 2334 ioat_get_ring_entry(sc, sc->head)->u.generic->next); 2335 2336 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2337 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2338 == ioat_get_ring_entry(sc, idx)->hw_desc_bus_addr) 2339 db_printf(" ring[%u] == hardware tail\n", idx); 2340 2341 db_printf(" cleanup_lock: "); 2342 db_show_lock(&sc->cleanup_lock); 2343 2344 db_printf(" refcnt: %u\n", sc->refcnt); 2345 #ifdef INVARIANTS 2346 CTASSERT(IOAT_NUM_REF_KINDS == 2); 2347 db_printf(" refkinds: [ENG=%u, DESCR=%u]\n", sc->refkinds[0], 2348 sc->refkinds[1]); 2349 #endif 2350 db_printf(" stats:\n"); 2351 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2352 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2353 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2354 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2355 2356 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2357 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2358 2359 if (db_pager_quit) 2360 return; 2361 2362 db_printf(" hw status:\n"); 2363 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2364 db_printf(" chanctrl: 0x%x\n", 2365 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2366 db_printf(" chancmd: 0x%x\n", 2367 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2368 db_printf(" dmacount: 0x%x\n", 2369 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2370 db_printf(" chainaddr: 0x%lx\n", 2371 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2372 db_printf(" chancmp: 0x%lx\n", 2373 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2374 db_printf(" chanerr: %b\n", 2375 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2376 return; 2377 usage: 2378 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2379 return; 2380 } 2381 #endif /* DDB */ 2382