1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * Copyright (C) 2018 Alexander Motin <mav@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_ddb.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/domainset.h> 38 #include <sys/fail.h> 39 #include <sys/ioccom.h> 40 #include <sys/kernel.h> 41 #include <sys/ktr.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/sysctl.h> 50 #include <sys/taskqueue.h> 51 #include <sys/time.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 #include <machine/stdarg.h> 57 58 #ifdef DDB 59 #include <ddb/ddb.h> 60 #endif 61 62 #include "ioat.h" 63 #include "ioat_hw.h" 64 #include "ioat_internal.h" 65 66 #ifndef BUS_SPACE_MAXADDR_40BIT 67 #define BUS_SPACE_MAXADDR_40BIT MIN(BUS_SPACE_MAXADDR, 0xFFFFFFFFFFULL) 68 #endif 69 #ifndef BUS_SPACE_MAXADDR_46BIT 70 #define BUS_SPACE_MAXADDR_46BIT MIN(BUS_SPACE_MAXADDR, 0x3FFFFFFFFFFFULL) 71 #endif 72 73 static int ioat_probe(device_t device); 74 static int ioat_attach(device_t device); 75 static int ioat_detach(device_t device); 76 static int ioat_setup_intr(struct ioat_softc *ioat); 77 static int ioat_teardown_intr(struct ioat_softc *ioat); 78 static int ioat3_attach(device_t device); 79 static int ioat_start_channel(struct ioat_softc *ioat); 80 static int ioat_map_pci_bar(struct ioat_softc *ioat); 81 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 82 int error); 83 static void ioat_interrupt_handler(void *arg); 84 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 85 static int chanerr_to_errno(uint32_t); 86 static void ioat_process_events(struct ioat_softc *ioat, boolean_t intr); 87 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 88 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 89 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 90 struct ioat_descriptor *); 91 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 92 static union ioat_hw_descriptor *ioat_get_descriptor(struct ioat_softc *, 93 uint32_t index); 94 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *, 95 uint32_t index); 96 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 97 static void ioat_poll_timer_callback(void *arg); 98 static void dump_descriptor(void *hw_desc); 99 static void ioat_submit_single(struct ioat_softc *ioat); 100 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 101 int error); 102 static int ioat_reset_hw(struct ioat_softc *ioat); 103 static void ioat_reset_hw_task(void *, int); 104 static void ioat_setup_sysctl(device_t device); 105 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 106 static void ioat_get(struct ioat_softc *); 107 static void ioat_put(struct ioat_softc *); 108 static void ioat_drain_locked(struct ioat_softc *); 109 110 #define ioat_log_message(v, ...) do { \ 111 if ((v) <= g_ioat_debug_level) { \ 112 device_printf(ioat->device, __VA_ARGS__); \ 113 } \ 114 } while (0) 115 116 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 117 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 118 "ioat node"); 119 120 static int g_force_legacy_interrupts; 121 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 122 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 123 124 int g_ioat_debug_level = 0; 125 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 126 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 127 128 unsigned g_ioat_ring_order = 13; 129 SYSCTL_UINT(_hw_ioat, OID_AUTO, ring_order, CTLFLAG_RDTUN, &g_ioat_ring_order, 130 0, "Set IOAT ring order. (1 << this) == ring size."); 131 132 /* 133 * OS <-> Driver interface structures 134 */ 135 static device_method_t ioat_pci_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, ioat_probe), 138 DEVMETHOD(device_attach, ioat_attach), 139 DEVMETHOD(device_detach, ioat_detach), 140 DEVMETHOD_END 141 }; 142 143 static driver_t ioat_pci_driver = { 144 "ioat", 145 ioat_pci_methods, 146 sizeof(struct ioat_softc), 147 }; 148 149 static devclass_t ioat_devclass; 150 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 151 MODULE_VERSION(ioat, 1); 152 153 /* 154 * Private data structures 155 */ 156 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 157 static unsigned ioat_channel_index = 0; 158 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 159 "Number of IOAT channels attached"); 160 static struct mtx ioat_list_mtx; 161 MTX_SYSINIT(ioat_list_mtx, &ioat_list_mtx, "ioat list mtx", MTX_DEF); 162 163 static struct _pcsid 164 { 165 u_int32_t type; 166 const char *desc; 167 } pci_ids[] = { 168 { 0x34308086, "TBG IOAT Ch0" }, 169 { 0x34318086, "TBG IOAT Ch1" }, 170 { 0x34328086, "TBG IOAT Ch2" }, 171 { 0x34338086, "TBG IOAT Ch3" }, 172 { 0x34298086, "TBG IOAT Ch4" }, 173 { 0x342a8086, "TBG IOAT Ch5" }, 174 { 0x342b8086, "TBG IOAT Ch6" }, 175 { 0x342c8086, "TBG IOAT Ch7" }, 176 177 { 0x37108086, "JSF IOAT Ch0" }, 178 { 0x37118086, "JSF IOAT Ch1" }, 179 { 0x37128086, "JSF IOAT Ch2" }, 180 { 0x37138086, "JSF IOAT Ch3" }, 181 { 0x37148086, "JSF IOAT Ch4" }, 182 { 0x37158086, "JSF IOAT Ch5" }, 183 { 0x37168086, "JSF IOAT Ch6" }, 184 { 0x37178086, "JSF IOAT Ch7" }, 185 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 186 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 187 188 { 0x3c208086, "SNB IOAT Ch0" }, 189 { 0x3c218086, "SNB IOAT Ch1" }, 190 { 0x3c228086, "SNB IOAT Ch2" }, 191 { 0x3c238086, "SNB IOAT Ch3" }, 192 { 0x3c248086, "SNB IOAT Ch4" }, 193 { 0x3c258086, "SNB IOAT Ch5" }, 194 { 0x3c268086, "SNB IOAT Ch6" }, 195 { 0x3c278086, "SNB IOAT Ch7" }, 196 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 197 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 198 199 { 0x0e208086, "IVB IOAT Ch0" }, 200 { 0x0e218086, "IVB IOAT Ch1" }, 201 { 0x0e228086, "IVB IOAT Ch2" }, 202 { 0x0e238086, "IVB IOAT Ch3" }, 203 { 0x0e248086, "IVB IOAT Ch4" }, 204 { 0x0e258086, "IVB IOAT Ch5" }, 205 { 0x0e268086, "IVB IOAT Ch6" }, 206 { 0x0e278086, "IVB IOAT Ch7" }, 207 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 208 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 209 210 { 0x2f208086, "HSW IOAT Ch0" }, 211 { 0x2f218086, "HSW IOAT Ch1" }, 212 { 0x2f228086, "HSW IOAT Ch2" }, 213 { 0x2f238086, "HSW IOAT Ch3" }, 214 { 0x2f248086, "HSW IOAT Ch4" }, 215 { 0x2f258086, "HSW IOAT Ch5" }, 216 { 0x2f268086, "HSW IOAT Ch6" }, 217 { 0x2f278086, "HSW IOAT Ch7" }, 218 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 219 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 220 221 { 0x0c508086, "BWD IOAT Ch0" }, 222 { 0x0c518086, "BWD IOAT Ch1" }, 223 { 0x0c528086, "BWD IOAT Ch2" }, 224 { 0x0c538086, "BWD IOAT Ch3" }, 225 226 { 0x6f508086, "BDXDE IOAT Ch0" }, 227 { 0x6f518086, "BDXDE IOAT Ch1" }, 228 { 0x6f528086, "BDXDE IOAT Ch2" }, 229 { 0x6f538086, "BDXDE IOAT Ch3" }, 230 231 { 0x6f208086, "BDX IOAT Ch0" }, 232 { 0x6f218086, "BDX IOAT Ch1" }, 233 { 0x6f228086, "BDX IOAT Ch2" }, 234 { 0x6f238086, "BDX IOAT Ch3" }, 235 { 0x6f248086, "BDX IOAT Ch4" }, 236 { 0x6f258086, "BDX IOAT Ch5" }, 237 { 0x6f268086, "BDX IOAT Ch6" }, 238 { 0x6f278086, "BDX IOAT Ch7" }, 239 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 240 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 241 242 { 0x20218086, "SKX IOAT" }, 243 }; 244 245 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, ioat, pci_ids, 246 nitems(pci_ids)); 247 248 /* 249 * OS <-> Driver linkage functions 250 */ 251 static int 252 ioat_probe(device_t device) 253 { 254 struct _pcsid *ep; 255 u_int32_t type; 256 257 type = pci_get_devid(device); 258 for (ep = pci_ids; ep < &pci_ids[nitems(pci_ids)]; ep++) { 259 if (ep->type == type) { 260 device_set_desc(device, ep->desc); 261 return (0); 262 } 263 } 264 return (ENXIO); 265 } 266 267 static int 268 ioat_attach(device_t device) 269 { 270 struct ioat_softc *ioat; 271 int error, i; 272 273 ioat = DEVICE2SOFTC(device); 274 ioat->device = device; 275 if (bus_get_domain(device, &ioat->domain) != 0) 276 ioat->domain = 0; 277 ioat->cpu = CPU_FFS(&cpuset_domain[ioat->domain]) - 1; 278 if (ioat->cpu < 0) 279 ioat->cpu = CPU_FIRST(); 280 281 error = ioat_map_pci_bar(ioat); 282 if (error != 0) 283 goto err; 284 285 ioat->version = ioat_read_cbver(ioat); 286 if (ioat->version < IOAT_VER_3_0) { 287 error = ENODEV; 288 goto err; 289 } 290 291 error = ioat3_attach(device); 292 if (error != 0) 293 goto err; 294 295 error = pci_enable_busmaster(device); 296 if (error != 0) 297 goto err; 298 299 error = ioat_setup_intr(ioat); 300 if (error != 0) 301 goto err; 302 303 error = ioat_reset_hw(ioat); 304 if (error != 0) 305 goto err; 306 307 ioat_process_events(ioat, FALSE); 308 ioat_setup_sysctl(device); 309 310 mtx_lock(&ioat_list_mtx); 311 for (i = 0; i < IOAT_MAX_CHANNELS; i++) { 312 if (ioat_channel[i] == NULL) 313 break; 314 } 315 if (i >= IOAT_MAX_CHANNELS) { 316 mtx_unlock(&ioat_list_mtx); 317 device_printf(device, "Too many I/OAT devices in system\n"); 318 error = ENXIO; 319 goto err; 320 } 321 ioat->chan_idx = i; 322 ioat_channel[i] = ioat; 323 if (i >= ioat_channel_index) 324 ioat_channel_index = i + 1; 325 mtx_unlock(&ioat_list_mtx); 326 327 ioat_test_attach(); 328 329 err: 330 if (error != 0) 331 ioat_detach(device); 332 return (error); 333 } 334 335 static inline int 336 ioat_bus_dmamap_destroy(struct ioat_softc *ioat, const char *func, 337 bus_dma_tag_t dmat, bus_dmamap_t map) 338 { 339 int error; 340 341 error = bus_dmamap_destroy(dmat, map); 342 if (error != 0) { 343 ioat_log_message(0, 344 "%s: bus_dmamap_destroy failed %d\n", func, error); 345 } 346 347 return (error); 348 } 349 350 static int 351 ioat_detach(device_t device) 352 { 353 struct ioat_softc *ioat; 354 int i, error; 355 356 ioat = DEVICE2SOFTC(device); 357 358 mtx_lock(&ioat_list_mtx); 359 ioat_channel[ioat->chan_idx] = NULL; 360 while (ioat_channel_index > 0 && 361 ioat_channel[ioat_channel_index - 1] == NULL) 362 ioat_channel_index--; 363 mtx_unlock(&ioat_list_mtx); 364 365 ioat_test_detach(); 366 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 367 368 mtx_lock(&ioat->submit_lock); 369 ioat->quiescing = TRUE; 370 ioat->destroying = TRUE; 371 wakeup(&ioat->quiescing); 372 wakeup(&ioat->resetting); 373 374 ioat_drain_locked(ioat); 375 mtx_unlock(&ioat->submit_lock); 376 mtx_lock(&ioat->cleanup_lock); 377 while (ioat_get_active(ioat) > 0) 378 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1); 379 mtx_unlock(&ioat->cleanup_lock); 380 381 ioat_teardown_intr(ioat); 382 callout_drain(&ioat->poll_timer); 383 384 pci_disable_busmaster(device); 385 386 if (ioat->pci_resource != NULL) 387 bus_release_resource(device, SYS_RES_MEMORY, 388 ioat->pci_resource_id, ioat->pci_resource); 389 390 if (ioat->data_tag != NULL) { 391 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 392 error = ioat_bus_dmamap_destroy(ioat, __func__, 393 ioat->data_tag, ioat->ring[i].src_dmamap); 394 if (error != 0) 395 return (error); 396 } 397 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 398 error = ioat_bus_dmamap_destroy(ioat, __func__, 399 ioat->data_tag, ioat->ring[i].dst_dmamap); 400 if (error != 0) 401 return (error); 402 } 403 404 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 405 error = ioat_bus_dmamap_destroy(ioat, __func__, 406 ioat->data_tag, ioat->ring[i].src2_dmamap); 407 if (error != 0) 408 return (error); 409 } 410 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 411 error = ioat_bus_dmamap_destroy(ioat, __func__, 412 ioat->data_tag, ioat->ring[i].dst2_dmamap); 413 if (error != 0) 414 return (error); 415 } 416 417 bus_dma_tag_destroy(ioat->data_tag); 418 } 419 420 if (ioat->ring != NULL) 421 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 422 423 if (ioat->comp_update != NULL) { 424 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 425 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 426 ioat->comp_update_map); 427 bus_dma_tag_destroy(ioat->comp_update_tag); 428 } 429 430 if (ioat->hw_desc_ring != NULL) { 431 bus_dmamap_unload(ioat->hw_desc_tag, ioat->hw_desc_map); 432 bus_dmamem_free(ioat->hw_desc_tag, ioat->hw_desc_ring, 433 ioat->hw_desc_map); 434 bus_dma_tag_destroy(ioat->hw_desc_tag); 435 } 436 437 return (0); 438 } 439 440 static int 441 ioat_teardown_intr(struct ioat_softc *ioat) 442 { 443 444 if (ioat->tag != NULL) 445 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 446 447 if (ioat->res != NULL) 448 bus_release_resource(ioat->device, SYS_RES_IRQ, 449 rman_get_rid(ioat->res), ioat->res); 450 451 pci_release_msi(ioat->device); 452 return (0); 453 } 454 455 static int 456 ioat_start_channel(struct ioat_softc *ioat) 457 { 458 struct ioat_dma_hw_descriptor *hw_desc; 459 struct ioat_descriptor *desc; 460 struct bus_dmadesc *dmadesc; 461 uint64_t status; 462 uint32_t chanerr; 463 int i; 464 465 ioat_acquire(&ioat->dmaengine); 466 467 /* Submit 'NULL' operation manually to avoid quiescing flag */ 468 desc = ioat_get_ring_entry(ioat, ioat->head); 469 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->dma; 470 dmadesc = &desc->bus_dmadesc; 471 472 dmadesc->callback_fn = NULL; 473 dmadesc->callback_arg = NULL; 474 475 hw_desc->u.control_raw = 0; 476 hw_desc->u.control_generic.op = IOAT_OP_COPY; 477 hw_desc->u.control_generic.completion_update = 1; 478 hw_desc->size = 8; 479 hw_desc->src_addr = 0; 480 hw_desc->dest_addr = 0; 481 hw_desc->u.control.null = 1; 482 483 ioat_submit_single(ioat); 484 ioat_release(&ioat->dmaengine); 485 486 for (i = 0; i < 100; i++) { 487 DELAY(1); 488 status = ioat_get_chansts(ioat); 489 if (is_ioat_idle(status)) 490 return (0); 491 } 492 493 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 494 ioat_log_message(0, "could not start channel: " 495 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 496 IOAT_CHANERR_STR); 497 return (ENXIO); 498 } 499 500 /* 501 * Initialize Hardware 502 */ 503 static int 504 ioat3_attach(device_t device) 505 { 506 struct ioat_softc *ioat; 507 struct ioat_descriptor *ring; 508 struct ioat_dma_hw_descriptor *dma_hw_desc; 509 void *hw_desc; 510 bus_addr_t lowaddr; 511 size_t ringsz; 512 int i, num_descriptors; 513 int error; 514 uint8_t xfercap; 515 516 error = 0; 517 ioat = DEVICE2SOFTC(device); 518 ioat->capabilities = ioat_read_dmacapability(ioat); 519 520 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 521 IOAT_DMACAP_STR); 522 523 xfercap = ioat_read_xfercap(ioat); 524 ioat->max_xfer_size = 1 << xfercap; 525 526 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 527 IOAT_INTRDELAY_SUPPORTED) != 0; 528 if (ioat->intrdelay_supported) 529 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 530 531 /* TODO: need to check DCA here if we ever do XOR/PQ */ 532 533 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 534 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 535 callout_init(&ioat->poll_timer, 1); 536 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 537 538 /* Establish lock order for Witness */ 539 mtx_lock(&ioat->cleanup_lock); 540 mtx_lock(&ioat->submit_lock); 541 mtx_unlock(&ioat->submit_lock); 542 mtx_unlock(&ioat->cleanup_lock); 543 544 ioat->is_submitter_processing = FALSE; 545 546 if (ioat->version >= IOAT_VER_3_3) 547 lowaddr = BUS_SPACE_MAXADDR_48BIT; 548 else if (ioat->version >= IOAT_VER_3_2) 549 lowaddr = BUS_SPACE_MAXADDR_46BIT; 550 else 551 lowaddr = BUS_SPACE_MAXADDR_40BIT; 552 553 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 554 sizeof(uint64_t), 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 555 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 556 &ioat->comp_update_tag); 557 if (error != 0) 558 return (error); 559 560 error = bus_dmamem_alloc(ioat->comp_update_tag, 561 (void **)&ioat->comp_update, BUS_DMA_ZERO | BUS_DMA_WAITOK, 562 &ioat->comp_update_map); 563 if (error != 0) 564 return (error); 565 566 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 567 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 568 BUS_DMA_NOWAIT); 569 if (error != 0) 570 return (error); 571 572 ioat->ring_size_order = g_ioat_ring_order; 573 num_descriptors = 1 << ioat->ring_size_order; 574 ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors; 575 576 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 577 2 * 1024 * 1024, 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 578 ringsz, 1, ringsz, 0, NULL, NULL, &ioat->hw_desc_tag); 579 if (error != 0) 580 return (error); 581 582 error = bus_dmamem_alloc(ioat->hw_desc_tag, &hw_desc, 583 BUS_DMA_ZERO | BUS_DMA_WAITOK, &ioat->hw_desc_map); 584 if (error != 0) 585 return (error); 586 587 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 588 ringsz, ioat_dmamap_cb, &ioat->hw_desc_bus_addr, BUS_DMA_NOWAIT); 589 if (error) 590 return (error); 591 592 ioat->hw_desc_ring = hw_desc; 593 594 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 595 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 596 ioat->max_xfer_size, 1, ioat->max_xfer_size, 0, NULL, NULL, 597 &ioat->data_tag); 598 if (error != 0) 599 return (error); 600 ioat->ring = malloc_domainset(num_descriptors * sizeof(*ring), M_IOAT, 601 DOMAINSET_PREF(ioat->domain), M_ZERO | M_WAITOK); 602 603 ring = ioat->ring; 604 for (i = 0; i < num_descriptors; i++) { 605 memset(&ring[i].bus_dmadesc, 0, sizeof(ring[i].bus_dmadesc)); 606 ring[i].id = i; 607 error = bus_dmamap_create(ioat->data_tag, 0, 608 &ring[i].src_dmamap); 609 if (error != 0) { 610 ioat_log_message(0, 611 "%s: bus_dmamap_create failed %d\n", __func__, 612 error); 613 return (error); 614 } 615 error = bus_dmamap_create(ioat->data_tag, 0, 616 &ring[i].dst_dmamap); 617 if (error != 0) { 618 ioat_log_message(0, 619 "%s: bus_dmamap_create failed %d\n", __func__, 620 error); 621 return (error); 622 } 623 error = bus_dmamap_create(ioat->data_tag, 0, 624 &ring[i].src2_dmamap); 625 if (error != 0) { 626 ioat_log_message(0, 627 "%s: bus_dmamap_create failed %d\n", __func__, 628 error); 629 return (error); 630 } 631 error = bus_dmamap_create(ioat->data_tag, 0, 632 &ring[i].dst2_dmamap); 633 if (error != 0) { 634 ioat_log_message(0, 635 "%s: bus_dmamap_create failed %d\n", __func__, 636 error); 637 return (error); 638 } 639 } 640 641 for (i = 0; i < num_descriptors; i++) { 642 dma_hw_desc = &ioat->hw_desc_ring[i].dma; 643 dma_hw_desc->next = RING_PHYS_ADDR(ioat, i + 1); 644 } 645 646 ioat->tail = ioat->head = 0; 647 *ioat->comp_update = ioat->last_seen = 648 RING_PHYS_ADDR(ioat, ioat->tail - 1); 649 return (0); 650 } 651 652 static int 653 ioat_map_pci_bar(struct ioat_softc *ioat) 654 { 655 656 ioat->pci_resource_id = PCIR_BAR(0); 657 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 658 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 659 660 if (ioat->pci_resource == NULL) { 661 ioat_log_message(0, "unable to allocate pci resource\n"); 662 return (ENODEV); 663 } 664 665 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 666 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 667 return (0); 668 } 669 670 static void 671 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 672 { 673 struct ioat_softc *ioat = arg; 674 675 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 676 ioat->comp_update_bus_addr = seg[0].ds_addr; 677 } 678 679 static void 680 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 681 { 682 bus_addr_t *baddr; 683 684 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 685 baddr = arg; 686 *baddr = segs->ds_addr; 687 } 688 689 /* 690 * Interrupt setup and handlers 691 */ 692 static int 693 ioat_setup_intr(struct ioat_softc *ioat) 694 { 695 uint32_t num_vectors; 696 int error; 697 boolean_t use_msix; 698 boolean_t force_legacy_interrupts; 699 700 use_msix = FALSE; 701 force_legacy_interrupts = FALSE; 702 703 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 704 num_vectors = 1; 705 pci_alloc_msix(ioat->device, &num_vectors); 706 if (num_vectors == 1) 707 use_msix = TRUE; 708 } 709 710 if (use_msix) { 711 ioat->rid = 1; 712 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 713 &ioat->rid, RF_ACTIVE); 714 } else { 715 ioat->rid = 0; 716 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 717 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 718 } 719 if (ioat->res == NULL) { 720 ioat_log_message(0, "bus_alloc_resource failed\n"); 721 return (ENOMEM); 722 } 723 724 ioat->tag = NULL; 725 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 726 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 727 if (error != 0) { 728 ioat_log_message(0, "bus_setup_intr failed\n"); 729 return (error); 730 } 731 732 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 733 return (0); 734 } 735 736 static boolean_t 737 ioat_model_resets_msix(struct ioat_softc *ioat) 738 { 739 u_int32_t pciid; 740 741 pciid = pci_get_devid(ioat->device); 742 switch (pciid) { 743 /* BWD: */ 744 case 0x0c508086: 745 case 0x0c518086: 746 case 0x0c528086: 747 case 0x0c538086: 748 /* BDXDE: */ 749 case 0x6f508086: 750 case 0x6f518086: 751 case 0x6f528086: 752 case 0x6f538086: 753 return (TRUE); 754 } 755 756 return (FALSE); 757 } 758 759 static void 760 ioat_interrupt_handler(void *arg) 761 { 762 struct ioat_softc *ioat = arg; 763 764 ioat->stats.interrupts++; 765 ioat_process_events(ioat, TRUE); 766 } 767 768 static int 769 chanerr_to_errno(uint32_t chanerr) 770 { 771 772 if (chanerr == 0) 773 return (0); 774 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 775 return (EFAULT); 776 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 777 return (EIO); 778 /* This one is probably our fault: */ 779 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 780 return (EIO); 781 return (EIO); 782 } 783 784 static void 785 ioat_process_events(struct ioat_softc *ioat, boolean_t intr) 786 { 787 struct ioat_descriptor *desc; 788 struct bus_dmadesc *dmadesc; 789 uint64_t comp_update, status; 790 uint32_t completed, chanerr; 791 int error; 792 793 if (intr) { 794 mtx_lock(&ioat->cleanup_lock); 795 } else { 796 if (!mtx_trylock(&ioat->cleanup_lock)) 797 return; 798 } 799 800 /* 801 * Don't run while the hardware is being reset. Reset is responsible 802 * for blocking new work and draining & completing existing work, so 803 * there is nothing to do until new work is queued after reset anyway. 804 */ 805 if (ioat->resetting_cleanup) { 806 mtx_unlock(&ioat->cleanup_lock); 807 return; 808 } 809 810 completed = 0; 811 comp_update = *ioat->comp_update; 812 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 813 814 if (status < ioat->hw_desc_bus_addr || 815 status >= ioat->hw_desc_bus_addr + (1 << ioat->ring_size_order) * 816 sizeof(struct ioat_generic_hw_descriptor)) 817 panic("Bogus completion address %jx (channel %u)", 818 (uintmax_t)status, ioat->chan_idx); 819 820 if (status == ioat->last_seen) { 821 /* 822 * If we landed in process_events and nothing has been 823 * completed, check for a timeout due to channel halt. 824 */ 825 goto out; 826 } 827 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx", 828 __func__, ioat->chan_idx, comp_update, ioat->last_seen); 829 830 while (RING_PHYS_ADDR(ioat, ioat->tail - 1) != status) { 831 desc = ioat_get_ring_entry(ioat, ioat->tail); 832 dmadesc = &desc->bus_dmadesc; 833 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) ok cb %p(%p)", 834 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 835 dmadesc->callback_arg); 836 837 bus_dmamap_unload(ioat->data_tag, desc->src_dmamap); 838 bus_dmamap_unload(ioat->data_tag, desc->dst_dmamap); 839 bus_dmamap_unload(ioat->data_tag, desc->src2_dmamap); 840 bus_dmamap_unload(ioat->data_tag, desc->dst2_dmamap); 841 842 if (dmadesc->callback_fn != NULL) 843 dmadesc->callback_fn(dmadesc->callback_arg, 0); 844 845 completed++; 846 ioat->tail++; 847 } 848 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 849 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 850 851 if (completed != 0) { 852 ioat->last_seen = RING_PHYS_ADDR(ioat, ioat->tail - 1); 853 ioat->stats.descriptors_processed += completed; 854 wakeup(&ioat->tail); 855 } 856 857 out: 858 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 859 mtx_unlock(&ioat->cleanup_lock); 860 861 /* 862 * The device doesn't seem to reliably push suspend/halt statuses to 863 * the channel completion memory address, so poll the device register 864 * here. For performance reasons skip it on interrupts, do it only 865 * on much more rare polling events. 866 */ 867 if (!intr) 868 comp_update = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 869 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 870 return; 871 872 ioat->stats.channel_halts++; 873 874 /* 875 * Fatal programming error on this DMA channel. Flush any outstanding 876 * work with error status and restart the engine. 877 */ 878 mtx_lock(&ioat->submit_lock); 879 ioat->quiescing = TRUE; 880 mtx_unlock(&ioat->submit_lock); 881 882 /* 883 * This is safe to do here because the submit queue is quiesced. We 884 * know that we will drain all outstanding events, so ioat_reset_hw 885 * can't deadlock. It is necessary to protect other ioat_process_event 886 * threads from racing ioat_reset_hw, reading an indeterminate hw 887 * state, and attempting to continue issuing completions. 888 */ 889 mtx_lock(&ioat->cleanup_lock); 890 ioat->resetting_cleanup = TRUE; 891 892 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 893 if (1 <= g_ioat_debug_level) 894 ioat_halted_debug(ioat, chanerr); 895 ioat->stats.last_halt_chanerr = chanerr; 896 897 while (ioat_get_active(ioat) > 0) { 898 desc = ioat_get_ring_entry(ioat, ioat->tail); 899 dmadesc = &desc->bus_dmadesc; 900 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) err cb %p(%p)", 901 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 902 dmadesc->callback_arg); 903 904 if (dmadesc->callback_fn != NULL) 905 dmadesc->callback_fn(dmadesc->callback_arg, 906 chanerr_to_errno(chanerr)); 907 908 ioat->tail++; 909 ioat->stats.descriptors_processed++; 910 ioat->stats.descriptors_error++; 911 } 912 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 913 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 914 915 /* Clear error status */ 916 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 917 918 mtx_unlock(&ioat->cleanup_lock); 919 920 ioat_log_message(0, "Resetting channel to recover from error\n"); 921 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 922 KASSERT(error == 0, 923 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 924 } 925 926 static void 927 ioat_reset_hw_task(void *ctx, int pending __unused) 928 { 929 struct ioat_softc *ioat; 930 int error; 931 932 ioat = ctx; 933 ioat_log_message(1, "%s: Resetting channel\n", __func__); 934 935 error = ioat_reset_hw(ioat); 936 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 937 (void)error; 938 } 939 940 /* 941 * User API functions 942 */ 943 unsigned 944 ioat_get_nchannels(void) 945 { 946 947 return (ioat_channel_index); 948 } 949 950 bus_dmaengine_t 951 ioat_get_dmaengine(uint32_t index, int flags) 952 { 953 struct ioat_softc *ioat; 954 955 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 956 ("invalid flags: 0x%08x", flags)); 957 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 958 ("invalid wait | nowait")); 959 960 mtx_lock(&ioat_list_mtx); 961 if (index >= ioat_channel_index || 962 (ioat = ioat_channel[index]) == NULL) { 963 mtx_unlock(&ioat_list_mtx); 964 return (NULL); 965 } 966 mtx_lock(&ioat->submit_lock); 967 mtx_unlock(&ioat_list_mtx); 968 969 if (ioat->destroying) { 970 mtx_unlock(&ioat->submit_lock); 971 return (NULL); 972 } 973 974 ioat_get(ioat); 975 if (ioat->quiescing) { 976 if ((flags & M_NOWAIT) != 0) { 977 ioat_put(ioat); 978 mtx_unlock(&ioat->submit_lock); 979 return (NULL); 980 } 981 982 while (ioat->quiescing && !ioat->destroying) 983 msleep(&ioat->quiescing, &ioat->submit_lock, 0, "getdma", 0); 984 985 if (ioat->destroying) { 986 ioat_put(ioat); 987 mtx_unlock(&ioat->submit_lock); 988 return (NULL); 989 } 990 } 991 mtx_unlock(&ioat->submit_lock); 992 return (&ioat->dmaengine); 993 } 994 995 void 996 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 997 { 998 struct ioat_softc *ioat; 999 1000 ioat = to_ioat_softc(dmaengine); 1001 mtx_lock(&ioat->submit_lock); 1002 ioat_put(ioat); 1003 mtx_unlock(&ioat->submit_lock); 1004 } 1005 1006 int 1007 ioat_get_hwversion(bus_dmaengine_t dmaengine) 1008 { 1009 struct ioat_softc *ioat; 1010 1011 ioat = to_ioat_softc(dmaengine); 1012 return (ioat->version); 1013 } 1014 1015 size_t 1016 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 1017 { 1018 struct ioat_softc *ioat; 1019 1020 ioat = to_ioat_softc(dmaengine); 1021 return (ioat->max_xfer_size); 1022 } 1023 1024 uint32_t 1025 ioat_get_capabilities(bus_dmaengine_t dmaengine) 1026 { 1027 struct ioat_softc *ioat; 1028 1029 ioat = to_ioat_softc(dmaengine); 1030 return (ioat->capabilities); 1031 } 1032 1033 int 1034 ioat_get_domain(bus_dmaengine_t dmaengine, int *domain) 1035 { 1036 struct ioat_softc *ioat; 1037 1038 ioat = to_ioat_softc(dmaengine); 1039 return (bus_get_domain(ioat->device, domain)); 1040 } 1041 1042 int 1043 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 1044 { 1045 struct ioat_softc *ioat; 1046 1047 ioat = to_ioat_softc(dmaengine); 1048 if (!ioat->intrdelay_supported) 1049 return (ENODEV); 1050 if (delay > ioat->intrdelay_max) 1051 return (ERANGE); 1052 1053 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 1054 ioat->cached_intrdelay = 1055 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 1056 return (0); 1057 } 1058 1059 uint16_t 1060 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 1061 { 1062 struct ioat_softc *ioat; 1063 1064 ioat = to_ioat_softc(dmaengine); 1065 return (ioat->intrdelay_max); 1066 } 1067 1068 void 1069 ioat_acquire(bus_dmaengine_t dmaengine) 1070 { 1071 struct ioat_softc *ioat; 1072 1073 ioat = to_ioat_softc(dmaengine); 1074 mtx_lock(&ioat->submit_lock); 1075 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1076 ioat->acq_head = ioat->head; 1077 } 1078 1079 int 1080 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 1081 { 1082 struct ioat_softc *ioat; 1083 int error; 1084 1085 ioat = to_ioat_softc(dmaengine); 1086 ioat_acquire(dmaengine); 1087 1088 error = ioat_reserve_space(ioat, n, mflags); 1089 if (error != 0) 1090 ioat_release(dmaengine); 1091 return (error); 1092 } 1093 1094 void 1095 ioat_release(bus_dmaengine_t dmaengine) 1096 { 1097 struct ioat_softc *ioat; 1098 1099 ioat = to_ioat_softc(dmaengine); 1100 CTR3(KTR_IOAT, "%s channel=%u dispatch1 head=%u", __func__, 1101 ioat->chan_idx, ioat->head); 1102 KFAIL_POINT_CODE(DEBUG_FP, ioat_release, /* do nothing */); 1103 CTR3(KTR_IOAT, "%s channel=%u dispatch2 head=%u", __func__, 1104 ioat->chan_idx, ioat->head); 1105 1106 if (ioat->acq_head != ioat->head) { 1107 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, 1108 (uint16_t)ioat->head); 1109 1110 if (!callout_pending(&ioat->poll_timer)) { 1111 callout_reset_on(&ioat->poll_timer, 1, 1112 ioat_poll_timer_callback, ioat, ioat->cpu); 1113 } 1114 } 1115 mtx_unlock(&ioat->submit_lock); 1116 } 1117 1118 static struct ioat_descriptor * 1119 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 1120 uint32_t size, uint64_t src, uint64_t dst, 1121 bus_dmaengine_callback_t callback_fn, void *callback_arg, 1122 uint32_t flags) 1123 { 1124 struct ioat_generic_hw_descriptor *hw_desc; 1125 struct ioat_descriptor *desc; 1126 bus_dma_segment_t seg; 1127 int mflags, nseg, error; 1128 1129 mtx_assert(&ioat->submit_lock, MA_OWNED); 1130 1131 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 1132 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 1133 KASSERT(size <= ioat->max_xfer_size, ("%s: size too big (%u > %u)", 1134 __func__, (unsigned)size, ioat->max_xfer_size)); 1135 1136 if ((flags & DMA_NO_WAIT) != 0) 1137 mflags = M_NOWAIT; 1138 else 1139 mflags = M_WAITOK; 1140 1141 if (ioat_reserve_space(ioat, 1, mflags) != 0) 1142 return (NULL); 1143 1144 desc = ioat_get_ring_entry(ioat, ioat->head); 1145 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->generic; 1146 1147 hw_desc->u.control_raw = 0; 1148 hw_desc->u.control_generic.op = op; 1149 hw_desc->u.control_generic.completion_update = 1; 1150 1151 if ((flags & DMA_INT_EN) != 0) 1152 hw_desc->u.control_generic.int_enable = 1; 1153 if ((flags & DMA_FENCE) != 0) 1154 hw_desc->u.control_generic.fence = 1; 1155 1156 hw_desc->size = size; 1157 1158 if (src != 0) { 1159 nseg = -1; 1160 error = _bus_dmamap_load_phys(ioat->data_tag, desc->src_dmamap, 1161 src, size, 0, &seg, &nseg); 1162 if (error != 0) { 1163 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1164 " failed %d\n", __func__, error); 1165 return (NULL); 1166 } 1167 hw_desc->src_addr = seg.ds_addr; 1168 } 1169 1170 if (dst != 0) { 1171 nseg = -1; 1172 error = _bus_dmamap_load_phys(ioat->data_tag, desc->dst_dmamap, 1173 dst, size, 0, &seg, &nseg); 1174 if (error != 0) { 1175 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1176 " failed %d\n", __func__, error); 1177 return (NULL); 1178 } 1179 hw_desc->dest_addr = seg.ds_addr; 1180 } 1181 1182 desc->bus_dmadesc.callback_fn = callback_fn; 1183 desc->bus_dmadesc.callback_arg = callback_arg; 1184 return (desc); 1185 } 1186 1187 struct bus_dmadesc * 1188 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1189 void *callback_arg, uint32_t flags) 1190 { 1191 struct ioat_dma_hw_descriptor *hw_desc; 1192 struct ioat_descriptor *desc; 1193 struct ioat_softc *ioat; 1194 1195 ioat = to_ioat_softc(dmaengine); 1196 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1197 1198 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1199 callback_arg, flags); 1200 if (desc == NULL) 1201 return (NULL); 1202 1203 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1204 hw_desc->u.control.null = 1; 1205 ioat_submit_single(ioat); 1206 return (&desc->bus_dmadesc); 1207 } 1208 1209 struct bus_dmadesc * 1210 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1211 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1212 void *callback_arg, uint32_t flags) 1213 { 1214 struct ioat_dma_hw_descriptor *hw_desc; 1215 struct ioat_descriptor *desc; 1216 struct ioat_softc *ioat; 1217 1218 ioat = to_ioat_softc(dmaengine); 1219 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1220 callback_arg, flags); 1221 if (desc == NULL) 1222 return (NULL); 1223 1224 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1225 if (g_ioat_debug_level >= 3) 1226 dump_descriptor(hw_desc); 1227 1228 ioat_submit_single(ioat); 1229 CTR6(KTR_IOAT, "%s channel=%u desc=%p dest=%lx src=%lx len=%lx", 1230 __func__, ioat->chan_idx, &desc->bus_dmadesc, dst, src, len); 1231 return (&desc->bus_dmadesc); 1232 } 1233 1234 struct bus_dmadesc * 1235 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1236 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1237 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1238 { 1239 struct ioat_dma_hw_descriptor *hw_desc; 1240 struct ioat_descriptor *desc; 1241 struct ioat_softc *ioat; 1242 bus_size_t src1_len, dst1_len; 1243 bus_dma_segment_t seg; 1244 int nseg, error; 1245 1246 ioat = to_ioat_softc(dmaengine); 1247 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1248 1249 KASSERT(((src1 | src2 | dst1 | dst2) & PAGE_MASK) == 0, 1250 ("%s: addresses are not page-aligned", __func__)); 1251 1252 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, 0, 0, 1253 callback_fn, callback_arg, flags); 1254 if (desc == NULL) 1255 return (NULL); 1256 1257 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1258 1259 src1_len = (src2 != src1 + PAGE_SIZE) ? PAGE_SIZE : 2 * PAGE_SIZE; 1260 nseg = -1; 1261 error = _bus_dmamap_load_phys(ioat->data_tag, 1262 desc->src_dmamap, src1, src1_len, 0, &seg, &nseg); 1263 if (error != 0) { 1264 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1265 " failed %d\n", __func__, error); 1266 return (NULL); 1267 } 1268 hw_desc->src_addr = seg.ds_addr; 1269 if (src1_len != 2 * PAGE_SIZE) { 1270 hw_desc->u.control.src_page_break = 1; 1271 nseg = -1; 1272 error = _bus_dmamap_load_phys(ioat->data_tag, 1273 desc->src2_dmamap, src2, PAGE_SIZE, 0, &seg, &nseg); 1274 if (error != 0) { 1275 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1276 " failed %d\n", __func__, error); 1277 return (NULL); 1278 } 1279 hw_desc->next_src_addr = seg.ds_addr; 1280 } 1281 1282 dst1_len = (dst2 != dst1 + PAGE_SIZE) ? PAGE_SIZE : 2 * PAGE_SIZE; 1283 nseg = -1; 1284 error = _bus_dmamap_load_phys(ioat->data_tag, 1285 desc->dst_dmamap, dst1, dst1_len, 0, &seg, &nseg); 1286 if (error != 0) { 1287 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1288 " failed %d\n", __func__, error); 1289 return (NULL); 1290 } 1291 hw_desc->dest_addr = seg.ds_addr; 1292 if (dst1_len != 2 * PAGE_SIZE) { 1293 hw_desc->u.control.dest_page_break = 1; 1294 nseg = -1; 1295 error = _bus_dmamap_load_phys(ioat->data_tag, 1296 desc->dst2_dmamap, dst2, PAGE_SIZE, 0, &seg, &nseg); 1297 if (error != 0) { 1298 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1299 " failed %d\n", __func__, error); 1300 return (NULL); 1301 } 1302 hw_desc->next_dest_addr = seg.ds_addr; 1303 } 1304 1305 if (g_ioat_debug_level >= 3) 1306 dump_descriptor(hw_desc); 1307 1308 ioat_submit_single(ioat); 1309 return (&desc->bus_dmadesc); 1310 } 1311 1312 struct bus_dmadesc * 1313 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1314 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1315 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1316 { 1317 struct ioat_crc32_hw_descriptor *hw_desc; 1318 struct ioat_descriptor *desc; 1319 struct ioat_softc *ioat; 1320 uint32_t teststore; 1321 uint8_t op; 1322 bus_dma_segment_t seg; 1323 int nseg, error; 1324 1325 ioat = to_ioat_softc(dmaengine); 1326 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1327 1328 KASSERT((ioat->capabilities & IOAT_DMACAP_MOVECRC) != 0, 1329 ("%s: device lacks MOVECRC capability", __func__)); 1330 teststore = (flags & _DMA_CRC_TESTSTORE); 1331 KASSERT(teststore != _DMA_CRC_TESTSTORE, 1332 ("%s: TEST and STORE invalid", __func__)); 1333 KASSERT(teststore != 0 || (flags & DMA_CRC_INLINE) == 0, 1334 ("%s: INLINE invalid without TEST or STORE", __func__)); 1335 1336 switch (teststore) { 1337 case DMA_CRC_STORE: 1338 op = IOAT_OP_MOVECRC_STORE; 1339 break; 1340 case DMA_CRC_TEST: 1341 op = IOAT_OP_MOVECRC_TEST; 1342 break; 1343 default: 1344 KASSERT(teststore == 0, ("bogus")); 1345 op = IOAT_OP_MOVECRC; 1346 break; 1347 } 1348 1349 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1350 callback_arg, flags & ~_DMA_CRC_FLAGS); 1351 if (desc == NULL) 1352 return (NULL); 1353 1354 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1355 1356 if ((flags & DMA_CRC_INLINE) == 0) { 1357 nseg = -1; 1358 error = _bus_dmamap_load_phys(ioat->data_tag, 1359 desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0, 1360 &seg, &nseg); 1361 if (error != 0) { 1362 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1363 " failed %d\n", __func__, error); 1364 return (NULL); 1365 } 1366 hw_desc->crc_address = seg.ds_addr; 1367 } else 1368 hw_desc->u.control.crc_location = 1; 1369 1370 if (initialseed != NULL) { 1371 hw_desc->u.control.use_seed = 1; 1372 hw_desc->seed = *initialseed; 1373 } 1374 1375 if (g_ioat_debug_level >= 3) 1376 dump_descriptor(hw_desc); 1377 1378 ioat_submit_single(ioat); 1379 return (&desc->bus_dmadesc); 1380 } 1381 1382 struct bus_dmadesc * 1383 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1384 uint32_t *initialseed, bus_addr_t crcptr, 1385 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1386 { 1387 struct ioat_crc32_hw_descriptor *hw_desc; 1388 struct ioat_descriptor *desc; 1389 struct ioat_softc *ioat; 1390 uint32_t teststore; 1391 uint8_t op; 1392 bus_dma_segment_t seg; 1393 int nseg, error; 1394 1395 ioat = to_ioat_softc(dmaengine); 1396 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1397 1398 KASSERT((ioat->capabilities & IOAT_DMACAP_CRC) != 0, 1399 ("%s: device lacks CRC capability", __func__)); 1400 teststore = (flags & _DMA_CRC_TESTSTORE); 1401 KASSERT(teststore != _DMA_CRC_TESTSTORE, 1402 ("%s: TEST and STORE invalid", __func__)); 1403 KASSERT(teststore != 0 || (flags & DMA_CRC_INLINE) == 0, 1404 ("%s: INLINE invalid without TEST or STORE", __func__)); 1405 1406 switch (teststore) { 1407 case DMA_CRC_STORE: 1408 op = IOAT_OP_CRC_STORE; 1409 break; 1410 case DMA_CRC_TEST: 1411 op = IOAT_OP_CRC_TEST; 1412 break; 1413 default: 1414 KASSERT(teststore == 0, ("bogus")); 1415 op = IOAT_OP_CRC; 1416 break; 1417 } 1418 1419 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1420 callback_arg, flags & ~_DMA_CRC_FLAGS); 1421 if (desc == NULL) 1422 return (NULL); 1423 1424 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1425 1426 if ((flags & DMA_CRC_INLINE) == 0) { 1427 nseg = -1; 1428 error = _bus_dmamap_load_phys(ioat->data_tag, 1429 desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0, 1430 &seg, &nseg); 1431 if (error != 0) { 1432 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1433 " failed %d\n", __func__, error); 1434 return (NULL); 1435 } 1436 hw_desc->crc_address = seg.ds_addr; 1437 } else 1438 hw_desc->u.control.crc_location = 1; 1439 1440 if (initialseed != NULL) { 1441 hw_desc->u.control.use_seed = 1; 1442 hw_desc->seed = *initialseed; 1443 } 1444 1445 if (g_ioat_debug_level >= 3) 1446 dump_descriptor(hw_desc); 1447 1448 ioat_submit_single(ioat); 1449 return (&desc->bus_dmadesc); 1450 } 1451 1452 struct bus_dmadesc * 1453 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1454 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1455 uint32_t flags) 1456 { 1457 struct ioat_fill_hw_descriptor *hw_desc; 1458 struct ioat_descriptor *desc; 1459 struct ioat_softc *ioat; 1460 1461 ioat = to_ioat_softc(dmaengine); 1462 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1463 1464 KASSERT((ioat->capabilities & IOAT_DMACAP_BFILL) != 0, 1465 ("%s: device lacks BFILL capability", __func__)); 1466 1467 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, 0, dst, 1468 callback_fn, callback_arg, flags); 1469 if (desc == NULL) 1470 return (NULL); 1471 1472 hw_desc = &ioat_get_descriptor(ioat, desc->id)->fill; 1473 hw_desc->src_data = fillpattern; 1474 if (g_ioat_debug_level >= 3) 1475 dump_descriptor(hw_desc); 1476 1477 ioat_submit_single(ioat); 1478 return (&desc->bus_dmadesc); 1479 } 1480 1481 /* 1482 * Ring Management 1483 */ 1484 static inline uint32_t 1485 ioat_get_active(struct ioat_softc *ioat) 1486 { 1487 1488 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1489 } 1490 1491 static inline uint32_t 1492 ioat_get_ring_space(struct ioat_softc *ioat) 1493 { 1494 1495 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1496 } 1497 1498 /* 1499 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1500 * for 'num_descs'. 1501 * 1502 * If mflags contains M_WAITOK, blocks until enough space is available. 1503 * 1504 * Returns zero on success, or an errno on error. If num_descs is beyond the 1505 * maximum ring size, returns EINVAl; if allocation would block and mflags 1506 * contains M_NOWAIT, returns EAGAIN. 1507 * 1508 * Must be called with the submit_lock held; returns with the lock held. The 1509 * lock may be dropped to allocate the ring. 1510 * 1511 * (The submit_lock is needed to add any entries to the ring, so callers are 1512 * assured enough room is available.) 1513 */ 1514 static int 1515 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1516 { 1517 boolean_t dug; 1518 int error; 1519 1520 mtx_assert(&ioat->submit_lock, MA_OWNED); 1521 error = 0; 1522 dug = FALSE; 1523 1524 if (num_descs < 1 || num_descs >= (1 << ioat->ring_size_order)) { 1525 error = EINVAL; 1526 goto out; 1527 } 1528 1529 for (;;) { 1530 if (ioat->quiescing) { 1531 error = ENXIO; 1532 goto out; 1533 } 1534 1535 if (ioat_get_ring_space(ioat) >= num_descs) 1536 goto out; 1537 1538 CTR3(KTR_IOAT, "%s channel=%u starved (%u)", __func__, 1539 ioat->chan_idx, num_descs); 1540 1541 if (!dug && !ioat->is_submitter_processing) { 1542 ioat->is_submitter_processing = TRUE; 1543 mtx_unlock(&ioat->submit_lock); 1544 1545 CTR2(KTR_IOAT, "%s channel=%u attempting to process events", 1546 __func__, ioat->chan_idx); 1547 ioat_process_events(ioat, FALSE); 1548 1549 mtx_lock(&ioat->submit_lock); 1550 dug = TRUE; 1551 KASSERT(ioat->is_submitter_processing == TRUE, 1552 ("is_submitter_processing")); 1553 ioat->is_submitter_processing = FALSE; 1554 wakeup(&ioat->tail); 1555 continue; 1556 } 1557 1558 if ((mflags & M_WAITOK) == 0) { 1559 error = EAGAIN; 1560 break; 1561 } 1562 CTR2(KTR_IOAT, "%s channel=%u blocking on completions", 1563 __func__, ioat->chan_idx); 1564 msleep(&ioat->tail, &ioat->submit_lock, 0, 1565 "ioat_full", 0); 1566 continue; 1567 } 1568 1569 out: 1570 mtx_assert(&ioat->submit_lock, MA_OWNED); 1571 KASSERT(!ioat->quiescing || error == ENXIO, 1572 ("reserved during quiesce")); 1573 return (error); 1574 } 1575 1576 static void 1577 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1578 struct ioat_descriptor *ring) 1579 { 1580 1581 free(ring, M_IOAT); 1582 } 1583 1584 static struct ioat_descriptor * 1585 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1586 { 1587 1588 return (&ioat->ring[index % (1 << ioat->ring_size_order)]); 1589 } 1590 1591 static union ioat_hw_descriptor * 1592 ioat_get_descriptor(struct ioat_softc *ioat, uint32_t index) 1593 { 1594 1595 return (&ioat->hw_desc_ring[index % (1 << ioat->ring_size_order)]); 1596 } 1597 1598 static void 1599 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1600 { 1601 union ioat_hw_descriptor *desc; 1602 1603 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1604 IOAT_CHANERR_STR); 1605 if (chanerr == 0) 1606 return; 1607 1608 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1609 1610 desc = ioat_get_descriptor(ioat, ioat->tail + 0); 1611 dump_descriptor(desc); 1612 1613 desc = ioat_get_descriptor(ioat, ioat->tail + 1); 1614 dump_descriptor(desc); 1615 } 1616 1617 static void 1618 ioat_poll_timer_callback(void *arg) 1619 { 1620 struct ioat_softc *ioat; 1621 1622 ioat = arg; 1623 CTR1(KTR_IOAT, "%s", __func__); 1624 1625 ioat_process_events(ioat, FALSE); 1626 1627 mtx_lock(&ioat->submit_lock); 1628 if (ioat_get_active(ioat) > 0) 1629 callout_schedule(&ioat->poll_timer, 1); 1630 mtx_unlock(&ioat->submit_lock); 1631 } 1632 1633 /* 1634 * Support Functions 1635 */ 1636 static void 1637 ioat_submit_single(struct ioat_softc *ioat) 1638 { 1639 1640 mtx_assert(&ioat->submit_lock, MA_OWNED); 1641 1642 ioat->head++; 1643 CTR4(KTR_IOAT, "%s channel=%u head=%u tail=%u", __func__, 1644 ioat->chan_idx, ioat->head, ioat->tail); 1645 1646 ioat->stats.descriptors_submitted++; 1647 } 1648 1649 static int 1650 ioat_reset_hw(struct ioat_softc *ioat) 1651 { 1652 uint64_t status; 1653 uint32_t chanerr; 1654 unsigned timeout; 1655 int error; 1656 1657 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1658 1659 mtx_lock(&ioat->submit_lock); 1660 while (ioat->resetting && !ioat->destroying) 1661 msleep(&ioat->resetting, &ioat->submit_lock, 0, "IRH_drain", 0); 1662 if (ioat->destroying) { 1663 mtx_unlock(&ioat->submit_lock); 1664 return (ENXIO); 1665 } 1666 ioat->resetting = TRUE; 1667 ioat->quiescing = TRUE; 1668 mtx_unlock(&ioat->submit_lock); 1669 mtx_lock(&ioat->cleanup_lock); 1670 while (ioat_get_active(ioat) > 0) 1671 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1); 1672 1673 /* 1674 * Suspend ioat_process_events while the hardware and softc are in an 1675 * indeterminate state. 1676 */ 1677 ioat->resetting_cleanup = TRUE; 1678 mtx_unlock(&ioat->cleanup_lock); 1679 1680 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__, 1681 ioat->chan_idx); 1682 1683 status = ioat_get_chansts(ioat); 1684 if (is_ioat_active(status) || is_ioat_idle(status)) 1685 ioat_suspend(ioat); 1686 1687 /* Wait at most 20 ms */ 1688 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1689 timeout < 20; timeout++) { 1690 DELAY(1000); 1691 status = ioat_get_chansts(ioat); 1692 } 1693 if (timeout == 20) { 1694 error = ETIMEDOUT; 1695 goto out; 1696 } 1697 1698 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1699 1700 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1701 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1702 1703 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__, 1704 ioat->chan_idx); 1705 1706 /* 1707 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1708 * that can cause stability issues for IOAT v3. 1709 */ 1710 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1711 4); 1712 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1713 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1714 1715 /* 1716 * BDXDE and BWD models reset MSI-X registers on device reset. 1717 * Save/restore their contents manually. 1718 */ 1719 if (ioat_model_resets_msix(ioat)) { 1720 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1721 pci_save_state(ioat->device); 1722 } 1723 1724 ioat_reset(ioat); 1725 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__, 1726 ioat->chan_idx); 1727 1728 /* Wait at most 20 ms */ 1729 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1730 DELAY(1000); 1731 if (timeout == 20) { 1732 error = ETIMEDOUT; 1733 goto out; 1734 } 1735 1736 if (ioat_model_resets_msix(ioat)) { 1737 ioat_log_message(1, "device resets registers; restored\n"); 1738 pci_restore_state(ioat->device); 1739 } 1740 1741 /* Reset attempts to return the hardware to "halted." */ 1742 status = ioat_get_chansts(ioat); 1743 if (is_ioat_active(status) || is_ioat_idle(status)) { 1744 /* So this really shouldn't happen... */ 1745 ioat_log_message(0, "Device is active after a reset?\n"); 1746 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1747 error = 0; 1748 goto out; 1749 } 1750 1751 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1752 if (chanerr != 0) { 1753 mtx_lock(&ioat->cleanup_lock); 1754 ioat_halted_debug(ioat, chanerr); 1755 mtx_unlock(&ioat->cleanup_lock); 1756 error = EIO; 1757 goto out; 1758 } 1759 1760 /* 1761 * Bring device back online after reset. Writing CHAINADDR brings the 1762 * device back to active. 1763 * 1764 * The internal ring counter resets to zero, so we have to start over 1765 * at zero as well. 1766 */ 1767 ioat->tail = ioat->head = 0; 1768 *ioat->comp_update = ioat->last_seen = 1769 RING_PHYS_ADDR(ioat, ioat->tail - 1); 1770 1771 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1772 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1773 ioat_write_chainaddr(ioat, RING_PHYS_ADDR(ioat, 0)); 1774 error = 0; 1775 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__, 1776 ioat->chan_idx); 1777 1778 out: 1779 /* Enqueues a null operation and ensures it completes. */ 1780 if (error == 0) { 1781 error = ioat_start_channel(ioat); 1782 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__, 1783 ioat->chan_idx); 1784 } 1785 1786 /* 1787 * Resume completions now that ring state is consistent. 1788 */ 1789 mtx_lock(&ioat->cleanup_lock); 1790 ioat->resetting_cleanup = FALSE; 1791 mtx_unlock(&ioat->cleanup_lock); 1792 1793 /* Unblock submission of new work */ 1794 mtx_lock(&ioat->submit_lock); 1795 ioat->quiescing = FALSE; 1796 wakeup(&ioat->quiescing); 1797 1798 ioat->resetting = FALSE; 1799 wakeup(&ioat->resetting); 1800 1801 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx); 1802 mtx_unlock(&ioat->submit_lock); 1803 1804 return (error); 1805 } 1806 1807 static int 1808 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1809 { 1810 struct ioat_softc *ioat; 1811 struct sbuf sb; 1812 uint64_t status; 1813 int error; 1814 1815 ioat = arg1; 1816 1817 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1818 1819 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1820 switch (status) { 1821 case IOAT_CHANSTS_ACTIVE: 1822 sbuf_printf(&sb, "ACTIVE"); 1823 break; 1824 case IOAT_CHANSTS_IDLE: 1825 sbuf_printf(&sb, "IDLE"); 1826 break; 1827 case IOAT_CHANSTS_SUSPENDED: 1828 sbuf_printf(&sb, "SUSPENDED"); 1829 break; 1830 case IOAT_CHANSTS_HALTED: 1831 sbuf_printf(&sb, "HALTED"); 1832 break; 1833 case IOAT_CHANSTS_ARMED: 1834 sbuf_printf(&sb, "ARMED"); 1835 break; 1836 default: 1837 sbuf_printf(&sb, "UNKNOWN"); 1838 break; 1839 } 1840 error = sbuf_finish(&sb); 1841 sbuf_delete(&sb); 1842 1843 if (error != 0 || req->newptr == NULL) 1844 return (error); 1845 return (EINVAL); 1846 } 1847 1848 static int 1849 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1850 { 1851 struct ioat_softc *ioat; 1852 struct sbuf sb; 1853 #define PRECISION "1" 1854 const uintmax_t factor = 10; 1855 uintmax_t rate; 1856 int error; 1857 1858 ioat = arg1; 1859 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1860 1861 if (ioat->stats.interrupts == 0) { 1862 sbuf_printf(&sb, "NaN"); 1863 goto out; 1864 } 1865 rate = ioat->stats.descriptors_processed * factor / 1866 ioat->stats.interrupts; 1867 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1868 rate % factor); 1869 #undef PRECISION 1870 out: 1871 error = sbuf_finish(&sb); 1872 sbuf_delete(&sb); 1873 if (error != 0 || req->newptr == NULL) 1874 return (error); 1875 return (EINVAL); 1876 } 1877 1878 static int 1879 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1880 { 1881 struct ioat_softc *ioat; 1882 int error, arg; 1883 1884 ioat = arg1; 1885 1886 arg = 0; 1887 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1888 if (error != 0 || req->newptr == NULL) 1889 return (error); 1890 1891 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1892 if (error != 0) 1893 return (error); 1894 1895 if (arg != 0) 1896 error = ioat_reset_hw(ioat); 1897 1898 return (error); 1899 } 1900 1901 static void 1902 dump_descriptor(void *hw_desc) 1903 { 1904 int i, j; 1905 1906 for (i = 0; i < 2; i++) { 1907 for (j = 0; j < 8; j++) 1908 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1909 printf("\n"); 1910 } 1911 } 1912 1913 static void 1914 ioat_setup_sysctl(device_t device) 1915 { 1916 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1917 struct sysctl_ctx_list *ctx; 1918 struct sysctl_oid *tree, *tmp; 1919 struct ioat_softc *ioat; 1920 1921 ioat = DEVICE2SOFTC(device); 1922 ctx = device_get_sysctl_ctx(device); 1923 tree = device_get_sysctl_tree(device); 1924 par = SYSCTL_CHILDREN(tree); 1925 1926 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1927 &ioat->version, 0, "HW version (0xMM form)"); 1928 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1929 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1930 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1931 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1932 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1933 &ioat->intrdelay_max, 0, 1934 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1935 1936 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", 1937 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IOAT channel internal state"); 1938 state = SYSCTL_CHILDREN(tmp); 1939 1940 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1941 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1942 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1943 0, "SW descriptor head pointer index"); 1944 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1945 0, "SW descriptor tail pointer index"); 1946 1947 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1948 ioat->comp_update, "HW addr of last completion"); 1949 1950 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 1951 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 1952 "submitter processing"); 1953 1954 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1955 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, ioat, 0, 1956 sysctl_handle_chansts, "A", "String of the channel status"); 1957 1958 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1959 &ioat->cached_intrdelay, 0, 1960 "Current INTRDELAY on this channel (cached, microseconds)"); 1961 1962 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", 1963 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1964 "Big hammers (mostly for testing)"); 1965 hammer = SYSCTL_CHILDREN(tmp); 1966 1967 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1968 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, ioat, 0, 1969 sysctl_handle_reset, "I", "Set to non-zero to reset the hardware"); 1970 1971 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", 1972 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IOAT channel statistics"); 1973 statpar = SYSCTL_CHILDREN(tmp); 1974 1975 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", 1976 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.interrupts, 1977 "Number of interrupts processed on this channel"); 1978 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", 1979 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_processed, 1980 "Number of descriptors processed on this channel"); 1981 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", 1982 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_submitted, 1983 "Number of descriptors submitted to this channel"); 1984 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", 1985 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_error, 1986 "Number of descriptors failed by channel errors"); 1987 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", 1988 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.channel_halts, 0, 1989 "Number of times the channel has halted"); 1990 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", 1991 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.last_halt_chanerr, 0, 1992 "The raw CHANERR when the channel was last halted"); 1993 1994 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 1995 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, ioat, 0, 1996 sysctl_handle_dpi, "A", "Descriptors per interrupt"); 1997 } 1998 1999 static void 2000 ioat_get(struct ioat_softc *ioat) 2001 { 2002 2003 mtx_assert(&ioat->submit_lock, MA_OWNED); 2004 KASSERT(ioat->refcnt < UINT32_MAX, ("refcnt overflow")); 2005 2006 ioat->refcnt++; 2007 } 2008 2009 static void 2010 ioat_put(struct ioat_softc *ioat) 2011 { 2012 2013 mtx_assert(&ioat->submit_lock, MA_OWNED); 2014 KASSERT(ioat->refcnt >= 1, ("refcnt error")); 2015 2016 if (--ioat->refcnt == 0) 2017 wakeup(&ioat->refcnt); 2018 } 2019 2020 static void 2021 ioat_drain_locked(struct ioat_softc *ioat) 2022 { 2023 2024 mtx_assert(&ioat->submit_lock, MA_OWNED); 2025 2026 while (ioat->refcnt > 0) 2027 msleep(&ioat->refcnt, &ioat->submit_lock, 0, "ioat_drain", 0); 2028 } 2029 2030 #ifdef DDB 2031 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 2032 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 2033 DB_SHOW_COMMAND(ioat, db_show_ioat) 2034 { 2035 struct ioat_softc *sc; 2036 unsigned idx; 2037 2038 if (!have_addr) 2039 goto usage; 2040 idx = (unsigned)addr; 2041 if (idx >= ioat_channel_index) 2042 goto usage; 2043 2044 sc = ioat_channel[idx]; 2045 db_printf("ioat softc at %p\n", sc); 2046 if (sc == NULL) 2047 return; 2048 2049 db_printf(" version: %d\n", sc->version); 2050 db_printf(" chan_idx: %u\n", sc->chan_idx); 2051 db_printf(" submit_lock: "); 2052 db_show_lock(&sc->submit_lock); 2053 2054 db_printf(" capabilities: %b\n", (int)sc->capabilities, 2055 IOAT_DMACAP_STR); 2056 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 2057 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 2058 2059 db_printf(" poll_timer:\n"); 2060 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 2061 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 2062 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 2063 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 2064 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 2065 2066 db_printf(" quiescing: %d\n", (int)sc->quiescing); 2067 db_printf(" destroying: %d\n", (int)sc->destroying); 2068 db_printf(" is_submitter_processing: %d\n", 2069 (int)sc->is_submitter_processing); 2070 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 2071 db_printf(" resetting: %d\n", (int)sc->resetting); 2072 2073 db_printf(" head: %u\n", sc->head); 2074 db_printf(" tail: %u\n", sc->tail); 2075 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2076 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2077 db_printf(" ring: %p\n", sc->ring); 2078 db_printf(" descriptors: %p\n", sc->hw_desc_ring); 2079 db_printf(" descriptors (phys): 0x%jx\n", 2080 (uintmax_t)sc->hw_desc_bus_addr); 2081 2082 db_printf(" ring[%u] (tail):\n", sc->tail % 2083 (1 << sc->ring_size_order)); 2084 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 2085 db_printf(" addr: 0x%lx\n", 2086 RING_PHYS_ADDR(sc, sc->tail)); 2087 db_printf(" next: 0x%lx\n", 2088 ioat_get_descriptor(sc, sc->tail)->generic.next); 2089 2090 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 2091 (1 << sc->ring_size_order)); 2092 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 2093 db_printf(" addr: 0x%lx\n", 2094 RING_PHYS_ADDR(sc, sc->head - 1)); 2095 db_printf(" next: 0x%lx\n", 2096 ioat_get_descriptor(sc, sc->head - 1)->generic.next); 2097 2098 db_printf(" ring[%u] (head):\n", (sc->head) % 2099 (1 << sc->ring_size_order)); 2100 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2101 db_printf(" addr: 0x%lx\n", 2102 RING_PHYS_ADDR(sc, sc->head)); 2103 db_printf(" next: 0x%lx\n", 2104 ioat_get_descriptor(sc, sc->head)->generic.next); 2105 2106 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2107 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2108 == RING_PHYS_ADDR(sc, idx)) 2109 db_printf(" ring[%u] == hardware tail\n", idx); 2110 2111 db_printf(" cleanup_lock: "); 2112 db_show_lock(&sc->cleanup_lock); 2113 2114 db_printf(" refcnt: %u\n", sc->refcnt); 2115 db_printf(" stats:\n"); 2116 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2117 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2118 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2119 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2120 2121 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2122 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2123 2124 if (db_pager_quit) 2125 return; 2126 2127 db_printf(" hw status:\n"); 2128 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2129 db_printf(" chanctrl: 0x%x\n", 2130 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2131 db_printf(" chancmd: 0x%x\n", 2132 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2133 db_printf(" dmacount: 0x%x\n", 2134 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2135 db_printf(" chainaddr: 0x%lx\n", 2136 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2137 db_printf(" chancmp: 0x%lx\n", 2138 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2139 db_printf(" chanerr: %b\n", 2140 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2141 return; 2142 usage: 2143 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2144 return; 2145 } 2146 #endif /* DDB */ 2147