1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/ioccom.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/sbuf.h> 42 #include <sys/sysctl.h> 43 #include <sys/time.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <machine/stdarg.h> 49 50 #include "ioat.h" 51 #include "ioat_hw.h" 52 #include "ioat_internal.h" 53 54 #define IOAT_INTR_TIMO (hz / 10) 55 #define IOAT_REFLK (&ioat->submit_lock) 56 57 static int ioat_probe(device_t device); 58 static int ioat_attach(device_t device); 59 static int ioat_detach(device_t device); 60 static int ioat_setup_intr(struct ioat_softc *ioat); 61 static int ioat_teardown_intr(struct ioat_softc *ioat); 62 static int ioat3_attach(device_t device); 63 static int ioat_start_channel(struct ioat_softc *ioat); 64 static int ioat_map_pci_bar(struct ioat_softc *ioat); 65 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 66 int error); 67 static void ioat_interrupt_handler(void *arg); 68 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 69 static int chanerr_to_errno(uint32_t); 70 static void ioat_process_events(struct ioat_softc *ioat); 71 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 72 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 73 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 74 struct ioat_descriptor **); 75 static void ioat_free_ring_entry(struct ioat_softc *ioat, 76 struct ioat_descriptor *desc); 77 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 78 int mflags); 79 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 80 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 81 uint32_t index); 82 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 83 uint32_t size, boolean_t need_dscr, int mflags); 84 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 85 struct ioat_descriptor **); 86 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 87 struct ioat_descriptor **); 88 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 89 static void ioat_timer_callback(void *arg); 90 static void dump_descriptor(void *hw_desc); 91 static void ioat_submit_single(struct ioat_softc *ioat); 92 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 93 int error); 94 static int ioat_reset_hw(struct ioat_softc *ioat); 95 static void ioat_setup_sysctl(device_t device); 96 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 97 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 98 enum ioat_ref_kind); 99 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 100 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 101 enum ioat_ref_kind, boolean_t); 102 static inline void ioat_putn(struct ioat_softc *, uint32_t, 103 enum ioat_ref_kind); 104 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 105 enum ioat_ref_kind); 106 static void ioat_drain_locked(struct ioat_softc *); 107 108 #define ioat_log_message(v, ...) do { \ 109 if ((v) <= g_ioat_debug_level) { \ 110 device_printf(ioat->device, __VA_ARGS__); \ 111 } \ 112 } while (0) 113 114 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 115 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 116 117 static int g_force_legacy_interrupts; 118 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 119 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 120 121 int g_ioat_debug_level = 0; 122 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 123 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 124 125 /* 126 * OS <-> Driver interface structures 127 */ 128 static device_method_t ioat_pci_methods[] = { 129 /* Device interface */ 130 DEVMETHOD(device_probe, ioat_probe), 131 DEVMETHOD(device_attach, ioat_attach), 132 DEVMETHOD(device_detach, ioat_detach), 133 { 0, 0 } 134 }; 135 136 static driver_t ioat_pci_driver = { 137 "ioat", 138 ioat_pci_methods, 139 sizeof(struct ioat_softc), 140 }; 141 142 static devclass_t ioat_devclass; 143 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 144 MODULE_VERSION(ioat, 1); 145 146 /* 147 * Private data structures 148 */ 149 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 150 static int ioat_channel_index = 0; 151 SYSCTL_INT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 152 "Number of IOAT channels attached"); 153 154 static struct _pcsid 155 { 156 u_int32_t type; 157 const char *desc; 158 } pci_ids[] = { 159 { 0x34308086, "TBG IOAT Ch0" }, 160 { 0x34318086, "TBG IOAT Ch1" }, 161 { 0x34328086, "TBG IOAT Ch2" }, 162 { 0x34338086, "TBG IOAT Ch3" }, 163 { 0x34298086, "TBG IOAT Ch4" }, 164 { 0x342a8086, "TBG IOAT Ch5" }, 165 { 0x342b8086, "TBG IOAT Ch6" }, 166 { 0x342c8086, "TBG IOAT Ch7" }, 167 168 { 0x37108086, "JSF IOAT Ch0" }, 169 { 0x37118086, "JSF IOAT Ch1" }, 170 { 0x37128086, "JSF IOAT Ch2" }, 171 { 0x37138086, "JSF IOAT Ch3" }, 172 { 0x37148086, "JSF IOAT Ch4" }, 173 { 0x37158086, "JSF IOAT Ch5" }, 174 { 0x37168086, "JSF IOAT Ch6" }, 175 { 0x37178086, "JSF IOAT Ch7" }, 176 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 177 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 178 179 { 0x3c208086, "SNB IOAT Ch0" }, 180 { 0x3c218086, "SNB IOAT Ch1" }, 181 { 0x3c228086, "SNB IOAT Ch2" }, 182 { 0x3c238086, "SNB IOAT Ch3" }, 183 { 0x3c248086, "SNB IOAT Ch4" }, 184 { 0x3c258086, "SNB IOAT Ch5" }, 185 { 0x3c268086, "SNB IOAT Ch6" }, 186 { 0x3c278086, "SNB IOAT Ch7" }, 187 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 188 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 189 190 { 0x0e208086, "IVB IOAT Ch0" }, 191 { 0x0e218086, "IVB IOAT Ch1" }, 192 { 0x0e228086, "IVB IOAT Ch2" }, 193 { 0x0e238086, "IVB IOAT Ch3" }, 194 { 0x0e248086, "IVB IOAT Ch4" }, 195 { 0x0e258086, "IVB IOAT Ch5" }, 196 { 0x0e268086, "IVB IOAT Ch6" }, 197 { 0x0e278086, "IVB IOAT Ch7" }, 198 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 199 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 200 201 { 0x2f208086, "HSW IOAT Ch0" }, 202 { 0x2f218086, "HSW IOAT Ch1" }, 203 { 0x2f228086, "HSW IOAT Ch2" }, 204 { 0x2f238086, "HSW IOAT Ch3" }, 205 { 0x2f248086, "HSW IOAT Ch4" }, 206 { 0x2f258086, "HSW IOAT Ch5" }, 207 { 0x2f268086, "HSW IOAT Ch6" }, 208 { 0x2f278086, "HSW IOAT Ch7" }, 209 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 210 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 211 212 { 0x0c508086, "BWD IOAT Ch0" }, 213 { 0x0c518086, "BWD IOAT Ch1" }, 214 { 0x0c528086, "BWD IOAT Ch2" }, 215 { 0x0c538086, "BWD IOAT Ch3" }, 216 217 { 0x6f508086, "BDXDE IOAT Ch0" }, 218 { 0x6f518086, "BDXDE IOAT Ch1" }, 219 { 0x6f528086, "BDXDE IOAT Ch2" }, 220 { 0x6f538086, "BDXDE IOAT Ch3" }, 221 222 { 0x6f208086, "BDX IOAT Ch0" }, 223 { 0x6f218086, "BDX IOAT Ch1" }, 224 { 0x6f228086, "BDX IOAT Ch2" }, 225 { 0x6f238086, "BDX IOAT Ch3" }, 226 { 0x6f248086, "BDX IOAT Ch4" }, 227 { 0x6f258086, "BDX IOAT Ch5" }, 228 { 0x6f268086, "BDX IOAT Ch6" }, 229 { 0x6f278086, "BDX IOAT Ch7" }, 230 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 231 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 232 233 { 0x00000000, NULL } 234 }; 235 236 /* 237 * OS <-> Driver linkage functions 238 */ 239 static int 240 ioat_probe(device_t device) 241 { 242 struct _pcsid *ep; 243 u_int32_t type; 244 245 type = pci_get_devid(device); 246 for (ep = pci_ids; ep->type; ep++) { 247 if (ep->type == type) { 248 device_set_desc(device, ep->desc); 249 return (0); 250 } 251 } 252 return (ENXIO); 253 } 254 255 static int 256 ioat_attach(device_t device) 257 { 258 struct ioat_softc *ioat; 259 int error; 260 261 ioat = DEVICE2SOFTC(device); 262 ioat->device = device; 263 264 error = ioat_map_pci_bar(ioat); 265 if (error != 0) 266 goto err; 267 268 ioat->version = ioat_read_cbver(ioat); 269 if (ioat->version < IOAT_VER_3_0) { 270 error = ENODEV; 271 goto err; 272 } 273 274 error = ioat3_attach(device); 275 if (error != 0) 276 goto err; 277 278 error = pci_enable_busmaster(device); 279 if (error != 0) 280 goto err; 281 282 error = ioat_setup_intr(ioat); 283 if (error != 0) 284 goto err; 285 286 error = ioat_reset_hw(ioat); 287 if (error != 0) 288 goto err; 289 290 ioat_process_events(ioat); 291 ioat_setup_sysctl(device); 292 293 ioat->chan_idx = ioat_channel_index; 294 ioat_channel[ioat_channel_index++] = ioat; 295 ioat_test_attach(); 296 297 err: 298 if (error != 0) 299 ioat_detach(device); 300 return (error); 301 } 302 303 static int 304 ioat_detach(device_t device) 305 { 306 struct ioat_softc *ioat; 307 308 ioat = DEVICE2SOFTC(device); 309 310 ioat_test_detach(); 311 312 mtx_lock(IOAT_REFLK); 313 ioat->quiescing = TRUE; 314 ioat_channel[ioat->chan_idx] = NULL; 315 316 ioat_drain_locked(ioat); 317 mtx_unlock(IOAT_REFLK); 318 319 ioat_teardown_intr(ioat); 320 callout_drain(&ioat->timer); 321 322 pci_disable_busmaster(device); 323 324 if (ioat->pci_resource != NULL) 325 bus_release_resource(device, SYS_RES_MEMORY, 326 ioat->pci_resource_id, ioat->pci_resource); 327 328 if (ioat->ring != NULL) 329 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 330 331 if (ioat->comp_update != NULL) { 332 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 333 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 334 ioat->comp_update_map); 335 bus_dma_tag_destroy(ioat->comp_update_tag); 336 } 337 338 bus_dma_tag_destroy(ioat->hw_desc_tag); 339 340 return (0); 341 } 342 343 static int 344 ioat_teardown_intr(struct ioat_softc *ioat) 345 { 346 347 if (ioat->tag != NULL) 348 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 349 350 if (ioat->res != NULL) 351 bus_release_resource(ioat->device, SYS_RES_IRQ, 352 rman_get_rid(ioat->res), ioat->res); 353 354 pci_release_msi(ioat->device); 355 return (0); 356 } 357 358 static int 359 ioat_start_channel(struct ioat_softc *ioat) 360 { 361 uint64_t status; 362 uint32_t chanerr; 363 int i; 364 365 ioat_acquire(&ioat->dmaengine); 366 ioat_null(&ioat->dmaengine, NULL, NULL, 0); 367 ioat_release(&ioat->dmaengine); 368 369 for (i = 0; i < 100; i++) { 370 DELAY(1); 371 status = ioat_get_chansts(ioat); 372 if (is_ioat_idle(status)) 373 return (0); 374 } 375 376 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 377 ioat_log_message(0, "could not start channel: " 378 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 379 IOAT_CHANERR_STR); 380 return (ENXIO); 381 } 382 383 /* 384 * Initialize Hardware 385 */ 386 static int 387 ioat3_attach(device_t device) 388 { 389 struct ioat_softc *ioat; 390 struct ioat_descriptor **ring; 391 struct ioat_descriptor *next; 392 struct ioat_dma_hw_descriptor *dma_hw_desc; 393 int i, num_descriptors; 394 int error; 395 uint8_t xfercap; 396 397 error = 0; 398 ioat = DEVICE2SOFTC(device); 399 ioat->capabilities = ioat_read_dmacapability(ioat); 400 401 ioat_log_message(1, "Capabilities: %b\n", (int)ioat->capabilities, 402 IOAT_DMACAP_STR); 403 404 xfercap = ioat_read_xfercap(ioat); 405 ioat->max_xfer_size = 1 << xfercap; 406 407 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 408 IOAT_INTRDELAY_SUPPORTED) != 0; 409 if (ioat->intrdelay_supported) 410 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 411 412 /* TODO: need to check DCA here if we ever do XOR/PQ */ 413 414 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 415 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 416 callout_init(&ioat->timer, 1); 417 418 /* Establish lock order for Witness */ 419 mtx_lock(&ioat->submit_lock); 420 mtx_lock(&ioat->cleanup_lock); 421 mtx_unlock(&ioat->cleanup_lock); 422 mtx_unlock(&ioat->submit_lock); 423 424 ioat->is_resize_pending = FALSE; 425 ioat->is_completion_pending = FALSE; 426 ioat->is_reset_pending = FALSE; 427 ioat->is_channel_running = FALSE; 428 429 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 430 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 431 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 432 &ioat->comp_update_tag); 433 434 error = bus_dmamem_alloc(ioat->comp_update_tag, 435 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 436 if (ioat->comp_update == NULL) 437 return (ENOMEM); 438 439 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 440 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 441 0); 442 if (error != 0) 443 return (error); 444 445 ioat->ring_size_order = IOAT_MIN_ORDER; 446 447 num_descriptors = 1 << ioat->ring_size_order; 448 449 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 450 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 451 sizeof(struct ioat_dma_hw_descriptor), 1, 452 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 453 &ioat->hw_desc_tag); 454 455 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 456 M_ZERO | M_WAITOK); 457 if (ioat->ring == NULL) 458 return (ENOMEM); 459 460 ring = ioat->ring; 461 for (i = 0; i < num_descriptors; i++) { 462 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 463 if (ring[i] == NULL) 464 return (ENOMEM); 465 466 ring[i]->id = i; 467 } 468 469 for (i = 0; i < num_descriptors - 1; i++) { 470 next = ring[i + 1]; 471 dma_hw_desc = ring[i]->u.dma; 472 473 dma_hw_desc->next = next->hw_desc_bus_addr; 474 } 475 476 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 477 478 ioat->head = ioat->hw_head = 0; 479 ioat->tail = 0; 480 ioat->last_seen = 0; 481 return (0); 482 } 483 484 static int 485 ioat_map_pci_bar(struct ioat_softc *ioat) 486 { 487 488 ioat->pci_resource_id = PCIR_BAR(0); 489 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 490 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 491 492 if (ioat->pci_resource == NULL) { 493 ioat_log_message(0, "unable to allocate pci resource\n"); 494 return (ENODEV); 495 } 496 497 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 498 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 499 return (0); 500 } 501 502 static void 503 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 504 { 505 struct ioat_softc *ioat = arg; 506 507 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 508 ioat->comp_update_bus_addr = seg[0].ds_addr; 509 } 510 511 static void 512 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 513 { 514 bus_addr_t *baddr; 515 516 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 517 baddr = arg; 518 *baddr = segs->ds_addr; 519 } 520 521 /* 522 * Interrupt setup and handlers 523 */ 524 static int 525 ioat_setup_intr(struct ioat_softc *ioat) 526 { 527 uint32_t num_vectors; 528 int error; 529 boolean_t use_msix; 530 boolean_t force_legacy_interrupts; 531 532 use_msix = FALSE; 533 force_legacy_interrupts = FALSE; 534 535 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 536 num_vectors = 1; 537 pci_alloc_msix(ioat->device, &num_vectors); 538 if (num_vectors == 1) 539 use_msix = TRUE; 540 } 541 542 if (use_msix) { 543 ioat->rid = 1; 544 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 545 &ioat->rid, RF_ACTIVE); 546 } else { 547 ioat->rid = 0; 548 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 549 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 550 } 551 if (ioat->res == NULL) { 552 ioat_log_message(0, "bus_alloc_resource failed\n"); 553 return (ENOMEM); 554 } 555 556 ioat->tag = NULL; 557 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 558 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 559 if (error != 0) { 560 ioat_log_message(0, "bus_setup_intr failed\n"); 561 return (error); 562 } 563 564 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 565 return (0); 566 } 567 568 static boolean_t 569 ioat_model_resets_msix(struct ioat_softc *ioat) 570 { 571 u_int32_t pciid; 572 573 pciid = pci_get_devid(ioat->device); 574 switch (pciid) { 575 /* BWD: */ 576 case 0x0c508086: 577 case 0x0c518086: 578 case 0x0c528086: 579 case 0x0c538086: 580 /* BDXDE: */ 581 case 0x6f508086: 582 case 0x6f518086: 583 case 0x6f528086: 584 case 0x6f538086: 585 return (TRUE); 586 } 587 588 return (FALSE); 589 } 590 591 static void 592 ioat_interrupt_handler(void *arg) 593 { 594 struct ioat_softc *ioat = arg; 595 596 ioat->stats.interrupts++; 597 ioat_process_events(ioat); 598 } 599 600 static int 601 chanerr_to_errno(uint32_t chanerr) 602 { 603 604 if (chanerr == 0) 605 return (0); 606 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 607 return (EFAULT); 608 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 609 return (EIO); 610 /* This one is probably our fault: */ 611 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 612 return (EIO); 613 return (EIO); 614 } 615 616 static void 617 ioat_process_events(struct ioat_softc *ioat) 618 { 619 struct ioat_descriptor *desc; 620 struct bus_dmadesc *dmadesc; 621 uint64_t comp_update, status; 622 uint32_t completed, chanerr; 623 int error; 624 625 mtx_lock(&ioat->cleanup_lock); 626 627 completed = 0; 628 comp_update = *ioat->comp_update; 629 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 630 631 CTR0(KTR_IOAT, __func__); 632 633 if (status == ioat->last_seen) 634 goto out; 635 636 while (1) { 637 desc = ioat_get_ring_entry(ioat, ioat->tail); 638 dmadesc = &desc->bus_dmadesc; 639 CTR1(KTR_IOAT, "completing desc %d", ioat->tail); 640 641 if (dmadesc->callback_fn != NULL) 642 dmadesc->callback_fn(dmadesc->callback_arg, 0); 643 644 completed++; 645 ioat->tail++; 646 if (desc->hw_desc_bus_addr == status) 647 break; 648 } 649 650 ioat->last_seen = desc->hw_desc_bus_addr; 651 652 if (ioat->head == ioat->tail) { 653 ioat->is_completion_pending = FALSE; 654 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 655 ioat_timer_callback, ioat); 656 } 657 658 ioat->stats.descriptors_processed += completed; 659 660 out: 661 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 662 mtx_unlock(&ioat->cleanup_lock); 663 664 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 665 wakeup(&ioat->tail); 666 667 if (!is_ioat_halted(comp_update)) 668 return; 669 670 ioat->stats.channel_halts++; 671 672 /* 673 * Fatal programming error on this DMA channel. Flush any outstanding 674 * work with error status and restart the engine. 675 */ 676 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 677 mtx_lock(&ioat->submit_lock); 678 mtx_lock(&ioat->cleanup_lock); 679 ioat->quiescing = TRUE; 680 681 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 682 ioat_halted_debug(ioat, chanerr); 683 ioat->stats.last_halt_chanerr = chanerr; 684 685 while (ioat_get_active(ioat) > 0) { 686 desc = ioat_get_ring_entry(ioat, ioat->tail); 687 dmadesc = &desc->bus_dmadesc; 688 CTR1(KTR_IOAT, "completing err desc %d", ioat->tail); 689 690 if (dmadesc->callback_fn != NULL) 691 dmadesc->callback_fn(dmadesc->callback_arg, 692 chanerr_to_errno(chanerr)); 693 694 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 695 ioat->tail++; 696 ioat->stats.descriptors_processed++; 697 ioat->stats.descriptors_error++; 698 } 699 700 /* Clear error status */ 701 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 702 703 mtx_unlock(&ioat->cleanup_lock); 704 mtx_unlock(&ioat->submit_lock); 705 706 ioat_log_message(0, "Resetting channel to recover from error\n"); 707 error = ioat_reset_hw(ioat); 708 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 709 } 710 711 /* 712 * User API functions 713 */ 714 bus_dmaengine_t 715 ioat_get_dmaengine(uint32_t index) 716 { 717 struct ioat_softc *sc; 718 719 if (index >= ioat_channel_index) 720 return (NULL); 721 722 sc = ioat_channel[index]; 723 if (sc == NULL || sc->quiescing) 724 return (NULL); 725 726 return (&ioat_get(sc, IOAT_DMAENGINE_REF)->dmaengine); 727 } 728 729 void 730 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 731 { 732 struct ioat_softc *ioat; 733 734 ioat = to_ioat_softc(dmaengine); 735 ioat_put(ioat, IOAT_DMAENGINE_REF); 736 } 737 738 int 739 ioat_get_hwversion(bus_dmaengine_t dmaengine) 740 { 741 struct ioat_softc *ioat; 742 743 ioat = to_ioat_softc(dmaengine); 744 return (ioat->version); 745 } 746 747 int 748 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 749 { 750 struct ioat_softc *ioat; 751 752 ioat = to_ioat_softc(dmaengine); 753 if (!ioat->intrdelay_supported) 754 return (ENODEV); 755 if (delay > ioat->intrdelay_max) 756 return (ERANGE); 757 758 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 759 ioat->cached_intrdelay = 760 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 761 return (0); 762 } 763 764 uint16_t 765 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 766 { 767 struct ioat_softc *ioat; 768 769 ioat = to_ioat_softc(dmaengine); 770 return (ioat->intrdelay_max); 771 } 772 773 void 774 ioat_acquire(bus_dmaengine_t dmaengine) 775 { 776 struct ioat_softc *ioat; 777 778 ioat = to_ioat_softc(dmaengine); 779 mtx_lock(&ioat->submit_lock); 780 CTR0(KTR_IOAT, __func__); 781 } 782 783 void 784 ioat_release(bus_dmaengine_t dmaengine) 785 { 786 struct ioat_softc *ioat; 787 788 ioat = to_ioat_softc(dmaengine); 789 CTR0(KTR_IOAT, __func__); 790 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 791 mtx_unlock(&ioat->submit_lock); 792 } 793 794 static struct ioat_descriptor * 795 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 796 uint32_t size, uint64_t src, uint64_t dst, 797 bus_dmaengine_callback_t callback_fn, void *callback_arg, 798 uint32_t flags) 799 { 800 struct ioat_generic_hw_descriptor *hw_desc; 801 struct ioat_descriptor *desc; 802 int mflags; 803 804 mtx_assert(&ioat->submit_lock, MA_OWNED); 805 806 KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x", 807 flags & ~DMA_ALL_FLAGS)); 808 if ((flags & DMA_NO_WAIT) != 0) 809 mflags = M_NOWAIT; 810 else 811 mflags = M_WAITOK; 812 813 if (size > ioat->max_xfer_size) { 814 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 815 __func__, ioat->max_xfer_size, (unsigned)size); 816 return (NULL); 817 } 818 819 if (ioat_reserve_space(ioat, 1, mflags) != 0) 820 return (NULL); 821 822 desc = ioat_get_ring_entry(ioat, ioat->head); 823 hw_desc = desc->u.generic; 824 825 hw_desc->u.control_raw = 0; 826 hw_desc->u.control_generic.op = op; 827 hw_desc->u.control_generic.completion_update = 1; 828 829 if ((flags & DMA_INT_EN) != 0) 830 hw_desc->u.control_generic.int_enable = 1; 831 832 hw_desc->size = size; 833 hw_desc->src_addr = src; 834 hw_desc->dest_addr = dst; 835 836 desc->bus_dmadesc.callback_fn = callback_fn; 837 desc->bus_dmadesc.callback_arg = callback_arg; 838 return (desc); 839 } 840 841 struct bus_dmadesc * 842 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 843 void *callback_arg, uint32_t flags) 844 { 845 struct ioat_dma_hw_descriptor *hw_desc; 846 struct ioat_descriptor *desc; 847 struct ioat_softc *ioat; 848 849 CTR0(KTR_IOAT, __func__); 850 ioat = to_ioat_softc(dmaengine); 851 852 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 853 callback_arg, flags); 854 if (desc == NULL) 855 return (NULL); 856 857 hw_desc = desc->u.dma; 858 hw_desc->u.control.null = 1; 859 ioat_submit_single(ioat); 860 return (&desc->bus_dmadesc); 861 } 862 863 struct bus_dmadesc * 864 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 865 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 866 void *callback_arg, uint32_t flags) 867 { 868 struct ioat_dma_hw_descriptor *hw_desc; 869 struct ioat_descriptor *desc; 870 struct ioat_softc *ioat; 871 872 CTR0(KTR_IOAT, __func__); 873 ioat = to_ioat_softc(dmaengine); 874 875 if (((src | dst) & (0xffffull << 48)) != 0) { 876 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 877 __func__); 878 return (NULL); 879 } 880 881 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 882 callback_arg, flags); 883 if (desc == NULL) 884 return (NULL); 885 886 hw_desc = desc->u.dma; 887 if (g_ioat_debug_level >= 3) 888 dump_descriptor(hw_desc); 889 890 ioat_submit_single(ioat); 891 return (&desc->bus_dmadesc); 892 } 893 894 struct bus_dmadesc * 895 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 896 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 897 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 898 { 899 struct ioat_dma_hw_descriptor *hw_desc; 900 struct ioat_descriptor *desc; 901 struct ioat_softc *ioat; 902 903 CTR0(KTR_IOAT, __func__); 904 ioat = to_ioat_softc(dmaengine); 905 906 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 907 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 908 __func__); 909 return (NULL); 910 } 911 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 912 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 913 __func__); 914 return (NULL); 915 } 916 917 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 918 callback_fn, callback_arg, flags); 919 if (desc == NULL) 920 return (NULL); 921 922 hw_desc = desc->u.dma; 923 if (src2 != src1 + PAGE_SIZE) { 924 hw_desc->u.control.src_page_break = 1; 925 hw_desc->next_src_addr = src2; 926 } 927 if (dst2 != dst1 + PAGE_SIZE) { 928 hw_desc->u.control.dest_page_break = 1; 929 hw_desc->next_dest_addr = dst2; 930 } 931 932 if (g_ioat_debug_level >= 3) 933 dump_descriptor(hw_desc); 934 935 ioat_submit_single(ioat); 936 return (&desc->bus_dmadesc); 937 } 938 939 struct bus_dmadesc * 940 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 941 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 942 uint32_t flags) 943 { 944 struct ioat_fill_hw_descriptor *hw_desc; 945 struct ioat_descriptor *desc; 946 struct ioat_softc *ioat; 947 948 CTR0(KTR_IOAT, __func__); 949 ioat = to_ioat_softc(dmaengine); 950 951 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 952 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 953 __func__); 954 return (NULL); 955 } 956 957 if ((dst & (0xffffull << 48)) != 0) { 958 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 959 __func__); 960 return (NULL); 961 } 962 963 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 964 callback_fn, callback_arg, flags); 965 if (desc == NULL) 966 return (NULL); 967 968 hw_desc = desc->u.fill; 969 if (g_ioat_debug_level >= 3) 970 dump_descriptor(hw_desc); 971 972 ioat_submit_single(ioat); 973 return (&desc->bus_dmadesc); 974 } 975 976 /* 977 * Ring Management 978 */ 979 static inline uint32_t 980 ioat_get_active(struct ioat_softc *ioat) 981 { 982 983 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 984 } 985 986 static inline uint32_t 987 ioat_get_ring_space(struct ioat_softc *ioat) 988 { 989 990 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 991 } 992 993 static struct ioat_descriptor * 994 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 995 { 996 struct ioat_generic_hw_descriptor *hw_desc; 997 struct ioat_descriptor *desc; 998 int error, busdmaflag; 999 1000 error = ENOMEM; 1001 hw_desc = NULL; 1002 1003 if ((mflags & M_WAITOK) != 0) 1004 busdmaflag = BUS_DMA_WAITOK; 1005 else 1006 busdmaflag = BUS_DMA_NOWAIT; 1007 1008 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1009 if (desc == NULL) 1010 goto out; 1011 1012 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1013 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1014 if (hw_desc == NULL) 1015 goto out; 1016 1017 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1018 desc->u.generic = hw_desc; 1019 1020 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1021 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1022 busdmaflag); 1023 if (error) 1024 goto out; 1025 1026 out: 1027 if (error) { 1028 ioat_free_ring_entry(ioat, desc); 1029 return (NULL); 1030 } 1031 return (desc); 1032 } 1033 1034 static void 1035 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1036 { 1037 1038 if (desc == NULL) 1039 return; 1040 1041 if (desc->u.generic) 1042 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1043 ioat->hw_desc_map); 1044 free(desc, M_IOAT); 1045 } 1046 1047 /* 1048 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1049 * for 'num_descs'. 1050 * 1051 * If mflags contains M_WAITOK, blocks until enough space is available. 1052 * 1053 * Returns zero on success, or an errno on error. If num_descs is beyond the 1054 * maximum ring size, returns EINVAl; if allocation would block and mflags 1055 * contains M_NOWAIT, returns EAGAIN. 1056 * 1057 * Must be called with the submit_lock held; returns with the lock held. The 1058 * lock may be dropped to allocate the ring. 1059 * 1060 * (The submit_lock is needed to add any entries to the ring, so callers are 1061 * assured enough room is available.) 1062 */ 1063 static int 1064 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1065 { 1066 struct ioat_descriptor **new_ring; 1067 uint32_t order; 1068 int error; 1069 1070 mtx_assert(&ioat->submit_lock, MA_OWNED); 1071 error = 0; 1072 1073 if (num_descs < 1 || num_descs > (1 << IOAT_MAX_ORDER)) { 1074 error = EINVAL; 1075 goto out; 1076 } 1077 if (ioat->quiescing) { 1078 error = ENXIO; 1079 goto out; 1080 } 1081 1082 for (;;) { 1083 if (ioat_get_ring_space(ioat) >= num_descs) 1084 goto out; 1085 1086 order = ioat->ring_size_order; 1087 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1088 if ((mflags & M_WAITOK) != 0) { 1089 msleep(&ioat->tail, &ioat->submit_lock, 0, 1090 "ioat_rsz", 0); 1091 continue; 1092 } 1093 1094 error = EAGAIN; 1095 break; 1096 } 1097 1098 ioat->is_resize_pending = TRUE; 1099 for (;;) { 1100 mtx_unlock(&ioat->submit_lock); 1101 1102 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1103 TRUE, mflags); 1104 1105 mtx_lock(&ioat->submit_lock); 1106 KASSERT(ioat->ring_size_order == order, 1107 ("is_resize_pending should protect order")); 1108 1109 if (new_ring == NULL) { 1110 KASSERT((mflags & M_WAITOK) == 0, 1111 ("allocation failed")); 1112 error = EAGAIN; 1113 break; 1114 } 1115 1116 error = ring_grow(ioat, order, new_ring); 1117 if (error == 0) 1118 break; 1119 } 1120 ioat->is_resize_pending = FALSE; 1121 wakeup(&ioat->tail); 1122 if (error) 1123 break; 1124 } 1125 1126 out: 1127 mtx_assert(&ioat->submit_lock, MA_OWNED); 1128 return (error); 1129 } 1130 1131 static struct ioat_descriptor ** 1132 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1133 int mflags) 1134 { 1135 struct ioat_descriptor **ring; 1136 uint32_t i; 1137 int error; 1138 1139 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1140 1141 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1142 if (ring == NULL) 1143 return (NULL); 1144 1145 if (need_dscr) { 1146 error = ENOMEM; 1147 for (i = size / 2; i < size; i++) { 1148 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1149 if (ring[i] == NULL) 1150 goto out; 1151 ring[i]->id = i; 1152 } 1153 } 1154 error = 0; 1155 1156 out: 1157 if (error != 0 && ring != NULL) { 1158 ioat_free_ring(ioat, size, ring); 1159 ring = NULL; 1160 } 1161 return (ring); 1162 } 1163 1164 static void 1165 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1166 struct ioat_descriptor **ring) 1167 { 1168 uint32_t i; 1169 1170 for (i = 0; i < size; i++) { 1171 if (ring[i] != NULL) 1172 ioat_free_ring_entry(ioat, ring[i]); 1173 } 1174 free(ring, M_IOAT); 1175 } 1176 1177 static struct ioat_descriptor * 1178 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1179 { 1180 1181 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1182 } 1183 1184 static int 1185 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1186 struct ioat_descriptor **newring) 1187 { 1188 struct ioat_descriptor *tmp, *next; 1189 struct ioat_dma_hw_descriptor *hw; 1190 uint32_t oldsize, newsize, head, tail, i, end; 1191 int error; 1192 1193 CTR0(KTR_IOAT, __func__); 1194 1195 mtx_assert(&ioat->submit_lock, MA_OWNED); 1196 1197 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1198 error = EINVAL; 1199 goto out; 1200 } 1201 1202 oldsize = (1 << oldorder); 1203 newsize = (1 << (oldorder + 1)); 1204 1205 mtx_lock(&ioat->cleanup_lock); 1206 1207 head = ioat->head & (oldsize - 1); 1208 tail = ioat->tail & (oldsize - 1); 1209 1210 /* Copy old descriptors to new ring */ 1211 for (i = 0; i < oldsize; i++) 1212 newring[i] = ioat->ring[i]; 1213 1214 /* 1215 * If head has wrapped but tail hasn't, we must swap some descriptors 1216 * around so that tail can increment directly to head. 1217 */ 1218 if (head < tail) { 1219 for (i = 0; i <= head; i++) { 1220 tmp = newring[oldsize + i]; 1221 1222 newring[oldsize + i] = newring[i]; 1223 newring[oldsize + i]->id = oldsize + i; 1224 1225 newring[i] = tmp; 1226 newring[i]->id = i; 1227 } 1228 head += oldsize; 1229 } 1230 1231 KASSERT(head >= tail, ("invariants")); 1232 1233 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1234 if (head < oldsize) { 1235 i = oldsize - 1; 1236 end = newsize; 1237 } else { 1238 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1239 i = head; 1240 end = newsize + (head - oldsize) + 1; 1241 } 1242 1243 /* 1244 * Fix up hardware ring, being careful not to trample the active 1245 * section (tail -> head). 1246 */ 1247 for (; i < end; i++) { 1248 KASSERT((i & (newsize - 1)) < tail || 1249 (i & (newsize - 1)) >= head, ("trampling snake")); 1250 1251 next = newring[(i + 1) & (newsize - 1)]; 1252 hw = newring[i & (newsize - 1)]->u.dma; 1253 hw->next = next->hw_desc_bus_addr; 1254 } 1255 1256 free(ioat->ring, M_IOAT); 1257 ioat->ring = newring; 1258 ioat->ring_size_order = oldorder + 1; 1259 ioat->tail = tail; 1260 ioat->head = head; 1261 error = 0; 1262 1263 mtx_unlock(&ioat->cleanup_lock); 1264 out: 1265 if (error) 1266 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1267 return (error); 1268 } 1269 1270 static int 1271 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1272 struct ioat_descriptor **newring) 1273 { 1274 struct ioat_dma_hw_descriptor *hw; 1275 struct ioat_descriptor *ent, *next; 1276 uint32_t oldsize, newsize, current_idx, new_idx, i; 1277 int error; 1278 1279 CTR0(KTR_IOAT, __func__); 1280 1281 mtx_assert(&ioat->submit_lock, MA_OWNED); 1282 1283 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1284 error = EINVAL; 1285 goto out_unlocked; 1286 } 1287 1288 oldsize = (1 << oldorder); 1289 newsize = (1 << (oldorder - 1)); 1290 1291 mtx_lock(&ioat->cleanup_lock); 1292 1293 /* Can't shrink below current active set! */ 1294 if (ioat_get_active(ioat) >= newsize) { 1295 error = ENOMEM; 1296 goto out; 1297 } 1298 1299 /* 1300 * Copy current descriptors to the new ring, dropping the removed 1301 * descriptors. 1302 */ 1303 for (i = 0; i < newsize; i++) { 1304 current_idx = (ioat->tail + i) & (oldsize - 1); 1305 new_idx = (ioat->tail + i) & (newsize - 1); 1306 1307 newring[new_idx] = ioat->ring[current_idx]; 1308 newring[new_idx]->id = new_idx; 1309 } 1310 1311 /* Free deleted descriptors */ 1312 for (i = newsize; i < oldsize; i++) { 1313 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1314 ioat_free_ring_entry(ioat, ent); 1315 } 1316 1317 /* Fix up hardware ring. */ 1318 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1319 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1320 hw->next = next->hw_desc_bus_addr; 1321 1322 free(ioat->ring, M_IOAT); 1323 ioat->ring = newring; 1324 ioat->ring_size_order = oldorder - 1; 1325 error = 0; 1326 1327 out: 1328 mtx_unlock(&ioat->cleanup_lock); 1329 out_unlocked: 1330 if (error) 1331 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1332 return (error); 1333 } 1334 1335 static void 1336 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1337 { 1338 struct ioat_descriptor *desc; 1339 1340 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1341 IOAT_CHANERR_STR); 1342 if (chanerr == 0) 1343 return; 1344 1345 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1346 1347 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1348 dump_descriptor(desc->u.raw); 1349 1350 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1351 dump_descriptor(desc->u.raw); 1352 } 1353 1354 static void 1355 ioat_timer_callback(void *arg) 1356 { 1357 struct ioat_descriptor **newring; 1358 struct ioat_softc *ioat; 1359 uint32_t order; 1360 1361 ioat = arg; 1362 ioat_log_message(1, "%s\n", __func__); 1363 1364 if (ioat->is_completion_pending) { 1365 ioat_process_events(ioat); 1366 return; 1367 } 1368 1369 /* Slowly scale the ring down if idle. */ 1370 mtx_lock(&ioat->submit_lock); 1371 order = ioat->ring_size_order; 1372 if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) { 1373 mtx_unlock(&ioat->submit_lock); 1374 goto out; 1375 } 1376 ioat->is_resize_pending = TRUE; 1377 mtx_unlock(&ioat->submit_lock); 1378 1379 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1380 M_NOWAIT); 1381 1382 mtx_lock(&ioat->submit_lock); 1383 KASSERT(ioat->ring_size_order == order, 1384 ("resize_pending protects order")); 1385 1386 if (newring != NULL) 1387 ring_shrink(ioat, order, newring); 1388 1389 ioat->is_resize_pending = FALSE; 1390 mtx_unlock(&ioat->submit_lock); 1391 1392 out: 1393 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1394 callout_reset(&ioat->timer, 10 * hz, 1395 ioat_timer_callback, ioat); 1396 } 1397 1398 /* 1399 * Support Functions 1400 */ 1401 static void 1402 ioat_submit_single(struct ioat_softc *ioat) 1403 { 1404 1405 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1406 atomic_add_rel_int(&ioat->head, 1); 1407 atomic_add_rel_int(&ioat->hw_head, 1); 1408 1409 if (!ioat->is_completion_pending) { 1410 ioat->is_completion_pending = TRUE; 1411 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 1412 ioat_timer_callback, ioat); 1413 } 1414 1415 ioat->stats.descriptors_submitted++; 1416 } 1417 1418 static int 1419 ioat_reset_hw(struct ioat_softc *ioat) 1420 { 1421 uint64_t status; 1422 uint32_t chanerr; 1423 unsigned timeout; 1424 int error; 1425 1426 mtx_lock(IOAT_REFLK); 1427 ioat->quiescing = TRUE; 1428 ioat_drain_locked(ioat); 1429 mtx_unlock(IOAT_REFLK); 1430 1431 status = ioat_get_chansts(ioat); 1432 if (is_ioat_active(status) || is_ioat_idle(status)) 1433 ioat_suspend(ioat); 1434 1435 /* Wait at most 20 ms */ 1436 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1437 timeout < 20; timeout++) { 1438 DELAY(1000); 1439 status = ioat_get_chansts(ioat); 1440 } 1441 if (timeout == 20) { 1442 error = ETIMEDOUT; 1443 goto out; 1444 } 1445 1446 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1447 1448 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1449 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1450 1451 /* 1452 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1453 * that can cause stability issues for IOAT v3. 1454 */ 1455 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1456 4); 1457 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1458 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1459 1460 /* 1461 * BDXDE and BWD models reset MSI-X registers on device reset. 1462 * Save/restore their contents manually. 1463 */ 1464 if (ioat_model_resets_msix(ioat)) { 1465 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1466 pci_save_state(ioat->device); 1467 } 1468 1469 ioat_reset(ioat); 1470 1471 /* Wait at most 20 ms */ 1472 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1473 DELAY(1000); 1474 if (timeout == 20) { 1475 error = ETIMEDOUT; 1476 goto out; 1477 } 1478 1479 if (ioat_model_resets_msix(ioat)) { 1480 ioat_log_message(1, "device resets registers; restored\n"); 1481 pci_restore_state(ioat->device); 1482 } 1483 1484 /* Reset attempts to return the hardware to "halted." */ 1485 status = ioat_get_chansts(ioat); 1486 if (is_ioat_active(status) || is_ioat_idle(status)) { 1487 /* So this really shouldn't happen... */ 1488 ioat_log_message(0, "Device is active after a reset?\n"); 1489 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1490 error = 0; 1491 goto out; 1492 } 1493 1494 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1495 if (chanerr != 0) { 1496 mtx_lock(&ioat->cleanup_lock); 1497 ioat_halted_debug(ioat, chanerr); 1498 mtx_unlock(&ioat->cleanup_lock); 1499 error = EIO; 1500 goto out; 1501 } 1502 1503 /* 1504 * Bring device back online after reset. Writing CHAINADDR brings the 1505 * device back to active. 1506 * 1507 * The internal ring counter resets to zero, so we have to start over 1508 * at zero as well. 1509 */ 1510 ioat->tail = ioat->head = ioat->hw_head = 0; 1511 ioat->last_seen = 0; 1512 1513 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1514 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1515 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1516 error = 0; 1517 1518 out: 1519 mtx_lock(IOAT_REFLK); 1520 ioat->quiescing = FALSE; 1521 mtx_unlock(IOAT_REFLK); 1522 1523 if (error == 0) 1524 error = ioat_start_channel(ioat); 1525 1526 return (error); 1527 } 1528 1529 static int 1530 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1531 { 1532 struct ioat_softc *ioat; 1533 struct sbuf sb; 1534 uint64_t status; 1535 int error; 1536 1537 ioat = arg1; 1538 1539 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1540 1541 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1542 switch (status) { 1543 case IOAT_CHANSTS_ACTIVE: 1544 sbuf_printf(&sb, "ACTIVE"); 1545 break; 1546 case IOAT_CHANSTS_IDLE: 1547 sbuf_printf(&sb, "IDLE"); 1548 break; 1549 case IOAT_CHANSTS_SUSPENDED: 1550 sbuf_printf(&sb, "SUSPENDED"); 1551 break; 1552 case IOAT_CHANSTS_HALTED: 1553 sbuf_printf(&sb, "HALTED"); 1554 break; 1555 case IOAT_CHANSTS_ARMED: 1556 sbuf_printf(&sb, "ARMED"); 1557 break; 1558 default: 1559 sbuf_printf(&sb, "UNKNOWN"); 1560 break; 1561 } 1562 error = sbuf_finish(&sb); 1563 sbuf_delete(&sb); 1564 1565 if (error != 0 || req->newptr == NULL) 1566 return (error); 1567 return (EINVAL); 1568 } 1569 1570 static int 1571 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1572 { 1573 struct ioat_softc *ioat; 1574 struct sbuf sb; 1575 #define PRECISION "1" 1576 const uintmax_t factor = 10; 1577 uintmax_t rate; 1578 int error; 1579 1580 ioat = arg1; 1581 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1582 1583 if (ioat->stats.interrupts == 0) { 1584 sbuf_printf(&sb, "NaN"); 1585 goto out; 1586 } 1587 rate = ioat->stats.descriptors_processed * factor / 1588 ioat->stats.interrupts; 1589 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1590 rate % factor); 1591 #undef PRECISION 1592 out: 1593 error = sbuf_finish(&sb); 1594 sbuf_delete(&sb); 1595 if (error != 0 || req->newptr == NULL) 1596 return (error); 1597 return (EINVAL); 1598 } 1599 1600 static int 1601 sysctl_handle_error(SYSCTL_HANDLER_ARGS) 1602 { 1603 struct ioat_descriptor *desc; 1604 struct ioat_softc *ioat; 1605 int error, arg; 1606 1607 ioat = arg1; 1608 1609 arg = 0; 1610 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1611 if (error != 0 || req->newptr == NULL) 1612 return (error); 1613 1614 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1615 if (error != 0) 1616 return (error); 1617 1618 if (arg != 0) { 1619 ioat_acquire(&ioat->dmaengine); 1620 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 1, 1621 0xffff000000000000ull, 0xffff000000000000ull, NULL, NULL, 1622 0); 1623 if (desc == NULL) 1624 error = ENOMEM; 1625 else 1626 ioat_submit_single(ioat); 1627 ioat_release(&ioat->dmaengine); 1628 } 1629 return (error); 1630 } 1631 1632 static int 1633 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1634 { 1635 struct ioat_softc *ioat; 1636 int error, arg; 1637 1638 ioat = arg1; 1639 1640 arg = 0; 1641 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1642 if (error != 0 || req->newptr == NULL) 1643 return (error); 1644 1645 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1646 if (error != 0) 1647 return (error); 1648 1649 if (arg != 0) 1650 error = ioat_reset_hw(ioat); 1651 1652 return (error); 1653 } 1654 1655 static void 1656 dump_descriptor(void *hw_desc) 1657 { 1658 int i, j; 1659 1660 for (i = 0; i < 2; i++) { 1661 for (j = 0; j < 8; j++) 1662 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1663 printf("\n"); 1664 } 1665 } 1666 1667 static void 1668 ioat_setup_sysctl(device_t device) 1669 { 1670 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1671 struct sysctl_ctx_list *ctx; 1672 struct sysctl_oid *tree, *tmp; 1673 struct ioat_softc *ioat; 1674 1675 ioat = DEVICE2SOFTC(device); 1676 ctx = device_get_sysctl_ctx(device); 1677 tree = device_get_sysctl_tree(device); 1678 par = SYSCTL_CHILDREN(tree); 1679 1680 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1681 &ioat->version, 0, "HW version (0xMM form)"); 1682 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1683 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1684 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1685 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1686 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1687 &ioat->intrdelay_max, 0, 1688 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1689 1690 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 1691 "IOAT channel internal state"); 1692 state = SYSCTL_CHILDREN(tmp); 1693 1694 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1695 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1696 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1697 0, "SW descriptor head pointer index"); 1698 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1699 0, "SW descriptor tail pointer index"); 1700 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 1701 &ioat->hw_head, 0, "HW DMACOUNT"); 1702 1703 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1704 ioat->comp_update, "HW addr of last completion"); 1705 1706 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 1707 &ioat->is_resize_pending, 0, "resize pending"); 1708 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 1709 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 1710 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1711 &ioat->is_reset_pending, 0, "reset pending"); 1712 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1713 &ioat->is_channel_running, 0, "channel running"); 1714 1715 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1716 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1717 "String of the channel status"); 1718 1719 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1720 &ioat->cached_intrdelay, 0, 1721 "Current INTRDELAY on this channel (cached, microseconds)"); 1722 1723 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 1724 "Big hammers (mostly for testing)"); 1725 hammer = SYSCTL_CHILDREN(tmp); 1726 1727 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1728 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1729 "Set to non-zero to reset the hardware"); 1730 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_error", 1731 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_error, "I", 1732 "Set to non-zero to inject a recoverable hardware error"); 1733 1734 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 1735 "IOAT channel statistics"); 1736 statpar = SYSCTL_CHILDREN(tmp); 1737 1738 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 1739 &ioat->stats.interrupts, 1740 "Number of interrupts processed on this channel"); 1741 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 1742 &ioat->stats.descriptors_processed, 1743 "Number of descriptors processed on this channel"); 1744 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 1745 &ioat->stats.descriptors_submitted, 1746 "Number of descriptors submitted to this channel"); 1747 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 1748 &ioat->stats.descriptors_error, 1749 "Number of descriptors failed by channel errors"); 1750 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 1751 &ioat->stats.channel_halts, 0, 1752 "Number of times the channel has halted"); 1753 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 1754 &ioat->stats.last_halt_chanerr, 0, 1755 "The raw CHANERR when the channel was last halted"); 1756 1757 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 1758 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 1759 "Descriptors per interrupt"); 1760 } 1761 1762 static inline struct ioat_softc * 1763 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1764 { 1765 uint32_t old; 1766 1767 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1768 1769 old = atomic_fetchadd_32(&ioat->refcnt, 1); 1770 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 1771 1772 #ifdef INVARIANTS 1773 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 1774 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 1775 #endif 1776 1777 return (ioat); 1778 } 1779 1780 static inline void 1781 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1782 { 1783 1784 _ioat_putn(ioat, n, kind, FALSE); 1785 } 1786 1787 static inline void 1788 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1789 { 1790 1791 _ioat_putn(ioat, n, kind, TRUE); 1792 } 1793 1794 static inline void 1795 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 1796 boolean_t locked) 1797 { 1798 uint32_t old; 1799 1800 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1801 1802 if (n == 0) 1803 return; 1804 1805 #ifdef INVARIANTS 1806 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 1807 KASSERT(old >= n, ("refcnt kind underflow")); 1808 #endif 1809 1810 /* Skip acquiring the lock if resulting refcnt > 0. */ 1811 for (;;) { 1812 old = ioat->refcnt; 1813 if (old <= n) 1814 break; 1815 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 1816 return; 1817 } 1818 1819 if (locked) 1820 mtx_assert(IOAT_REFLK, MA_OWNED); 1821 else 1822 mtx_lock(IOAT_REFLK); 1823 1824 old = atomic_fetchadd_32(&ioat->refcnt, -n); 1825 KASSERT(old >= n, ("refcnt error")); 1826 1827 if (old == n) 1828 wakeup(IOAT_REFLK); 1829 if (!locked) 1830 mtx_unlock(IOAT_REFLK); 1831 } 1832 1833 static inline void 1834 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1835 { 1836 1837 ioat_putn(ioat, 1, kind); 1838 } 1839 1840 static void 1841 ioat_drain_locked(struct ioat_softc *ioat) 1842 { 1843 1844 mtx_assert(IOAT_REFLK, MA_OWNED); 1845 while (ioat->refcnt > 0) 1846 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 1847 } 1848