1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ddb.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/ioccom.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/sbuf.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #include <machine/stdarg.h> 52 53 #ifdef DDB 54 #include <ddb/ddb.h> 55 #endif 56 57 #include "ioat.h" 58 #include "ioat_hw.h" 59 #include "ioat_internal.h" 60 61 #ifndef BUS_SPACE_MAXADDR_40BIT 62 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 63 #endif 64 #define IOAT_REFLK (&ioat->submit_lock) 65 #define IOAT_SHRINK_PERIOD (10 * hz) 66 67 static int ioat_probe(device_t device); 68 static int ioat_attach(device_t device); 69 static int ioat_detach(device_t device); 70 static int ioat_setup_intr(struct ioat_softc *ioat); 71 static int ioat_teardown_intr(struct ioat_softc *ioat); 72 static int ioat3_attach(device_t device); 73 static int ioat_start_channel(struct ioat_softc *ioat); 74 static int ioat_map_pci_bar(struct ioat_softc *ioat); 75 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 76 int error); 77 static void ioat_interrupt_handler(void *arg); 78 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 79 static int chanerr_to_errno(uint32_t); 80 static void ioat_process_events(struct ioat_softc *ioat); 81 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 82 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 83 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 84 struct ioat_descriptor **); 85 static void ioat_free_ring_entry(struct ioat_softc *ioat, 86 struct ioat_descriptor *desc); 87 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 88 int mflags); 89 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 90 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 91 uint32_t index); 92 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 93 uint32_t size, boolean_t need_dscr, int mflags); 94 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 95 struct ioat_descriptor **); 96 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 97 struct ioat_descriptor **); 98 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 99 static void ioat_poll_timer_callback(void *arg); 100 static void ioat_shrink_timer_callback(void *arg); 101 static void dump_descriptor(void *hw_desc); 102 static void ioat_submit_single(struct ioat_softc *ioat); 103 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 104 int error); 105 static int ioat_reset_hw(struct ioat_softc *ioat); 106 static void ioat_reset_hw_task(void *, int); 107 static void ioat_setup_sysctl(device_t device); 108 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 109 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 110 enum ioat_ref_kind); 111 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 112 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 113 enum ioat_ref_kind, boolean_t); 114 static inline void ioat_putn(struct ioat_softc *, uint32_t, 115 enum ioat_ref_kind); 116 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 117 enum ioat_ref_kind); 118 static void ioat_drain_locked(struct ioat_softc *); 119 120 #define ioat_log_message(v, ...) do { \ 121 if ((v) <= g_ioat_debug_level) { \ 122 device_printf(ioat->device, __VA_ARGS__); \ 123 } \ 124 } while (0) 125 126 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 127 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 128 129 static int g_force_legacy_interrupts; 130 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 131 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 132 133 int g_ioat_debug_level = 0; 134 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 135 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 136 137 /* 138 * OS <-> Driver interface structures 139 */ 140 static device_method_t ioat_pci_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, ioat_probe), 143 DEVMETHOD(device_attach, ioat_attach), 144 DEVMETHOD(device_detach, ioat_detach), 145 DEVMETHOD_END 146 }; 147 148 static driver_t ioat_pci_driver = { 149 "ioat", 150 ioat_pci_methods, 151 sizeof(struct ioat_softc), 152 }; 153 154 static devclass_t ioat_devclass; 155 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 156 MODULE_VERSION(ioat, 1); 157 158 /* 159 * Private data structures 160 */ 161 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 162 static unsigned ioat_channel_index = 0; 163 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 164 "Number of IOAT channels attached"); 165 166 static struct _pcsid 167 { 168 u_int32_t type; 169 const char *desc; 170 } pci_ids[] = { 171 { 0x34308086, "TBG IOAT Ch0" }, 172 { 0x34318086, "TBG IOAT Ch1" }, 173 { 0x34328086, "TBG IOAT Ch2" }, 174 { 0x34338086, "TBG IOAT Ch3" }, 175 { 0x34298086, "TBG IOAT Ch4" }, 176 { 0x342a8086, "TBG IOAT Ch5" }, 177 { 0x342b8086, "TBG IOAT Ch6" }, 178 { 0x342c8086, "TBG IOAT Ch7" }, 179 180 { 0x37108086, "JSF IOAT Ch0" }, 181 { 0x37118086, "JSF IOAT Ch1" }, 182 { 0x37128086, "JSF IOAT Ch2" }, 183 { 0x37138086, "JSF IOAT Ch3" }, 184 { 0x37148086, "JSF IOAT Ch4" }, 185 { 0x37158086, "JSF IOAT Ch5" }, 186 { 0x37168086, "JSF IOAT Ch6" }, 187 { 0x37178086, "JSF IOAT Ch7" }, 188 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 189 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 190 191 { 0x3c208086, "SNB IOAT Ch0" }, 192 { 0x3c218086, "SNB IOAT Ch1" }, 193 { 0x3c228086, "SNB IOAT Ch2" }, 194 { 0x3c238086, "SNB IOAT Ch3" }, 195 { 0x3c248086, "SNB IOAT Ch4" }, 196 { 0x3c258086, "SNB IOAT Ch5" }, 197 { 0x3c268086, "SNB IOAT Ch6" }, 198 { 0x3c278086, "SNB IOAT Ch7" }, 199 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 200 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 201 202 { 0x0e208086, "IVB IOAT Ch0" }, 203 { 0x0e218086, "IVB IOAT Ch1" }, 204 { 0x0e228086, "IVB IOAT Ch2" }, 205 { 0x0e238086, "IVB IOAT Ch3" }, 206 { 0x0e248086, "IVB IOAT Ch4" }, 207 { 0x0e258086, "IVB IOAT Ch5" }, 208 { 0x0e268086, "IVB IOAT Ch6" }, 209 { 0x0e278086, "IVB IOAT Ch7" }, 210 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 211 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 212 213 { 0x2f208086, "HSW IOAT Ch0" }, 214 { 0x2f218086, "HSW IOAT Ch1" }, 215 { 0x2f228086, "HSW IOAT Ch2" }, 216 { 0x2f238086, "HSW IOAT Ch3" }, 217 { 0x2f248086, "HSW IOAT Ch4" }, 218 { 0x2f258086, "HSW IOAT Ch5" }, 219 { 0x2f268086, "HSW IOAT Ch6" }, 220 { 0x2f278086, "HSW IOAT Ch7" }, 221 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 222 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 223 224 { 0x0c508086, "BWD IOAT Ch0" }, 225 { 0x0c518086, "BWD IOAT Ch1" }, 226 { 0x0c528086, "BWD IOAT Ch2" }, 227 { 0x0c538086, "BWD IOAT Ch3" }, 228 229 { 0x6f508086, "BDXDE IOAT Ch0" }, 230 { 0x6f518086, "BDXDE IOAT Ch1" }, 231 { 0x6f528086, "BDXDE IOAT Ch2" }, 232 { 0x6f538086, "BDXDE IOAT Ch3" }, 233 234 { 0x6f208086, "BDX IOAT Ch0" }, 235 { 0x6f218086, "BDX IOAT Ch1" }, 236 { 0x6f228086, "BDX IOAT Ch2" }, 237 { 0x6f238086, "BDX IOAT Ch3" }, 238 { 0x6f248086, "BDX IOAT Ch4" }, 239 { 0x6f258086, "BDX IOAT Ch5" }, 240 { 0x6f268086, "BDX IOAT Ch6" }, 241 { 0x6f278086, "BDX IOAT Ch7" }, 242 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 243 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 244 245 { 0x00000000, NULL } 246 }; 247 248 /* 249 * OS <-> Driver linkage functions 250 */ 251 static int 252 ioat_probe(device_t device) 253 { 254 struct _pcsid *ep; 255 u_int32_t type; 256 257 type = pci_get_devid(device); 258 for (ep = pci_ids; ep->type; ep++) { 259 if (ep->type == type) { 260 device_set_desc(device, ep->desc); 261 return (0); 262 } 263 } 264 return (ENXIO); 265 } 266 267 static int 268 ioat_attach(device_t device) 269 { 270 struct ioat_softc *ioat; 271 int error; 272 273 ioat = DEVICE2SOFTC(device); 274 ioat->device = device; 275 276 error = ioat_map_pci_bar(ioat); 277 if (error != 0) 278 goto err; 279 280 ioat->version = ioat_read_cbver(ioat); 281 if (ioat->version < IOAT_VER_3_0) { 282 error = ENODEV; 283 goto err; 284 } 285 286 error = ioat3_attach(device); 287 if (error != 0) 288 goto err; 289 290 error = pci_enable_busmaster(device); 291 if (error != 0) 292 goto err; 293 294 error = ioat_setup_intr(ioat); 295 if (error != 0) 296 goto err; 297 298 error = ioat_reset_hw(ioat); 299 if (error != 0) 300 goto err; 301 302 ioat_process_events(ioat); 303 ioat_setup_sysctl(device); 304 305 ioat->chan_idx = ioat_channel_index; 306 ioat_channel[ioat_channel_index++] = ioat; 307 ioat_test_attach(); 308 309 err: 310 if (error != 0) 311 ioat_detach(device); 312 return (error); 313 } 314 315 static int 316 ioat_detach(device_t device) 317 { 318 struct ioat_softc *ioat; 319 320 ioat = DEVICE2SOFTC(device); 321 322 ioat_test_detach(); 323 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 324 325 mtx_lock(IOAT_REFLK); 326 ioat->quiescing = TRUE; 327 ioat->destroying = TRUE; 328 wakeup(&ioat->quiescing); 329 wakeup(&ioat->resetting); 330 331 ioat_channel[ioat->chan_idx] = NULL; 332 333 ioat_drain_locked(ioat); 334 mtx_unlock(IOAT_REFLK); 335 336 ioat_teardown_intr(ioat); 337 callout_drain(&ioat->poll_timer); 338 callout_drain(&ioat->shrink_timer); 339 340 pci_disable_busmaster(device); 341 342 if (ioat->pci_resource != NULL) 343 bus_release_resource(device, SYS_RES_MEMORY, 344 ioat->pci_resource_id, ioat->pci_resource); 345 346 if (ioat->ring != NULL) 347 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 348 349 if (ioat->comp_update != NULL) { 350 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 351 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 352 ioat->comp_update_map); 353 bus_dma_tag_destroy(ioat->comp_update_tag); 354 } 355 356 bus_dma_tag_destroy(ioat->hw_desc_tag); 357 358 return (0); 359 } 360 361 static int 362 ioat_teardown_intr(struct ioat_softc *ioat) 363 { 364 365 if (ioat->tag != NULL) 366 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 367 368 if (ioat->res != NULL) 369 bus_release_resource(ioat->device, SYS_RES_IRQ, 370 rman_get_rid(ioat->res), ioat->res); 371 372 pci_release_msi(ioat->device); 373 return (0); 374 } 375 376 static int 377 ioat_start_channel(struct ioat_softc *ioat) 378 { 379 struct ioat_dma_hw_descriptor *hw_desc; 380 struct ioat_descriptor *desc; 381 struct bus_dmadesc *dmadesc; 382 uint64_t status; 383 uint32_t chanerr; 384 int i; 385 386 ioat_acquire(&ioat->dmaengine); 387 388 /* Submit 'NULL' operation manually to avoid quiescing flag */ 389 desc = ioat_get_ring_entry(ioat, ioat->head); 390 dmadesc = &desc->bus_dmadesc; 391 hw_desc = desc->u.dma; 392 393 dmadesc->callback_fn = NULL; 394 dmadesc->callback_arg = NULL; 395 396 hw_desc->u.control_raw = 0; 397 hw_desc->u.control_generic.op = IOAT_OP_COPY; 398 hw_desc->u.control_generic.completion_update = 1; 399 hw_desc->size = 8; 400 hw_desc->src_addr = 0; 401 hw_desc->dest_addr = 0; 402 hw_desc->u.control.null = 1; 403 404 ioat_submit_single(ioat); 405 ioat_release(&ioat->dmaengine); 406 407 for (i = 0; i < 100; i++) { 408 DELAY(1); 409 status = ioat_get_chansts(ioat); 410 if (is_ioat_idle(status)) 411 return (0); 412 } 413 414 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 415 ioat_log_message(0, "could not start channel: " 416 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 417 IOAT_CHANERR_STR); 418 return (ENXIO); 419 } 420 421 /* 422 * Initialize Hardware 423 */ 424 static int 425 ioat3_attach(device_t device) 426 { 427 struct ioat_softc *ioat; 428 struct ioat_descriptor **ring; 429 struct ioat_descriptor *next; 430 struct ioat_dma_hw_descriptor *dma_hw_desc; 431 int i, num_descriptors; 432 int error; 433 uint8_t xfercap; 434 435 error = 0; 436 ioat = DEVICE2SOFTC(device); 437 ioat->capabilities = ioat_read_dmacapability(ioat); 438 439 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 440 IOAT_DMACAP_STR); 441 442 xfercap = ioat_read_xfercap(ioat); 443 ioat->max_xfer_size = 1 << xfercap; 444 445 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 446 IOAT_INTRDELAY_SUPPORTED) != 0; 447 if (ioat->intrdelay_supported) 448 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 449 450 /* TODO: need to check DCA here if we ever do XOR/PQ */ 451 452 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 453 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 454 callout_init(&ioat->poll_timer, 1); 455 callout_init(&ioat->shrink_timer, 1); 456 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 457 458 /* Establish lock order for Witness */ 459 mtx_lock(&ioat->submit_lock); 460 mtx_lock(&ioat->cleanup_lock); 461 mtx_unlock(&ioat->cleanup_lock); 462 mtx_unlock(&ioat->submit_lock); 463 464 ioat->is_resize_pending = FALSE; 465 ioat->is_submitter_processing = FALSE; 466 ioat->is_completion_pending = FALSE; 467 ioat->is_reset_pending = FALSE; 468 ioat->is_channel_running = FALSE; 469 470 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 471 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 472 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 473 &ioat->comp_update_tag); 474 475 error = bus_dmamem_alloc(ioat->comp_update_tag, 476 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 477 if (ioat->comp_update == NULL) 478 return (ENOMEM); 479 480 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 481 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 482 0); 483 if (error != 0) 484 return (error); 485 486 ioat->ring_size_order = IOAT_MIN_ORDER; 487 488 num_descriptors = 1 << ioat->ring_size_order; 489 490 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 491 BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL, 492 sizeof(struct ioat_dma_hw_descriptor), 1, 493 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 494 &ioat->hw_desc_tag); 495 496 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 497 M_ZERO | M_WAITOK); 498 499 ring = ioat->ring; 500 for (i = 0; i < num_descriptors; i++) { 501 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 502 if (ring[i] == NULL) 503 return (ENOMEM); 504 505 ring[i]->id = i; 506 } 507 508 for (i = 0; i < num_descriptors - 1; i++) { 509 next = ring[i + 1]; 510 dma_hw_desc = ring[i]->u.dma; 511 512 dma_hw_desc->next = next->hw_desc_bus_addr; 513 } 514 515 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 516 517 ioat->head = ioat->hw_head = 0; 518 ioat->tail = 0; 519 ioat->last_seen = 0; 520 *ioat->comp_update = 0; 521 return (0); 522 } 523 524 static int 525 ioat_map_pci_bar(struct ioat_softc *ioat) 526 { 527 528 ioat->pci_resource_id = PCIR_BAR(0); 529 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 530 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 531 532 if (ioat->pci_resource == NULL) { 533 ioat_log_message(0, "unable to allocate pci resource\n"); 534 return (ENODEV); 535 } 536 537 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 538 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 539 return (0); 540 } 541 542 static void 543 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 544 { 545 struct ioat_softc *ioat = arg; 546 547 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 548 ioat->comp_update_bus_addr = seg[0].ds_addr; 549 } 550 551 static void 552 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 553 { 554 bus_addr_t *baddr; 555 556 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 557 baddr = arg; 558 *baddr = segs->ds_addr; 559 } 560 561 /* 562 * Interrupt setup and handlers 563 */ 564 static int 565 ioat_setup_intr(struct ioat_softc *ioat) 566 { 567 uint32_t num_vectors; 568 int error; 569 boolean_t use_msix; 570 boolean_t force_legacy_interrupts; 571 572 use_msix = FALSE; 573 force_legacy_interrupts = FALSE; 574 575 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 576 num_vectors = 1; 577 pci_alloc_msix(ioat->device, &num_vectors); 578 if (num_vectors == 1) 579 use_msix = TRUE; 580 } 581 582 if (use_msix) { 583 ioat->rid = 1; 584 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 585 &ioat->rid, RF_ACTIVE); 586 } else { 587 ioat->rid = 0; 588 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 589 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 590 } 591 if (ioat->res == NULL) { 592 ioat_log_message(0, "bus_alloc_resource failed\n"); 593 return (ENOMEM); 594 } 595 596 ioat->tag = NULL; 597 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 598 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 599 if (error != 0) { 600 ioat_log_message(0, "bus_setup_intr failed\n"); 601 return (error); 602 } 603 604 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 605 return (0); 606 } 607 608 static boolean_t 609 ioat_model_resets_msix(struct ioat_softc *ioat) 610 { 611 u_int32_t pciid; 612 613 pciid = pci_get_devid(ioat->device); 614 switch (pciid) { 615 /* BWD: */ 616 case 0x0c508086: 617 case 0x0c518086: 618 case 0x0c528086: 619 case 0x0c538086: 620 /* BDXDE: */ 621 case 0x6f508086: 622 case 0x6f518086: 623 case 0x6f528086: 624 case 0x6f538086: 625 return (TRUE); 626 } 627 628 return (FALSE); 629 } 630 631 static void 632 ioat_interrupt_handler(void *arg) 633 { 634 struct ioat_softc *ioat = arg; 635 636 ioat->stats.interrupts++; 637 ioat_process_events(ioat); 638 } 639 640 static int 641 chanerr_to_errno(uint32_t chanerr) 642 { 643 644 if (chanerr == 0) 645 return (0); 646 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 647 return (EFAULT); 648 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 649 return (EIO); 650 /* This one is probably our fault: */ 651 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 652 return (EIO); 653 return (EIO); 654 } 655 656 static void 657 ioat_process_events(struct ioat_softc *ioat) 658 { 659 struct ioat_descriptor *desc; 660 struct bus_dmadesc *dmadesc; 661 uint64_t comp_update, status; 662 uint32_t completed, chanerr; 663 boolean_t pending; 664 int error; 665 666 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 667 668 mtx_lock(&ioat->cleanup_lock); 669 670 /* 671 * Don't run while the hardware is being reset. Reset is responsible 672 * for blocking new work and draining & completing existing work, so 673 * there is nothing to do until new work is queued after reset anyway. 674 */ 675 if (ioat->resetting_cleanup) { 676 mtx_unlock(&ioat->cleanup_lock); 677 return; 678 } 679 680 completed = 0; 681 comp_update = ioat_get_chansts(ioat); 682 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx", 683 __func__, ioat->chan_idx, comp_update, ioat->last_seen); 684 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 685 686 while (ioat_get_active(ioat) > 0) { 687 desc = ioat_get_ring_entry(ioat, ioat->tail); 688 dmadesc = &desc->bus_dmadesc; 689 CTR4(KTR_IOAT, "channel=%u completing desc %u ok cb %p(%p)", 690 ioat->chan_idx, ioat->tail, dmadesc->callback_fn, 691 dmadesc->callback_arg); 692 693 if (dmadesc->callback_fn != NULL) 694 dmadesc->callback_fn(dmadesc->callback_arg, 0); 695 696 completed++; 697 ioat->tail++; 698 if (desc->hw_desc_bus_addr == status) 699 break; 700 } 701 702 if (completed != 0) { 703 ioat->last_seen = desc->hw_desc_bus_addr; 704 ioat->stats.descriptors_processed += completed; 705 } 706 707 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 708 709 /* Perform a racy check first; only take the locks if it passes. */ 710 pending = (ioat_get_active(ioat) != 0); 711 if (!pending && ioat->is_completion_pending) { 712 mtx_unlock(&ioat->cleanup_lock); 713 mtx_lock(&ioat->submit_lock); 714 mtx_lock(&ioat->cleanup_lock); 715 716 pending = (ioat_get_active(ioat) != 0); 717 if (!pending && ioat->is_completion_pending) { 718 ioat->is_completion_pending = FALSE; 719 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 720 ioat_shrink_timer_callback, ioat); 721 callout_stop(&ioat->poll_timer); 722 } 723 mtx_unlock(&ioat->submit_lock); 724 } 725 mtx_unlock(&ioat->cleanup_lock); 726 727 if (pending) 728 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 729 ioat); 730 731 if (completed != 0) { 732 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 733 wakeup(&ioat->tail); 734 } 735 736 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 737 return; 738 739 ioat->stats.channel_halts++; 740 741 /* 742 * Fatal programming error on this DMA channel. Flush any outstanding 743 * work with error status and restart the engine. 744 */ 745 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 746 mtx_lock(&ioat->submit_lock); 747 mtx_lock(&ioat->cleanup_lock); 748 ioat->quiescing = TRUE; 749 750 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 751 ioat_halted_debug(ioat, chanerr); 752 ioat->stats.last_halt_chanerr = chanerr; 753 754 while (ioat_get_active(ioat) > 0) { 755 desc = ioat_get_ring_entry(ioat, ioat->tail); 756 dmadesc = &desc->bus_dmadesc; 757 CTR4(KTR_IOAT, "channel=%u completing desc %u err cb %p(%p)", 758 ioat->chan_idx, ioat->tail, dmadesc->callback_fn, 759 dmadesc->callback_arg); 760 761 if (dmadesc->callback_fn != NULL) 762 dmadesc->callback_fn(dmadesc->callback_arg, 763 chanerr_to_errno(chanerr)); 764 765 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 766 ioat->tail++; 767 ioat->stats.descriptors_processed++; 768 ioat->stats.descriptors_error++; 769 } 770 771 if (ioat->is_completion_pending) { 772 ioat->is_completion_pending = FALSE; 773 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 774 ioat_shrink_timer_callback, ioat); 775 callout_stop(&ioat->poll_timer); 776 } 777 778 /* Clear error status */ 779 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 780 781 mtx_unlock(&ioat->cleanup_lock); 782 mtx_unlock(&ioat->submit_lock); 783 784 ioat_log_message(0, "Resetting channel to recover from error\n"); 785 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 786 KASSERT(error == 0, 787 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 788 } 789 790 static void 791 ioat_reset_hw_task(void *ctx, int pending __unused) 792 { 793 struct ioat_softc *ioat; 794 int error; 795 796 ioat = ctx; 797 ioat_log_message(1, "%s: Resetting channel\n", __func__); 798 799 error = ioat_reset_hw(ioat); 800 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 801 (void)error; 802 } 803 804 /* 805 * User API functions 806 */ 807 unsigned 808 ioat_get_nchannels(void) 809 { 810 811 return (ioat_channel_index); 812 } 813 814 bus_dmaengine_t 815 ioat_get_dmaengine(uint32_t index, int flags) 816 { 817 struct ioat_softc *ioat; 818 819 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 820 ("invalid flags: 0x%08x", flags)); 821 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 822 ("invalid wait | nowait")); 823 824 if (index >= ioat_channel_index) 825 return (NULL); 826 827 ioat = ioat_channel[index]; 828 if (ioat == NULL || ioat->destroying) 829 return (NULL); 830 831 if (ioat->quiescing) { 832 if ((flags & M_NOWAIT) != 0) 833 return (NULL); 834 835 mtx_lock(IOAT_REFLK); 836 while (ioat->quiescing && !ioat->destroying) 837 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 838 mtx_unlock(IOAT_REFLK); 839 840 if (ioat->destroying) 841 return (NULL); 842 } 843 844 /* 845 * There's a race here between the quiescing check and HW reset or 846 * module destroy. 847 */ 848 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 849 } 850 851 void 852 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 853 { 854 struct ioat_softc *ioat; 855 856 ioat = to_ioat_softc(dmaengine); 857 ioat_put(ioat, IOAT_DMAENGINE_REF); 858 } 859 860 int 861 ioat_get_hwversion(bus_dmaengine_t dmaengine) 862 { 863 struct ioat_softc *ioat; 864 865 ioat = to_ioat_softc(dmaengine); 866 return (ioat->version); 867 } 868 869 size_t 870 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 871 { 872 struct ioat_softc *ioat; 873 874 ioat = to_ioat_softc(dmaengine); 875 return (ioat->max_xfer_size); 876 } 877 878 uint32_t 879 ioat_get_capabilities(bus_dmaengine_t dmaengine) 880 { 881 struct ioat_softc *ioat; 882 883 ioat = to_ioat_softc(dmaengine); 884 return (ioat->capabilities); 885 } 886 887 int 888 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 889 { 890 struct ioat_softc *ioat; 891 892 ioat = to_ioat_softc(dmaengine); 893 if (!ioat->intrdelay_supported) 894 return (ENODEV); 895 if (delay > ioat->intrdelay_max) 896 return (ERANGE); 897 898 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 899 ioat->cached_intrdelay = 900 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 901 return (0); 902 } 903 904 uint16_t 905 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 906 { 907 struct ioat_softc *ioat; 908 909 ioat = to_ioat_softc(dmaengine); 910 return (ioat->intrdelay_max); 911 } 912 913 void 914 ioat_acquire(bus_dmaengine_t dmaengine) 915 { 916 struct ioat_softc *ioat; 917 918 ioat = to_ioat_softc(dmaengine); 919 mtx_lock(&ioat->submit_lock); 920 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 921 } 922 923 int 924 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 925 { 926 struct ioat_softc *ioat; 927 int error; 928 929 ioat = to_ioat_softc(dmaengine); 930 ioat_acquire(dmaengine); 931 932 error = ioat_reserve_space(ioat, n, mflags); 933 if (error != 0) 934 ioat_release(dmaengine); 935 return (error); 936 } 937 938 void 939 ioat_release(bus_dmaengine_t dmaengine) 940 { 941 struct ioat_softc *ioat; 942 943 ioat = to_ioat_softc(dmaengine); 944 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 945 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 946 mtx_unlock(&ioat->submit_lock); 947 } 948 949 static struct ioat_descriptor * 950 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 951 uint32_t size, uint64_t src, uint64_t dst, 952 bus_dmaengine_callback_t callback_fn, void *callback_arg, 953 uint32_t flags) 954 { 955 struct ioat_generic_hw_descriptor *hw_desc; 956 struct ioat_descriptor *desc; 957 int mflags; 958 959 mtx_assert(&ioat->submit_lock, MA_OWNED); 960 961 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 962 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 963 if ((flags & DMA_NO_WAIT) != 0) 964 mflags = M_NOWAIT; 965 else 966 mflags = M_WAITOK; 967 968 if (size > ioat->max_xfer_size) { 969 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 970 __func__, ioat->max_xfer_size, (unsigned)size); 971 return (NULL); 972 } 973 974 if (ioat_reserve_space(ioat, 1, mflags) != 0) 975 return (NULL); 976 977 desc = ioat_get_ring_entry(ioat, ioat->head); 978 hw_desc = desc->u.generic; 979 980 hw_desc->u.control_raw = 0; 981 hw_desc->u.control_generic.op = op; 982 hw_desc->u.control_generic.completion_update = 1; 983 984 if ((flags & DMA_INT_EN) != 0) 985 hw_desc->u.control_generic.int_enable = 1; 986 if ((flags & DMA_FENCE) != 0) 987 hw_desc->u.control_generic.fence = 1; 988 989 hw_desc->size = size; 990 hw_desc->src_addr = src; 991 hw_desc->dest_addr = dst; 992 993 desc->bus_dmadesc.callback_fn = callback_fn; 994 desc->bus_dmadesc.callback_arg = callback_arg; 995 return (desc); 996 } 997 998 struct bus_dmadesc * 999 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1000 void *callback_arg, uint32_t flags) 1001 { 1002 struct ioat_dma_hw_descriptor *hw_desc; 1003 struct ioat_descriptor *desc; 1004 struct ioat_softc *ioat; 1005 1006 ioat = to_ioat_softc(dmaengine); 1007 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1008 1009 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1010 callback_arg, flags); 1011 if (desc == NULL) 1012 return (NULL); 1013 1014 hw_desc = desc->u.dma; 1015 hw_desc->u.control.null = 1; 1016 ioat_submit_single(ioat); 1017 return (&desc->bus_dmadesc); 1018 } 1019 1020 struct bus_dmadesc * 1021 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1022 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1023 void *callback_arg, uint32_t flags) 1024 { 1025 struct ioat_dma_hw_descriptor *hw_desc; 1026 struct ioat_descriptor *desc; 1027 struct ioat_softc *ioat; 1028 1029 ioat = to_ioat_softc(dmaengine); 1030 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1031 1032 if (((src | dst) & (0xffffull << 48)) != 0) { 1033 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1034 __func__); 1035 return (NULL); 1036 } 1037 1038 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1039 callback_arg, flags); 1040 if (desc == NULL) 1041 return (NULL); 1042 1043 hw_desc = desc->u.dma; 1044 if (g_ioat_debug_level >= 3) 1045 dump_descriptor(hw_desc); 1046 1047 ioat_submit_single(ioat); 1048 return (&desc->bus_dmadesc); 1049 } 1050 1051 struct bus_dmadesc * 1052 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1053 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1054 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1055 { 1056 struct ioat_dma_hw_descriptor *hw_desc; 1057 struct ioat_descriptor *desc; 1058 struct ioat_softc *ioat; 1059 1060 ioat = to_ioat_softc(dmaengine); 1061 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1062 1063 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 1064 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1065 __func__); 1066 return (NULL); 1067 } 1068 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 1069 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 1070 __func__); 1071 return (NULL); 1072 } 1073 1074 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 1075 callback_fn, callback_arg, flags); 1076 if (desc == NULL) 1077 return (NULL); 1078 1079 hw_desc = desc->u.dma; 1080 if (src2 != src1 + PAGE_SIZE) { 1081 hw_desc->u.control.src_page_break = 1; 1082 hw_desc->next_src_addr = src2; 1083 } 1084 if (dst2 != dst1 + PAGE_SIZE) { 1085 hw_desc->u.control.dest_page_break = 1; 1086 hw_desc->next_dest_addr = dst2; 1087 } 1088 1089 if (g_ioat_debug_level >= 3) 1090 dump_descriptor(hw_desc); 1091 1092 ioat_submit_single(ioat); 1093 return (&desc->bus_dmadesc); 1094 } 1095 1096 struct bus_dmadesc * 1097 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1098 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1099 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1100 { 1101 struct ioat_crc32_hw_descriptor *hw_desc; 1102 struct ioat_descriptor *desc; 1103 struct ioat_softc *ioat; 1104 uint32_t teststore; 1105 uint8_t op; 1106 1107 ioat = to_ioat_softc(dmaengine); 1108 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1109 1110 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1111 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1112 __func__); 1113 return (NULL); 1114 } 1115 if (((src | dst) & (0xffffffull << 40)) != 0) { 1116 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1117 __func__); 1118 return (NULL); 1119 } 1120 teststore = (flags & _DMA_CRC_TESTSTORE); 1121 if (teststore == _DMA_CRC_TESTSTORE) { 1122 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1123 return (NULL); 1124 } 1125 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1126 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1127 __func__); 1128 return (NULL); 1129 } 1130 1131 switch (teststore) { 1132 case DMA_CRC_STORE: 1133 op = IOAT_OP_MOVECRC_STORE; 1134 break; 1135 case DMA_CRC_TEST: 1136 op = IOAT_OP_MOVECRC_TEST; 1137 break; 1138 default: 1139 KASSERT(teststore == 0, ("bogus")); 1140 op = IOAT_OP_MOVECRC; 1141 break; 1142 } 1143 1144 if ((flags & DMA_CRC_INLINE) == 0 && 1145 (crcptr & (0xffffffull << 40)) != 0) { 1146 ioat_log_message(0, 1147 "%s: High 24 bits of crcptr invalid\n", __func__); 1148 return (NULL); 1149 } 1150 1151 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1152 callback_arg, flags & ~_DMA_CRC_FLAGS); 1153 if (desc == NULL) 1154 return (NULL); 1155 1156 hw_desc = desc->u.crc32; 1157 1158 if ((flags & DMA_CRC_INLINE) == 0) 1159 hw_desc->crc_address = crcptr; 1160 else 1161 hw_desc->u.control.crc_location = 1; 1162 1163 if (initialseed != NULL) { 1164 hw_desc->u.control.use_seed = 1; 1165 hw_desc->seed = *initialseed; 1166 } 1167 1168 if (g_ioat_debug_level >= 3) 1169 dump_descriptor(hw_desc); 1170 1171 ioat_submit_single(ioat); 1172 return (&desc->bus_dmadesc); 1173 } 1174 1175 struct bus_dmadesc * 1176 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1177 uint32_t *initialseed, bus_addr_t crcptr, 1178 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1179 { 1180 struct ioat_crc32_hw_descriptor *hw_desc; 1181 struct ioat_descriptor *desc; 1182 struct ioat_softc *ioat; 1183 uint32_t teststore; 1184 uint8_t op; 1185 1186 ioat = to_ioat_softc(dmaengine); 1187 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1188 1189 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1190 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1191 __func__); 1192 return (NULL); 1193 } 1194 if ((src & (0xffffffull << 40)) != 0) { 1195 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1196 __func__); 1197 return (NULL); 1198 } 1199 teststore = (flags & _DMA_CRC_TESTSTORE); 1200 if (teststore == _DMA_CRC_TESTSTORE) { 1201 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1202 return (NULL); 1203 } 1204 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1205 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1206 __func__); 1207 return (NULL); 1208 } 1209 1210 switch (teststore) { 1211 case DMA_CRC_STORE: 1212 op = IOAT_OP_CRC_STORE; 1213 break; 1214 case DMA_CRC_TEST: 1215 op = IOAT_OP_CRC_TEST; 1216 break; 1217 default: 1218 KASSERT(teststore == 0, ("bogus")); 1219 op = IOAT_OP_CRC; 1220 break; 1221 } 1222 1223 if ((flags & DMA_CRC_INLINE) == 0 && 1224 (crcptr & (0xffffffull << 40)) != 0) { 1225 ioat_log_message(0, 1226 "%s: High 24 bits of crcptr invalid\n", __func__); 1227 return (NULL); 1228 } 1229 1230 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1231 callback_arg, flags & ~_DMA_CRC_FLAGS); 1232 if (desc == NULL) 1233 return (NULL); 1234 1235 hw_desc = desc->u.crc32; 1236 1237 if ((flags & DMA_CRC_INLINE) == 0) 1238 hw_desc->crc_address = crcptr; 1239 else 1240 hw_desc->u.control.crc_location = 1; 1241 1242 if (initialseed != NULL) { 1243 hw_desc->u.control.use_seed = 1; 1244 hw_desc->seed = *initialseed; 1245 } 1246 1247 if (g_ioat_debug_level >= 3) 1248 dump_descriptor(hw_desc); 1249 1250 ioat_submit_single(ioat); 1251 return (&desc->bus_dmadesc); 1252 } 1253 1254 struct bus_dmadesc * 1255 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1256 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1257 uint32_t flags) 1258 { 1259 struct ioat_fill_hw_descriptor *hw_desc; 1260 struct ioat_descriptor *desc; 1261 struct ioat_softc *ioat; 1262 1263 ioat = to_ioat_softc(dmaengine); 1264 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1265 1266 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1267 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1268 __func__); 1269 return (NULL); 1270 } 1271 1272 if ((dst & (0xffffull << 48)) != 0) { 1273 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1274 __func__); 1275 return (NULL); 1276 } 1277 1278 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1279 callback_fn, callback_arg, flags); 1280 if (desc == NULL) 1281 return (NULL); 1282 1283 hw_desc = desc->u.fill; 1284 if (g_ioat_debug_level >= 3) 1285 dump_descriptor(hw_desc); 1286 1287 ioat_submit_single(ioat); 1288 return (&desc->bus_dmadesc); 1289 } 1290 1291 /* 1292 * Ring Management 1293 */ 1294 static inline uint32_t 1295 ioat_get_active(struct ioat_softc *ioat) 1296 { 1297 1298 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1299 } 1300 1301 static inline uint32_t 1302 ioat_get_ring_space(struct ioat_softc *ioat) 1303 { 1304 1305 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1306 } 1307 1308 static struct ioat_descriptor * 1309 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 1310 { 1311 struct ioat_generic_hw_descriptor *hw_desc; 1312 struct ioat_descriptor *desc; 1313 int error, busdmaflag; 1314 1315 error = ENOMEM; 1316 hw_desc = NULL; 1317 1318 if ((mflags & M_WAITOK) != 0) 1319 busdmaflag = BUS_DMA_WAITOK; 1320 else 1321 busdmaflag = BUS_DMA_NOWAIT; 1322 1323 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1324 if (desc == NULL) 1325 goto out; 1326 1327 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1328 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1329 if (hw_desc == NULL) 1330 goto out; 1331 1332 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1333 desc->u.generic = hw_desc; 1334 1335 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1336 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1337 busdmaflag); 1338 if (error) 1339 goto out; 1340 1341 out: 1342 if (error) { 1343 ioat_free_ring_entry(ioat, desc); 1344 return (NULL); 1345 } 1346 return (desc); 1347 } 1348 1349 static void 1350 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1351 { 1352 1353 if (desc == NULL) 1354 return; 1355 1356 if (desc->u.generic) 1357 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1358 ioat->hw_desc_map); 1359 free(desc, M_IOAT); 1360 } 1361 1362 /* 1363 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1364 * for 'num_descs'. 1365 * 1366 * If mflags contains M_WAITOK, blocks until enough space is available. 1367 * 1368 * Returns zero on success, or an errno on error. If num_descs is beyond the 1369 * maximum ring size, returns EINVAl; if allocation would block and mflags 1370 * contains M_NOWAIT, returns EAGAIN. 1371 * 1372 * Must be called with the submit_lock held; returns with the lock held. The 1373 * lock may be dropped to allocate the ring. 1374 * 1375 * (The submit_lock is needed to add any entries to the ring, so callers are 1376 * assured enough room is available.) 1377 */ 1378 static int 1379 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1380 { 1381 struct ioat_descriptor **new_ring; 1382 uint32_t order; 1383 boolean_t dug; 1384 int error; 1385 1386 mtx_assert(&ioat->submit_lock, MA_OWNED); 1387 error = 0; 1388 dug = FALSE; 1389 1390 if (num_descs < 1 || num_descs >= (1 << IOAT_MAX_ORDER)) { 1391 error = EINVAL; 1392 goto out; 1393 } 1394 1395 for (;;) { 1396 if (ioat->quiescing) { 1397 error = ENXIO; 1398 goto out; 1399 } 1400 1401 if (ioat_get_ring_space(ioat) >= num_descs) 1402 goto out; 1403 1404 if (!dug && !ioat->is_submitter_processing && 1405 (1 << ioat->ring_size_order) > num_descs) { 1406 ioat->is_submitter_processing = TRUE; 1407 mtx_unlock(&ioat->submit_lock); 1408 1409 ioat_process_events(ioat); 1410 1411 mtx_lock(&ioat->submit_lock); 1412 dug = TRUE; 1413 KASSERT(ioat->is_submitter_processing == TRUE, 1414 ("is_submitter_processing")); 1415 ioat->is_submitter_processing = FALSE; 1416 wakeup(&ioat->tail); 1417 continue; 1418 } 1419 1420 order = ioat->ring_size_order; 1421 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1422 if ((mflags & M_WAITOK) != 0) { 1423 msleep(&ioat->tail, &ioat->submit_lock, 0, 1424 "ioat_rsz", 0); 1425 continue; 1426 } 1427 1428 error = EAGAIN; 1429 break; 1430 } 1431 1432 ioat->is_resize_pending = TRUE; 1433 for (;;) { 1434 mtx_unlock(&ioat->submit_lock); 1435 1436 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1437 TRUE, mflags); 1438 1439 mtx_lock(&ioat->submit_lock); 1440 KASSERT(ioat->ring_size_order == order, 1441 ("is_resize_pending should protect order")); 1442 1443 if (new_ring == NULL) { 1444 KASSERT((mflags & M_WAITOK) == 0, 1445 ("allocation failed")); 1446 error = EAGAIN; 1447 break; 1448 } 1449 1450 error = ring_grow(ioat, order, new_ring); 1451 if (error == 0) 1452 break; 1453 } 1454 ioat->is_resize_pending = FALSE; 1455 wakeup(&ioat->tail); 1456 if (error) 1457 break; 1458 } 1459 1460 out: 1461 mtx_assert(&ioat->submit_lock, MA_OWNED); 1462 KASSERT(!ioat->quiescing || error == ENXIO, 1463 ("reserved during quiesce")); 1464 return (error); 1465 } 1466 1467 static struct ioat_descriptor ** 1468 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1469 int mflags) 1470 { 1471 struct ioat_descriptor **ring; 1472 uint32_t i; 1473 int error; 1474 1475 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1476 1477 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1478 if (ring == NULL) 1479 return (NULL); 1480 1481 if (need_dscr) { 1482 error = ENOMEM; 1483 for (i = size / 2; i < size; i++) { 1484 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1485 if (ring[i] == NULL) 1486 goto out; 1487 ring[i]->id = i; 1488 } 1489 } 1490 error = 0; 1491 1492 out: 1493 if (error != 0 && ring != NULL) { 1494 ioat_free_ring(ioat, size, ring); 1495 ring = NULL; 1496 } 1497 return (ring); 1498 } 1499 1500 static void 1501 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1502 struct ioat_descriptor **ring) 1503 { 1504 uint32_t i; 1505 1506 for (i = 0; i < size; i++) { 1507 if (ring[i] != NULL) 1508 ioat_free_ring_entry(ioat, ring[i]); 1509 } 1510 free(ring, M_IOAT); 1511 } 1512 1513 static struct ioat_descriptor * 1514 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1515 { 1516 1517 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1518 } 1519 1520 static int 1521 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1522 struct ioat_descriptor **newring) 1523 { 1524 struct ioat_descriptor *tmp, *next; 1525 struct ioat_dma_hw_descriptor *hw; 1526 uint32_t oldsize, newsize, head, tail, i, end; 1527 int error; 1528 1529 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1530 1531 mtx_assert(&ioat->submit_lock, MA_OWNED); 1532 1533 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1534 error = EINVAL; 1535 goto out; 1536 } 1537 1538 oldsize = (1 << oldorder); 1539 newsize = (1 << (oldorder + 1)); 1540 1541 mtx_lock(&ioat->cleanup_lock); 1542 1543 head = ioat->head & (oldsize - 1); 1544 tail = ioat->tail & (oldsize - 1); 1545 1546 /* Copy old descriptors to new ring */ 1547 for (i = 0; i < oldsize; i++) 1548 newring[i] = ioat->ring[i]; 1549 1550 /* 1551 * If head has wrapped but tail hasn't, we must swap some descriptors 1552 * around so that tail can increment directly to head. 1553 */ 1554 if (head < tail) { 1555 for (i = 0; i <= head; i++) { 1556 tmp = newring[oldsize + i]; 1557 1558 newring[oldsize + i] = newring[i]; 1559 newring[oldsize + i]->id = oldsize + i; 1560 1561 newring[i] = tmp; 1562 newring[i]->id = i; 1563 } 1564 head += oldsize; 1565 } 1566 1567 KASSERT(head >= tail, ("invariants")); 1568 1569 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1570 if (head < oldsize) { 1571 i = oldsize - 1; 1572 end = newsize; 1573 } else { 1574 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1575 i = head; 1576 end = newsize + (head - oldsize) + 1; 1577 } 1578 1579 /* 1580 * Fix up hardware ring, being careful not to trample the active 1581 * section (tail -> head). 1582 */ 1583 for (; i < end; i++) { 1584 KASSERT((i & (newsize - 1)) < tail || 1585 (i & (newsize - 1)) >= head, ("trampling snake")); 1586 1587 next = newring[(i + 1) & (newsize - 1)]; 1588 hw = newring[i & (newsize - 1)]->u.dma; 1589 hw->next = next->hw_desc_bus_addr; 1590 } 1591 1592 #ifdef INVARIANTS 1593 for (i = 0; i < newsize; i++) { 1594 next = newring[(i + 1) & (newsize - 1)]; 1595 hw = newring[i & (newsize - 1)]->u.dma; 1596 1597 KASSERT(hw->next == next->hw_desc_bus_addr, 1598 ("mismatch at i:%u (oldsize:%u); next=%p nextaddr=0x%lx" 1599 " (tail:%u)", i, oldsize, next, next->hw_desc_bus_addr, 1600 tail)); 1601 } 1602 #endif 1603 1604 free(ioat->ring, M_IOAT); 1605 ioat->ring = newring; 1606 ioat->ring_size_order = oldorder + 1; 1607 ioat->tail = tail; 1608 ioat->head = head; 1609 error = 0; 1610 1611 mtx_unlock(&ioat->cleanup_lock); 1612 out: 1613 if (error) 1614 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1615 return (error); 1616 } 1617 1618 static int 1619 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1620 struct ioat_descriptor **newring) 1621 { 1622 struct ioat_dma_hw_descriptor *hw; 1623 struct ioat_descriptor *ent, *next; 1624 uint32_t oldsize, newsize, current_idx, new_idx, i; 1625 int error; 1626 1627 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1628 1629 mtx_assert(&ioat->submit_lock, MA_OWNED); 1630 1631 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1632 error = EINVAL; 1633 goto out_unlocked; 1634 } 1635 1636 oldsize = (1 << oldorder); 1637 newsize = (1 << (oldorder - 1)); 1638 1639 mtx_lock(&ioat->cleanup_lock); 1640 1641 /* Can't shrink below current active set! */ 1642 if (ioat_get_active(ioat) >= newsize) { 1643 error = ENOMEM; 1644 goto out; 1645 } 1646 1647 /* 1648 * Copy current descriptors to the new ring, dropping the removed 1649 * descriptors. 1650 */ 1651 for (i = 0; i < newsize; i++) { 1652 current_idx = (ioat->tail + i) & (oldsize - 1); 1653 new_idx = (ioat->tail + i) & (newsize - 1); 1654 1655 newring[new_idx] = ioat->ring[current_idx]; 1656 newring[new_idx]->id = new_idx; 1657 } 1658 1659 /* Free deleted descriptors */ 1660 for (i = newsize; i < oldsize; i++) { 1661 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1662 ioat_free_ring_entry(ioat, ent); 1663 } 1664 1665 /* Fix up hardware ring. */ 1666 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1667 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1668 hw->next = next->hw_desc_bus_addr; 1669 1670 #ifdef INVARIANTS 1671 for (i = 0; i < newsize; i++) { 1672 next = newring[(i + 1) & (newsize - 1)]; 1673 hw = newring[i & (newsize - 1)]->u.dma; 1674 1675 KASSERT(hw->next == next->hw_desc_bus_addr, 1676 ("mismatch at i:%u (newsize:%u); next=%p nextaddr=0x%lx " 1677 "(tail:%u)", i, newsize, next, next->hw_desc_bus_addr, 1678 ioat->tail)); 1679 } 1680 #endif 1681 1682 free(ioat->ring, M_IOAT); 1683 ioat->ring = newring; 1684 ioat->ring_size_order = oldorder - 1; 1685 error = 0; 1686 1687 out: 1688 mtx_unlock(&ioat->cleanup_lock); 1689 out_unlocked: 1690 if (error) 1691 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1692 return (error); 1693 } 1694 1695 static void 1696 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1697 { 1698 struct ioat_descriptor *desc; 1699 1700 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1701 IOAT_CHANERR_STR); 1702 if (chanerr == 0) 1703 return; 1704 1705 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1706 1707 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1708 dump_descriptor(desc->u.raw); 1709 1710 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1711 dump_descriptor(desc->u.raw); 1712 } 1713 1714 static void 1715 ioat_poll_timer_callback(void *arg) 1716 { 1717 struct ioat_softc *ioat; 1718 1719 ioat = arg; 1720 ioat_log_message(3, "%s\n", __func__); 1721 1722 ioat_process_events(ioat); 1723 } 1724 1725 static void 1726 ioat_shrink_timer_callback(void *arg) 1727 { 1728 struct ioat_descriptor **newring; 1729 struct ioat_softc *ioat; 1730 uint32_t order; 1731 1732 ioat = arg; 1733 ioat_log_message(1, "%s\n", __func__); 1734 1735 /* Slowly scale the ring down if idle. */ 1736 mtx_lock(&ioat->submit_lock); 1737 1738 /* Don't run while the hardware is being reset. */ 1739 if (ioat->resetting) { 1740 mtx_unlock(&ioat->submit_lock); 1741 return; 1742 } 1743 1744 order = ioat->ring_size_order; 1745 if (ioat->is_completion_pending || ioat->is_resize_pending || 1746 order == IOAT_MIN_ORDER) { 1747 mtx_unlock(&ioat->submit_lock); 1748 goto out; 1749 } 1750 ioat->is_resize_pending = TRUE; 1751 mtx_unlock(&ioat->submit_lock); 1752 1753 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1754 M_NOWAIT); 1755 1756 mtx_lock(&ioat->submit_lock); 1757 KASSERT(ioat->ring_size_order == order, 1758 ("resize_pending protects order")); 1759 1760 if (newring != NULL && !ioat->is_completion_pending) 1761 ring_shrink(ioat, order, newring); 1762 else if (newring != NULL) 1763 ioat_free_ring(ioat, (1 << (order - 1)), newring); 1764 1765 ioat->is_resize_pending = FALSE; 1766 mtx_unlock(&ioat->submit_lock); 1767 1768 out: 1769 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1770 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 1771 ioat_shrink_timer_callback, ioat); 1772 } 1773 1774 /* 1775 * Support Functions 1776 */ 1777 static void 1778 ioat_submit_single(struct ioat_softc *ioat) 1779 { 1780 1781 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1782 atomic_add_rel_int(&ioat->head, 1); 1783 atomic_add_rel_int(&ioat->hw_head, 1); 1784 1785 if (!ioat->is_completion_pending) { 1786 ioat->is_completion_pending = TRUE; 1787 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 1788 ioat); 1789 callout_stop(&ioat->shrink_timer); 1790 } 1791 1792 ioat->stats.descriptors_submitted++; 1793 } 1794 1795 static int 1796 ioat_reset_hw(struct ioat_softc *ioat) 1797 { 1798 uint64_t status; 1799 uint32_t chanerr; 1800 unsigned timeout; 1801 int error; 1802 1803 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1804 1805 mtx_lock(IOAT_REFLK); 1806 while (ioat->resetting && !ioat->destroying) 1807 msleep(&ioat->resetting, IOAT_REFLK, 0, "IRH_drain", 0); 1808 if (ioat->destroying) { 1809 mtx_unlock(IOAT_REFLK); 1810 return (ENXIO); 1811 } 1812 ioat->resetting = TRUE; 1813 1814 ioat->quiescing = TRUE; 1815 ioat_drain_locked(ioat); 1816 mtx_unlock(IOAT_REFLK); 1817 1818 /* 1819 * Suspend ioat_process_events while the hardware and softc are in an 1820 * indeterminate state. 1821 */ 1822 mtx_lock(&ioat->cleanup_lock); 1823 ioat->resetting_cleanup = TRUE; 1824 mtx_unlock(&ioat->cleanup_lock); 1825 1826 status = ioat_get_chansts(ioat); 1827 if (is_ioat_active(status) || is_ioat_idle(status)) 1828 ioat_suspend(ioat); 1829 1830 /* Wait at most 20 ms */ 1831 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1832 timeout < 20; timeout++) { 1833 DELAY(1000); 1834 status = ioat_get_chansts(ioat); 1835 } 1836 if (timeout == 20) { 1837 error = ETIMEDOUT; 1838 goto out; 1839 } 1840 1841 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1842 1843 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1844 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1845 1846 /* 1847 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1848 * that can cause stability issues for IOAT v3. 1849 */ 1850 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1851 4); 1852 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1853 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1854 1855 /* 1856 * BDXDE and BWD models reset MSI-X registers on device reset. 1857 * Save/restore their contents manually. 1858 */ 1859 if (ioat_model_resets_msix(ioat)) { 1860 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1861 pci_save_state(ioat->device); 1862 } 1863 1864 ioat_reset(ioat); 1865 1866 /* Wait at most 20 ms */ 1867 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1868 DELAY(1000); 1869 if (timeout == 20) { 1870 error = ETIMEDOUT; 1871 goto out; 1872 } 1873 1874 if (ioat_model_resets_msix(ioat)) { 1875 ioat_log_message(1, "device resets registers; restored\n"); 1876 pci_restore_state(ioat->device); 1877 } 1878 1879 /* Reset attempts to return the hardware to "halted." */ 1880 status = ioat_get_chansts(ioat); 1881 if (is_ioat_active(status) || is_ioat_idle(status)) { 1882 /* So this really shouldn't happen... */ 1883 ioat_log_message(0, "Device is active after a reset?\n"); 1884 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1885 error = 0; 1886 goto out; 1887 } 1888 1889 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1890 if (chanerr != 0) { 1891 mtx_lock(&ioat->cleanup_lock); 1892 ioat_halted_debug(ioat, chanerr); 1893 mtx_unlock(&ioat->cleanup_lock); 1894 error = EIO; 1895 goto out; 1896 } 1897 1898 /* 1899 * Bring device back online after reset. Writing CHAINADDR brings the 1900 * device back to active. 1901 * 1902 * The internal ring counter resets to zero, so we have to start over 1903 * at zero as well. 1904 */ 1905 ioat->tail = ioat->head = ioat->hw_head = 0; 1906 ioat->last_seen = 0; 1907 *ioat->comp_update = 0; 1908 KASSERT(!ioat->is_completion_pending, ("bogus completion_pending")); 1909 1910 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1911 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1912 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1913 error = 0; 1914 1915 out: 1916 /* 1917 * Resume completions now that ring state is consistent. 1918 * ioat_start_channel will add a pending completion and if we are still 1919 * blocking completions, we may livelock. 1920 */ 1921 mtx_lock(&ioat->cleanup_lock); 1922 ioat->resetting_cleanup = FALSE; 1923 mtx_unlock(&ioat->cleanup_lock); 1924 1925 /* Enqueues a null operation and ensures it completes. */ 1926 if (error == 0) 1927 error = ioat_start_channel(ioat); 1928 1929 /* Unblock submission of new work */ 1930 mtx_lock(IOAT_REFLK); 1931 ioat->quiescing = FALSE; 1932 wakeup(&ioat->quiescing); 1933 1934 ioat->resetting = FALSE; 1935 wakeup(&ioat->resetting); 1936 mtx_unlock(IOAT_REFLK); 1937 1938 return (error); 1939 } 1940 1941 static int 1942 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1943 { 1944 struct ioat_softc *ioat; 1945 struct sbuf sb; 1946 uint64_t status; 1947 int error; 1948 1949 ioat = arg1; 1950 1951 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1952 1953 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1954 switch (status) { 1955 case IOAT_CHANSTS_ACTIVE: 1956 sbuf_printf(&sb, "ACTIVE"); 1957 break; 1958 case IOAT_CHANSTS_IDLE: 1959 sbuf_printf(&sb, "IDLE"); 1960 break; 1961 case IOAT_CHANSTS_SUSPENDED: 1962 sbuf_printf(&sb, "SUSPENDED"); 1963 break; 1964 case IOAT_CHANSTS_HALTED: 1965 sbuf_printf(&sb, "HALTED"); 1966 break; 1967 case IOAT_CHANSTS_ARMED: 1968 sbuf_printf(&sb, "ARMED"); 1969 break; 1970 default: 1971 sbuf_printf(&sb, "UNKNOWN"); 1972 break; 1973 } 1974 error = sbuf_finish(&sb); 1975 sbuf_delete(&sb); 1976 1977 if (error != 0 || req->newptr == NULL) 1978 return (error); 1979 return (EINVAL); 1980 } 1981 1982 static int 1983 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1984 { 1985 struct ioat_softc *ioat; 1986 struct sbuf sb; 1987 #define PRECISION "1" 1988 const uintmax_t factor = 10; 1989 uintmax_t rate; 1990 int error; 1991 1992 ioat = arg1; 1993 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1994 1995 if (ioat->stats.interrupts == 0) { 1996 sbuf_printf(&sb, "NaN"); 1997 goto out; 1998 } 1999 rate = ioat->stats.descriptors_processed * factor / 2000 ioat->stats.interrupts; 2001 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 2002 rate % factor); 2003 #undef PRECISION 2004 out: 2005 error = sbuf_finish(&sb); 2006 sbuf_delete(&sb); 2007 if (error != 0 || req->newptr == NULL) 2008 return (error); 2009 return (EINVAL); 2010 } 2011 2012 static int 2013 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 2014 { 2015 struct ioat_softc *ioat; 2016 int error, arg; 2017 2018 ioat = arg1; 2019 2020 arg = 0; 2021 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 2022 if (error != 0 || req->newptr == NULL) 2023 return (error); 2024 2025 error = SYSCTL_IN(req, &arg, sizeof(arg)); 2026 if (error != 0) 2027 return (error); 2028 2029 if (arg != 0) 2030 error = ioat_reset_hw(ioat); 2031 2032 return (error); 2033 } 2034 2035 static void 2036 dump_descriptor(void *hw_desc) 2037 { 2038 int i, j; 2039 2040 for (i = 0; i < 2; i++) { 2041 for (j = 0; j < 8; j++) 2042 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 2043 printf("\n"); 2044 } 2045 } 2046 2047 static void 2048 ioat_setup_sysctl(device_t device) 2049 { 2050 struct sysctl_oid_list *par, *statpar, *state, *hammer; 2051 struct sysctl_ctx_list *ctx; 2052 struct sysctl_oid *tree, *tmp; 2053 struct ioat_softc *ioat; 2054 2055 ioat = DEVICE2SOFTC(device); 2056 ctx = device_get_sysctl_ctx(device); 2057 tree = device_get_sysctl_tree(device); 2058 par = SYSCTL_CHILDREN(tree); 2059 2060 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 2061 &ioat->version, 0, "HW version (0xMM form)"); 2062 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 2063 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 2064 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 2065 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 2066 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 2067 &ioat->intrdelay_max, 0, 2068 "Maximum configurable INTRDELAY on this channel (microseconds)"); 2069 2070 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 2071 "IOAT channel internal state"); 2072 state = SYSCTL_CHILDREN(tmp); 2073 2074 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 2075 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 2076 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 2077 0, "SW descriptor head pointer index"); 2078 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 2079 0, "SW descriptor tail pointer index"); 2080 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 2081 &ioat->hw_head, 0, "HW DMACOUNT"); 2082 2083 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 2084 ioat->comp_update, "HW addr of last completion"); 2085 2086 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 2087 &ioat->is_resize_pending, 0, "resize pending"); 2088 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 2089 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 2090 "submitter processing"); 2091 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 2092 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 2093 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 2094 &ioat->is_reset_pending, 0, "reset pending"); 2095 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 2096 &ioat->is_channel_running, 0, "channel running"); 2097 2098 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 2099 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 2100 "String of the channel status"); 2101 2102 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 2103 &ioat->cached_intrdelay, 0, 2104 "Current INTRDELAY on this channel (cached, microseconds)"); 2105 2106 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 2107 "Big hammers (mostly for testing)"); 2108 hammer = SYSCTL_CHILDREN(tmp); 2109 2110 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 2111 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 2112 "Set to non-zero to reset the hardware"); 2113 2114 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 2115 "IOAT channel statistics"); 2116 statpar = SYSCTL_CHILDREN(tmp); 2117 2118 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 2119 &ioat->stats.interrupts, 2120 "Number of interrupts processed on this channel"); 2121 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 2122 &ioat->stats.descriptors_processed, 2123 "Number of descriptors processed on this channel"); 2124 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 2125 &ioat->stats.descriptors_submitted, 2126 "Number of descriptors submitted to this channel"); 2127 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 2128 &ioat->stats.descriptors_error, 2129 "Number of descriptors failed by channel errors"); 2130 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 2131 &ioat->stats.channel_halts, 0, 2132 "Number of times the channel has halted"); 2133 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 2134 &ioat->stats.last_halt_chanerr, 0, 2135 "The raw CHANERR when the channel was last halted"); 2136 2137 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 2138 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 2139 "Descriptors per interrupt"); 2140 } 2141 2142 static inline struct ioat_softc * 2143 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2144 { 2145 uint32_t old; 2146 2147 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2148 2149 old = atomic_fetchadd_32(&ioat->refcnt, 1); 2150 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 2151 2152 #ifdef INVARIANTS 2153 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 2154 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 2155 #endif 2156 2157 return (ioat); 2158 } 2159 2160 static inline void 2161 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2162 { 2163 2164 _ioat_putn(ioat, n, kind, FALSE); 2165 } 2166 2167 static inline void 2168 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2169 { 2170 2171 _ioat_putn(ioat, n, kind, TRUE); 2172 } 2173 2174 static inline void 2175 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 2176 boolean_t locked) 2177 { 2178 uint32_t old; 2179 2180 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2181 2182 if (n == 0) 2183 return; 2184 2185 #ifdef INVARIANTS 2186 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 2187 KASSERT(old >= n, ("refcnt kind underflow")); 2188 #endif 2189 2190 /* Skip acquiring the lock if resulting refcnt > 0. */ 2191 for (;;) { 2192 old = ioat->refcnt; 2193 if (old <= n) 2194 break; 2195 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 2196 return; 2197 } 2198 2199 if (locked) 2200 mtx_assert(IOAT_REFLK, MA_OWNED); 2201 else 2202 mtx_lock(IOAT_REFLK); 2203 2204 old = atomic_fetchadd_32(&ioat->refcnt, -n); 2205 KASSERT(old >= n, ("refcnt error")); 2206 2207 if (old == n) 2208 wakeup(IOAT_REFLK); 2209 if (!locked) 2210 mtx_unlock(IOAT_REFLK); 2211 } 2212 2213 static inline void 2214 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2215 { 2216 2217 ioat_putn(ioat, 1, kind); 2218 } 2219 2220 static void 2221 ioat_drain_locked(struct ioat_softc *ioat) 2222 { 2223 2224 mtx_assert(IOAT_REFLK, MA_OWNED); 2225 while (ioat->refcnt > 0) 2226 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 2227 } 2228 2229 #ifdef DDB 2230 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 2231 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 2232 DB_SHOW_COMMAND(ioat, db_show_ioat) 2233 { 2234 struct ioat_softc *sc; 2235 unsigned idx; 2236 2237 if (!have_addr) 2238 goto usage; 2239 idx = (unsigned)addr; 2240 if (idx >= ioat_channel_index) 2241 goto usage; 2242 2243 sc = ioat_channel[idx]; 2244 db_printf("ioat softc at %p\n", sc); 2245 if (sc == NULL) 2246 return; 2247 2248 db_printf(" version: %d\n", sc->version); 2249 db_printf(" chan_idx: %u\n", sc->chan_idx); 2250 db_printf(" submit_lock: "); 2251 db_show_lock(&sc->submit_lock); 2252 2253 db_printf(" capabilities: %b\n", (int)sc->capabilities, 2254 IOAT_DMACAP_STR); 2255 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 2256 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 2257 2258 db_printf(" poll_timer:\n"); 2259 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 2260 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 2261 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 2262 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 2263 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 2264 2265 db_printf(" shrink_timer:\n"); 2266 db_printf(" c_time: %ju\n", (uintmax_t)sc->shrink_timer.c_time); 2267 db_printf(" c_arg: %p\n", sc->shrink_timer.c_arg); 2268 db_printf(" c_func: %p\n", sc->shrink_timer.c_func); 2269 db_printf(" c_lock: %p\n", sc->shrink_timer.c_lock); 2270 db_printf(" c_flags: 0x%x\n", (unsigned)sc->shrink_timer.c_flags); 2271 2272 db_printf(" quiescing: %d\n", (int)sc->quiescing); 2273 db_printf(" destroying: %d\n", (int)sc->destroying); 2274 db_printf(" is_resize_pending: %d\n", (int)sc->is_resize_pending); 2275 db_printf(" is_submitter_processing: %d\n", 2276 (int)sc->is_submitter_processing); 2277 db_printf(" is_completion_pending: %d\n", (int)sc->is_completion_pending); 2278 db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending); 2279 db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running); 2280 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 2281 db_printf(" resetting: %d\n", (int)sc->resetting); 2282 2283 db_printf(" head: %u\n", sc->head); 2284 db_printf(" tail: %u\n", sc->tail); 2285 db_printf(" hw_head: %u\n", sc->hw_head); 2286 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2287 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2288 db_printf(" ring: %p\n", sc->ring); 2289 2290 db_printf(" ring[%u] (tail):\n", sc->tail % 2291 (1 << sc->ring_size_order)); 2292 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 2293 db_printf(" addr: 0x%lx\n", 2294 ioat_get_ring_entry(sc, sc->tail)->hw_desc_bus_addr); 2295 db_printf(" next: 0x%lx\n", 2296 ioat_get_ring_entry(sc, sc->tail)->u.generic->next); 2297 2298 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 2299 (1 << sc->ring_size_order)); 2300 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 2301 db_printf(" addr: 0x%lx\n", 2302 ioat_get_ring_entry(sc, sc->head - 1)->hw_desc_bus_addr); 2303 db_printf(" next: 0x%lx\n", 2304 ioat_get_ring_entry(sc, sc->head - 1)->u.generic->next); 2305 2306 db_printf(" ring[%u] (head):\n", (sc->head) % 2307 (1 << sc->ring_size_order)); 2308 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2309 db_printf(" addr: 0x%lx\n", 2310 ioat_get_ring_entry(sc, sc->head)->hw_desc_bus_addr); 2311 db_printf(" next: 0x%lx\n", 2312 ioat_get_ring_entry(sc, sc->head)->u.generic->next); 2313 2314 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2315 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2316 == ioat_get_ring_entry(sc, idx)->hw_desc_bus_addr) 2317 db_printf(" ring[%u] == hardware tail\n", idx); 2318 2319 db_printf(" cleanup_lock: "); 2320 db_show_lock(&sc->cleanup_lock); 2321 2322 db_printf(" refcnt: %u\n", sc->refcnt); 2323 #ifdef INVARIANTS 2324 CTASSERT(IOAT_NUM_REF_KINDS == 2); 2325 db_printf(" refkinds: [ENG=%u, DESCR=%u]\n", sc->refkinds[0], 2326 sc->refkinds[1]); 2327 #endif 2328 db_printf(" stats:\n"); 2329 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2330 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2331 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2332 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2333 2334 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2335 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2336 2337 if (db_pager_quit) 2338 return; 2339 2340 db_printf(" hw status:\n"); 2341 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2342 db_printf(" chanctrl: 0x%x\n", 2343 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2344 db_printf(" chancmd: 0x%x\n", 2345 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2346 db_printf(" dmacount: 0x%x\n", 2347 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2348 db_printf(" chainaddr: 0x%lx\n", 2349 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2350 db_printf(" chancmp: 0x%lx\n", 2351 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2352 db_printf(" chanerr: %b\n", 2353 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2354 return; 2355 usage: 2356 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2357 return; 2358 } 2359 #endif /* DDB */ 2360