1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/ioccom.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/sysctl.h> 42 #include <sys/time.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <machine/stdarg.h> 48 49 #include "ioat.h" 50 #include "ioat_hw.h" 51 #include "ioat_internal.h" 52 53 static int ioat_probe(device_t device); 54 static int ioat_attach(device_t device); 55 static int ioat_detach(device_t device); 56 static int ioat3_attach(device_t device); 57 static int ioat_map_pci_bar(struct ioat_softc *ioat); 58 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 59 int error); 60 static int ioat_interrupt_setup(struct ioat_softc *ioat); 61 static void ioat_interrupt_handler(void *arg); 62 static void ioat_process_events(struct ioat_softc *ioat); 63 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 64 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 65 static void ioat_free_ring_entry(struct ioat_softc *ioat, 66 struct ioat_descriptor *desc); 67 static struct ioat_descriptor * ioat_alloc_ring_entry(struct ioat_softc *ioat); 68 static int ioat_reserve_space_and_lock(struct ioat_softc *ioat, int num_descs); 69 static struct ioat_descriptor * ioat_get_ring_entry(struct ioat_softc *ioat, 70 uint32_t index); 71 static boolean_t resize_ring(struct ioat_softc *ioat, int order); 72 static void ioat_timer_callback(void *arg); 73 static void dump_descriptor(void *hw_desc); 74 static void ioat_submit_single(struct ioat_softc *ioat); 75 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 76 int error); 77 static int ioat_reset_hw(struct ioat_softc *ioat); 78 static void ioat_setup_sysctl(device_t device); 79 80 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 81 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 82 83 static int g_force_legacy_interrupts; 84 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 85 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 86 87 static int g_ioat_debug_level = 0; 88 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 89 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 90 91 /* 92 * OS <-> Driver interface structures 93 */ 94 static device_method_t ioat_pci_methods[] = { 95 /* Device interface */ 96 DEVMETHOD(device_probe, ioat_probe), 97 DEVMETHOD(device_attach, ioat_attach), 98 DEVMETHOD(device_detach, ioat_detach), 99 { 0, 0 } 100 }; 101 102 static driver_t ioat_pci_driver = { 103 "ioat", 104 ioat_pci_methods, 105 sizeof(struct ioat_softc), 106 }; 107 108 static devclass_t ioat_devclass; 109 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 110 111 /* 112 * Private data structures 113 */ 114 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 115 static int ioat_channel_index = 0; 116 SYSCTL_INT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 117 "Number of IOAT channels attached"); 118 119 static struct _pcsid 120 { 121 u_int32_t type; 122 const char *desc; 123 } pci_ids[] = { 124 { 0x34308086, "TBG IOAT Ch0" }, 125 { 0x34318086, "TBG IOAT Ch1" }, 126 { 0x34328086, "TBG IOAT Ch2" }, 127 { 0x34338086, "TBG IOAT Ch3" }, 128 { 0x34298086, "TBG IOAT Ch4" }, 129 { 0x342a8086, "TBG IOAT Ch5" }, 130 { 0x342b8086, "TBG IOAT Ch6" }, 131 { 0x342c8086, "TBG IOAT Ch7" }, 132 133 { 0x37108086, "JSF IOAT Ch0" }, 134 { 0x37118086, "JSF IOAT Ch1" }, 135 { 0x37128086, "JSF IOAT Ch2" }, 136 { 0x37138086, "JSF IOAT Ch3" }, 137 { 0x37148086, "JSF IOAT Ch4" }, 138 { 0x37158086, "JSF IOAT Ch5" }, 139 { 0x37168086, "JSF IOAT Ch6" }, 140 { 0x37178086, "JSF IOAT Ch7" }, 141 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 142 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 143 144 { 0x3c208086, "SNB IOAT Ch0" }, 145 { 0x3c218086, "SNB IOAT Ch1" }, 146 { 0x3c228086, "SNB IOAT Ch2" }, 147 { 0x3c238086, "SNB IOAT Ch3" }, 148 { 0x3c248086, "SNB IOAT Ch4" }, 149 { 0x3c258086, "SNB IOAT Ch5" }, 150 { 0x3c268086, "SNB IOAT Ch6" }, 151 { 0x3c278086, "SNB IOAT Ch7" }, 152 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 153 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 154 155 { 0x0e208086, "IVB IOAT Ch0" }, 156 { 0x0e218086, "IVB IOAT Ch1" }, 157 { 0x0e228086, "IVB IOAT Ch2" }, 158 { 0x0e238086, "IVB IOAT Ch3" }, 159 { 0x0e248086, "IVB IOAT Ch4" }, 160 { 0x0e258086, "IVB IOAT Ch5" }, 161 { 0x0e268086, "IVB IOAT Ch6" }, 162 { 0x0e278086, "IVB IOAT Ch7" }, 163 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 164 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 165 166 { 0x2f208086, "HSW IOAT Ch0" }, 167 { 0x2f218086, "HSW IOAT Ch1" }, 168 { 0x2f228086, "HSW IOAT Ch2" }, 169 { 0x2f238086, "HSW IOAT Ch3" }, 170 { 0x2f248086, "HSW IOAT Ch4" }, 171 { 0x2f258086, "HSW IOAT Ch5" }, 172 { 0x2f268086, "HSW IOAT Ch6" }, 173 { 0x2f278086, "HSW IOAT Ch7" }, 174 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 175 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 176 177 { 0x0c508086, "BWD IOAT Ch0" }, 178 { 0x0c518086, "BWD IOAT Ch1" }, 179 { 0x0c528086, "BWD IOAT Ch2" }, 180 { 0x0c538086, "BWD IOAT Ch3" }, 181 182 { 0x6f508086, "BDXDE IOAT Ch0" }, 183 { 0x6f518086, "BDXDE IOAT Ch1" }, 184 { 0x6f528086, "BDXDE IOAT Ch2" }, 185 { 0x6f538086, "BDXDE IOAT Ch3" }, 186 187 { 0x00000000, NULL } 188 }; 189 190 /* 191 * OS <-> Driver linkage functions 192 */ 193 static int 194 ioat_probe(device_t device) 195 { 196 struct _pcsid *ep; 197 u_int32_t type; 198 199 type = pci_get_devid(device); 200 for (ep = pci_ids; ep->type; ep++) { 201 if (ep->type == type) { 202 device_set_desc(device, ep->desc); 203 return (0); 204 } 205 } 206 return (ENXIO); 207 } 208 209 static int 210 ioat_attach(device_t device) 211 { 212 struct ioat_softc *ioat; 213 int error; 214 215 ioat = DEVICE2SOFTC(device); 216 ioat->device = device; 217 218 error = ioat_map_pci_bar(ioat); 219 if (error != 0) 220 goto err; 221 222 ioat->version = ioat_read_cbver(ioat); 223 ioat_interrupt_setup(ioat); 224 225 if (ioat->version < IOAT_VER_3_0) { 226 error = ENODEV; 227 goto err; 228 } 229 230 error = ioat3_attach(device); 231 if (error != 0) 232 goto err; 233 234 error = pci_enable_busmaster(device); 235 if (error != 0) 236 goto err; 237 238 ioat_channel[ioat_channel_index++] = ioat; 239 240 err: 241 if (error != 0) 242 ioat_detach(device); 243 return (error); 244 } 245 246 static int 247 ioat_detach(device_t device) 248 { 249 struct ioat_softc *ioat; 250 uint32_t i; 251 252 ioat = DEVICE2SOFTC(device); 253 callout_drain(&ioat->timer); 254 255 pci_disable_busmaster(device); 256 257 if (ioat->pci_resource != NULL) 258 bus_release_resource(device, SYS_RES_MEMORY, 259 ioat->pci_resource_id, ioat->pci_resource); 260 261 if (ioat->ring != NULL) { 262 for (i = 0; i < (1 << ioat->ring_size_order); i++) 263 ioat_free_ring_entry(ioat, ioat->ring[i]); 264 free(ioat->ring, M_IOAT); 265 } 266 267 if (ioat->comp_update != NULL) { 268 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 269 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 270 ioat->comp_update_map); 271 bus_dma_tag_destroy(ioat->comp_update_tag); 272 } 273 274 bus_dma_tag_destroy(ioat->hw_desc_tag); 275 276 if (ioat->tag != NULL) 277 bus_teardown_intr(device, ioat->res, ioat->tag); 278 279 if (ioat->res != NULL) 280 bus_release_resource(device, SYS_RES_IRQ, 281 rman_get_rid(ioat->res), ioat->res); 282 283 pci_release_msi(device); 284 285 return (0); 286 } 287 288 static int 289 ioat3_selftest(struct ioat_softc *ioat) 290 { 291 uint64_t status; 292 uint32_t chanerr; 293 int i; 294 295 ioat_acquire(&ioat->dmaengine); 296 ioat_null(&ioat->dmaengine, NULL, NULL, 0); 297 ioat_release(&ioat->dmaengine); 298 299 for (i = 0; i < 100; i++) { 300 DELAY(1); 301 status = ioat_get_chansts(ioat); 302 if (is_ioat_idle(status)) 303 return (0); 304 } 305 306 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 307 ioat_log_message(0, "could not start channel: " 308 "status = %#jx error = %x\n", (uintmax_t)status, chanerr); 309 return (ENXIO); 310 } 311 312 /* 313 * Initialize Hardware 314 */ 315 static int 316 ioat3_attach(device_t device) 317 { 318 struct ioat_softc *ioat; 319 struct ioat_descriptor **ring; 320 struct ioat_descriptor *next; 321 struct ioat_dma_hw_descriptor *dma_hw_desc; 322 uint32_t capabilities; 323 int i, num_descriptors; 324 int error; 325 uint8_t xfercap; 326 327 error = 0; 328 ioat = DEVICE2SOFTC(device); 329 capabilities = ioat_read_dmacapability(ioat); 330 331 xfercap = ioat_read_xfercap(ioat); 332 333 /* Only bits [4:0] are valid. */ 334 xfercap &= 0x1f; 335 ioat->max_xfer_size = 1 << xfercap; 336 337 /* TODO: need to check DCA here if we ever do XOR/PQ */ 338 339 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 340 mtx_init(&ioat->cleanup_lock, "ioat_process_events", NULL, MTX_DEF); 341 callout_init(&ioat->timer, CALLOUT_MPSAFE); 342 343 ioat->is_resize_pending = FALSE; 344 ioat->is_completion_pending = FALSE; 345 ioat->is_reset_pending = FALSE; 346 ioat->is_channel_running = FALSE; 347 ioat->is_waiting_for_ack = FALSE; 348 349 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 350 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 351 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 352 &ioat->comp_update_tag); 353 354 error = bus_dmamem_alloc(ioat->comp_update_tag, 355 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 356 if (ioat->comp_update == NULL) 357 return (ENOMEM); 358 359 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 360 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 361 0); 362 if (error != 0) 363 return (error); 364 365 ioat->ring_size_order = IOAT_MIN_ORDER; 366 367 num_descriptors = 1 << ioat->ring_size_order; 368 369 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 370 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 371 sizeof(struct ioat_dma_hw_descriptor), 1, 372 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 373 &ioat->hw_desc_tag); 374 375 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 376 M_ZERO | M_NOWAIT); 377 if (ioat->ring == NULL) 378 return (ENOMEM); 379 380 ring = ioat->ring; 381 for (i = 0; i < num_descriptors; i++) { 382 ring[i] = ioat_alloc_ring_entry(ioat); 383 if (ring[i] == NULL) 384 return (ENOMEM); 385 386 ring[i]->id = i; 387 } 388 389 for (i = 0; i < num_descriptors - 1; i++) { 390 next = ring[i + 1]; 391 dma_hw_desc = ring[i]->u.dma; 392 393 dma_hw_desc->next = next->hw_desc_bus_addr; 394 } 395 396 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 397 398 ioat->head = 0; 399 ioat->tail = 0; 400 ioat->last_seen = 0; 401 402 error = ioat_reset_hw(ioat); 403 if (error != 0) 404 return (error); 405 406 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 407 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 408 ioat_write_chainaddr(ioat, ring[0]->hw_desc_bus_addr); 409 410 error = ioat3_selftest(ioat); 411 if (error != 0) 412 return (error); 413 414 ioat_process_events(ioat); 415 ioat_setup_sysctl(device); 416 return (0); 417 } 418 419 static int 420 ioat_map_pci_bar(struct ioat_softc *ioat) 421 { 422 423 ioat->pci_resource_id = PCIR_BAR(0); 424 ioat->pci_resource = bus_alloc_resource(ioat->device, SYS_RES_MEMORY, 425 &ioat->pci_resource_id, 0, ~0, 1, RF_ACTIVE); 426 427 if (ioat->pci_resource == NULL) { 428 ioat_log_message(0, "unable to allocate pci resource\n"); 429 return (ENODEV); 430 } 431 432 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 433 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 434 return (0); 435 } 436 437 static void 438 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 439 { 440 struct ioat_softc *ioat = arg; 441 442 ioat->comp_update_bus_addr = seg[0].ds_addr; 443 } 444 445 static void 446 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 447 { 448 bus_addr_t *baddr; 449 450 baddr = arg; 451 *baddr = segs->ds_addr; 452 } 453 454 /* 455 * Interrupt setup and handlers 456 */ 457 static int 458 ioat_interrupt_setup(struct ioat_softc *ioat) 459 { 460 uint32_t num_vectors; 461 int error; 462 boolean_t use_msix; 463 boolean_t force_legacy_interrupts; 464 465 use_msix = FALSE; 466 force_legacy_interrupts = FALSE; 467 468 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 469 num_vectors = 1; 470 pci_alloc_msix(ioat->device, &num_vectors); 471 if (num_vectors == 1) 472 use_msix = TRUE; 473 } 474 475 if (use_msix) { 476 ioat->rid = 1; 477 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 478 &ioat->rid, RF_ACTIVE); 479 } else { 480 ioat->rid = 0; 481 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 482 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 483 } 484 if (ioat->res == NULL) { 485 ioat_log_message(0, "bus_alloc_resource failed\n"); 486 return (ENOMEM); 487 } 488 489 ioat->tag = NULL; 490 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 491 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 492 if (error != 0) { 493 ioat_log_message(0, "bus_setup_intr failed\n"); 494 return (error); 495 } 496 497 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 498 return (0); 499 } 500 501 static void 502 ioat_interrupt_handler(void *arg) 503 { 504 struct ioat_softc *ioat = arg; 505 506 ioat_process_events(ioat); 507 } 508 509 static void 510 ioat_process_events(struct ioat_softc *ioat) 511 { 512 struct ioat_descriptor *desc; 513 struct bus_dmadesc *dmadesc; 514 uint64_t comp_update, status; 515 uint32_t completed; 516 517 mtx_lock(&ioat->cleanup_lock); 518 519 completed = 0; 520 comp_update = *ioat->comp_update; 521 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 522 523 ioat_log_message(3, "%s\n", __func__); 524 525 if (status == ioat->last_seen) { 526 mtx_unlock(&ioat->cleanup_lock); 527 return; 528 } 529 530 while (1) { 531 desc = ioat_get_ring_entry(ioat, ioat->tail); 532 dmadesc = &desc->bus_dmadesc; 533 ioat_log_message(3, "completing desc %d\n", ioat->tail); 534 535 if (dmadesc->callback_fn) 536 (*dmadesc->callback_fn)(dmadesc->callback_arg); 537 538 ioat->tail++; 539 if (desc->hw_desc_bus_addr == status) 540 break; 541 } 542 543 ioat->last_seen = desc->hw_desc_bus_addr; 544 545 if (ioat->head == ioat->tail) { 546 ioat->is_completion_pending = FALSE; 547 callout_reset(&ioat->timer, 5 * hz, ioat_timer_callback, ioat); 548 } 549 550 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 551 mtx_unlock(&ioat->cleanup_lock); 552 } 553 554 /* 555 * User API functions 556 */ 557 bus_dmaengine_t 558 ioat_get_dmaengine(uint32_t index) 559 { 560 561 if (index < ioat_channel_index) 562 return (&ioat_channel[index]->dmaengine); 563 return (NULL); 564 } 565 566 void 567 ioat_acquire(bus_dmaengine_t dmaengine) 568 { 569 struct ioat_softc *ioat; 570 571 ioat = to_ioat_softc(dmaengine); 572 mtx_lock(&ioat->submit_lock); 573 ioat_log_message(3, "%s\n", __func__); 574 } 575 576 void 577 ioat_release(bus_dmaengine_t dmaengine) 578 { 579 struct ioat_softc *ioat; 580 581 ioat_log_message(3, "%s\n", __func__); 582 ioat = to_ioat_softc(dmaengine); 583 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->head); 584 mtx_unlock(&ioat->submit_lock); 585 } 586 587 struct bus_dmadesc * 588 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 589 void *callback_arg, uint32_t flags) 590 { 591 struct ioat_softc *ioat; 592 struct ioat_descriptor *desc; 593 struct ioat_dma_hw_descriptor *hw_desc; 594 595 KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x", 596 flags & ~DMA_ALL_FLAGS)); 597 598 ioat = to_ioat_softc(dmaengine); 599 600 if (ioat_reserve_space_and_lock(ioat, 1) != 0) 601 return (NULL); 602 603 ioat_log_message(3, "%s\n", __func__); 604 605 desc = ioat_get_ring_entry(ioat, ioat->head); 606 hw_desc = desc->u.dma; 607 608 hw_desc->u.control_raw = 0; 609 hw_desc->u.control.null = 1; 610 hw_desc->u.control.completion_update = 1; 611 612 if ((flags & DMA_INT_EN) != 0) 613 hw_desc->u.control.int_enable = 1; 614 615 hw_desc->size = 8; 616 hw_desc->src_addr = 0; 617 hw_desc->dest_addr = 0; 618 619 desc->bus_dmadesc.callback_fn = callback_fn; 620 desc->bus_dmadesc.callback_arg = callback_arg; 621 622 ioat_submit_single(ioat); 623 return (&desc->bus_dmadesc); 624 } 625 626 struct bus_dmadesc * 627 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 628 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 629 void *callback_arg, uint32_t flags) 630 { 631 struct ioat_descriptor *desc; 632 struct ioat_dma_hw_descriptor *hw_desc; 633 struct ioat_softc *ioat; 634 635 KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x", 636 flags & ~DMA_ALL_FLAGS)); 637 638 ioat = to_ioat_softc(dmaengine); 639 640 if (len > ioat->max_xfer_size) { 641 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %d\n", 642 __func__, ioat->max_xfer_size, (int)len); 643 return (NULL); 644 } 645 646 if (ioat_reserve_space_and_lock(ioat, 1) != 0) 647 return (NULL); 648 649 ioat_log_message(3, "%s\n", __func__); 650 651 desc = ioat_get_ring_entry(ioat, ioat->head); 652 hw_desc = desc->u.dma; 653 654 hw_desc->u.control_raw = 0; 655 hw_desc->u.control.completion_update = 1; 656 657 if ((flags & DMA_INT_EN) != 0) 658 hw_desc->u.control.int_enable = 1; 659 660 hw_desc->size = len; 661 hw_desc->src_addr = src; 662 hw_desc->dest_addr = dst; 663 664 if (g_ioat_debug_level >= 3) 665 dump_descriptor(hw_desc); 666 667 desc->bus_dmadesc.callback_fn = callback_fn; 668 desc->bus_dmadesc.callback_arg = callback_arg; 669 670 ioat_submit_single(ioat); 671 return (&desc->bus_dmadesc); 672 } 673 674 /* 675 * Ring Management 676 */ 677 static inline uint32_t 678 ioat_get_active(struct ioat_softc *ioat) 679 { 680 681 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 682 } 683 684 static inline uint32_t 685 ioat_get_ring_space(struct ioat_softc *ioat) 686 { 687 688 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 689 } 690 691 static struct ioat_descriptor * 692 ioat_alloc_ring_entry(struct ioat_softc *ioat) 693 { 694 struct ioat_dma_hw_descriptor *hw_desc; 695 struct ioat_descriptor *desc; 696 697 desc = malloc(sizeof(struct ioat_descriptor), M_IOAT, M_NOWAIT); 698 if (desc == NULL) 699 return (NULL); 700 701 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, BUS_DMA_ZERO, 702 &ioat->hw_desc_map); 703 if (hw_desc == NULL) { 704 free(desc, M_IOAT); 705 return (NULL); 706 } 707 708 bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 709 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 0); 710 711 desc->u.dma = hw_desc; 712 return (desc); 713 } 714 715 static void 716 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 717 { 718 719 if (desc == NULL) 720 return; 721 722 if (desc->u.dma) 723 bus_dmamem_free(ioat->hw_desc_tag, desc->u.dma, 724 ioat->hw_desc_map); 725 free(desc, M_IOAT); 726 } 727 728 static int 729 ioat_reserve_space_and_lock(struct ioat_softc *ioat, int num_descs) 730 { 731 boolean_t retry; 732 733 while (1) { 734 if (ioat_get_ring_space(ioat) >= num_descs) 735 return (0); 736 737 mtx_lock(&ioat->cleanup_lock); 738 retry = resize_ring(ioat, ioat->ring_size_order + 1); 739 mtx_unlock(&ioat->cleanup_lock); 740 741 if (!retry) 742 return (ENOMEM); 743 } 744 } 745 746 static struct ioat_descriptor * 747 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 748 { 749 750 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 751 } 752 753 static boolean_t 754 resize_ring(struct ioat_softc *ioat, int order) 755 { 756 struct ioat_descriptor **ring; 757 struct ioat_descriptor *next; 758 struct ioat_dma_hw_descriptor *hw; 759 struct ioat_descriptor *ent; 760 uint32_t current_size, active, new_size, i, new_idx, current_idx; 761 uint32_t new_idx2; 762 763 current_size = 1 << ioat->ring_size_order; 764 active = (ioat->head - ioat->tail) & (current_size - 1); 765 new_size = 1 << order; 766 767 if (order > IOAT_MAX_ORDER) 768 return (FALSE); 769 770 /* 771 * when shrinking, verify that we can hold the current active 772 * set in the new ring 773 */ 774 if (active >= new_size) 775 return (FALSE); 776 777 /* allocate the array to hold the software ring */ 778 ring = malloc(new_size * sizeof(*ring), M_IOAT, M_ZERO | M_NOWAIT); 779 if (ring == NULL) 780 return (FALSE); 781 782 ioat_log_message(2, "ring resize: new: %d old: %d\n", 783 new_size, current_size); 784 785 /* allocate/trim descriptors as needed */ 786 if (new_size > current_size) { 787 /* copy current descriptors to the new ring */ 788 for (i = 0; i < current_size; i++) { 789 current_idx = (ioat->tail + i) & (current_size - 1); 790 new_idx = (ioat->tail + i) & (new_size - 1); 791 792 ring[new_idx] = ioat->ring[current_idx]; 793 ring[new_idx]->id = new_idx; 794 } 795 796 /* add new descriptors to the ring */ 797 for (i = current_size; i < new_size; i++) { 798 new_idx = (ioat->tail + i) & (new_size - 1); 799 800 ring[new_idx] = ioat_alloc_ring_entry(ioat); 801 if (ring[new_idx] == NULL) { 802 while (i--) { 803 new_idx2 = (ioat->tail + i) & 804 (new_size - 1); 805 806 ioat_free_ring_entry(ioat, 807 ring[new_idx2]); 808 } 809 free(ring, M_IOAT); 810 return (FALSE); 811 } 812 ring[new_idx]->id = new_idx; 813 } 814 815 for (i = current_size - 1; i < new_size; i++) { 816 new_idx = (ioat->tail + i) & (new_size - 1); 817 next = ring[(new_idx + 1) & (new_size - 1)]; 818 hw = ring[new_idx]->u.dma; 819 820 hw->next = next->hw_desc_bus_addr; 821 } 822 } else { 823 /* 824 * copy current descriptors to the new ring, dropping the 825 * removed descriptors 826 */ 827 for (i = 0; i < new_size; i++) { 828 current_idx = (ioat->tail + i) & (current_size - 1); 829 new_idx = (ioat->tail + i) & (new_size - 1); 830 831 ring[new_idx] = ioat->ring[current_idx]; 832 ring[new_idx]->id = new_idx; 833 } 834 835 /* free deleted descriptors */ 836 for (i = new_size; i < current_size; i++) { 837 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 838 ioat_free_ring_entry(ioat, ent); 839 } 840 841 /* fix up hardware ring */ 842 hw = ring[(ioat->tail + new_size - 1) & (new_size - 1)]->u.dma; 843 next = ring[(ioat->tail + new_size) & (new_size - 1)]; 844 hw->next = next->hw_desc_bus_addr; 845 } 846 847 free(ioat->ring, M_IOAT); 848 ioat->ring = ring; 849 ioat->ring_size_order = order; 850 851 return (TRUE); 852 } 853 854 static void 855 ioat_timer_callback(void *arg) 856 { 857 struct ioat_descriptor *desc; 858 struct ioat_softc *ioat; 859 uint64_t status; 860 uint32_t chanerr; 861 862 ioat = arg; 863 ioat_log_message(2, "%s\n", __func__); 864 865 if (ioat->is_completion_pending) { 866 status = ioat_get_chansts(ioat); 867 868 /* 869 * When halted due to errors, check for channel programming 870 * errors before advancing the completion state. 871 */ 872 if (is_ioat_halted(status)) { 873 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 874 ioat_log_message(0, "Channel halted (%x)\n", chanerr); 875 876 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 877 dump_descriptor(desc->u.raw); 878 879 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 880 dump_descriptor(desc->u.raw); 881 } 882 ioat_process_events(ioat); 883 } else { 884 mtx_lock(&ioat->submit_lock); 885 mtx_lock(&ioat->cleanup_lock); 886 887 if (ioat_get_active(ioat) == 0 && 888 ioat->ring_size_order > IOAT_MIN_ORDER) 889 resize_ring(ioat, ioat->ring_size_order - 1); 890 891 mtx_unlock(&ioat->cleanup_lock); 892 mtx_unlock(&ioat->submit_lock); 893 894 if (ioat->ring_size_order > IOAT_MIN_ORDER) 895 callout_reset(&ioat->timer, 5 * hz, 896 ioat_timer_callback, ioat); 897 } 898 } 899 900 /* 901 * Support Functions 902 */ 903 static void 904 ioat_submit_single(struct ioat_softc *ioat) 905 { 906 907 atomic_add_rel_int(&ioat->head, 1); 908 909 if (!ioat->is_completion_pending) { 910 ioat->is_completion_pending = TRUE; 911 callout_reset(&ioat->timer, 10 * hz, ioat_timer_callback, 912 ioat); 913 } 914 } 915 916 static int 917 ioat_reset_hw(struct ioat_softc *ioat) 918 { 919 uint64_t status; 920 uint32_t chanerr; 921 int timeout; 922 923 status = ioat_get_chansts(ioat); 924 if (is_ioat_active(status) || is_ioat_idle(status)) 925 ioat_suspend(ioat); 926 927 /* Wait at most 20 ms */ 928 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 929 timeout < 20; timeout++) { 930 DELAY(1000); 931 status = ioat_get_chansts(ioat); 932 } 933 if (timeout == 20) 934 return (ETIMEDOUT); 935 936 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 937 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 938 939 /* 940 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 941 * that can cause stability issues for IOAT v3. 942 */ 943 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 944 4); 945 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 946 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 947 948 ioat_reset(ioat); 949 950 /* Wait at most 20 ms */ 951 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 952 DELAY(1000); 953 if (timeout == 20) 954 return (ETIMEDOUT); 955 956 return (0); 957 } 958 959 static void 960 dump_descriptor(void *hw_desc) 961 { 962 int i, j; 963 964 for (i = 0; i < 2; i++) { 965 for (j = 0; j < 8; j++) 966 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 967 printf("\n"); 968 } 969 } 970 971 static void 972 ioat_setup_sysctl(device_t device) 973 { 974 struct sysctl_ctx_list *sysctl_ctx; 975 struct sysctl_oid *sysctl_tree; 976 struct ioat_softc *ioat; 977 978 ioat = DEVICE2SOFTC(device); 979 sysctl_ctx = device_get_sysctl_ctx(device); 980 sysctl_tree = device_get_sysctl_tree(device); 981 982 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, 983 "ring_size_order", CTLFLAG_RD, &ioat->ring_size_order, 984 0, "HW descriptor ring size order"); 985 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, 986 "head", CTLFLAG_RD, &ioat->head, 987 0, "HW descriptor head pointer index"); 988 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO, 989 "tail", CTLFLAG_RD, &ioat->tail, 990 0, "HW descriptor tail pointer index"); 991 } 992 993 void 994 ioat_log_message(int verbosity, char *fmt, ...) 995 { 996 va_list argp; 997 char buffer[512]; 998 struct timeval tv; 999 1000 if (verbosity > g_ioat_debug_level) 1001 return; 1002 1003 va_start(argp, fmt); 1004 vsnprintf(buffer, sizeof(buffer) - 1, fmt, argp); 1005 va_end(argp); 1006 microuptime(&tv); 1007 1008 printf("[%d:%06d] ioat: %s", (int)tv.tv_sec, (int)tv.tv_usec, buffer); 1009 } 1010