1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/ioccom.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/sysctl.h> 42 #include <sys/time.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <machine/stdarg.h> 48 49 #include "ioat.h" 50 #include "ioat_hw.h" 51 #include "ioat_internal.h" 52 53 #define IOAT_INTR_TIMO (hz / 10) 54 #define IOAT_REFLK (&ioat->submit_lock) 55 56 static int ioat_probe(device_t device); 57 static int ioat_attach(device_t device); 58 static int ioat_detach(device_t device); 59 static int ioat_setup_intr(struct ioat_softc *ioat); 60 static int ioat_teardown_intr(struct ioat_softc *ioat); 61 static int ioat3_attach(device_t device); 62 static int ioat_start_channel(struct ioat_softc *ioat); 63 static int ioat_map_pci_bar(struct ioat_softc *ioat); 64 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 65 int error); 66 static void ioat_interrupt_handler(void *arg); 67 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 68 static void ioat_process_events(struct ioat_softc *ioat); 69 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 70 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 71 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 72 struct ioat_descriptor **); 73 static void ioat_free_ring_entry(struct ioat_softc *ioat, 74 struct ioat_descriptor *desc); 75 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 76 int mflags); 77 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 78 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 79 uint32_t index); 80 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 81 uint32_t size, boolean_t need_dscr, int mflags); 82 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 83 struct ioat_descriptor **); 84 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 85 struct ioat_descriptor **); 86 static void ioat_timer_callback(void *arg); 87 static void dump_descriptor(void *hw_desc); 88 static void ioat_submit_single(struct ioat_softc *ioat); 89 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 90 int error); 91 static int ioat_reset_hw(struct ioat_softc *ioat); 92 static void ioat_setup_sysctl(device_t device); 93 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 94 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 95 enum ioat_ref_kind); 96 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 97 static inline void ioat_putn(struct ioat_softc *, uint32_t, 98 enum ioat_ref_kind); 99 static void ioat_drain_locked(struct ioat_softc *); 100 101 #define ioat_log_message(v, ...) do { \ 102 if ((v) <= g_ioat_debug_level) { \ 103 device_printf(ioat->device, __VA_ARGS__); \ 104 } \ 105 } while (0) 106 107 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 108 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 109 110 static int g_force_legacy_interrupts; 111 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 112 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 113 114 int g_ioat_debug_level = 0; 115 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 116 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 117 118 /* 119 * OS <-> Driver interface structures 120 */ 121 static device_method_t ioat_pci_methods[] = { 122 /* Device interface */ 123 DEVMETHOD(device_probe, ioat_probe), 124 DEVMETHOD(device_attach, ioat_attach), 125 DEVMETHOD(device_detach, ioat_detach), 126 { 0, 0 } 127 }; 128 129 static driver_t ioat_pci_driver = { 130 "ioat", 131 ioat_pci_methods, 132 sizeof(struct ioat_softc), 133 }; 134 135 static devclass_t ioat_devclass; 136 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 137 138 /* 139 * Private data structures 140 */ 141 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 142 static int ioat_channel_index = 0; 143 SYSCTL_INT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 144 "Number of IOAT channels attached"); 145 146 static struct _pcsid 147 { 148 u_int32_t type; 149 const char *desc; 150 } pci_ids[] = { 151 { 0x34308086, "TBG IOAT Ch0" }, 152 { 0x34318086, "TBG IOAT Ch1" }, 153 { 0x34328086, "TBG IOAT Ch2" }, 154 { 0x34338086, "TBG IOAT Ch3" }, 155 { 0x34298086, "TBG IOAT Ch4" }, 156 { 0x342a8086, "TBG IOAT Ch5" }, 157 { 0x342b8086, "TBG IOAT Ch6" }, 158 { 0x342c8086, "TBG IOAT Ch7" }, 159 160 { 0x37108086, "JSF IOAT Ch0" }, 161 { 0x37118086, "JSF IOAT Ch1" }, 162 { 0x37128086, "JSF IOAT Ch2" }, 163 { 0x37138086, "JSF IOAT Ch3" }, 164 { 0x37148086, "JSF IOAT Ch4" }, 165 { 0x37158086, "JSF IOAT Ch5" }, 166 { 0x37168086, "JSF IOAT Ch6" }, 167 { 0x37178086, "JSF IOAT Ch7" }, 168 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 169 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 170 171 { 0x3c208086, "SNB IOAT Ch0" }, 172 { 0x3c218086, "SNB IOAT Ch1" }, 173 { 0x3c228086, "SNB IOAT Ch2" }, 174 { 0x3c238086, "SNB IOAT Ch3" }, 175 { 0x3c248086, "SNB IOAT Ch4" }, 176 { 0x3c258086, "SNB IOAT Ch5" }, 177 { 0x3c268086, "SNB IOAT Ch6" }, 178 { 0x3c278086, "SNB IOAT Ch7" }, 179 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 180 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 181 182 { 0x0e208086, "IVB IOAT Ch0" }, 183 { 0x0e218086, "IVB IOAT Ch1" }, 184 { 0x0e228086, "IVB IOAT Ch2" }, 185 { 0x0e238086, "IVB IOAT Ch3" }, 186 { 0x0e248086, "IVB IOAT Ch4" }, 187 { 0x0e258086, "IVB IOAT Ch5" }, 188 { 0x0e268086, "IVB IOAT Ch6" }, 189 { 0x0e278086, "IVB IOAT Ch7" }, 190 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 191 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 192 193 { 0x2f208086, "HSW IOAT Ch0" }, 194 { 0x2f218086, "HSW IOAT Ch1" }, 195 { 0x2f228086, "HSW IOAT Ch2" }, 196 { 0x2f238086, "HSW IOAT Ch3" }, 197 { 0x2f248086, "HSW IOAT Ch4" }, 198 { 0x2f258086, "HSW IOAT Ch5" }, 199 { 0x2f268086, "HSW IOAT Ch6" }, 200 { 0x2f278086, "HSW IOAT Ch7" }, 201 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 202 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 203 204 { 0x0c508086, "BWD IOAT Ch0" }, 205 { 0x0c518086, "BWD IOAT Ch1" }, 206 { 0x0c528086, "BWD IOAT Ch2" }, 207 { 0x0c538086, "BWD IOAT Ch3" }, 208 209 { 0x6f508086, "BDXDE IOAT Ch0" }, 210 { 0x6f518086, "BDXDE IOAT Ch1" }, 211 { 0x6f528086, "BDXDE IOAT Ch2" }, 212 { 0x6f538086, "BDXDE IOAT Ch3" }, 213 214 { 0x00000000, NULL } 215 }; 216 217 /* 218 * OS <-> Driver linkage functions 219 */ 220 static int 221 ioat_probe(device_t device) 222 { 223 struct _pcsid *ep; 224 u_int32_t type; 225 226 type = pci_get_devid(device); 227 for (ep = pci_ids; ep->type; ep++) { 228 if (ep->type == type) { 229 device_set_desc(device, ep->desc); 230 return (0); 231 } 232 } 233 return (ENXIO); 234 } 235 236 static int 237 ioat_attach(device_t device) 238 { 239 struct ioat_softc *ioat; 240 int error; 241 242 ioat = DEVICE2SOFTC(device); 243 ioat->device = device; 244 245 error = ioat_map_pci_bar(ioat); 246 if (error != 0) 247 goto err; 248 249 ioat->version = ioat_read_cbver(ioat); 250 if (ioat->version < IOAT_VER_3_0) { 251 error = ENODEV; 252 goto err; 253 } 254 255 error = ioat3_attach(device); 256 if (error != 0) 257 goto err; 258 259 error = pci_enable_busmaster(device); 260 if (error != 0) 261 goto err; 262 263 error = ioat_setup_intr(ioat); 264 if (error != 0) 265 goto err; 266 267 error = ioat_reset_hw(ioat); 268 if (error != 0) 269 goto err; 270 271 ioat_process_events(ioat); 272 ioat_setup_sysctl(device); 273 274 ioat->chan_idx = ioat_channel_index; 275 ioat_channel[ioat_channel_index++] = ioat; 276 ioat_test_attach(); 277 278 err: 279 if (error != 0) 280 ioat_detach(device); 281 return (error); 282 } 283 284 static int 285 ioat_detach(device_t device) 286 { 287 struct ioat_softc *ioat; 288 289 ioat = DEVICE2SOFTC(device); 290 291 ioat_test_detach(); 292 293 mtx_lock(IOAT_REFLK); 294 ioat->quiescing = TRUE; 295 ioat_channel[ioat->chan_idx] = NULL; 296 297 ioat_drain_locked(ioat); 298 mtx_unlock(IOAT_REFLK); 299 300 ioat_teardown_intr(ioat); 301 callout_drain(&ioat->timer); 302 303 pci_disable_busmaster(device); 304 305 if (ioat->pci_resource != NULL) 306 bus_release_resource(device, SYS_RES_MEMORY, 307 ioat->pci_resource_id, ioat->pci_resource); 308 309 if (ioat->ring != NULL) 310 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 311 312 if (ioat->comp_update != NULL) { 313 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 314 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 315 ioat->comp_update_map); 316 bus_dma_tag_destroy(ioat->comp_update_tag); 317 } 318 319 bus_dma_tag_destroy(ioat->hw_desc_tag); 320 321 return (0); 322 } 323 324 static int 325 ioat_teardown_intr(struct ioat_softc *ioat) 326 { 327 328 if (ioat->tag != NULL) 329 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 330 331 if (ioat->res != NULL) 332 bus_release_resource(ioat->device, SYS_RES_IRQ, 333 rman_get_rid(ioat->res), ioat->res); 334 335 pci_release_msi(ioat->device); 336 return (0); 337 } 338 339 static int 340 ioat_start_channel(struct ioat_softc *ioat) 341 { 342 uint64_t status; 343 uint32_t chanerr; 344 int i; 345 346 ioat_acquire(&ioat->dmaengine); 347 ioat_null(&ioat->dmaengine, NULL, NULL, 0); 348 ioat_release(&ioat->dmaengine); 349 350 for (i = 0; i < 100; i++) { 351 DELAY(1); 352 status = ioat_get_chansts(ioat); 353 if (is_ioat_idle(status)) 354 return (0); 355 } 356 357 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 358 ioat_log_message(0, "could not start channel: " 359 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 360 IOAT_CHANERR_STR); 361 return (ENXIO); 362 } 363 364 /* 365 * Initialize Hardware 366 */ 367 static int 368 ioat3_attach(device_t device) 369 { 370 struct ioat_softc *ioat; 371 struct ioat_descriptor **ring; 372 struct ioat_descriptor *next; 373 struct ioat_dma_hw_descriptor *dma_hw_desc; 374 int i, num_descriptors; 375 int error; 376 uint8_t xfercap; 377 378 error = 0; 379 ioat = DEVICE2SOFTC(device); 380 ioat->capabilities = ioat_read_dmacapability(ioat); 381 382 ioat_log_message(1, "Capabilities: %b\n", (int)ioat->capabilities, 383 IOAT_DMACAP_STR); 384 385 xfercap = ioat_read_xfercap(ioat); 386 ioat->max_xfer_size = 1 << xfercap; 387 388 /* TODO: need to check DCA here if we ever do XOR/PQ */ 389 390 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 391 mtx_init(&ioat->cleanup_lock, "ioat_process_events", NULL, MTX_DEF); 392 callout_init(&ioat->timer, 1); 393 394 ioat->is_resize_pending = FALSE; 395 ioat->is_completion_pending = FALSE; 396 ioat->is_reset_pending = FALSE; 397 ioat->is_channel_running = FALSE; 398 399 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 400 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 401 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 402 &ioat->comp_update_tag); 403 404 error = bus_dmamem_alloc(ioat->comp_update_tag, 405 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 406 if (ioat->comp_update == NULL) 407 return (ENOMEM); 408 409 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 410 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 411 0); 412 if (error != 0) 413 return (error); 414 415 ioat->ring_size_order = IOAT_MIN_ORDER; 416 417 num_descriptors = 1 << ioat->ring_size_order; 418 419 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 420 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 421 sizeof(struct ioat_dma_hw_descriptor), 1, 422 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 423 &ioat->hw_desc_tag); 424 425 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 426 M_ZERO | M_WAITOK); 427 if (ioat->ring == NULL) 428 return (ENOMEM); 429 430 ring = ioat->ring; 431 for (i = 0; i < num_descriptors; i++) { 432 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 433 if (ring[i] == NULL) 434 return (ENOMEM); 435 436 ring[i]->id = i; 437 } 438 439 for (i = 0; i < num_descriptors - 1; i++) { 440 next = ring[i + 1]; 441 dma_hw_desc = ring[i]->u.dma; 442 443 dma_hw_desc->next = next->hw_desc_bus_addr; 444 } 445 446 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 447 448 ioat->head = ioat->hw_head = 0; 449 ioat->tail = 0; 450 ioat->last_seen = 0; 451 return (0); 452 } 453 454 static int 455 ioat_map_pci_bar(struct ioat_softc *ioat) 456 { 457 458 ioat->pci_resource_id = PCIR_BAR(0); 459 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 460 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 461 462 if (ioat->pci_resource == NULL) { 463 ioat_log_message(0, "unable to allocate pci resource\n"); 464 return (ENODEV); 465 } 466 467 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 468 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 469 return (0); 470 } 471 472 static void 473 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 474 { 475 struct ioat_softc *ioat = arg; 476 477 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 478 ioat->comp_update_bus_addr = seg[0].ds_addr; 479 } 480 481 static void 482 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 483 { 484 bus_addr_t *baddr; 485 486 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 487 baddr = arg; 488 *baddr = segs->ds_addr; 489 } 490 491 /* 492 * Interrupt setup and handlers 493 */ 494 static int 495 ioat_setup_intr(struct ioat_softc *ioat) 496 { 497 uint32_t num_vectors; 498 int error; 499 boolean_t use_msix; 500 boolean_t force_legacy_interrupts; 501 502 use_msix = FALSE; 503 force_legacy_interrupts = FALSE; 504 505 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 506 num_vectors = 1; 507 pci_alloc_msix(ioat->device, &num_vectors); 508 if (num_vectors == 1) 509 use_msix = TRUE; 510 } 511 512 if (use_msix) { 513 ioat->rid = 1; 514 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 515 &ioat->rid, RF_ACTIVE); 516 } else { 517 ioat->rid = 0; 518 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 519 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 520 } 521 if (ioat->res == NULL) { 522 ioat_log_message(0, "bus_alloc_resource failed\n"); 523 return (ENOMEM); 524 } 525 526 ioat->tag = NULL; 527 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 528 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 529 if (error != 0) { 530 ioat_log_message(0, "bus_setup_intr failed\n"); 531 return (error); 532 } 533 534 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 535 return (0); 536 } 537 538 static boolean_t 539 ioat_model_resets_msix(struct ioat_softc *ioat) 540 { 541 u_int32_t pciid; 542 543 pciid = pci_get_devid(ioat->device); 544 switch (pciid) { 545 /* BWD: */ 546 case 0x0c508086: 547 case 0x0c518086: 548 case 0x0c528086: 549 case 0x0c538086: 550 /* BDXDE: */ 551 case 0x6f508086: 552 case 0x6f518086: 553 case 0x6f528086: 554 case 0x6f538086: 555 return (TRUE); 556 } 557 558 return (FALSE); 559 } 560 561 static void 562 ioat_interrupt_handler(void *arg) 563 { 564 struct ioat_softc *ioat = arg; 565 566 ioat_process_events(ioat); 567 } 568 569 static void 570 ioat_process_events(struct ioat_softc *ioat) 571 { 572 struct ioat_descriptor *desc; 573 struct bus_dmadesc *dmadesc; 574 uint64_t comp_update, status; 575 uint32_t completed; 576 577 mtx_lock(&ioat->cleanup_lock); 578 579 completed = 0; 580 comp_update = *ioat->comp_update; 581 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 582 583 CTR0(KTR_IOAT, __func__); 584 585 if (status == ioat->last_seen) 586 goto out; 587 588 while (1) { 589 desc = ioat_get_ring_entry(ioat, ioat->tail); 590 dmadesc = &desc->bus_dmadesc; 591 CTR1(KTR_IOAT, "completing desc %d", ioat->tail); 592 593 if (dmadesc->callback_fn) 594 (*dmadesc->callback_fn)(dmadesc->callback_arg); 595 596 completed++; 597 ioat->tail++; 598 if (desc->hw_desc_bus_addr == status) 599 break; 600 } 601 602 ioat->last_seen = desc->hw_desc_bus_addr; 603 604 if (ioat->head == ioat->tail) { 605 ioat->is_completion_pending = FALSE; 606 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 607 ioat_timer_callback, ioat); 608 } 609 610 out: 611 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 612 mtx_unlock(&ioat->cleanup_lock); 613 614 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 615 wakeup(&ioat->tail); 616 } 617 618 /* 619 * User API functions 620 */ 621 bus_dmaengine_t 622 ioat_get_dmaengine(uint32_t index) 623 { 624 struct ioat_softc *sc; 625 626 if (index >= ioat_channel_index) 627 return (NULL); 628 629 sc = ioat_channel[index]; 630 if (sc == NULL || sc->quiescing) 631 return (NULL); 632 633 return (&ioat_get(sc, IOAT_DMAENGINE_REF)->dmaengine); 634 } 635 636 void 637 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 638 { 639 struct ioat_softc *ioat; 640 641 ioat = to_ioat_softc(dmaengine); 642 ioat_put(ioat, IOAT_DMAENGINE_REF); 643 } 644 645 void 646 ioat_acquire(bus_dmaengine_t dmaengine) 647 { 648 struct ioat_softc *ioat; 649 650 ioat = to_ioat_softc(dmaengine); 651 mtx_lock(&ioat->submit_lock); 652 CTR0(KTR_IOAT, __func__); 653 } 654 655 void 656 ioat_release(bus_dmaengine_t dmaengine) 657 { 658 struct ioat_softc *ioat; 659 660 ioat = to_ioat_softc(dmaengine); 661 CTR0(KTR_IOAT, __func__); 662 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 663 mtx_unlock(&ioat->submit_lock); 664 } 665 666 static struct ioat_descriptor * 667 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 668 uint32_t size, uint64_t src, uint64_t dst, 669 bus_dmaengine_callback_t callback_fn, void *callback_arg, 670 uint32_t flags) 671 { 672 struct ioat_generic_hw_descriptor *hw_desc; 673 struct ioat_descriptor *desc; 674 int mflags; 675 676 mtx_assert(&ioat->submit_lock, MA_OWNED); 677 678 KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x", 679 flags & ~DMA_ALL_FLAGS)); 680 if ((flags & DMA_NO_WAIT) != 0) 681 mflags = M_NOWAIT; 682 else 683 mflags = M_WAITOK; 684 685 if (size > ioat->max_xfer_size) { 686 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 687 __func__, ioat->max_xfer_size, (unsigned)size); 688 return (NULL); 689 } 690 691 if (ioat_reserve_space(ioat, 1, mflags) != 0) 692 return (NULL); 693 694 desc = ioat_get_ring_entry(ioat, ioat->head); 695 hw_desc = desc->u.generic; 696 697 hw_desc->u.control_raw = 0; 698 hw_desc->u.control_generic.op = op; 699 hw_desc->u.control_generic.completion_update = 1; 700 701 if ((flags & DMA_INT_EN) != 0) 702 hw_desc->u.control_generic.int_enable = 1; 703 704 hw_desc->size = size; 705 hw_desc->src_addr = src; 706 hw_desc->dest_addr = dst; 707 708 desc->bus_dmadesc.callback_fn = callback_fn; 709 desc->bus_dmadesc.callback_arg = callback_arg; 710 return (desc); 711 } 712 713 struct bus_dmadesc * 714 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 715 void *callback_arg, uint32_t flags) 716 { 717 struct ioat_dma_hw_descriptor *hw_desc; 718 struct ioat_descriptor *desc; 719 struct ioat_softc *ioat; 720 721 CTR0(KTR_IOAT, __func__); 722 ioat = to_ioat_softc(dmaengine); 723 724 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 725 callback_arg, flags); 726 if (desc == NULL) 727 return (NULL); 728 729 hw_desc = desc->u.dma; 730 hw_desc->u.control.null = 1; 731 ioat_submit_single(ioat); 732 return (&desc->bus_dmadesc); 733 } 734 735 struct bus_dmadesc * 736 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 737 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 738 void *callback_arg, uint32_t flags) 739 { 740 struct ioat_dma_hw_descriptor *hw_desc; 741 struct ioat_descriptor *desc; 742 struct ioat_softc *ioat; 743 744 CTR0(KTR_IOAT, __func__); 745 ioat = to_ioat_softc(dmaengine); 746 747 if (((src | dst) & (0xffffull << 48)) != 0) { 748 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 749 __func__); 750 return (NULL); 751 } 752 753 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 754 callback_arg, flags); 755 if (desc == NULL) 756 return (NULL); 757 758 hw_desc = desc->u.dma; 759 if (g_ioat_debug_level >= 3) 760 dump_descriptor(hw_desc); 761 762 ioat_submit_single(ioat); 763 return (&desc->bus_dmadesc); 764 } 765 766 struct bus_dmadesc * 767 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 768 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 769 uint32_t flags) 770 { 771 struct ioat_fill_hw_descriptor *hw_desc; 772 struct ioat_descriptor *desc; 773 struct ioat_softc *ioat; 774 775 CTR0(KTR_IOAT, __func__); 776 ioat = to_ioat_softc(dmaengine); 777 778 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 779 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 780 __func__); 781 return (NULL); 782 } 783 784 if ((dst & (0xffffull << 48)) != 0) { 785 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 786 __func__); 787 return (NULL); 788 } 789 790 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 791 callback_fn, callback_arg, flags); 792 if (desc == NULL) 793 return (NULL); 794 795 hw_desc = desc->u.fill; 796 if (g_ioat_debug_level >= 3) 797 dump_descriptor(hw_desc); 798 799 ioat_submit_single(ioat); 800 return (&desc->bus_dmadesc); 801 } 802 803 /* 804 * Ring Management 805 */ 806 static inline uint32_t 807 ioat_get_active(struct ioat_softc *ioat) 808 { 809 810 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 811 } 812 813 static inline uint32_t 814 ioat_get_ring_space(struct ioat_softc *ioat) 815 { 816 817 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 818 } 819 820 static struct ioat_descriptor * 821 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 822 { 823 struct ioat_generic_hw_descriptor *hw_desc; 824 struct ioat_descriptor *desc; 825 int error, busdmaflag; 826 827 error = ENOMEM; 828 hw_desc = NULL; 829 830 if ((mflags & M_WAITOK) != 0) 831 busdmaflag = BUS_DMA_WAITOK; 832 else 833 busdmaflag = BUS_DMA_NOWAIT; 834 835 desc = malloc(sizeof(*desc), M_IOAT, mflags); 836 if (desc == NULL) 837 goto out; 838 839 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 840 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 841 if (hw_desc == NULL) 842 goto out; 843 844 desc->u.generic = hw_desc; 845 846 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 847 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 848 busdmaflag); 849 if (error) 850 goto out; 851 852 out: 853 if (error) { 854 ioat_free_ring_entry(ioat, desc); 855 return (NULL); 856 } 857 return (desc); 858 } 859 860 static void 861 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 862 { 863 864 if (desc == NULL) 865 return; 866 867 if (desc->u.generic) 868 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 869 ioat->hw_desc_map); 870 free(desc, M_IOAT); 871 } 872 873 /* 874 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 875 * for 'num_descs'. 876 * 877 * If mflags contains M_WAITOK, blocks until enough space is available. 878 * 879 * Returns zero on success, or an errno on error. If num_descs is beyond the 880 * maximum ring size, returns EINVAl; if allocation would block and mflags 881 * contains M_NOWAIT, returns EAGAIN. 882 * 883 * Must be called with the submit_lock held; returns with the lock held. The 884 * lock may be dropped to allocate the ring. 885 * 886 * (The submit_lock is needed to add any entries to the ring, so callers are 887 * assured enough room is available.) 888 */ 889 static int 890 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 891 { 892 struct ioat_descriptor **new_ring; 893 uint32_t order; 894 int error; 895 896 mtx_assert(&ioat->submit_lock, MA_OWNED); 897 error = 0; 898 899 if (num_descs < 1 || num_descs > (1 << IOAT_MAX_ORDER)) { 900 error = EINVAL; 901 goto out; 902 } 903 if (ioat->quiescing) { 904 error = ENXIO; 905 goto out; 906 } 907 908 for (;;) { 909 if (ioat_get_ring_space(ioat) >= num_descs) 910 goto out; 911 912 order = ioat->ring_size_order; 913 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 914 if ((mflags & M_WAITOK) != 0) { 915 msleep(&ioat->tail, &ioat->submit_lock, 0, 916 "ioat_rsz", 0); 917 continue; 918 } 919 920 error = EAGAIN; 921 break; 922 } 923 924 ioat->is_resize_pending = TRUE; 925 for (;;) { 926 mtx_unlock(&ioat->submit_lock); 927 928 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 929 TRUE, mflags); 930 931 mtx_lock(&ioat->submit_lock); 932 KASSERT(ioat->ring_size_order == order, 933 ("is_resize_pending should protect order")); 934 935 if (new_ring == NULL) { 936 KASSERT((mflags & M_WAITOK) == 0, 937 ("allocation failed")); 938 error = EAGAIN; 939 break; 940 } 941 942 error = ring_grow(ioat, order, new_ring); 943 if (error == 0) 944 break; 945 } 946 ioat->is_resize_pending = FALSE; 947 wakeup(&ioat->tail); 948 if (error) 949 break; 950 } 951 952 out: 953 mtx_assert(&ioat->submit_lock, MA_OWNED); 954 return (error); 955 } 956 957 static struct ioat_descriptor ** 958 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 959 int mflags) 960 { 961 struct ioat_descriptor **ring; 962 uint32_t i; 963 int error; 964 965 KASSERT(size > 0 && powerof2(size), ("bogus size")); 966 967 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 968 if (ring == NULL) 969 return (NULL); 970 971 if (need_dscr) { 972 error = ENOMEM; 973 for (i = size / 2; i < size; i++) { 974 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 975 if (ring[i] == NULL) 976 goto out; 977 ring[i]->id = i; 978 } 979 } 980 error = 0; 981 982 out: 983 if (error != 0 && ring != NULL) { 984 ioat_free_ring(ioat, size, ring); 985 ring = NULL; 986 } 987 return (ring); 988 } 989 990 static void 991 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 992 struct ioat_descriptor **ring) 993 { 994 uint32_t i; 995 996 for (i = 0; i < size; i++) { 997 if (ring[i] != NULL) 998 ioat_free_ring_entry(ioat, ring[i]); 999 } 1000 free(ring, M_IOAT); 1001 } 1002 1003 static struct ioat_descriptor * 1004 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1005 { 1006 1007 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1008 } 1009 1010 static int 1011 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1012 struct ioat_descriptor **newring) 1013 { 1014 struct ioat_descriptor *tmp, *next; 1015 struct ioat_dma_hw_descriptor *hw; 1016 uint32_t oldsize, newsize, head, tail, i, end; 1017 int error; 1018 1019 CTR0(KTR_IOAT, __func__); 1020 1021 mtx_assert(&ioat->submit_lock, MA_OWNED); 1022 1023 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1024 error = EINVAL; 1025 goto out; 1026 } 1027 1028 oldsize = (1 << oldorder); 1029 newsize = (1 << (oldorder + 1)); 1030 1031 mtx_lock(&ioat->cleanup_lock); 1032 1033 head = ioat->head & (oldsize - 1); 1034 tail = ioat->tail & (oldsize - 1); 1035 1036 /* Copy old descriptors to new ring */ 1037 for (i = 0; i < oldsize; i++) 1038 newring[i] = ioat->ring[i]; 1039 1040 /* 1041 * If head has wrapped but tail hasn't, we must swap some descriptors 1042 * around so that tail can increment directly to head. 1043 */ 1044 if (head < tail) { 1045 for (i = 0; i <= head; i++) { 1046 tmp = newring[oldsize + i]; 1047 1048 newring[oldsize + i] = newring[i]; 1049 newring[oldsize + i]->id = oldsize + i; 1050 1051 newring[i] = tmp; 1052 newring[i]->id = i; 1053 } 1054 head += oldsize; 1055 } 1056 1057 KASSERT(head >= tail, ("invariants")); 1058 1059 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1060 if (head < oldsize) { 1061 i = oldsize - 1; 1062 end = newsize; 1063 } else { 1064 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1065 i = head; 1066 end = newsize + (head - oldsize) + 1; 1067 } 1068 1069 /* 1070 * Fix up hardware ring, being careful not to trample the active 1071 * section (tail -> head). 1072 */ 1073 for (; i < end; i++) { 1074 KASSERT((i & (newsize - 1)) < tail || 1075 (i & (newsize - 1)) >= head, ("trampling snake")); 1076 1077 next = newring[(i + 1) & (newsize - 1)]; 1078 hw = newring[i & (newsize - 1)]->u.dma; 1079 hw->next = next->hw_desc_bus_addr; 1080 } 1081 1082 free(ioat->ring, M_IOAT); 1083 ioat->ring = newring; 1084 ioat->ring_size_order = oldorder + 1; 1085 ioat->tail = tail; 1086 ioat->head = head; 1087 error = 0; 1088 1089 mtx_unlock(&ioat->cleanup_lock); 1090 out: 1091 if (error) 1092 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1093 return (error); 1094 } 1095 1096 static int 1097 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1098 struct ioat_descriptor **newring) 1099 { 1100 struct ioat_dma_hw_descriptor *hw; 1101 struct ioat_descriptor *ent, *next; 1102 uint32_t oldsize, newsize, current_idx, new_idx, i; 1103 int error; 1104 1105 CTR0(KTR_IOAT, __func__); 1106 1107 mtx_assert(&ioat->submit_lock, MA_OWNED); 1108 1109 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1110 error = EINVAL; 1111 goto out_unlocked; 1112 } 1113 1114 oldsize = (1 << oldorder); 1115 newsize = (1 << (oldorder - 1)); 1116 1117 mtx_lock(&ioat->cleanup_lock); 1118 1119 /* Can't shrink below current active set! */ 1120 if (ioat_get_active(ioat) >= newsize) { 1121 error = ENOMEM; 1122 goto out; 1123 } 1124 1125 /* 1126 * Copy current descriptors to the new ring, dropping the removed 1127 * descriptors. 1128 */ 1129 for (i = 0; i < newsize; i++) { 1130 current_idx = (ioat->tail + i) & (oldsize - 1); 1131 new_idx = (ioat->tail + i) & (newsize - 1); 1132 1133 newring[new_idx] = ioat->ring[current_idx]; 1134 newring[new_idx]->id = new_idx; 1135 } 1136 1137 /* Free deleted descriptors */ 1138 for (i = newsize; i < oldsize; i++) { 1139 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1140 ioat_free_ring_entry(ioat, ent); 1141 } 1142 1143 /* Fix up hardware ring. */ 1144 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1145 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1146 hw->next = next->hw_desc_bus_addr; 1147 1148 free(ioat->ring, M_IOAT); 1149 ioat->ring = newring; 1150 ioat->ring_size_order = oldorder - 1; 1151 error = 0; 1152 1153 out: 1154 mtx_unlock(&ioat->cleanup_lock); 1155 out_unlocked: 1156 if (error) 1157 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1158 return (error); 1159 } 1160 1161 static void 1162 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1163 { 1164 struct ioat_descriptor *desc; 1165 1166 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1167 IOAT_CHANERR_STR); 1168 if (chanerr == 0) 1169 return; 1170 1171 mtx_lock(&ioat->submit_lock); 1172 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1173 dump_descriptor(desc->u.raw); 1174 1175 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1176 dump_descriptor(desc->u.raw); 1177 mtx_unlock(&ioat->submit_lock); 1178 } 1179 1180 static void 1181 ioat_timer_callback(void *arg) 1182 { 1183 struct ioat_descriptor **newring; 1184 struct ioat_softc *ioat; 1185 uint64_t status; 1186 uint32_t chanerr, order; 1187 1188 ioat = arg; 1189 ioat_log_message(1, "%s\n", __func__); 1190 1191 if (ioat->is_completion_pending) { 1192 status = ioat_get_chansts(ioat); 1193 1194 /* 1195 * When halted due to errors, check for channel programming 1196 * errors before advancing the completion state. 1197 */ 1198 if (is_ioat_halted(status)) { 1199 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1200 ioat_halted_debug(ioat, chanerr); 1201 } 1202 ioat_process_events(ioat); 1203 } else { 1204 mtx_lock(&ioat->submit_lock); 1205 order = ioat->ring_size_order; 1206 if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) { 1207 mtx_unlock(&ioat->submit_lock); 1208 goto out; 1209 } 1210 ioat->is_resize_pending = TRUE; 1211 mtx_unlock(&ioat->submit_lock); 1212 1213 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1214 M_NOWAIT); 1215 1216 mtx_lock(&ioat->submit_lock); 1217 KASSERT(ioat->ring_size_order == order, 1218 ("resize_pending protects order")); 1219 1220 if (newring != NULL) 1221 ring_shrink(ioat, order, newring); 1222 1223 ioat->is_resize_pending = FALSE; 1224 mtx_unlock(&ioat->submit_lock); 1225 1226 out: 1227 /* Slowly scale the ring down if idle. */ 1228 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1229 callout_reset(&ioat->timer, 10 * hz, 1230 ioat_timer_callback, ioat); 1231 } 1232 } 1233 1234 /* 1235 * Support Functions 1236 */ 1237 static void 1238 ioat_submit_single(struct ioat_softc *ioat) 1239 { 1240 1241 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1242 atomic_add_rel_int(&ioat->head, 1); 1243 atomic_add_rel_int(&ioat->hw_head, 1); 1244 1245 if (!ioat->is_completion_pending) { 1246 ioat->is_completion_pending = TRUE; 1247 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 1248 ioat_timer_callback, ioat); 1249 } 1250 } 1251 1252 static int 1253 ioat_reset_hw(struct ioat_softc *ioat) 1254 { 1255 uint64_t status; 1256 uint32_t chanerr; 1257 unsigned timeout; 1258 int error; 1259 1260 mtx_lock(IOAT_REFLK); 1261 ioat->quiescing = TRUE; 1262 ioat_drain_locked(ioat); 1263 mtx_unlock(IOAT_REFLK); 1264 1265 status = ioat_get_chansts(ioat); 1266 if (is_ioat_active(status) || is_ioat_idle(status)) 1267 ioat_suspend(ioat); 1268 1269 /* Wait at most 20 ms */ 1270 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1271 timeout < 20; timeout++) { 1272 DELAY(1000); 1273 status = ioat_get_chansts(ioat); 1274 } 1275 if (timeout == 20) { 1276 error = ETIMEDOUT; 1277 goto out; 1278 } 1279 1280 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1281 1282 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1283 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1284 1285 /* 1286 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1287 * that can cause stability issues for IOAT v3. 1288 */ 1289 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1290 4); 1291 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1292 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1293 1294 /* 1295 * BDXDE and BWD models reset MSI-X registers on device reset. 1296 * Save/restore their contents manually. 1297 */ 1298 if (ioat_model_resets_msix(ioat)) { 1299 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1300 pci_save_state(ioat->device); 1301 } 1302 1303 ioat_reset(ioat); 1304 1305 /* Wait at most 20 ms */ 1306 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1307 DELAY(1000); 1308 if (timeout == 20) { 1309 error = ETIMEDOUT; 1310 goto out; 1311 } 1312 1313 if (ioat_model_resets_msix(ioat)) { 1314 ioat_log_message(1, "device resets registers; restored\n"); 1315 pci_restore_state(ioat->device); 1316 } 1317 1318 /* Reset attempts to return the hardware to "halted." */ 1319 status = ioat_get_chansts(ioat); 1320 if (is_ioat_active(status) || is_ioat_idle(status)) { 1321 /* So this really shouldn't happen... */ 1322 ioat_log_message(0, "Device is active after a reset?\n"); 1323 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1324 error = 0; 1325 goto out; 1326 } 1327 1328 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1329 ioat_halted_debug(ioat, chanerr); 1330 if (chanerr != 0) { 1331 error = EIO; 1332 goto out; 1333 } 1334 1335 /* 1336 * Bring device back online after reset. Writing CHAINADDR brings the 1337 * device back to active. 1338 * 1339 * The internal ring counter resets to zero, so we have to start over 1340 * at zero as well. 1341 */ 1342 ioat->tail = ioat->head = ioat->hw_head = 0; 1343 ioat->last_seen = 0; 1344 1345 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1346 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1347 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1348 error = 0; 1349 1350 out: 1351 mtx_lock(IOAT_REFLK); 1352 ioat->quiescing = FALSE; 1353 mtx_unlock(IOAT_REFLK); 1354 1355 if (error == 0) 1356 error = ioat_start_channel(ioat); 1357 1358 return (error); 1359 } 1360 1361 static int 1362 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1363 { 1364 struct ioat_softc *ioat; 1365 int error, arg; 1366 1367 ioat = arg1; 1368 1369 arg = 0; 1370 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1371 if (error != 0 || req->newptr == NULL) 1372 return (error); 1373 1374 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1375 if (error != 0) 1376 return (error); 1377 1378 if (arg != 0) 1379 error = ioat_reset_hw(ioat); 1380 1381 return (error); 1382 } 1383 1384 static void 1385 dump_descriptor(void *hw_desc) 1386 { 1387 int i, j; 1388 1389 for (i = 0; i < 2; i++) { 1390 for (j = 0; j < 8; j++) 1391 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1392 printf("\n"); 1393 } 1394 } 1395 1396 static void 1397 ioat_setup_sysctl(device_t device) 1398 { 1399 struct sysctl_oid_list *par; 1400 struct sysctl_ctx_list *ctx; 1401 struct sysctl_oid *tree; 1402 struct ioat_softc *ioat; 1403 1404 ioat = DEVICE2SOFTC(device); 1405 ctx = device_get_sysctl_ctx(device); 1406 tree = device_get_sysctl_tree(device); 1407 par = SYSCTL_CHILDREN(tree); 1408 1409 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1410 &ioat->version, 0, "HW version (0xMM form)"); 1411 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1412 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1413 1414 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1415 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1416 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 0, 1417 "SW descriptor head pointer index"); 1418 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 0, 1419 "SW descriptor tail pointer index"); 1420 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "hw_head", CTLFLAG_RD, 1421 &ioat->hw_head, 0, "HW DMACOUNT"); 1422 1423 SYSCTL_ADD_UQUAD(ctx, par, OID_AUTO, "last_completion", CTLFLAG_RD, 1424 ioat->comp_update, "HW addr of last completion"); 1425 1426 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 1427 &ioat->is_resize_pending, 0, "resize pending"); 1428 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_completion_pending", CTLFLAG_RD, 1429 &ioat->is_completion_pending, 0, "completion pending"); 1430 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1431 &ioat->is_reset_pending, 0, "reset pending"); 1432 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1433 &ioat->is_channel_running, 0, "channel running"); 1434 1435 SYSCTL_ADD_PROC(ctx, par, OID_AUTO, "force_hw_reset", 1436 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1437 "Set to non-zero to reset the hardware"); 1438 } 1439 1440 static inline struct ioat_softc * 1441 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1442 { 1443 uint32_t old; 1444 1445 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1446 1447 old = atomic_fetchadd_32(&ioat->refcnt, 1); 1448 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 1449 1450 #ifdef INVARIANTS 1451 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 1452 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 1453 #endif 1454 1455 return (ioat); 1456 } 1457 1458 static inline void 1459 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1460 { 1461 uint32_t old; 1462 1463 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1464 1465 if (n == 0) 1466 return; 1467 1468 #ifdef INVARIANTS 1469 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 1470 KASSERT(old >= n, ("refcnt kind underflow")); 1471 #endif 1472 1473 /* Skip acquiring the lock if resulting refcnt > 0. */ 1474 for (;;) { 1475 old = ioat->refcnt; 1476 if (old <= n) 1477 break; 1478 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 1479 return; 1480 } 1481 1482 mtx_lock(IOAT_REFLK); 1483 old = atomic_fetchadd_32(&ioat->refcnt, -n); 1484 KASSERT(old >= n, ("refcnt error")); 1485 1486 if (old == n) 1487 wakeup(IOAT_REFLK); 1488 mtx_unlock(IOAT_REFLK); 1489 } 1490 1491 static inline void 1492 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1493 { 1494 1495 ioat_putn(ioat, 1, kind); 1496 } 1497 1498 static void 1499 ioat_drain_locked(struct ioat_softc *ioat) 1500 { 1501 1502 mtx_assert(IOAT_REFLK, MA_OWNED); 1503 while (ioat->refcnt > 0) 1504 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 1505 } 1506