1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/ioccom.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/sbuf.h> 42 #include <sys/sysctl.h> 43 #include <sys/taskqueue.h> 44 #include <sys/time.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <machine/bus.h> 48 #include <machine/resource.h> 49 #include <machine/stdarg.h> 50 51 #include "ioat.h" 52 #include "ioat_hw.h" 53 #include "ioat_internal.h" 54 55 #ifndef BUS_SPACE_MAXADDR_40BIT 56 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 57 #endif 58 #define IOAT_INTR_TIMO (hz / 10) 59 #define IOAT_REFLK (&ioat->submit_lock) 60 61 static int ioat_probe(device_t device); 62 static int ioat_attach(device_t device); 63 static int ioat_detach(device_t device); 64 static int ioat_setup_intr(struct ioat_softc *ioat); 65 static int ioat_teardown_intr(struct ioat_softc *ioat); 66 static int ioat3_attach(device_t device); 67 static int ioat_start_channel(struct ioat_softc *ioat); 68 static int ioat_map_pci_bar(struct ioat_softc *ioat); 69 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 70 int error); 71 static void ioat_interrupt_handler(void *arg); 72 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 73 static int chanerr_to_errno(uint32_t); 74 static void ioat_process_events(struct ioat_softc *ioat); 75 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 76 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 77 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 78 struct ioat_descriptor **); 79 static void ioat_free_ring_entry(struct ioat_softc *ioat, 80 struct ioat_descriptor *desc); 81 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 82 int mflags); 83 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 84 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 85 uint32_t index); 86 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 87 uint32_t size, boolean_t need_dscr, int mflags); 88 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 89 struct ioat_descriptor **); 90 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 91 struct ioat_descriptor **); 92 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 93 static void ioat_timer_callback(void *arg); 94 static void dump_descriptor(void *hw_desc); 95 static void ioat_submit_single(struct ioat_softc *ioat); 96 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 97 int error); 98 static int ioat_reset_hw(struct ioat_softc *ioat); 99 static void ioat_reset_hw_task(void *, int); 100 static void ioat_setup_sysctl(device_t device); 101 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 102 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 103 enum ioat_ref_kind); 104 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 105 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 106 enum ioat_ref_kind, boolean_t); 107 static inline void ioat_putn(struct ioat_softc *, uint32_t, 108 enum ioat_ref_kind); 109 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 110 enum ioat_ref_kind); 111 static void ioat_drain_locked(struct ioat_softc *); 112 113 #define ioat_log_message(v, ...) do { \ 114 if ((v) <= g_ioat_debug_level) { \ 115 device_printf(ioat->device, __VA_ARGS__); \ 116 } \ 117 } while (0) 118 119 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 120 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 121 122 static int g_force_legacy_interrupts; 123 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 124 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 125 126 int g_ioat_debug_level = 0; 127 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 128 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 129 130 /* 131 * OS <-> Driver interface structures 132 */ 133 static device_method_t ioat_pci_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, ioat_probe), 136 DEVMETHOD(device_attach, ioat_attach), 137 DEVMETHOD(device_detach, ioat_detach), 138 DEVMETHOD_END 139 }; 140 141 static driver_t ioat_pci_driver = { 142 "ioat", 143 ioat_pci_methods, 144 sizeof(struct ioat_softc), 145 }; 146 147 static devclass_t ioat_devclass; 148 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 149 MODULE_VERSION(ioat, 1); 150 151 /* 152 * Private data structures 153 */ 154 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 155 static int ioat_channel_index = 0; 156 SYSCTL_INT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 157 "Number of IOAT channels attached"); 158 159 static struct _pcsid 160 { 161 u_int32_t type; 162 const char *desc; 163 } pci_ids[] = { 164 { 0x34308086, "TBG IOAT Ch0" }, 165 { 0x34318086, "TBG IOAT Ch1" }, 166 { 0x34328086, "TBG IOAT Ch2" }, 167 { 0x34338086, "TBG IOAT Ch3" }, 168 { 0x34298086, "TBG IOAT Ch4" }, 169 { 0x342a8086, "TBG IOAT Ch5" }, 170 { 0x342b8086, "TBG IOAT Ch6" }, 171 { 0x342c8086, "TBG IOAT Ch7" }, 172 173 { 0x37108086, "JSF IOAT Ch0" }, 174 { 0x37118086, "JSF IOAT Ch1" }, 175 { 0x37128086, "JSF IOAT Ch2" }, 176 { 0x37138086, "JSF IOAT Ch3" }, 177 { 0x37148086, "JSF IOAT Ch4" }, 178 { 0x37158086, "JSF IOAT Ch5" }, 179 { 0x37168086, "JSF IOAT Ch6" }, 180 { 0x37178086, "JSF IOAT Ch7" }, 181 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 182 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 183 184 { 0x3c208086, "SNB IOAT Ch0" }, 185 { 0x3c218086, "SNB IOAT Ch1" }, 186 { 0x3c228086, "SNB IOAT Ch2" }, 187 { 0x3c238086, "SNB IOAT Ch3" }, 188 { 0x3c248086, "SNB IOAT Ch4" }, 189 { 0x3c258086, "SNB IOAT Ch5" }, 190 { 0x3c268086, "SNB IOAT Ch6" }, 191 { 0x3c278086, "SNB IOAT Ch7" }, 192 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 193 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 194 195 { 0x0e208086, "IVB IOAT Ch0" }, 196 { 0x0e218086, "IVB IOAT Ch1" }, 197 { 0x0e228086, "IVB IOAT Ch2" }, 198 { 0x0e238086, "IVB IOAT Ch3" }, 199 { 0x0e248086, "IVB IOAT Ch4" }, 200 { 0x0e258086, "IVB IOAT Ch5" }, 201 { 0x0e268086, "IVB IOAT Ch6" }, 202 { 0x0e278086, "IVB IOAT Ch7" }, 203 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 204 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 205 206 { 0x2f208086, "HSW IOAT Ch0" }, 207 { 0x2f218086, "HSW IOAT Ch1" }, 208 { 0x2f228086, "HSW IOAT Ch2" }, 209 { 0x2f238086, "HSW IOAT Ch3" }, 210 { 0x2f248086, "HSW IOAT Ch4" }, 211 { 0x2f258086, "HSW IOAT Ch5" }, 212 { 0x2f268086, "HSW IOAT Ch6" }, 213 { 0x2f278086, "HSW IOAT Ch7" }, 214 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 215 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 216 217 { 0x0c508086, "BWD IOAT Ch0" }, 218 { 0x0c518086, "BWD IOAT Ch1" }, 219 { 0x0c528086, "BWD IOAT Ch2" }, 220 { 0x0c538086, "BWD IOAT Ch3" }, 221 222 { 0x6f508086, "BDXDE IOAT Ch0" }, 223 { 0x6f518086, "BDXDE IOAT Ch1" }, 224 { 0x6f528086, "BDXDE IOAT Ch2" }, 225 { 0x6f538086, "BDXDE IOAT Ch3" }, 226 227 { 0x6f208086, "BDX IOAT Ch0" }, 228 { 0x6f218086, "BDX IOAT Ch1" }, 229 { 0x6f228086, "BDX IOAT Ch2" }, 230 { 0x6f238086, "BDX IOAT Ch3" }, 231 { 0x6f248086, "BDX IOAT Ch4" }, 232 { 0x6f258086, "BDX IOAT Ch5" }, 233 { 0x6f268086, "BDX IOAT Ch6" }, 234 { 0x6f278086, "BDX IOAT Ch7" }, 235 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 236 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 237 238 { 0x00000000, NULL } 239 }; 240 241 /* 242 * OS <-> Driver linkage functions 243 */ 244 static int 245 ioat_probe(device_t device) 246 { 247 struct _pcsid *ep; 248 u_int32_t type; 249 250 type = pci_get_devid(device); 251 for (ep = pci_ids; ep->type; ep++) { 252 if (ep->type == type) { 253 device_set_desc(device, ep->desc); 254 return (0); 255 } 256 } 257 return (ENXIO); 258 } 259 260 static int 261 ioat_attach(device_t device) 262 { 263 struct ioat_softc *ioat; 264 int error; 265 266 ioat = DEVICE2SOFTC(device); 267 ioat->device = device; 268 269 error = ioat_map_pci_bar(ioat); 270 if (error != 0) 271 goto err; 272 273 ioat->version = ioat_read_cbver(ioat); 274 if (ioat->version < IOAT_VER_3_0) { 275 error = ENODEV; 276 goto err; 277 } 278 279 error = ioat3_attach(device); 280 if (error != 0) 281 goto err; 282 283 error = pci_enable_busmaster(device); 284 if (error != 0) 285 goto err; 286 287 error = ioat_setup_intr(ioat); 288 if (error != 0) 289 goto err; 290 291 error = ioat_reset_hw(ioat); 292 if (error != 0) 293 goto err; 294 295 ioat_process_events(ioat); 296 ioat_setup_sysctl(device); 297 298 ioat->chan_idx = ioat_channel_index; 299 ioat_channel[ioat_channel_index++] = ioat; 300 ioat_test_attach(); 301 302 err: 303 if (error != 0) 304 ioat_detach(device); 305 return (error); 306 } 307 308 static int 309 ioat_detach(device_t device) 310 { 311 struct ioat_softc *ioat; 312 313 ioat = DEVICE2SOFTC(device); 314 315 ioat_test_detach(); 316 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 317 318 mtx_lock(IOAT_REFLK); 319 ioat->quiescing = TRUE; 320 ioat->destroying = TRUE; 321 wakeup(&ioat->quiescing); 322 323 ioat_channel[ioat->chan_idx] = NULL; 324 325 ioat_drain_locked(ioat); 326 mtx_unlock(IOAT_REFLK); 327 328 ioat_teardown_intr(ioat); 329 callout_drain(&ioat->timer); 330 331 pci_disable_busmaster(device); 332 333 if (ioat->pci_resource != NULL) 334 bus_release_resource(device, SYS_RES_MEMORY, 335 ioat->pci_resource_id, ioat->pci_resource); 336 337 if (ioat->ring != NULL) 338 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 339 340 if (ioat->comp_update != NULL) { 341 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 342 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 343 ioat->comp_update_map); 344 bus_dma_tag_destroy(ioat->comp_update_tag); 345 } 346 347 bus_dma_tag_destroy(ioat->hw_desc_tag); 348 349 return (0); 350 } 351 352 static int 353 ioat_teardown_intr(struct ioat_softc *ioat) 354 { 355 356 if (ioat->tag != NULL) 357 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 358 359 if (ioat->res != NULL) 360 bus_release_resource(ioat->device, SYS_RES_IRQ, 361 rman_get_rid(ioat->res), ioat->res); 362 363 pci_release_msi(ioat->device); 364 return (0); 365 } 366 367 static int 368 ioat_start_channel(struct ioat_softc *ioat) 369 { 370 uint64_t status; 371 uint32_t chanerr; 372 int i; 373 374 ioat_acquire(&ioat->dmaengine); 375 ioat_null(&ioat->dmaengine, NULL, NULL, 0); 376 ioat_release(&ioat->dmaengine); 377 378 for (i = 0; i < 100; i++) { 379 DELAY(1); 380 status = ioat_get_chansts(ioat); 381 if (is_ioat_idle(status)) 382 return (0); 383 } 384 385 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 386 ioat_log_message(0, "could not start channel: " 387 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 388 IOAT_CHANERR_STR); 389 return (ENXIO); 390 } 391 392 /* 393 * Initialize Hardware 394 */ 395 static int 396 ioat3_attach(device_t device) 397 { 398 struct ioat_softc *ioat; 399 struct ioat_descriptor **ring; 400 struct ioat_descriptor *next; 401 struct ioat_dma_hw_descriptor *dma_hw_desc; 402 int i, num_descriptors; 403 int error; 404 uint8_t xfercap; 405 406 error = 0; 407 ioat = DEVICE2SOFTC(device); 408 ioat->capabilities = ioat_read_dmacapability(ioat); 409 410 ioat_log_message(1, "Capabilities: %b\n", (int)ioat->capabilities, 411 IOAT_DMACAP_STR); 412 413 xfercap = ioat_read_xfercap(ioat); 414 ioat->max_xfer_size = 1 << xfercap; 415 416 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 417 IOAT_INTRDELAY_SUPPORTED) != 0; 418 if (ioat->intrdelay_supported) 419 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 420 421 /* TODO: need to check DCA here if we ever do XOR/PQ */ 422 423 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 424 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 425 callout_init(&ioat->timer, 1); 426 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 427 428 /* Establish lock order for Witness */ 429 mtx_lock(&ioat->submit_lock); 430 mtx_lock(&ioat->cleanup_lock); 431 mtx_unlock(&ioat->cleanup_lock); 432 mtx_unlock(&ioat->submit_lock); 433 434 ioat->is_resize_pending = FALSE; 435 ioat->is_completion_pending = FALSE; 436 ioat->is_reset_pending = FALSE; 437 ioat->is_channel_running = FALSE; 438 439 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 440 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 441 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 442 &ioat->comp_update_tag); 443 444 error = bus_dmamem_alloc(ioat->comp_update_tag, 445 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 446 if (ioat->comp_update == NULL) 447 return (ENOMEM); 448 449 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 450 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 451 0); 452 if (error != 0) 453 return (error); 454 455 ioat->ring_size_order = IOAT_MIN_ORDER; 456 457 num_descriptors = 1 << ioat->ring_size_order; 458 459 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 460 BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL, 461 sizeof(struct ioat_dma_hw_descriptor), 1, 462 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 463 &ioat->hw_desc_tag); 464 465 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 466 M_ZERO | M_WAITOK); 467 if (ioat->ring == NULL) 468 return (ENOMEM); 469 470 ring = ioat->ring; 471 for (i = 0; i < num_descriptors; i++) { 472 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 473 if (ring[i] == NULL) 474 return (ENOMEM); 475 476 ring[i]->id = i; 477 } 478 479 for (i = 0; i < num_descriptors - 1; i++) { 480 next = ring[i + 1]; 481 dma_hw_desc = ring[i]->u.dma; 482 483 dma_hw_desc->next = next->hw_desc_bus_addr; 484 } 485 486 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 487 488 ioat->head = ioat->hw_head = 0; 489 ioat->tail = 0; 490 ioat->last_seen = 0; 491 return (0); 492 } 493 494 static int 495 ioat_map_pci_bar(struct ioat_softc *ioat) 496 { 497 498 ioat->pci_resource_id = PCIR_BAR(0); 499 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 500 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 501 502 if (ioat->pci_resource == NULL) { 503 ioat_log_message(0, "unable to allocate pci resource\n"); 504 return (ENODEV); 505 } 506 507 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 508 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 509 return (0); 510 } 511 512 static void 513 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 514 { 515 struct ioat_softc *ioat = arg; 516 517 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 518 ioat->comp_update_bus_addr = seg[0].ds_addr; 519 } 520 521 static void 522 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 523 { 524 bus_addr_t *baddr; 525 526 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 527 baddr = arg; 528 *baddr = segs->ds_addr; 529 } 530 531 /* 532 * Interrupt setup and handlers 533 */ 534 static int 535 ioat_setup_intr(struct ioat_softc *ioat) 536 { 537 uint32_t num_vectors; 538 int error; 539 boolean_t use_msix; 540 boolean_t force_legacy_interrupts; 541 542 use_msix = FALSE; 543 force_legacy_interrupts = FALSE; 544 545 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 546 num_vectors = 1; 547 pci_alloc_msix(ioat->device, &num_vectors); 548 if (num_vectors == 1) 549 use_msix = TRUE; 550 } 551 552 if (use_msix) { 553 ioat->rid = 1; 554 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 555 &ioat->rid, RF_ACTIVE); 556 } else { 557 ioat->rid = 0; 558 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 559 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 560 } 561 if (ioat->res == NULL) { 562 ioat_log_message(0, "bus_alloc_resource failed\n"); 563 return (ENOMEM); 564 } 565 566 ioat->tag = NULL; 567 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 568 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 569 if (error != 0) { 570 ioat_log_message(0, "bus_setup_intr failed\n"); 571 return (error); 572 } 573 574 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 575 return (0); 576 } 577 578 static boolean_t 579 ioat_model_resets_msix(struct ioat_softc *ioat) 580 { 581 u_int32_t pciid; 582 583 pciid = pci_get_devid(ioat->device); 584 switch (pciid) { 585 /* BWD: */ 586 case 0x0c508086: 587 case 0x0c518086: 588 case 0x0c528086: 589 case 0x0c538086: 590 /* BDXDE: */ 591 case 0x6f508086: 592 case 0x6f518086: 593 case 0x6f528086: 594 case 0x6f538086: 595 return (TRUE); 596 } 597 598 return (FALSE); 599 } 600 601 static void 602 ioat_interrupt_handler(void *arg) 603 { 604 struct ioat_softc *ioat = arg; 605 606 ioat->stats.interrupts++; 607 ioat_process_events(ioat); 608 } 609 610 static int 611 chanerr_to_errno(uint32_t chanerr) 612 { 613 614 if (chanerr == 0) 615 return (0); 616 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 617 return (EFAULT); 618 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 619 return (EIO); 620 /* This one is probably our fault: */ 621 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 622 return (EIO); 623 return (EIO); 624 } 625 626 static void 627 ioat_process_events(struct ioat_softc *ioat) 628 { 629 struct ioat_descriptor *desc; 630 struct bus_dmadesc *dmadesc; 631 uint64_t comp_update, status; 632 uint32_t completed, chanerr; 633 int error; 634 635 mtx_lock(&ioat->cleanup_lock); 636 637 completed = 0; 638 comp_update = *ioat->comp_update; 639 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 640 641 CTR0(KTR_IOAT, __func__); 642 643 if (status == ioat->last_seen) { 644 /* 645 * If we landed in process_events and nothing has been 646 * completed, check for a timeout due to channel halt. 647 */ 648 comp_update = ioat_get_chansts(ioat); 649 goto out; 650 } 651 652 while (1) { 653 desc = ioat_get_ring_entry(ioat, ioat->tail); 654 dmadesc = &desc->bus_dmadesc; 655 CTR1(KTR_IOAT, "completing desc %d", ioat->tail); 656 657 if (dmadesc->callback_fn != NULL) 658 dmadesc->callback_fn(dmadesc->callback_arg, 0); 659 660 completed++; 661 ioat->tail++; 662 if (desc->hw_desc_bus_addr == status) 663 break; 664 } 665 666 ioat->last_seen = desc->hw_desc_bus_addr; 667 668 if (ioat->head == ioat->tail) { 669 ioat->is_completion_pending = FALSE; 670 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 671 ioat_timer_callback, ioat); 672 } 673 674 ioat->stats.descriptors_processed += completed; 675 676 out: 677 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 678 mtx_unlock(&ioat->cleanup_lock); 679 680 if (completed != 0) { 681 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 682 wakeup(&ioat->tail); 683 } 684 685 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 686 return; 687 688 ioat->stats.channel_halts++; 689 690 /* 691 * Fatal programming error on this DMA channel. Flush any outstanding 692 * work with error status and restart the engine. 693 */ 694 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 695 mtx_lock(&ioat->submit_lock); 696 mtx_lock(&ioat->cleanup_lock); 697 ioat->quiescing = TRUE; 698 699 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 700 ioat_halted_debug(ioat, chanerr); 701 ioat->stats.last_halt_chanerr = chanerr; 702 703 while (ioat_get_active(ioat) > 0) { 704 desc = ioat_get_ring_entry(ioat, ioat->tail); 705 dmadesc = &desc->bus_dmadesc; 706 CTR1(KTR_IOAT, "completing err desc %d", ioat->tail); 707 708 if (dmadesc->callback_fn != NULL) 709 dmadesc->callback_fn(dmadesc->callback_arg, 710 chanerr_to_errno(chanerr)); 711 712 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 713 ioat->tail++; 714 ioat->stats.descriptors_processed++; 715 ioat->stats.descriptors_error++; 716 } 717 718 /* Clear error status */ 719 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 720 721 mtx_unlock(&ioat->cleanup_lock); 722 mtx_unlock(&ioat->submit_lock); 723 724 ioat_log_message(0, "Resetting channel to recover from error\n"); 725 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 726 KASSERT(error == 0, 727 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 728 } 729 730 static void 731 ioat_reset_hw_task(void *ctx, int pending __unused) 732 { 733 struct ioat_softc *ioat; 734 int error; 735 736 ioat = ctx; 737 ioat_log_message(1, "%s: Resetting channel\n", __func__); 738 739 error = ioat_reset_hw(ioat); 740 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 741 (void)error; 742 } 743 744 /* 745 * User API functions 746 */ 747 bus_dmaengine_t 748 ioat_get_dmaengine(uint32_t index, int flags) 749 { 750 struct ioat_softc *ioat; 751 752 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 753 ("invalid flags: 0x%08x", flags)); 754 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 755 ("invalid wait | nowait")); 756 757 if (index >= ioat_channel_index) 758 return (NULL); 759 760 ioat = ioat_channel[index]; 761 if (ioat == NULL || ioat->destroying) 762 return (NULL); 763 764 if (ioat->quiescing) { 765 if ((flags & M_NOWAIT) != 0) 766 return (NULL); 767 768 mtx_lock(IOAT_REFLK); 769 while (ioat->quiescing && !ioat->destroying) 770 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 771 mtx_unlock(IOAT_REFLK); 772 773 if (ioat->destroying) 774 return (NULL); 775 } 776 777 /* 778 * There's a race here between the quiescing check and HW reset or 779 * module destroy. 780 */ 781 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 782 } 783 784 void 785 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 786 { 787 struct ioat_softc *ioat; 788 789 ioat = to_ioat_softc(dmaengine); 790 ioat_put(ioat, IOAT_DMAENGINE_REF); 791 } 792 793 int 794 ioat_get_hwversion(bus_dmaengine_t dmaengine) 795 { 796 struct ioat_softc *ioat; 797 798 ioat = to_ioat_softc(dmaengine); 799 return (ioat->version); 800 } 801 802 size_t 803 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 804 { 805 struct ioat_softc *ioat; 806 807 ioat = to_ioat_softc(dmaengine); 808 return (ioat->max_xfer_size); 809 } 810 811 int 812 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 813 { 814 struct ioat_softc *ioat; 815 816 ioat = to_ioat_softc(dmaengine); 817 if (!ioat->intrdelay_supported) 818 return (ENODEV); 819 if (delay > ioat->intrdelay_max) 820 return (ERANGE); 821 822 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 823 ioat->cached_intrdelay = 824 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 825 return (0); 826 } 827 828 uint16_t 829 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 830 { 831 struct ioat_softc *ioat; 832 833 ioat = to_ioat_softc(dmaengine); 834 return (ioat->intrdelay_max); 835 } 836 837 void 838 ioat_acquire(bus_dmaengine_t dmaengine) 839 { 840 struct ioat_softc *ioat; 841 842 ioat = to_ioat_softc(dmaengine); 843 mtx_lock(&ioat->submit_lock); 844 CTR0(KTR_IOAT, __func__); 845 } 846 847 int 848 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 849 { 850 struct ioat_softc *ioat; 851 int error; 852 853 ioat = to_ioat_softc(dmaengine); 854 ioat_acquire(dmaengine); 855 856 error = ioat_reserve_space(ioat, n, mflags); 857 if (error != 0) 858 ioat_release(dmaengine); 859 return (error); 860 } 861 862 void 863 ioat_release(bus_dmaengine_t dmaengine) 864 { 865 struct ioat_softc *ioat; 866 867 ioat = to_ioat_softc(dmaengine); 868 CTR0(KTR_IOAT, __func__); 869 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 870 mtx_unlock(&ioat->submit_lock); 871 } 872 873 static struct ioat_descriptor * 874 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 875 uint32_t size, uint64_t src, uint64_t dst, 876 bus_dmaengine_callback_t callback_fn, void *callback_arg, 877 uint32_t flags) 878 { 879 struct ioat_generic_hw_descriptor *hw_desc; 880 struct ioat_descriptor *desc; 881 int mflags; 882 883 mtx_assert(&ioat->submit_lock, MA_OWNED); 884 885 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 886 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 887 if ((flags & DMA_NO_WAIT) != 0) 888 mflags = M_NOWAIT; 889 else 890 mflags = M_WAITOK; 891 892 if (size > ioat->max_xfer_size) { 893 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 894 __func__, ioat->max_xfer_size, (unsigned)size); 895 return (NULL); 896 } 897 898 if (ioat_reserve_space(ioat, 1, mflags) != 0) 899 return (NULL); 900 901 desc = ioat_get_ring_entry(ioat, ioat->head); 902 hw_desc = desc->u.generic; 903 904 hw_desc->u.control_raw = 0; 905 hw_desc->u.control_generic.op = op; 906 hw_desc->u.control_generic.completion_update = 1; 907 908 if ((flags & DMA_INT_EN) != 0) 909 hw_desc->u.control_generic.int_enable = 1; 910 if ((flags & DMA_FENCE) != 0) 911 hw_desc->u.control_generic.fence = 1; 912 913 hw_desc->size = size; 914 hw_desc->src_addr = src; 915 hw_desc->dest_addr = dst; 916 917 desc->bus_dmadesc.callback_fn = callback_fn; 918 desc->bus_dmadesc.callback_arg = callback_arg; 919 return (desc); 920 } 921 922 struct bus_dmadesc * 923 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 924 void *callback_arg, uint32_t flags) 925 { 926 struct ioat_dma_hw_descriptor *hw_desc; 927 struct ioat_descriptor *desc; 928 struct ioat_softc *ioat; 929 930 CTR0(KTR_IOAT, __func__); 931 ioat = to_ioat_softc(dmaengine); 932 933 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 934 callback_arg, flags); 935 if (desc == NULL) 936 return (NULL); 937 938 hw_desc = desc->u.dma; 939 hw_desc->u.control.null = 1; 940 ioat_submit_single(ioat); 941 return (&desc->bus_dmadesc); 942 } 943 944 struct bus_dmadesc * 945 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 946 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 947 void *callback_arg, uint32_t flags) 948 { 949 struct ioat_dma_hw_descriptor *hw_desc; 950 struct ioat_descriptor *desc; 951 struct ioat_softc *ioat; 952 953 CTR0(KTR_IOAT, __func__); 954 ioat = to_ioat_softc(dmaengine); 955 956 if (((src | dst) & (0xffffull << 48)) != 0) { 957 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 958 __func__); 959 return (NULL); 960 } 961 962 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 963 callback_arg, flags); 964 if (desc == NULL) 965 return (NULL); 966 967 hw_desc = desc->u.dma; 968 if (g_ioat_debug_level >= 3) 969 dump_descriptor(hw_desc); 970 971 ioat_submit_single(ioat); 972 return (&desc->bus_dmadesc); 973 } 974 975 struct bus_dmadesc * 976 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 977 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 978 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 979 { 980 struct ioat_dma_hw_descriptor *hw_desc; 981 struct ioat_descriptor *desc; 982 struct ioat_softc *ioat; 983 984 CTR0(KTR_IOAT, __func__); 985 ioat = to_ioat_softc(dmaengine); 986 987 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 988 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 989 __func__); 990 return (NULL); 991 } 992 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 993 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 994 __func__); 995 return (NULL); 996 } 997 998 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 999 callback_fn, callback_arg, flags); 1000 if (desc == NULL) 1001 return (NULL); 1002 1003 hw_desc = desc->u.dma; 1004 if (src2 != src1 + PAGE_SIZE) { 1005 hw_desc->u.control.src_page_break = 1; 1006 hw_desc->next_src_addr = src2; 1007 } 1008 if (dst2 != dst1 + PAGE_SIZE) { 1009 hw_desc->u.control.dest_page_break = 1; 1010 hw_desc->next_dest_addr = dst2; 1011 } 1012 1013 if (g_ioat_debug_level >= 3) 1014 dump_descriptor(hw_desc); 1015 1016 ioat_submit_single(ioat); 1017 return (&desc->bus_dmadesc); 1018 } 1019 1020 struct bus_dmadesc * 1021 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1022 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1023 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1024 { 1025 struct ioat_crc32_hw_descriptor *hw_desc; 1026 struct ioat_descriptor *desc; 1027 struct ioat_softc *ioat; 1028 uint32_t teststore; 1029 uint8_t op; 1030 1031 CTR0(KTR_IOAT, __func__); 1032 ioat = to_ioat_softc(dmaengine); 1033 1034 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1035 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1036 __func__); 1037 return (NULL); 1038 } 1039 if (((src | dst) & (0xffffffull << 40)) != 0) { 1040 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1041 __func__); 1042 return (NULL); 1043 } 1044 teststore = (flags & _DMA_CRC_TESTSTORE); 1045 if (teststore == _DMA_CRC_TESTSTORE) { 1046 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1047 return (NULL); 1048 } 1049 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1050 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1051 __func__); 1052 return (NULL); 1053 } 1054 1055 switch (teststore) { 1056 case DMA_CRC_STORE: 1057 op = IOAT_OP_MOVECRC_STORE; 1058 break; 1059 case DMA_CRC_TEST: 1060 op = IOAT_OP_MOVECRC_TEST; 1061 break; 1062 default: 1063 KASSERT(teststore == 0, ("bogus")); 1064 op = IOAT_OP_MOVECRC; 1065 break; 1066 } 1067 1068 if ((flags & DMA_CRC_INLINE) == 0 && 1069 (crcptr & (0xffffffull << 40)) != 0) { 1070 ioat_log_message(0, 1071 "%s: High 24 bits of crcptr invalid\n", __func__); 1072 return (NULL); 1073 } 1074 1075 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1076 callback_arg, flags & ~_DMA_CRC_FLAGS); 1077 if (desc == NULL) 1078 return (NULL); 1079 1080 hw_desc = desc->u.crc32; 1081 1082 if ((flags & DMA_CRC_INLINE) == 0) 1083 hw_desc->crc_address = crcptr; 1084 else 1085 hw_desc->u.control.crc_location = 1; 1086 1087 if (initialseed != NULL) { 1088 hw_desc->u.control.use_seed = 1; 1089 hw_desc->seed = *initialseed; 1090 } 1091 1092 if (g_ioat_debug_level >= 3) 1093 dump_descriptor(hw_desc); 1094 1095 ioat_submit_single(ioat); 1096 return (&desc->bus_dmadesc); 1097 } 1098 1099 struct bus_dmadesc * 1100 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1101 uint32_t *initialseed, bus_addr_t crcptr, 1102 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1103 { 1104 struct ioat_crc32_hw_descriptor *hw_desc; 1105 struct ioat_descriptor *desc; 1106 struct ioat_softc *ioat; 1107 uint32_t teststore; 1108 uint8_t op; 1109 1110 CTR0(KTR_IOAT, __func__); 1111 ioat = to_ioat_softc(dmaengine); 1112 1113 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1114 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1115 __func__); 1116 return (NULL); 1117 } 1118 if ((src & (0xffffffull << 40)) != 0) { 1119 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1120 __func__); 1121 return (NULL); 1122 } 1123 teststore = (flags & _DMA_CRC_TESTSTORE); 1124 if (teststore == _DMA_CRC_TESTSTORE) { 1125 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1126 return (NULL); 1127 } 1128 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1129 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1130 __func__); 1131 return (NULL); 1132 } 1133 1134 switch (teststore) { 1135 case DMA_CRC_STORE: 1136 op = IOAT_OP_CRC_STORE; 1137 break; 1138 case DMA_CRC_TEST: 1139 op = IOAT_OP_CRC_TEST; 1140 break; 1141 default: 1142 KASSERT(teststore == 0, ("bogus")); 1143 op = IOAT_OP_CRC; 1144 break; 1145 } 1146 1147 if ((flags & DMA_CRC_INLINE) == 0 && 1148 (crcptr & (0xffffffull << 40)) != 0) { 1149 ioat_log_message(0, 1150 "%s: High 24 bits of crcptr invalid\n", __func__); 1151 return (NULL); 1152 } 1153 1154 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1155 callback_arg, flags & ~_DMA_CRC_FLAGS); 1156 if (desc == NULL) 1157 return (NULL); 1158 1159 hw_desc = desc->u.crc32; 1160 1161 if ((flags & DMA_CRC_INLINE) == 0) 1162 hw_desc->crc_address = crcptr; 1163 else 1164 hw_desc->u.control.crc_location = 1; 1165 1166 if (initialseed != NULL) { 1167 hw_desc->u.control.use_seed = 1; 1168 hw_desc->seed = *initialseed; 1169 } 1170 1171 if (g_ioat_debug_level >= 3) 1172 dump_descriptor(hw_desc); 1173 1174 ioat_submit_single(ioat); 1175 return (&desc->bus_dmadesc); 1176 } 1177 1178 struct bus_dmadesc * 1179 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1180 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1181 uint32_t flags) 1182 { 1183 struct ioat_fill_hw_descriptor *hw_desc; 1184 struct ioat_descriptor *desc; 1185 struct ioat_softc *ioat; 1186 1187 CTR0(KTR_IOAT, __func__); 1188 ioat = to_ioat_softc(dmaengine); 1189 1190 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1191 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1192 __func__); 1193 return (NULL); 1194 } 1195 1196 if ((dst & (0xffffull << 48)) != 0) { 1197 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1198 __func__); 1199 return (NULL); 1200 } 1201 1202 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1203 callback_fn, callback_arg, flags); 1204 if (desc == NULL) 1205 return (NULL); 1206 1207 hw_desc = desc->u.fill; 1208 if (g_ioat_debug_level >= 3) 1209 dump_descriptor(hw_desc); 1210 1211 ioat_submit_single(ioat); 1212 return (&desc->bus_dmadesc); 1213 } 1214 1215 /* 1216 * Ring Management 1217 */ 1218 static inline uint32_t 1219 ioat_get_active(struct ioat_softc *ioat) 1220 { 1221 1222 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1223 } 1224 1225 static inline uint32_t 1226 ioat_get_ring_space(struct ioat_softc *ioat) 1227 { 1228 1229 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1230 } 1231 1232 static struct ioat_descriptor * 1233 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 1234 { 1235 struct ioat_generic_hw_descriptor *hw_desc; 1236 struct ioat_descriptor *desc; 1237 int error, busdmaflag; 1238 1239 error = ENOMEM; 1240 hw_desc = NULL; 1241 1242 if ((mflags & M_WAITOK) != 0) 1243 busdmaflag = BUS_DMA_WAITOK; 1244 else 1245 busdmaflag = BUS_DMA_NOWAIT; 1246 1247 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1248 if (desc == NULL) 1249 goto out; 1250 1251 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1252 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1253 if (hw_desc == NULL) 1254 goto out; 1255 1256 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1257 desc->u.generic = hw_desc; 1258 1259 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1260 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1261 busdmaflag); 1262 if (error) 1263 goto out; 1264 1265 out: 1266 if (error) { 1267 ioat_free_ring_entry(ioat, desc); 1268 return (NULL); 1269 } 1270 return (desc); 1271 } 1272 1273 static void 1274 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1275 { 1276 1277 if (desc == NULL) 1278 return; 1279 1280 if (desc->u.generic) 1281 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1282 ioat->hw_desc_map); 1283 free(desc, M_IOAT); 1284 } 1285 1286 /* 1287 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1288 * for 'num_descs'. 1289 * 1290 * If mflags contains M_WAITOK, blocks until enough space is available. 1291 * 1292 * Returns zero on success, or an errno on error. If num_descs is beyond the 1293 * maximum ring size, returns EINVAl; if allocation would block and mflags 1294 * contains M_NOWAIT, returns EAGAIN. 1295 * 1296 * Must be called with the submit_lock held; returns with the lock held. The 1297 * lock may be dropped to allocate the ring. 1298 * 1299 * (The submit_lock is needed to add any entries to the ring, so callers are 1300 * assured enough room is available.) 1301 */ 1302 static int 1303 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1304 { 1305 struct ioat_descriptor **new_ring; 1306 uint32_t order; 1307 int error; 1308 1309 mtx_assert(&ioat->submit_lock, MA_OWNED); 1310 error = 0; 1311 1312 if (num_descs < 1 || num_descs > (1 << IOAT_MAX_ORDER)) { 1313 error = EINVAL; 1314 goto out; 1315 } 1316 if (ioat->quiescing) { 1317 error = ENXIO; 1318 goto out; 1319 } 1320 1321 for (;;) { 1322 if (ioat_get_ring_space(ioat) >= num_descs) 1323 goto out; 1324 1325 order = ioat->ring_size_order; 1326 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1327 if ((mflags & M_WAITOK) != 0) { 1328 msleep(&ioat->tail, &ioat->submit_lock, 0, 1329 "ioat_rsz", 0); 1330 continue; 1331 } 1332 1333 error = EAGAIN; 1334 break; 1335 } 1336 1337 ioat->is_resize_pending = TRUE; 1338 for (;;) { 1339 mtx_unlock(&ioat->submit_lock); 1340 1341 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1342 TRUE, mflags); 1343 1344 mtx_lock(&ioat->submit_lock); 1345 KASSERT(ioat->ring_size_order == order, 1346 ("is_resize_pending should protect order")); 1347 1348 if (new_ring == NULL) { 1349 KASSERT((mflags & M_WAITOK) == 0, 1350 ("allocation failed")); 1351 error = EAGAIN; 1352 break; 1353 } 1354 1355 error = ring_grow(ioat, order, new_ring); 1356 if (error == 0) 1357 break; 1358 } 1359 ioat->is_resize_pending = FALSE; 1360 wakeup(&ioat->tail); 1361 if (error) 1362 break; 1363 } 1364 1365 out: 1366 mtx_assert(&ioat->submit_lock, MA_OWNED); 1367 return (error); 1368 } 1369 1370 static struct ioat_descriptor ** 1371 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1372 int mflags) 1373 { 1374 struct ioat_descriptor **ring; 1375 uint32_t i; 1376 int error; 1377 1378 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1379 1380 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1381 if (ring == NULL) 1382 return (NULL); 1383 1384 if (need_dscr) { 1385 error = ENOMEM; 1386 for (i = size / 2; i < size; i++) { 1387 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1388 if (ring[i] == NULL) 1389 goto out; 1390 ring[i]->id = i; 1391 } 1392 } 1393 error = 0; 1394 1395 out: 1396 if (error != 0 && ring != NULL) { 1397 ioat_free_ring(ioat, size, ring); 1398 ring = NULL; 1399 } 1400 return (ring); 1401 } 1402 1403 static void 1404 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1405 struct ioat_descriptor **ring) 1406 { 1407 uint32_t i; 1408 1409 for (i = 0; i < size; i++) { 1410 if (ring[i] != NULL) 1411 ioat_free_ring_entry(ioat, ring[i]); 1412 } 1413 free(ring, M_IOAT); 1414 } 1415 1416 static struct ioat_descriptor * 1417 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1418 { 1419 1420 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1421 } 1422 1423 static int 1424 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1425 struct ioat_descriptor **newring) 1426 { 1427 struct ioat_descriptor *tmp, *next; 1428 struct ioat_dma_hw_descriptor *hw; 1429 uint32_t oldsize, newsize, head, tail, i, end; 1430 int error; 1431 1432 CTR0(KTR_IOAT, __func__); 1433 1434 mtx_assert(&ioat->submit_lock, MA_OWNED); 1435 1436 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1437 error = EINVAL; 1438 goto out; 1439 } 1440 1441 oldsize = (1 << oldorder); 1442 newsize = (1 << (oldorder + 1)); 1443 1444 mtx_lock(&ioat->cleanup_lock); 1445 1446 head = ioat->head & (oldsize - 1); 1447 tail = ioat->tail & (oldsize - 1); 1448 1449 /* Copy old descriptors to new ring */ 1450 for (i = 0; i < oldsize; i++) 1451 newring[i] = ioat->ring[i]; 1452 1453 /* 1454 * If head has wrapped but tail hasn't, we must swap some descriptors 1455 * around so that tail can increment directly to head. 1456 */ 1457 if (head < tail) { 1458 for (i = 0; i <= head; i++) { 1459 tmp = newring[oldsize + i]; 1460 1461 newring[oldsize + i] = newring[i]; 1462 newring[oldsize + i]->id = oldsize + i; 1463 1464 newring[i] = tmp; 1465 newring[i]->id = i; 1466 } 1467 head += oldsize; 1468 } 1469 1470 KASSERT(head >= tail, ("invariants")); 1471 1472 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1473 if (head < oldsize) { 1474 i = oldsize - 1; 1475 end = newsize; 1476 } else { 1477 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1478 i = head; 1479 end = newsize + (head - oldsize) + 1; 1480 } 1481 1482 /* 1483 * Fix up hardware ring, being careful not to trample the active 1484 * section (tail -> head). 1485 */ 1486 for (; i < end; i++) { 1487 KASSERT((i & (newsize - 1)) < tail || 1488 (i & (newsize - 1)) >= head, ("trampling snake")); 1489 1490 next = newring[(i + 1) & (newsize - 1)]; 1491 hw = newring[i & (newsize - 1)]->u.dma; 1492 hw->next = next->hw_desc_bus_addr; 1493 } 1494 1495 free(ioat->ring, M_IOAT); 1496 ioat->ring = newring; 1497 ioat->ring_size_order = oldorder + 1; 1498 ioat->tail = tail; 1499 ioat->head = head; 1500 error = 0; 1501 1502 mtx_unlock(&ioat->cleanup_lock); 1503 out: 1504 if (error) 1505 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1506 return (error); 1507 } 1508 1509 static int 1510 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1511 struct ioat_descriptor **newring) 1512 { 1513 struct ioat_dma_hw_descriptor *hw; 1514 struct ioat_descriptor *ent, *next; 1515 uint32_t oldsize, newsize, current_idx, new_idx, i; 1516 int error; 1517 1518 CTR0(KTR_IOAT, __func__); 1519 1520 mtx_assert(&ioat->submit_lock, MA_OWNED); 1521 1522 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1523 error = EINVAL; 1524 goto out_unlocked; 1525 } 1526 1527 oldsize = (1 << oldorder); 1528 newsize = (1 << (oldorder - 1)); 1529 1530 mtx_lock(&ioat->cleanup_lock); 1531 1532 /* Can't shrink below current active set! */ 1533 if (ioat_get_active(ioat) >= newsize) { 1534 error = ENOMEM; 1535 goto out; 1536 } 1537 1538 /* 1539 * Copy current descriptors to the new ring, dropping the removed 1540 * descriptors. 1541 */ 1542 for (i = 0; i < newsize; i++) { 1543 current_idx = (ioat->tail + i) & (oldsize - 1); 1544 new_idx = (ioat->tail + i) & (newsize - 1); 1545 1546 newring[new_idx] = ioat->ring[current_idx]; 1547 newring[new_idx]->id = new_idx; 1548 } 1549 1550 /* Free deleted descriptors */ 1551 for (i = newsize; i < oldsize; i++) { 1552 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1553 ioat_free_ring_entry(ioat, ent); 1554 } 1555 1556 /* Fix up hardware ring. */ 1557 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1558 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1559 hw->next = next->hw_desc_bus_addr; 1560 1561 free(ioat->ring, M_IOAT); 1562 ioat->ring = newring; 1563 ioat->ring_size_order = oldorder - 1; 1564 error = 0; 1565 1566 out: 1567 mtx_unlock(&ioat->cleanup_lock); 1568 out_unlocked: 1569 if (error) 1570 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1571 return (error); 1572 } 1573 1574 static void 1575 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1576 { 1577 struct ioat_descriptor *desc; 1578 1579 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1580 IOAT_CHANERR_STR); 1581 if (chanerr == 0) 1582 return; 1583 1584 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1585 1586 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1587 dump_descriptor(desc->u.raw); 1588 1589 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1590 dump_descriptor(desc->u.raw); 1591 } 1592 1593 static void 1594 ioat_timer_callback(void *arg) 1595 { 1596 struct ioat_descriptor **newring; 1597 struct ioat_softc *ioat; 1598 uint32_t order; 1599 1600 ioat = arg; 1601 ioat_log_message(1, "%s\n", __func__); 1602 1603 if (ioat->is_completion_pending) { 1604 ioat_process_events(ioat); 1605 return; 1606 } 1607 1608 /* Slowly scale the ring down if idle. */ 1609 mtx_lock(&ioat->submit_lock); 1610 order = ioat->ring_size_order; 1611 if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) { 1612 mtx_unlock(&ioat->submit_lock); 1613 goto out; 1614 } 1615 ioat->is_resize_pending = TRUE; 1616 mtx_unlock(&ioat->submit_lock); 1617 1618 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1619 M_NOWAIT); 1620 1621 mtx_lock(&ioat->submit_lock); 1622 KASSERT(ioat->ring_size_order == order, 1623 ("resize_pending protects order")); 1624 1625 if (newring != NULL) 1626 ring_shrink(ioat, order, newring); 1627 1628 ioat->is_resize_pending = FALSE; 1629 mtx_unlock(&ioat->submit_lock); 1630 1631 out: 1632 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1633 callout_reset(&ioat->timer, 10 * hz, 1634 ioat_timer_callback, ioat); 1635 } 1636 1637 /* 1638 * Support Functions 1639 */ 1640 static void 1641 ioat_submit_single(struct ioat_softc *ioat) 1642 { 1643 1644 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1645 atomic_add_rel_int(&ioat->head, 1); 1646 atomic_add_rel_int(&ioat->hw_head, 1); 1647 1648 if (!ioat->is_completion_pending) { 1649 ioat->is_completion_pending = TRUE; 1650 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 1651 ioat_timer_callback, ioat); 1652 } 1653 1654 ioat->stats.descriptors_submitted++; 1655 } 1656 1657 static int 1658 ioat_reset_hw(struct ioat_softc *ioat) 1659 { 1660 uint64_t status; 1661 uint32_t chanerr; 1662 unsigned timeout; 1663 int error; 1664 1665 mtx_lock(IOAT_REFLK); 1666 ioat->quiescing = TRUE; 1667 ioat_drain_locked(ioat); 1668 mtx_unlock(IOAT_REFLK); 1669 1670 status = ioat_get_chansts(ioat); 1671 if (is_ioat_active(status) || is_ioat_idle(status)) 1672 ioat_suspend(ioat); 1673 1674 /* Wait at most 20 ms */ 1675 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1676 timeout < 20; timeout++) { 1677 DELAY(1000); 1678 status = ioat_get_chansts(ioat); 1679 } 1680 if (timeout == 20) { 1681 error = ETIMEDOUT; 1682 goto out; 1683 } 1684 1685 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1686 1687 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1688 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1689 1690 /* 1691 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1692 * that can cause stability issues for IOAT v3. 1693 */ 1694 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1695 4); 1696 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1697 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1698 1699 /* 1700 * BDXDE and BWD models reset MSI-X registers on device reset. 1701 * Save/restore their contents manually. 1702 */ 1703 if (ioat_model_resets_msix(ioat)) { 1704 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1705 pci_save_state(ioat->device); 1706 } 1707 1708 ioat_reset(ioat); 1709 1710 /* Wait at most 20 ms */ 1711 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1712 DELAY(1000); 1713 if (timeout == 20) { 1714 error = ETIMEDOUT; 1715 goto out; 1716 } 1717 1718 if (ioat_model_resets_msix(ioat)) { 1719 ioat_log_message(1, "device resets registers; restored\n"); 1720 pci_restore_state(ioat->device); 1721 } 1722 1723 /* Reset attempts to return the hardware to "halted." */ 1724 status = ioat_get_chansts(ioat); 1725 if (is_ioat_active(status) || is_ioat_idle(status)) { 1726 /* So this really shouldn't happen... */ 1727 ioat_log_message(0, "Device is active after a reset?\n"); 1728 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1729 error = 0; 1730 goto out; 1731 } 1732 1733 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1734 if (chanerr != 0) { 1735 mtx_lock(&ioat->cleanup_lock); 1736 ioat_halted_debug(ioat, chanerr); 1737 mtx_unlock(&ioat->cleanup_lock); 1738 error = EIO; 1739 goto out; 1740 } 1741 1742 /* 1743 * Bring device back online after reset. Writing CHAINADDR brings the 1744 * device back to active. 1745 * 1746 * The internal ring counter resets to zero, so we have to start over 1747 * at zero as well. 1748 */ 1749 ioat->tail = ioat->head = ioat->hw_head = 0; 1750 ioat->last_seen = 0; 1751 1752 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1753 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1754 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1755 error = 0; 1756 1757 out: 1758 mtx_lock(IOAT_REFLK); 1759 ioat->quiescing = FALSE; 1760 wakeup(&ioat->quiescing); 1761 mtx_unlock(IOAT_REFLK); 1762 1763 if (error == 0) 1764 error = ioat_start_channel(ioat); 1765 1766 return (error); 1767 } 1768 1769 static int 1770 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1771 { 1772 struct ioat_softc *ioat; 1773 struct sbuf sb; 1774 uint64_t status; 1775 int error; 1776 1777 ioat = arg1; 1778 1779 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1780 1781 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1782 switch (status) { 1783 case IOAT_CHANSTS_ACTIVE: 1784 sbuf_printf(&sb, "ACTIVE"); 1785 break; 1786 case IOAT_CHANSTS_IDLE: 1787 sbuf_printf(&sb, "IDLE"); 1788 break; 1789 case IOAT_CHANSTS_SUSPENDED: 1790 sbuf_printf(&sb, "SUSPENDED"); 1791 break; 1792 case IOAT_CHANSTS_HALTED: 1793 sbuf_printf(&sb, "HALTED"); 1794 break; 1795 case IOAT_CHANSTS_ARMED: 1796 sbuf_printf(&sb, "ARMED"); 1797 break; 1798 default: 1799 sbuf_printf(&sb, "UNKNOWN"); 1800 break; 1801 } 1802 error = sbuf_finish(&sb); 1803 sbuf_delete(&sb); 1804 1805 if (error != 0 || req->newptr == NULL) 1806 return (error); 1807 return (EINVAL); 1808 } 1809 1810 static int 1811 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1812 { 1813 struct ioat_softc *ioat; 1814 struct sbuf sb; 1815 #define PRECISION "1" 1816 const uintmax_t factor = 10; 1817 uintmax_t rate; 1818 int error; 1819 1820 ioat = arg1; 1821 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1822 1823 if (ioat->stats.interrupts == 0) { 1824 sbuf_printf(&sb, "NaN"); 1825 goto out; 1826 } 1827 rate = ioat->stats.descriptors_processed * factor / 1828 ioat->stats.interrupts; 1829 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1830 rate % factor); 1831 #undef PRECISION 1832 out: 1833 error = sbuf_finish(&sb); 1834 sbuf_delete(&sb); 1835 if (error != 0 || req->newptr == NULL) 1836 return (error); 1837 return (EINVAL); 1838 } 1839 1840 static int 1841 sysctl_handle_error(SYSCTL_HANDLER_ARGS) 1842 { 1843 struct ioat_descriptor *desc; 1844 struct ioat_softc *ioat; 1845 int error, arg; 1846 1847 ioat = arg1; 1848 1849 arg = 0; 1850 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1851 if (error != 0 || req->newptr == NULL) 1852 return (error); 1853 1854 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1855 if (error != 0) 1856 return (error); 1857 1858 if (arg != 0) { 1859 ioat_acquire(&ioat->dmaengine); 1860 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 1, 1861 0xffff000000000000ull, 0xffff000000000000ull, NULL, NULL, 1862 0); 1863 if (desc == NULL) 1864 error = ENOMEM; 1865 else 1866 ioat_submit_single(ioat); 1867 ioat_release(&ioat->dmaengine); 1868 } 1869 return (error); 1870 } 1871 1872 static int 1873 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1874 { 1875 struct ioat_softc *ioat; 1876 int error, arg; 1877 1878 ioat = arg1; 1879 1880 arg = 0; 1881 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1882 if (error != 0 || req->newptr == NULL) 1883 return (error); 1884 1885 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1886 if (error != 0) 1887 return (error); 1888 1889 if (arg != 0) 1890 error = ioat_reset_hw(ioat); 1891 1892 return (error); 1893 } 1894 1895 static void 1896 dump_descriptor(void *hw_desc) 1897 { 1898 int i, j; 1899 1900 for (i = 0; i < 2; i++) { 1901 for (j = 0; j < 8; j++) 1902 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1903 printf("\n"); 1904 } 1905 } 1906 1907 static void 1908 ioat_setup_sysctl(device_t device) 1909 { 1910 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1911 struct sysctl_ctx_list *ctx; 1912 struct sysctl_oid *tree, *tmp; 1913 struct ioat_softc *ioat; 1914 1915 ioat = DEVICE2SOFTC(device); 1916 ctx = device_get_sysctl_ctx(device); 1917 tree = device_get_sysctl_tree(device); 1918 par = SYSCTL_CHILDREN(tree); 1919 1920 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1921 &ioat->version, 0, "HW version (0xMM form)"); 1922 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1923 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1924 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1925 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1926 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1927 &ioat->intrdelay_max, 0, 1928 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1929 1930 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 1931 "IOAT channel internal state"); 1932 state = SYSCTL_CHILDREN(tmp); 1933 1934 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1935 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1936 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1937 0, "SW descriptor head pointer index"); 1938 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1939 0, "SW descriptor tail pointer index"); 1940 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 1941 &ioat->hw_head, 0, "HW DMACOUNT"); 1942 1943 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1944 ioat->comp_update, "HW addr of last completion"); 1945 1946 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 1947 &ioat->is_resize_pending, 0, "resize pending"); 1948 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 1949 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 1950 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1951 &ioat->is_reset_pending, 0, "reset pending"); 1952 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1953 &ioat->is_channel_running, 0, "channel running"); 1954 1955 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1956 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1957 "String of the channel status"); 1958 1959 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1960 &ioat->cached_intrdelay, 0, 1961 "Current INTRDELAY on this channel (cached, microseconds)"); 1962 1963 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 1964 "Big hammers (mostly for testing)"); 1965 hammer = SYSCTL_CHILDREN(tmp); 1966 1967 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1968 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1969 "Set to non-zero to reset the hardware"); 1970 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_error", 1971 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_error, "I", 1972 "Set to non-zero to inject a recoverable hardware error"); 1973 1974 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 1975 "IOAT channel statistics"); 1976 statpar = SYSCTL_CHILDREN(tmp); 1977 1978 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 1979 &ioat->stats.interrupts, 1980 "Number of interrupts processed on this channel"); 1981 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 1982 &ioat->stats.descriptors_processed, 1983 "Number of descriptors processed on this channel"); 1984 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 1985 &ioat->stats.descriptors_submitted, 1986 "Number of descriptors submitted to this channel"); 1987 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 1988 &ioat->stats.descriptors_error, 1989 "Number of descriptors failed by channel errors"); 1990 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 1991 &ioat->stats.channel_halts, 0, 1992 "Number of times the channel has halted"); 1993 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 1994 &ioat->stats.last_halt_chanerr, 0, 1995 "The raw CHANERR when the channel was last halted"); 1996 1997 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 1998 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 1999 "Descriptors per interrupt"); 2000 } 2001 2002 static inline struct ioat_softc * 2003 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2004 { 2005 uint32_t old; 2006 2007 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2008 2009 old = atomic_fetchadd_32(&ioat->refcnt, 1); 2010 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 2011 2012 #ifdef INVARIANTS 2013 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 2014 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 2015 #endif 2016 2017 return (ioat); 2018 } 2019 2020 static inline void 2021 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2022 { 2023 2024 _ioat_putn(ioat, n, kind, FALSE); 2025 } 2026 2027 static inline void 2028 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2029 { 2030 2031 _ioat_putn(ioat, n, kind, TRUE); 2032 } 2033 2034 static inline void 2035 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 2036 boolean_t locked) 2037 { 2038 uint32_t old; 2039 2040 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2041 2042 if (n == 0) 2043 return; 2044 2045 #ifdef INVARIANTS 2046 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 2047 KASSERT(old >= n, ("refcnt kind underflow")); 2048 #endif 2049 2050 /* Skip acquiring the lock if resulting refcnt > 0. */ 2051 for (;;) { 2052 old = ioat->refcnt; 2053 if (old <= n) 2054 break; 2055 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 2056 return; 2057 } 2058 2059 if (locked) 2060 mtx_assert(IOAT_REFLK, MA_OWNED); 2061 else 2062 mtx_lock(IOAT_REFLK); 2063 2064 old = atomic_fetchadd_32(&ioat->refcnt, -n); 2065 KASSERT(old >= n, ("refcnt error")); 2066 2067 if (old == n) 2068 wakeup(IOAT_REFLK); 2069 if (!locked) 2070 mtx_unlock(IOAT_REFLK); 2071 } 2072 2073 static inline void 2074 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2075 { 2076 2077 ioat_putn(ioat, 1, kind); 2078 } 2079 2080 static void 2081 ioat_drain_locked(struct ioat_softc *ioat) 2082 { 2083 2084 mtx_assert(IOAT_REFLK, MA_OWNED); 2085 while (ioat->refcnt > 0) 2086 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 2087 } 2088