1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ddb.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/ioccom.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/sbuf.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #include <machine/stdarg.h> 52 53 #ifdef DDB 54 #include <ddb/ddb.h> 55 #endif 56 57 #include "ioat.h" 58 #include "ioat_hw.h" 59 #include "ioat_internal.h" 60 61 #ifndef BUS_SPACE_MAXADDR_40BIT 62 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 63 #endif 64 #define IOAT_REFLK (&ioat->submit_lock) 65 #define IOAT_SHRINK_PERIOD (10 * hz) 66 67 static int ioat_probe(device_t device); 68 static int ioat_attach(device_t device); 69 static int ioat_detach(device_t device); 70 static int ioat_setup_intr(struct ioat_softc *ioat); 71 static int ioat_teardown_intr(struct ioat_softc *ioat); 72 static int ioat3_attach(device_t device); 73 static int ioat_start_channel(struct ioat_softc *ioat); 74 static int ioat_map_pci_bar(struct ioat_softc *ioat); 75 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 76 int error); 77 static void ioat_interrupt_handler(void *arg); 78 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 79 static int chanerr_to_errno(uint32_t); 80 static void ioat_process_events(struct ioat_softc *ioat); 81 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 82 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 83 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 84 struct ioat_descriptor **); 85 static void ioat_free_ring_entry(struct ioat_softc *ioat, 86 struct ioat_descriptor *desc); 87 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 88 int mflags); 89 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 90 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 91 uint32_t index); 92 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 93 uint32_t size, boolean_t need_dscr, int mflags); 94 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 95 struct ioat_descriptor **); 96 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 97 struct ioat_descriptor **); 98 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 99 static void ioat_poll_timer_callback(void *arg); 100 static void ioat_shrink_timer_callback(void *arg); 101 static void dump_descriptor(void *hw_desc); 102 static void ioat_submit_single(struct ioat_softc *ioat); 103 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 104 int error); 105 static int ioat_reset_hw(struct ioat_softc *ioat); 106 static void ioat_reset_hw_task(void *, int); 107 static void ioat_setup_sysctl(device_t device); 108 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 109 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 110 enum ioat_ref_kind); 111 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 112 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 113 enum ioat_ref_kind, boolean_t); 114 static inline void ioat_putn(struct ioat_softc *, uint32_t, 115 enum ioat_ref_kind); 116 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 117 enum ioat_ref_kind); 118 static void ioat_drain_locked(struct ioat_softc *); 119 120 #define ioat_log_message(v, ...) do { \ 121 if ((v) <= g_ioat_debug_level) { \ 122 device_printf(ioat->device, __VA_ARGS__); \ 123 } \ 124 } while (0) 125 126 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 127 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 128 129 static int g_force_legacy_interrupts; 130 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 131 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 132 133 int g_ioat_debug_level = 0; 134 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 135 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 136 137 /* 138 * OS <-> Driver interface structures 139 */ 140 static device_method_t ioat_pci_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, ioat_probe), 143 DEVMETHOD(device_attach, ioat_attach), 144 DEVMETHOD(device_detach, ioat_detach), 145 DEVMETHOD_END 146 }; 147 148 static driver_t ioat_pci_driver = { 149 "ioat", 150 ioat_pci_methods, 151 sizeof(struct ioat_softc), 152 }; 153 154 static devclass_t ioat_devclass; 155 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 156 MODULE_VERSION(ioat, 1); 157 158 /* 159 * Private data structures 160 */ 161 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 162 static unsigned ioat_channel_index = 0; 163 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 164 "Number of IOAT channels attached"); 165 166 static struct _pcsid 167 { 168 u_int32_t type; 169 const char *desc; 170 } pci_ids[] = { 171 { 0x34308086, "TBG IOAT Ch0" }, 172 { 0x34318086, "TBG IOAT Ch1" }, 173 { 0x34328086, "TBG IOAT Ch2" }, 174 { 0x34338086, "TBG IOAT Ch3" }, 175 { 0x34298086, "TBG IOAT Ch4" }, 176 { 0x342a8086, "TBG IOAT Ch5" }, 177 { 0x342b8086, "TBG IOAT Ch6" }, 178 { 0x342c8086, "TBG IOAT Ch7" }, 179 180 { 0x37108086, "JSF IOAT Ch0" }, 181 { 0x37118086, "JSF IOAT Ch1" }, 182 { 0x37128086, "JSF IOAT Ch2" }, 183 { 0x37138086, "JSF IOAT Ch3" }, 184 { 0x37148086, "JSF IOAT Ch4" }, 185 { 0x37158086, "JSF IOAT Ch5" }, 186 { 0x37168086, "JSF IOAT Ch6" }, 187 { 0x37178086, "JSF IOAT Ch7" }, 188 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 189 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 190 191 { 0x3c208086, "SNB IOAT Ch0" }, 192 { 0x3c218086, "SNB IOAT Ch1" }, 193 { 0x3c228086, "SNB IOAT Ch2" }, 194 { 0x3c238086, "SNB IOAT Ch3" }, 195 { 0x3c248086, "SNB IOAT Ch4" }, 196 { 0x3c258086, "SNB IOAT Ch5" }, 197 { 0x3c268086, "SNB IOAT Ch6" }, 198 { 0x3c278086, "SNB IOAT Ch7" }, 199 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 200 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 201 202 { 0x0e208086, "IVB IOAT Ch0" }, 203 { 0x0e218086, "IVB IOAT Ch1" }, 204 { 0x0e228086, "IVB IOAT Ch2" }, 205 { 0x0e238086, "IVB IOAT Ch3" }, 206 { 0x0e248086, "IVB IOAT Ch4" }, 207 { 0x0e258086, "IVB IOAT Ch5" }, 208 { 0x0e268086, "IVB IOAT Ch6" }, 209 { 0x0e278086, "IVB IOAT Ch7" }, 210 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 211 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 212 213 { 0x2f208086, "HSW IOAT Ch0" }, 214 { 0x2f218086, "HSW IOAT Ch1" }, 215 { 0x2f228086, "HSW IOAT Ch2" }, 216 { 0x2f238086, "HSW IOAT Ch3" }, 217 { 0x2f248086, "HSW IOAT Ch4" }, 218 { 0x2f258086, "HSW IOAT Ch5" }, 219 { 0x2f268086, "HSW IOAT Ch6" }, 220 { 0x2f278086, "HSW IOAT Ch7" }, 221 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 222 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 223 224 { 0x0c508086, "BWD IOAT Ch0" }, 225 { 0x0c518086, "BWD IOAT Ch1" }, 226 { 0x0c528086, "BWD IOAT Ch2" }, 227 { 0x0c538086, "BWD IOAT Ch3" }, 228 229 { 0x6f508086, "BDXDE IOAT Ch0" }, 230 { 0x6f518086, "BDXDE IOAT Ch1" }, 231 { 0x6f528086, "BDXDE IOAT Ch2" }, 232 { 0x6f538086, "BDXDE IOAT Ch3" }, 233 234 { 0x6f208086, "BDX IOAT Ch0" }, 235 { 0x6f218086, "BDX IOAT Ch1" }, 236 { 0x6f228086, "BDX IOAT Ch2" }, 237 { 0x6f238086, "BDX IOAT Ch3" }, 238 { 0x6f248086, "BDX IOAT Ch4" }, 239 { 0x6f258086, "BDX IOAT Ch5" }, 240 { 0x6f268086, "BDX IOAT Ch6" }, 241 { 0x6f278086, "BDX IOAT Ch7" }, 242 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 243 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 244 245 { 0x00000000, NULL } 246 }; 247 248 /* 249 * OS <-> Driver linkage functions 250 */ 251 static int 252 ioat_probe(device_t device) 253 { 254 struct _pcsid *ep; 255 u_int32_t type; 256 257 type = pci_get_devid(device); 258 for (ep = pci_ids; ep->type; ep++) { 259 if (ep->type == type) { 260 device_set_desc(device, ep->desc); 261 return (0); 262 } 263 } 264 return (ENXIO); 265 } 266 267 static int 268 ioat_attach(device_t device) 269 { 270 struct ioat_softc *ioat; 271 int error; 272 273 ioat = DEVICE2SOFTC(device); 274 ioat->device = device; 275 276 error = ioat_map_pci_bar(ioat); 277 if (error != 0) 278 goto err; 279 280 ioat->version = ioat_read_cbver(ioat); 281 if (ioat->version < IOAT_VER_3_0) { 282 error = ENODEV; 283 goto err; 284 } 285 286 error = ioat3_attach(device); 287 if (error != 0) 288 goto err; 289 290 error = pci_enable_busmaster(device); 291 if (error != 0) 292 goto err; 293 294 error = ioat_setup_intr(ioat); 295 if (error != 0) 296 goto err; 297 298 error = ioat_reset_hw(ioat); 299 if (error != 0) 300 goto err; 301 302 ioat_process_events(ioat); 303 ioat_setup_sysctl(device); 304 305 ioat->chan_idx = ioat_channel_index; 306 ioat_channel[ioat_channel_index++] = ioat; 307 ioat_test_attach(); 308 309 err: 310 if (error != 0) 311 ioat_detach(device); 312 return (error); 313 } 314 315 static int 316 ioat_detach(device_t device) 317 { 318 struct ioat_softc *ioat; 319 320 ioat = DEVICE2SOFTC(device); 321 322 ioat_test_detach(); 323 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 324 325 mtx_lock(IOAT_REFLK); 326 ioat->quiescing = TRUE; 327 ioat->destroying = TRUE; 328 wakeup(&ioat->quiescing); 329 wakeup(&ioat->resetting); 330 331 ioat_channel[ioat->chan_idx] = NULL; 332 333 ioat_drain_locked(ioat); 334 mtx_unlock(IOAT_REFLK); 335 336 ioat_teardown_intr(ioat); 337 callout_drain(&ioat->poll_timer); 338 callout_drain(&ioat->shrink_timer); 339 340 pci_disable_busmaster(device); 341 342 if (ioat->pci_resource != NULL) 343 bus_release_resource(device, SYS_RES_MEMORY, 344 ioat->pci_resource_id, ioat->pci_resource); 345 346 if (ioat->ring != NULL) 347 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 348 349 if (ioat->comp_update != NULL) { 350 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 351 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 352 ioat->comp_update_map); 353 bus_dma_tag_destroy(ioat->comp_update_tag); 354 } 355 356 bus_dma_tag_destroy(ioat->hw_desc_tag); 357 358 return (0); 359 } 360 361 static int 362 ioat_teardown_intr(struct ioat_softc *ioat) 363 { 364 365 if (ioat->tag != NULL) 366 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 367 368 if (ioat->res != NULL) 369 bus_release_resource(ioat->device, SYS_RES_IRQ, 370 rman_get_rid(ioat->res), ioat->res); 371 372 pci_release_msi(ioat->device); 373 return (0); 374 } 375 376 static int 377 ioat_start_channel(struct ioat_softc *ioat) 378 { 379 struct ioat_dma_hw_descriptor *hw_desc; 380 struct ioat_descriptor *desc; 381 struct bus_dmadesc *dmadesc; 382 uint64_t status; 383 uint32_t chanerr; 384 int i; 385 386 ioat_acquire(&ioat->dmaengine); 387 388 /* Submit 'NULL' operation manually to avoid quiescing flag */ 389 desc = ioat_get_ring_entry(ioat, ioat->head); 390 dmadesc = &desc->bus_dmadesc; 391 hw_desc = desc->u.dma; 392 393 dmadesc->callback_fn = NULL; 394 dmadesc->callback_arg = NULL; 395 396 hw_desc->u.control_raw = 0; 397 hw_desc->u.control_generic.op = IOAT_OP_COPY; 398 hw_desc->u.control_generic.completion_update = 1; 399 hw_desc->size = 8; 400 hw_desc->src_addr = 0; 401 hw_desc->dest_addr = 0; 402 hw_desc->u.control.null = 1; 403 404 ioat_submit_single(ioat); 405 ioat_release(&ioat->dmaengine); 406 407 for (i = 0; i < 100; i++) { 408 DELAY(1); 409 status = ioat_get_chansts(ioat); 410 if (is_ioat_idle(status)) 411 return (0); 412 } 413 414 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 415 ioat_log_message(0, "could not start channel: " 416 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 417 IOAT_CHANERR_STR); 418 return (ENXIO); 419 } 420 421 /* 422 * Initialize Hardware 423 */ 424 static int 425 ioat3_attach(device_t device) 426 { 427 struct ioat_softc *ioat; 428 struct ioat_descriptor **ring; 429 struct ioat_descriptor *next; 430 struct ioat_dma_hw_descriptor *dma_hw_desc; 431 int i, num_descriptors; 432 int error; 433 uint8_t xfercap; 434 435 error = 0; 436 ioat = DEVICE2SOFTC(device); 437 ioat->capabilities = ioat_read_dmacapability(ioat); 438 439 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 440 IOAT_DMACAP_STR); 441 442 xfercap = ioat_read_xfercap(ioat); 443 ioat->max_xfer_size = 1 << xfercap; 444 445 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 446 IOAT_INTRDELAY_SUPPORTED) != 0; 447 if (ioat->intrdelay_supported) 448 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 449 450 /* TODO: need to check DCA here if we ever do XOR/PQ */ 451 452 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 453 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 454 callout_init(&ioat->poll_timer, 1); 455 callout_init(&ioat->shrink_timer, 1); 456 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 457 458 /* Establish lock order for Witness */ 459 mtx_lock(&ioat->submit_lock); 460 mtx_lock(&ioat->cleanup_lock); 461 mtx_unlock(&ioat->cleanup_lock); 462 mtx_unlock(&ioat->submit_lock); 463 464 ioat->is_resize_pending = FALSE; 465 ioat->is_submitter_processing = FALSE; 466 ioat->is_completion_pending = FALSE; 467 ioat->is_reset_pending = FALSE; 468 ioat->is_channel_running = FALSE; 469 470 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 471 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 472 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 473 &ioat->comp_update_tag); 474 475 error = bus_dmamem_alloc(ioat->comp_update_tag, 476 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 477 if (ioat->comp_update == NULL) 478 return (ENOMEM); 479 480 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 481 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 482 0); 483 if (error != 0) 484 return (error); 485 486 ioat->ring_size_order = IOAT_MIN_ORDER; 487 488 num_descriptors = 1 << ioat->ring_size_order; 489 490 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 491 BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL, 492 sizeof(struct ioat_dma_hw_descriptor), 1, 493 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 494 &ioat->hw_desc_tag); 495 496 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 497 M_ZERO | M_WAITOK); 498 499 ring = ioat->ring; 500 for (i = 0; i < num_descriptors; i++) { 501 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 502 if (ring[i] == NULL) 503 return (ENOMEM); 504 505 ring[i]->id = i; 506 } 507 508 for (i = 0; i < num_descriptors - 1; i++) { 509 next = ring[i + 1]; 510 dma_hw_desc = ring[i]->u.dma; 511 512 dma_hw_desc->next = next->hw_desc_bus_addr; 513 } 514 515 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 516 517 ioat->head = ioat->hw_head = 0; 518 ioat->tail = 0; 519 ioat->last_seen = 0; 520 *ioat->comp_update = 0; 521 return (0); 522 } 523 524 static int 525 ioat_map_pci_bar(struct ioat_softc *ioat) 526 { 527 528 ioat->pci_resource_id = PCIR_BAR(0); 529 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 530 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 531 532 if (ioat->pci_resource == NULL) { 533 ioat_log_message(0, "unable to allocate pci resource\n"); 534 return (ENODEV); 535 } 536 537 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 538 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 539 return (0); 540 } 541 542 static void 543 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 544 { 545 struct ioat_softc *ioat = arg; 546 547 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 548 ioat->comp_update_bus_addr = seg[0].ds_addr; 549 } 550 551 static void 552 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 553 { 554 bus_addr_t *baddr; 555 556 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 557 baddr = arg; 558 *baddr = segs->ds_addr; 559 } 560 561 /* 562 * Interrupt setup and handlers 563 */ 564 static int 565 ioat_setup_intr(struct ioat_softc *ioat) 566 { 567 uint32_t num_vectors; 568 int error; 569 boolean_t use_msix; 570 boolean_t force_legacy_interrupts; 571 572 use_msix = FALSE; 573 force_legacy_interrupts = FALSE; 574 575 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 576 num_vectors = 1; 577 pci_alloc_msix(ioat->device, &num_vectors); 578 if (num_vectors == 1) 579 use_msix = TRUE; 580 } 581 582 if (use_msix) { 583 ioat->rid = 1; 584 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 585 &ioat->rid, RF_ACTIVE); 586 } else { 587 ioat->rid = 0; 588 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 589 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 590 } 591 if (ioat->res == NULL) { 592 ioat_log_message(0, "bus_alloc_resource failed\n"); 593 return (ENOMEM); 594 } 595 596 ioat->tag = NULL; 597 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 598 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 599 if (error != 0) { 600 ioat_log_message(0, "bus_setup_intr failed\n"); 601 return (error); 602 } 603 604 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 605 return (0); 606 } 607 608 static boolean_t 609 ioat_model_resets_msix(struct ioat_softc *ioat) 610 { 611 u_int32_t pciid; 612 613 pciid = pci_get_devid(ioat->device); 614 switch (pciid) { 615 /* BWD: */ 616 case 0x0c508086: 617 case 0x0c518086: 618 case 0x0c528086: 619 case 0x0c538086: 620 /* BDXDE: */ 621 case 0x6f508086: 622 case 0x6f518086: 623 case 0x6f528086: 624 case 0x6f538086: 625 return (TRUE); 626 } 627 628 return (FALSE); 629 } 630 631 static void 632 ioat_interrupt_handler(void *arg) 633 { 634 struct ioat_softc *ioat = arg; 635 636 ioat->stats.interrupts++; 637 ioat_process_events(ioat); 638 } 639 640 static int 641 chanerr_to_errno(uint32_t chanerr) 642 { 643 644 if (chanerr == 0) 645 return (0); 646 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 647 return (EFAULT); 648 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 649 return (EIO); 650 /* This one is probably our fault: */ 651 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 652 return (EIO); 653 return (EIO); 654 } 655 656 static void 657 ioat_process_events(struct ioat_softc *ioat) 658 { 659 struct ioat_descriptor *desc; 660 struct bus_dmadesc *dmadesc; 661 uint64_t comp_update, status; 662 uint32_t completed, chanerr; 663 boolean_t pending; 664 int error; 665 666 CTR0(KTR_IOAT, __func__); 667 668 mtx_lock(&ioat->cleanup_lock); 669 670 /* 671 * Don't run while the hardware is being reset. Reset is responsible 672 * for blocking new work and draining & completing existing work, so 673 * there is nothing to do until new work is queued after reset anyway. 674 */ 675 if (ioat->resetting_cleanup) { 676 mtx_unlock(&ioat->cleanup_lock); 677 return; 678 } 679 680 completed = 0; 681 comp_update = *ioat->comp_update; 682 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 683 684 if (status == ioat->last_seen) { 685 /* 686 * If we landed in process_events and nothing has been 687 * completed, check for a timeout due to channel halt. 688 */ 689 comp_update = ioat_get_chansts(ioat); 690 goto out; 691 } 692 693 while (1) { 694 desc = ioat_get_ring_entry(ioat, ioat->tail); 695 dmadesc = &desc->bus_dmadesc; 696 CTR3(KTR_IOAT, "completing desc %u ok cb %p(%p)", ioat->tail, 697 dmadesc->callback_fn, dmadesc->callback_arg); 698 699 if (dmadesc->callback_fn != NULL) 700 dmadesc->callback_fn(dmadesc->callback_arg, 0); 701 702 completed++; 703 ioat->tail++; 704 if (desc->hw_desc_bus_addr == status) 705 break; 706 707 KASSERT(ioat_get_active(ioat) > 0, ("overrunning ring t:%u " 708 "h:%u st:0x%016lx last_seen:%016lx completed:%u\n", 709 ioat->tail, ioat->head, comp_update, ioat->last_seen, 710 completed)); 711 } 712 713 ioat->last_seen = desc->hw_desc_bus_addr; 714 ioat->stats.descriptors_processed += completed; 715 716 out: 717 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 718 719 /* Perform a racy check first; only take the locks if it passes. */ 720 pending = (ioat_get_active(ioat) != 0); 721 if (!pending && ioat->is_completion_pending) { 722 mtx_unlock(&ioat->cleanup_lock); 723 mtx_lock(&ioat->submit_lock); 724 mtx_lock(&ioat->cleanup_lock); 725 726 pending = (ioat_get_active(ioat) != 0); 727 if (!pending && ioat->is_completion_pending) { 728 ioat->is_completion_pending = FALSE; 729 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 730 ioat_shrink_timer_callback, ioat); 731 callout_stop(&ioat->poll_timer); 732 } 733 mtx_unlock(&ioat->submit_lock); 734 } 735 mtx_unlock(&ioat->cleanup_lock); 736 737 if (pending) 738 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 739 ioat); 740 741 if (completed != 0) { 742 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 743 wakeup(&ioat->tail); 744 } 745 746 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 747 return; 748 749 ioat->stats.channel_halts++; 750 751 /* 752 * Fatal programming error on this DMA channel. Flush any outstanding 753 * work with error status and restart the engine. 754 */ 755 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 756 mtx_lock(&ioat->submit_lock); 757 mtx_lock(&ioat->cleanup_lock); 758 ioat->quiescing = TRUE; 759 760 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 761 ioat_halted_debug(ioat, chanerr); 762 ioat->stats.last_halt_chanerr = chanerr; 763 764 while (ioat_get_active(ioat) > 0) { 765 desc = ioat_get_ring_entry(ioat, ioat->tail); 766 dmadesc = &desc->bus_dmadesc; 767 CTR3(KTR_IOAT, "completing desc %u err cb %p(%p)", ioat->tail, 768 dmadesc->callback_fn, dmadesc->callback_arg); 769 770 if (dmadesc->callback_fn != NULL) 771 dmadesc->callback_fn(dmadesc->callback_arg, 772 chanerr_to_errno(chanerr)); 773 774 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 775 ioat->tail++; 776 ioat->stats.descriptors_processed++; 777 ioat->stats.descriptors_error++; 778 } 779 780 /* Clear error status */ 781 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 782 783 mtx_unlock(&ioat->cleanup_lock); 784 mtx_unlock(&ioat->submit_lock); 785 786 ioat_log_message(0, "Resetting channel to recover from error\n"); 787 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 788 KASSERT(error == 0, 789 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 790 } 791 792 static void 793 ioat_reset_hw_task(void *ctx, int pending __unused) 794 { 795 struct ioat_softc *ioat; 796 int error; 797 798 ioat = ctx; 799 ioat_log_message(1, "%s: Resetting channel\n", __func__); 800 801 error = ioat_reset_hw(ioat); 802 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 803 (void)error; 804 } 805 806 /* 807 * User API functions 808 */ 809 unsigned 810 ioat_get_nchannels(void) 811 { 812 813 return (ioat_channel_index); 814 } 815 816 bus_dmaengine_t 817 ioat_get_dmaengine(uint32_t index, int flags) 818 { 819 struct ioat_softc *ioat; 820 821 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 822 ("invalid flags: 0x%08x", flags)); 823 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 824 ("invalid wait | nowait")); 825 826 if (index >= ioat_channel_index) 827 return (NULL); 828 829 ioat = ioat_channel[index]; 830 if (ioat == NULL || ioat->destroying) 831 return (NULL); 832 833 if (ioat->quiescing) { 834 if ((flags & M_NOWAIT) != 0) 835 return (NULL); 836 837 mtx_lock(IOAT_REFLK); 838 while (ioat->quiescing && !ioat->destroying) 839 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 840 mtx_unlock(IOAT_REFLK); 841 842 if (ioat->destroying) 843 return (NULL); 844 } 845 846 /* 847 * There's a race here between the quiescing check and HW reset or 848 * module destroy. 849 */ 850 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 851 } 852 853 void 854 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 855 { 856 struct ioat_softc *ioat; 857 858 ioat = to_ioat_softc(dmaengine); 859 ioat_put(ioat, IOAT_DMAENGINE_REF); 860 } 861 862 int 863 ioat_get_hwversion(bus_dmaengine_t dmaengine) 864 { 865 struct ioat_softc *ioat; 866 867 ioat = to_ioat_softc(dmaengine); 868 return (ioat->version); 869 } 870 871 size_t 872 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 873 { 874 struct ioat_softc *ioat; 875 876 ioat = to_ioat_softc(dmaengine); 877 return (ioat->max_xfer_size); 878 } 879 880 uint32_t 881 ioat_get_capabilities(bus_dmaengine_t dmaengine) 882 { 883 struct ioat_softc *ioat; 884 885 ioat = to_ioat_softc(dmaengine); 886 return (ioat->capabilities); 887 } 888 889 int 890 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 891 { 892 struct ioat_softc *ioat; 893 894 ioat = to_ioat_softc(dmaengine); 895 if (!ioat->intrdelay_supported) 896 return (ENODEV); 897 if (delay > ioat->intrdelay_max) 898 return (ERANGE); 899 900 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 901 ioat->cached_intrdelay = 902 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 903 return (0); 904 } 905 906 uint16_t 907 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 908 { 909 struct ioat_softc *ioat; 910 911 ioat = to_ioat_softc(dmaengine); 912 return (ioat->intrdelay_max); 913 } 914 915 void 916 ioat_acquire(bus_dmaengine_t dmaengine) 917 { 918 struct ioat_softc *ioat; 919 920 ioat = to_ioat_softc(dmaengine); 921 mtx_lock(&ioat->submit_lock); 922 CTR0(KTR_IOAT, __func__); 923 } 924 925 int 926 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 927 { 928 struct ioat_softc *ioat; 929 int error; 930 931 ioat = to_ioat_softc(dmaengine); 932 ioat_acquire(dmaengine); 933 934 error = ioat_reserve_space(ioat, n, mflags); 935 if (error != 0) 936 ioat_release(dmaengine); 937 return (error); 938 } 939 940 void 941 ioat_release(bus_dmaengine_t dmaengine) 942 { 943 struct ioat_softc *ioat; 944 945 ioat = to_ioat_softc(dmaengine); 946 CTR0(KTR_IOAT, __func__); 947 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 948 mtx_unlock(&ioat->submit_lock); 949 } 950 951 static struct ioat_descriptor * 952 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 953 uint32_t size, uint64_t src, uint64_t dst, 954 bus_dmaengine_callback_t callback_fn, void *callback_arg, 955 uint32_t flags) 956 { 957 struct ioat_generic_hw_descriptor *hw_desc; 958 struct ioat_descriptor *desc; 959 int mflags; 960 961 mtx_assert(&ioat->submit_lock, MA_OWNED); 962 963 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 964 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 965 if ((flags & DMA_NO_WAIT) != 0) 966 mflags = M_NOWAIT; 967 else 968 mflags = M_WAITOK; 969 970 if (size > ioat->max_xfer_size) { 971 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 972 __func__, ioat->max_xfer_size, (unsigned)size); 973 return (NULL); 974 } 975 976 if (ioat_reserve_space(ioat, 1, mflags) != 0) 977 return (NULL); 978 979 desc = ioat_get_ring_entry(ioat, ioat->head); 980 hw_desc = desc->u.generic; 981 982 hw_desc->u.control_raw = 0; 983 hw_desc->u.control_generic.op = op; 984 hw_desc->u.control_generic.completion_update = 1; 985 986 if ((flags & DMA_INT_EN) != 0) 987 hw_desc->u.control_generic.int_enable = 1; 988 if ((flags & DMA_FENCE) != 0) 989 hw_desc->u.control_generic.fence = 1; 990 991 hw_desc->size = size; 992 hw_desc->src_addr = src; 993 hw_desc->dest_addr = dst; 994 995 desc->bus_dmadesc.callback_fn = callback_fn; 996 desc->bus_dmadesc.callback_arg = callback_arg; 997 return (desc); 998 } 999 1000 struct bus_dmadesc * 1001 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1002 void *callback_arg, uint32_t flags) 1003 { 1004 struct ioat_dma_hw_descriptor *hw_desc; 1005 struct ioat_descriptor *desc; 1006 struct ioat_softc *ioat; 1007 1008 CTR0(KTR_IOAT, __func__); 1009 ioat = to_ioat_softc(dmaengine); 1010 1011 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1012 callback_arg, flags); 1013 if (desc == NULL) 1014 return (NULL); 1015 1016 hw_desc = desc->u.dma; 1017 hw_desc->u.control.null = 1; 1018 ioat_submit_single(ioat); 1019 return (&desc->bus_dmadesc); 1020 } 1021 1022 struct bus_dmadesc * 1023 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1024 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1025 void *callback_arg, uint32_t flags) 1026 { 1027 struct ioat_dma_hw_descriptor *hw_desc; 1028 struct ioat_descriptor *desc; 1029 struct ioat_softc *ioat; 1030 1031 CTR0(KTR_IOAT, __func__); 1032 ioat = to_ioat_softc(dmaengine); 1033 1034 if (((src | dst) & (0xffffull << 48)) != 0) { 1035 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1036 __func__); 1037 return (NULL); 1038 } 1039 1040 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1041 callback_arg, flags); 1042 if (desc == NULL) 1043 return (NULL); 1044 1045 hw_desc = desc->u.dma; 1046 if (g_ioat_debug_level >= 3) 1047 dump_descriptor(hw_desc); 1048 1049 ioat_submit_single(ioat); 1050 return (&desc->bus_dmadesc); 1051 } 1052 1053 struct bus_dmadesc * 1054 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1055 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1056 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1057 { 1058 struct ioat_dma_hw_descriptor *hw_desc; 1059 struct ioat_descriptor *desc; 1060 struct ioat_softc *ioat; 1061 1062 CTR0(KTR_IOAT, __func__); 1063 ioat = to_ioat_softc(dmaengine); 1064 1065 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 1066 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1067 __func__); 1068 return (NULL); 1069 } 1070 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 1071 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 1072 __func__); 1073 return (NULL); 1074 } 1075 1076 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 1077 callback_fn, callback_arg, flags); 1078 if (desc == NULL) 1079 return (NULL); 1080 1081 hw_desc = desc->u.dma; 1082 if (src2 != src1 + PAGE_SIZE) { 1083 hw_desc->u.control.src_page_break = 1; 1084 hw_desc->next_src_addr = src2; 1085 } 1086 if (dst2 != dst1 + PAGE_SIZE) { 1087 hw_desc->u.control.dest_page_break = 1; 1088 hw_desc->next_dest_addr = dst2; 1089 } 1090 1091 if (g_ioat_debug_level >= 3) 1092 dump_descriptor(hw_desc); 1093 1094 ioat_submit_single(ioat); 1095 return (&desc->bus_dmadesc); 1096 } 1097 1098 struct bus_dmadesc * 1099 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1100 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1101 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1102 { 1103 struct ioat_crc32_hw_descriptor *hw_desc; 1104 struct ioat_descriptor *desc; 1105 struct ioat_softc *ioat; 1106 uint32_t teststore; 1107 uint8_t op; 1108 1109 CTR0(KTR_IOAT, __func__); 1110 ioat = to_ioat_softc(dmaengine); 1111 1112 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1113 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1114 __func__); 1115 return (NULL); 1116 } 1117 if (((src | dst) & (0xffffffull << 40)) != 0) { 1118 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1119 __func__); 1120 return (NULL); 1121 } 1122 teststore = (flags & _DMA_CRC_TESTSTORE); 1123 if (teststore == _DMA_CRC_TESTSTORE) { 1124 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1125 return (NULL); 1126 } 1127 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1128 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1129 __func__); 1130 return (NULL); 1131 } 1132 1133 switch (teststore) { 1134 case DMA_CRC_STORE: 1135 op = IOAT_OP_MOVECRC_STORE; 1136 break; 1137 case DMA_CRC_TEST: 1138 op = IOAT_OP_MOVECRC_TEST; 1139 break; 1140 default: 1141 KASSERT(teststore == 0, ("bogus")); 1142 op = IOAT_OP_MOVECRC; 1143 break; 1144 } 1145 1146 if ((flags & DMA_CRC_INLINE) == 0 && 1147 (crcptr & (0xffffffull << 40)) != 0) { 1148 ioat_log_message(0, 1149 "%s: High 24 bits of crcptr invalid\n", __func__); 1150 return (NULL); 1151 } 1152 1153 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1154 callback_arg, flags & ~_DMA_CRC_FLAGS); 1155 if (desc == NULL) 1156 return (NULL); 1157 1158 hw_desc = desc->u.crc32; 1159 1160 if ((flags & DMA_CRC_INLINE) == 0) 1161 hw_desc->crc_address = crcptr; 1162 else 1163 hw_desc->u.control.crc_location = 1; 1164 1165 if (initialseed != NULL) { 1166 hw_desc->u.control.use_seed = 1; 1167 hw_desc->seed = *initialseed; 1168 } 1169 1170 if (g_ioat_debug_level >= 3) 1171 dump_descriptor(hw_desc); 1172 1173 ioat_submit_single(ioat); 1174 return (&desc->bus_dmadesc); 1175 } 1176 1177 struct bus_dmadesc * 1178 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1179 uint32_t *initialseed, bus_addr_t crcptr, 1180 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1181 { 1182 struct ioat_crc32_hw_descriptor *hw_desc; 1183 struct ioat_descriptor *desc; 1184 struct ioat_softc *ioat; 1185 uint32_t teststore; 1186 uint8_t op; 1187 1188 CTR0(KTR_IOAT, __func__); 1189 ioat = to_ioat_softc(dmaengine); 1190 1191 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1192 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1193 __func__); 1194 return (NULL); 1195 } 1196 if ((src & (0xffffffull << 40)) != 0) { 1197 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1198 __func__); 1199 return (NULL); 1200 } 1201 teststore = (flags & _DMA_CRC_TESTSTORE); 1202 if (teststore == _DMA_CRC_TESTSTORE) { 1203 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1204 return (NULL); 1205 } 1206 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1207 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1208 __func__); 1209 return (NULL); 1210 } 1211 1212 switch (teststore) { 1213 case DMA_CRC_STORE: 1214 op = IOAT_OP_CRC_STORE; 1215 break; 1216 case DMA_CRC_TEST: 1217 op = IOAT_OP_CRC_TEST; 1218 break; 1219 default: 1220 KASSERT(teststore == 0, ("bogus")); 1221 op = IOAT_OP_CRC; 1222 break; 1223 } 1224 1225 if ((flags & DMA_CRC_INLINE) == 0 && 1226 (crcptr & (0xffffffull << 40)) != 0) { 1227 ioat_log_message(0, 1228 "%s: High 24 bits of crcptr invalid\n", __func__); 1229 return (NULL); 1230 } 1231 1232 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1233 callback_arg, flags & ~_DMA_CRC_FLAGS); 1234 if (desc == NULL) 1235 return (NULL); 1236 1237 hw_desc = desc->u.crc32; 1238 1239 if ((flags & DMA_CRC_INLINE) == 0) 1240 hw_desc->crc_address = crcptr; 1241 else 1242 hw_desc->u.control.crc_location = 1; 1243 1244 if (initialseed != NULL) { 1245 hw_desc->u.control.use_seed = 1; 1246 hw_desc->seed = *initialseed; 1247 } 1248 1249 if (g_ioat_debug_level >= 3) 1250 dump_descriptor(hw_desc); 1251 1252 ioat_submit_single(ioat); 1253 return (&desc->bus_dmadesc); 1254 } 1255 1256 struct bus_dmadesc * 1257 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1258 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1259 uint32_t flags) 1260 { 1261 struct ioat_fill_hw_descriptor *hw_desc; 1262 struct ioat_descriptor *desc; 1263 struct ioat_softc *ioat; 1264 1265 CTR0(KTR_IOAT, __func__); 1266 ioat = to_ioat_softc(dmaengine); 1267 1268 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1269 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1270 __func__); 1271 return (NULL); 1272 } 1273 1274 if ((dst & (0xffffull << 48)) != 0) { 1275 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1276 __func__); 1277 return (NULL); 1278 } 1279 1280 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1281 callback_fn, callback_arg, flags); 1282 if (desc == NULL) 1283 return (NULL); 1284 1285 hw_desc = desc->u.fill; 1286 if (g_ioat_debug_level >= 3) 1287 dump_descriptor(hw_desc); 1288 1289 ioat_submit_single(ioat); 1290 return (&desc->bus_dmadesc); 1291 } 1292 1293 /* 1294 * Ring Management 1295 */ 1296 static inline uint32_t 1297 ioat_get_active(struct ioat_softc *ioat) 1298 { 1299 1300 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1301 } 1302 1303 static inline uint32_t 1304 ioat_get_ring_space(struct ioat_softc *ioat) 1305 { 1306 1307 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1308 } 1309 1310 static struct ioat_descriptor * 1311 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 1312 { 1313 struct ioat_generic_hw_descriptor *hw_desc; 1314 struct ioat_descriptor *desc; 1315 int error, busdmaflag; 1316 1317 error = ENOMEM; 1318 hw_desc = NULL; 1319 1320 if ((mflags & M_WAITOK) != 0) 1321 busdmaflag = BUS_DMA_WAITOK; 1322 else 1323 busdmaflag = BUS_DMA_NOWAIT; 1324 1325 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1326 if (desc == NULL) 1327 goto out; 1328 1329 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1330 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1331 if (hw_desc == NULL) 1332 goto out; 1333 1334 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1335 desc->u.generic = hw_desc; 1336 1337 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1338 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1339 busdmaflag); 1340 if (error) 1341 goto out; 1342 1343 out: 1344 if (error) { 1345 ioat_free_ring_entry(ioat, desc); 1346 return (NULL); 1347 } 1348 return (desc); 1349 } 1350 1351 static void 1352 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1353 { 1354 1355 if (desc == NULL) 1356 return; 1357 1358 if (desc->u.generic) 1359 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1360 ioat->hw_desc_map); 1361 free(desc, M_IOAT); 1362 } 1363 1364 /* 1365 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1366 * for 'num_descs'. 1367 * 1368 * If mflags contains M_WAITOK, blocks until enough space is available. 1369 * 1370 * Returns zero on success, or an errno on error. If num_descs is beyond the 1371 * maximum ring size, returns EINVAl; if allocation would block and mflags 1372 * contains M_NOWAIT, returns EAGAIN. 1373 * 1374 * Must be called with the submit_lock held; returns with the lock held. The 1375 * lock may be dropped to allocate the ring. 1376 * 1377 * (The submit_lock is needed to add any entries to the ring, so callers are 1378 * assured enough room is available.) 1379 */ 1380 static int 1381 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1382 { 1383 struct ioat_descriptor **new_ring; 1384 uint32_t order; 1385 boolean_t dug; 1386 int error; 1387 1388 mtx_assert(&ioat->submit_lock, MA_OWNED); 1389 error = 0; 1390 dug = FALSE; 1391 1392 if (num_descs < 1 || num_descs >= (1 << IOAT_MAX_ORDER)) { 1393 error = EINVAL; 1394 goto out; 1395 } 1396 1397 for (;;) { 1398 if (ioat->quiescing) { 1399 error = ENXIO; 1400 goto out; 1401 } 1402 1403 if (ioat_get_ring_space(ioat) >= num_descs) 1404 goto out; 1405 1406 if (!dug && !ioat->is_submitter_processing && 1407 (1 << ioat->ring_size_order) > num_descs) { 1408 ioat->is_submitter_processing = TRUE; 1409 mtx_unlock(&ioat->submit_lock); 1410 1411 ioat_process_events(ioat); 1412 1413 mtx_lock(&ioat->submit_lock); 1414 dug = TRUE; 1415 KASSERT(ioat->is_submitter_processing == TRUE, 1416 ("is_submitter_processing")); 1417 ioat->is_submitter_processing = FALSE; 1418 wakeup(&ioat->tail); 1419 continue; 1420 } 1421 1422 order = ioat->ring_size_order; 1423 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1424 if ((mflags & M_WAITOK) != 0) { 1425 msleep(&ioat->tail, &ioat->submit_lock, 0, 1426 "ioat_rsz", 0); 1427 continue; 1428 } 1429 1430 error = EAGAIN; 1431 break; 1432 } 1433 1434 ioat->is_resize_pending = TRUE; 1435 for (;;) { 1436 mtx_unlock(&ioat->submit_lock); 1437 1438 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1439 TRUE, mflags); 1440 1441 mtx_lock(&ioat->submit_lock); 1442 KASSERT(ioat->ring_size_order == order, 1443 ("is_resize_pending should protect order")); 1444 1445 if (new_ring == NULL) { 1446 KASSERT((mflags & M_WAITOK) == 0, 1447 ("allocation failed")); 1448 error = EAGAIN; 1449 break; 1450 } 1451 1452 error = ring_grow(ioat, order, new_ring); 1453 if (error == 0) 1454 break; 1455 } 1456 ioat->is_resize_pending = FALSE; 1457 wakeup(&ioat->tail); 1458 if (error) 1459 break; 1460 } 1461 1462 out: 1463 mtx_assert(&ioat->submit_lock, MA_OWNED); 1464 KASSERT(!ioat->quiescing || error == ENXIO, 1465 ("reserved during quiesce")); 1466 return (error); 1467 } 1468 1469 static struct ioat_descriptor ** 1470 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1471 int mflags) 1472 { 1473 struct ioat_descriptor **ring; 1474 uint32_t i; 1475 int error; 1476 1477 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1478 1479 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1480 if (ring == NULL) 1481 return (NULL); 1482 1483 if (need_dscr) { 1484 error = ENOMEM; 1485 for (i = size / 2; i < size; i++) { 1486 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1487 if (ring[i] == NULL) 1488 goto out; 1489 ring[i]->id = i; 1490 } 1491 } 1492 error = 0; 1493 1494 out: 1495 if (error != 0 && ring != NULL) { 1496 ioat_free_ring(ioat, size, ring); 1497 ring = NULL; 1498 } 1499 return (ring); 1500 } 1501 1502 static void 1503 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1504 struct ioat_descriptor **ring) 1505 { 1506 uint32_t i; 1507 1508 for (i = 0; i < size; i++) { 1509 if (ring[i] != NULL) 1510 ioat_free_ring_entry(ioat, ring[i]); 1511 } 1512 free(ring, M_IOAT); 1513 } 1514 1515 static struct ioat_descriptor * 1516 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1517 { 1518 1519 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1520 } 1521 1522 static int 1523 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1524 struct ioat_descriptor **newring) 1525 { 1526 struct ioat_descriptor *tmp, *next; 1527 struct ioat_dma_hw_descriptor *hw; 1528 uint32_t oldsize, newsize, head, tail, i, end; 1529 int error; 1530 1531 CTR0(KTR_IOAT, __func__); 1532 1533 mtx_assert(&ioat->submit_lock, MA_OWNED); 1534 1535 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1536 error = EINVAL; 1537 goto out; 1538 } 1539 1540 oldsize = (1 << oldorder); 1541 newsize = (1 << (oldorder + 1)); 1542 1543 mtx_lock(&ioat->cleanup_lock); 1544 1545 head = ioat->head & (oldsize - 1); 1546 tail = ioat->tail & (oldsize - 1); 1547 1548 /* Copy old descriptors to new ring */ 1549 for (i = 0; i < oldsize; i++) 1550 newring[i] = ioat->ring[i]; 1551 1552 /* 1553 * If head has wrapped but tail hasn't, we must swap some descriptors 1554 * around so that tail can increment directly to head. 1555 */ 1556 if (head < tail) { 1557 for (i = 0; i <= head; i++) { 1558 tmp = newring[oldsize + i]; 1559 1560 newring[oldsize + i] = newring[i]; 1561 newring[oldsize + i]->id = oldsize + i; 1562 1563 newring[i] = tmp; 1564 newring[i]->id = i; 1565 } 1566 head += oldsize; 1567 } 1568 1569 KASSERT(head >= tail, ("invariants")); 1570 1571 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1572 if (head < oldsize) { 1573 i = oldsize - 1; 1574 end = newsize; 1575 } else { 1576 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1577 i = head; 1578 end = newsize + (head - oldsize) + 1; 1579 } 1580 1581 /* 1582 * Fix up hardware ring, being careful not to trample the active 1583 * section (tail -> head). 1584 */ 1585 for (; i < end; i++) { 1586 KASSERT((i & (newsize - 1)) < tail || 1587 (i & (newsize - 1)) >= head, ("trampling snake")); 1588 1589 next = newring[(i + 1) & (newsize - 1)]; 1590 hw = newring[i & (newsize - 1)]->u.dma; 1591 hw->next = next->hw_desc_bus_addr; 1592 } 1593 1594 #ifdef INVARIANTS 1595 for (i = 0; i < newsize; i++) { 1596 next = newring[(i + 1) & (newsize - 1)]; 1597 hw = newring[i & (newsize - 1)]->u.dma; 1598 1599 KASSERT(hw->next == next->hw_desc_bus_addr, 1600 ("mismatch at i:%u (oldsize:%u); next=%p nextaddr=0x%lx" 1601 " (tail:%u)", i, oldsize, next, next->hw_desc_bus_addr, 1602 tail)); 1603 } 1604 #endif 1605 1606 free(ioat->ring, M_IOAT); 1607 ioat->ring = newring; 1608 ioat->ring_size_order = oldorder + 1; 1609 ioat->tail = tail; 1610 ioat->head = head; 1611 error = 0; 1612 1613 mtx_unlock(&ioat->cleanup_lock); 1614 out: 1615 if (error) 1616 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1617 return (error); 1618 } 1619 1620 static int 1621 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1622 struct ioat_descriptor **newring) 1623 { 1624 struct ioat_dma_hw_descriptor *hw; 1625 struct ioat_descriptor *ent, *next; 1626 uint32_t oldsize, newsize, current_idx, new_idx, i; 1627 int error; 1628 1629 CTR0(KTR_IOAT, __func__); 1630 1631 mtx_assert(&ioat->submit_lock, MA_OWNED); 1632 1633 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1634 error = EINVAL; 1635 goto out_unlocked; 1636 } 1637 1638 oldsize = (1 << oldorder); 1639 newsize = (1 << (oldorder - 1)); 1640 1641 mtx_lock(&ioat->cleanup_lock); 1642 1643 /* Can't shrink below current active set! */ 1644 if (ioat_get_active(ioat) >= newsize) { 1645 error = ENOMEM; 1646 goto out; 1647 } 1648 1649 /* 1650 * Copy current descriptors to the new ring, dropping the removed 1651 * descriptors. 1652 */ 1653 for (i = 0; i < newsize; i++) { 1654 current_idx = (ioat->tail + i) & (oldsize - 1); 1655 new_idx = (ioat->tail + i) & (newsize - 1); 1656 1657 newring[new_idx] = ioat->ring[current_idx]; 1658 newring[new_idx]->id = new_idx; 1659 } 1660 1661 /* Free deleted descriptors */ 1662 for (i = newsize; i < oldsize; i++) { 1663 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1664 ioat_free_ring_entry(ioat, ent); 1665 } 1666 1667 /* Fix up hardware ring. */ 1668 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1669 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1670 hw->next = next->hw_desc_bus_addr; 1671 1672 #ifdef INVARIANTS 1673 for (i = 0; i < newsize; i++) { 1674 next = newring[(i + 1) & (newsize - 1)]; 1675 hw = newring[i & (newsize - 1)]->u.dma; 1676 1677 KASSERT(hw->next == next->hw_desc_bus_addr, 1678 ("mismatch at i:%u (newsize:%u); next=%p nextaddr=0x%lx " 1679 "(tail:%u)", i, newsize, next, next->hw_desc_bus_addr, 1680 ioat->tail)); 1681 } 1682 #endif 1683 1684 free(ioat->ring, M_IOAT); 1685 ioat->ring = newring; 1686 ioat->ring_size_order = oldorder - 1; 1687 error = 0; 1688 1689 out: 1690 mtx_unlock(&ioat->cleanup_lock); 1691 out_unlocked: 1692 if (error) 1693 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1694 return (error); 1695 } 1696 1697 static void 1698 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1699 { 1700 struct ioat_descriptor *desc; 1701 1702 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1703 IOAT_CHANERR_STR); 1704 if (chanerr == 0) 1705 return; 1706 1707 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1708 1709 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1710 dump_descriptor(desc->u.raw); 1711 1712 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1713 dump_descriptor(desc->u.raw); 1714 } 1715 1716 static void 1717 ioat_poll_timer_callback(void *arg) 1718 { 1719 struct ioat_softc *ioat; 1720 1721 ioat = arg; 1722 ioat_log_message(3, "%s\n", __func__); 1723 1724 ioat_process_events(ioat); 1725 } 1726 1727 static void 1728 ioat_shrink_timer_callback(void *arg) 1729 { 1730 struct ioat_descriptor **newring; 1731 struct ioat_softc *ioat; 1732 uint32_t order; 1733 1734 ioat = arg; 1735 ioat_log_message(1, "%s\n", __func__); 1736 1737 /* Slowly scale the ring down if idle. */ 1738 mtx_lock(&ioat->submit_lock); 1739 1740 /* Don't run while the hardware is being reset. */ 1741 if (ioat->resetting) { 1742 mtx_unlock(&ioat->submit_lock); 1743 return; 1744 } 1745 1746 order = ioat->ring_size_order; 1747 if (ioat->is_completion_pending || ioat->is_resize_pending || 1748 order == IOAT_MIN_ORDER) { 1749 mtx_unlock(&ioat->submit_lock); 1750 goto out; 1751 } 1752 ioat->is_resize_pending = TRUE; 1753 mtx_unlock(&ioat->submit_lock); 1754 1755 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1756 M_NOWAIT); 1757 1758 mtx_lock(&ioat->submit_lock); 1759 KASSERT(ioat->ring_size_order == order, 1760 ("resize_pending protects order")); 1761 1762 if (newring != NULL && !ioat->is_completion_pending) 1763 ring_shrink(ioat, order, newring); 1764 else if (newring != NULL) 1765 ioat_free_ring(ioat, (1 << (order - 1)), newring); 1766 1767 ioat->is_resize_pending = FALSE; 1768 mtx_unlock(&ioat->submit_lock); 1769 1770 out: 1771 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1772 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 1773 ioat_shrink_timer_callback, ioat); 1774 } 1775 1776 /* 1777 * Support Functions 1778 */ 1779 static void 1780 ioat_submit_single(struct ioat_softc *ioat) 1781 { 1782 1783 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1784 atomic_add_rel_int(&ioat->head, 1); 1785 atomic_add_rel_int(&ioat->hw_head, 1); 1786 1787 if (!ioat->is_completion_pending) { 1788 ioat->is_completion_pending = TRUE; 1789 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 1790 ioat); 1791 callout_stop(&ioat->shrink_timer); 1792 } 1793 1794 ioat->stats.descriptors_submitted++; 1795 } 1796 1797 static int 1798 ioat_reset_hw(struct ioat_softc *ioat) 1799 { 1800 uint64_t status; 1801 uint32_t chanerr; 1802 unsigned timeout; 1803 int error; 1804 1805 CTR0(KTR_IOAT, __func__); 1806 1807 mtx_lock(IOAT_REFLK); 1808 while (ioat->resetting && !ioat->destroying) 1809 msleep(&ioat->resetting, IOAT_REFLK, 0, "IRH_drain", 0); 1810 if (ioat->destroying) { 1811 mtx_unlock(IOAT_REFLK); 1812 return (ENXIO); 1813 } 1814 ioat->resetting = TRUE; 1815 1816 ioat->quiescing = TRUE; 1817 ioat_drain_locked(ioat); 1818 mtx_unlock(IOAT_REFLK); 1819 1820 /* 1821 * Suspend ioat_process_events while the hardware and softc are in an 1822 * indeterminate state. 1823 */ 1824 mtx_lock(&ioat->cleanup_lock); 1825 ioat->resetting_cleanup = TRUE; 1826 mtx_unlock(&ioat->cleanup_lock); 1827 1828 status = ioat_get_chansts(ioat); 1829 if (is_ioat_active(status) || is_ioat_idle(status)) 1830 ioat_suspend(ioat); 1831 1832 /* Wait at most 20 ms */ 1833 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1834 timeout < 20; timeout++) { 1835 DELAY(1000); 1836 status = ioat_get_chansts(ioat); 1837 } 1838 if (timeout == 20) { 1839 error = ETIMEDOUT; 1840 goto out; 1841 } 1842 1843 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1844 1845 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1846 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1847 1848 /* 1849 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1850 * that can cause stability issues for IOAT v3. 1851 */ 1852 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1853 4); 1854 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1855 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1856 1857 /* 1858 * BDXDE and BWD models reset MSI-X registers on device reset. 1859 * Save/restore their contents manually. 1860 */ 1861 if (ioat_model_resets_msix(ioat)) { 1862 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1863 pci_save_state(ioat->device); 1864 } 1865 1866 ioat_reset(ioat); 1867 1868 /* Wait at most 20 ms */ 1869 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1870 DELAY(1000); 1871 if (timeout == 20) { 1872 error = ETIMEDOUT; 1873 goto out; 1874 } 1875 1876 if (ioat_model_resets_msix(ioat)) { 1877 ioat_log_message(1, "device resets registers; restored\n"); 1878 pci_restore_state(ioat->device); 1879 } 1880 1881 /* Reset attempts to return the hardware to "halted." */ 1882 status = ioat_get_chansts(ioat); 1883 if (is_ioat_active(status) || is_ioat_idle(status)) { 1884 /* So this really shouldn't happen... */ 1885 ioat_log_message(0, "Device is active after a reset?\n"); 1886 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1887 error = 0; 1888 goto out; 1889 } 1890 1891 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1892 if (chanerr != 0) { 1893 mtx_lock(&ioat->cleanup_lock); 1894 ioat_halted_debug(ioat, chanerr); 1895 mtx_unlock(&ioat->cleanup_lock); 1896 error = EIO; 1897 goto out; 1898 } 1899 1900 /* 1901 * Bring device back online after reset. Writing CHAINADDR brings the 1902 * device back to active. 1903 * 1904 * The internal ring counter resets to zero, so we have to start over 1905 * at zero as well. 1906 */ 1907 ioat->tail = ioat->head = ioat->hw_head = 0; 1908 ioat->last_seen = 0; 1909 *ioat->comp_update = 0; 1910 1911 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1912 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1913 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1914 error = 0; 1915 1916 out: 1917 /* 1918 * Resume completions now that ring state is consistent. 1919 * ioat_start_channel will add a pending completion and if we are still 1920 * blocking completions, we may livelock. 1921 */ 1922 mtx_lock(&ioat->cleanup_lock); 1923 ioat->resetting_cleanup = FALSE; 1924 mtx_unlock(&ioat->cleanup_lock); 1925 1926 /* Enqueues a null operation and ensures it completes. */ 1927 if (error == 0) 1928 error = ioat_start_channel(ioat); 1929 1930 /* Unblock submission of new work */ 1931 mtx_lock(IOAT_REFLK); 1932 ioat->quiescing = FALSE; 1933 wakeup(&ioat->quiescing); 1934 1935 ioat->resetting = FALSE; 1936 wakeup(&ioat->resetting); 1937 mtx_unlock(IOAT_REFLK); 1938 1939 return (error); 1940 } 1941 1942 static int 1943 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1944 { 1945 struct ioat_softc *ioat; 1946 struct sbuf sb; 1947 uint64_t status; 1948 int error; 1949 1950 ioat = arg1; 1951 1952 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1953 1954 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1955 switch (status) { 1956 case IOAT_CHANSTS_ACTIVE: 1957 sbuf_printf(&sb, "ACTIVE"); 1958 break; 1959 case IOAT_CHANSTS_IDLE: 1960 sbuf_printf(&sb, "IDLE"); 1961 break; 1962 case IOAT_CHANSTS_SUSPENDED: 1963 sbuf_printf(&sb, "SUSPENDED"); 1964 break; 1965 case IOAT_CHANSTS_HALTED: 1966 sbuf_printf(&sb, "HALTED"); 1967 break; 1968 case IOAT_CHANSTS_ARMED: 1969 sbuf_printf(&sb, "ARMED"); 1970 break; 1971 default: 1972 sbuf_printf(&sb, "UNKNOWN"); 1973 break; 1974 } 1975 error = sbuf_finish(&sb); 1976 sbuf_delete(&sb); 1977 1978 if (error != 0 || req->newptr == NULL) 1979 return (error); 1980 return (EINVAL); 1981 } 1982 1983 static int 1984 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1985 { 1986 struct ioat_softc *ioat; 1987 struct sbuf sb; 1988 #define PRECISION "1" 1989 const uintmax_t factor = 10; 1990 uintmax_t rate; 1991 int error; 1992 1993 ioat = arg1; 1994 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1995 1996 if (ioat->stats.interrupts == 0) { 1997 sbuf_printf(&sb, "NaN"); 1998 goto out; 1999 } 2000 rate = ioat->stats.descriptors_processed * factor / 2001 ioat->stats.interrupts; 2002 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 2003 rate % factor); 2004 #undef PRECISION 2005 out: 2006 error = sbuf_finish(&sb); 2007 sbuf_delete(&sb); 2008 if (error != 0 || req->newptr == NULL) 2009 return (error); 2010 return (EINVAL); 2011 } 2012 2013 static int 2014 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 2015 { 2016 struct ioat_softc *ioat; 2017 int error, arg; 2018 2019 ioat = arg1; 2020 2021 arg = 0; 2022 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 2023 if (error != 0 || req->newptr == NULL) 2024 return (error); 2025 2026 error = SYSCTL_IN(req, &arg, sizeof(arg)); 2027 if (error != 0) 2028 return (error); 2029 2030 if (arg != 0) 2031 error = ioat_reset_hw(ioat); 2032 2033 return (error); 2034 } 2035 2036 static void 2037 dump_descriptor(void *hw_desc) 2038 { 2039 int i, j; 2040 2041 for (i = 0; i < 2; i++) { 2042 for (j = 0; j < 8; j++) 2043 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 2044 printf("\n"); 2045 } 2046 } 2047 2048 static void 2049 ioat_setup_sysctl(device_t device) 2050 { 2051 struct sysctl_oid_list *par, *statpar, *state, *hammer; 2052 struct sysctl_ctx_list *ctx; 2053 struct sysctl_oid *tree, *tmp; 2054 struct ioat_softc *ioat; 2055 2056 ioat = DEVICE2SOFTC(device); 2057 ctx = device_get_sysctl_ctx(device); 2058 tree = device_get_sysctl_tree(device); 2059 par = SYSCTL_CHILDREN(tree); 2060 2061 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 2062 &ioat->version, 0, "HW version (0xMM form)"); 2063 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 2064 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 2065 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 2066 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 2067 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 2068 &ioat->intrdelay_max, 0, 2069 "Maximum configurable INTRDELAY on this channel (microseconds)"); 2070 2071 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 2072 "IOAT channel internal state"); 2073 state = SYSCTL_CHILDREN(tmp); 2074 2075 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 2076 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 2077 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 2078 0, "SW descriptor head pointer index"); 2079 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 2080 0, "SW descriptor tail pointer index"); 2081 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 2082 &ioat->hw_head, 0, "HW DMACOUNT"); 2083 2084 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 2085 ioat->comp_update, "HW addr of last completion"); 2086 2087 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 2088 &ioat->is_resize_pending, 0, "resize pending"); 2089 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 2090 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 2091 "submitter processing"); 2092 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 2093 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 2094 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 2095 &ioat->is_reset_pending, 0, "reset pending"); 2096 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 2097 &ioat->is_channel_running, 0, "channel running"); 2098 2099 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 2100 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 2101 "String of the channel status"); 2102 2103 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 2104 &ioat->cached_intrdelay, 0, 2105 "Current INTRDELAY on this channel (cached, microseconds)"); 2106 2107 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 2108 "Big hammers (mostly for testing)"); 2109 hammer = SYSCTL_CHILDREN(tmp); 2110 2111 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 2112 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 2113 "Set to non-zero to reset the hardware"); 2114 2115 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 2116 "IOAT channel statistics"); 2117 statpar = SYSCTL_CHILDREN(tmp); 2118 2119 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 2120 &ioat->stats.interrupts, 2121 "Number of interrupts processed on this channel"); 2122 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 2123 &ioat->stats.descriptors_processed, 2124 "Number of descriptors processed on this channel"); 2125 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 2126 &ioat->stats.descriptors_submitted, 2127 "Number of descriptors submitted to this channel"); 2128 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 2129 &ioat->stats.descriptors_error, 2130 "Number of descriptors failed by channel errors"); 2131 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 2132 &ioat->stats.channel_halts, 0, 2133 "Number of times the channel has halted"); 2134 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 2135 &ioat->stats.last_halt_chanerr, 0, 2136 "The raw CHANERR when the channel was last halted"); 2137 2138 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 2139 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 2140 "Descriptors per interrupt"); 2141 } 2142 2143 static inline struct ioat_softc * 2144 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2145 { 2146 uint32_t old; 2147 2148 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2149 2150 old = atomic_fetchadd_32(&ioat->refcnt, 1); 2151 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 2152 2153 #ifdef INVARIANTS 2154 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 2155 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 2156 #endif 2157 2158 return (ioat); 2159 } 2160 2161 static inline void 2162 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2163 { 2164 2165 _ioat_putn(ioat, n, kind, FALSE); 2166 } 2167 2168 static inline void 2169 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2170 { 2171 2172 _ioat_putn(ioat, n, kind, TRUE); 2173 } 2174 2175 static inline void 2176 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 2177 boolean_t locked) 2178 { 2179 uint32_t old; 2180 2181 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2182 2183 if (n == 0) 2184 return; 2185 2186 #ifdef INVARIANTS 2187 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 2188 KASSERT(old >= n, ("refcnt kind underflow")); 2189 #endif 2190 2191 /* Skip acquiring the lock if resulting refcnt > 0. */ 2192 for (;;) { 2193 old = ioat->refcnt; 2194 if (old <= n) 2195 break; 2196 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 2197 return; 2198 } 2199 2200 if (locked) 2201 mtx_assert(IOAT_REFLK, MA_OWNED); 2202 else 2203 mtx_lock(IOAT_REFLK); 2204 2205 old = atomic_fetchadd_32(&ioat->refcnt, -n); 2206 KASSERT(old >= n, ("refcnt error")); 2207 2208 if (old == n) 2209 wakeup(IOAT_REFLK); 2210 if (!locked) 2211 mtx_unlock(IOAT_REFLK); 2212 } 2213 2214 static inline void 2215 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2216 { 2217 2218 ioat_putn(ioat, 1, kind); 2219 } 2220 2221 static void 2222 ioat_drain_locked(struct ioat_softc *ioat) 2223 { 2224 2225 mtx_assert(IOAT_REFLK, MA_OWNED); 2226 while (ioat->refcnt > 0) 2227 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 2228 } 2229 2230 #ifdef DDB 2231 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 2232 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 2233 DB_SHOW_COMMAND(ioat, db_show_ioat) 2234 { 2235 struct ioat_softc *sc; 2236 unsigned idx; 2237 2238 if (!have_addr) 2239 goto usage; 2240 idx = (unsigned)addr; 2241 if (idx >= ioat_channel_index) 2242 goto usage; 2243 2244 sc = ioat_channel[idx]; 2245 db_printf("ioat softc at %p\n", sc); 2246 if (sc == NULL) 2247 return; 2248 2249 db_printf(" version: %d\n", sc->version); 2250 db_printf(" chan_idx: %u\n", sc->chan_idx); 2251 db_printf(" submit_lock: "); 2252 db_show_lock(&sc->submit_lock); 2253 2254 db_printf(" capabilities: %b\n", (int)sc->capabilities, 2255 IOAT_DMACAP_STR); 2256 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 2257 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 2258 2259 db_printf(" poll_timer:\n"); 2260 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 2261 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 2262 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 2263 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 2264 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 2265 2266 db_printf(" shrink_timer:\n"); 2267 db_printf(" c_time: %ju\n", (uintmax_t)sc->shrink_timer.c_time); 2268 db_printf(" c_arg: %p\n", sc->shrink_timer.c_arg); 2269 db_printf(" c_func: %p\n", sc->shrink_timer.c_func); 2270 db_printf(" c_lock: %p\n", sc->shrink_timer.c_lock); 2271 db_printf(" c_flags: 0x%x\n", (unsigned)sc->shrink_timer.c_flags); 2272 2273 db_printf(" quiescing: %d\n", (int)sc->quiescing); 2274 db_printf(" destroying: %d\n", (int)sc->destroying); 2275 db_printf(" is_resize_pending: %d\n", (int)sc->is_resize_pending); 2276 db_printf(" is_submitter_processing: %d\n", 2277 (int)sc->is_submitter_processing); 2278 db_printf(" is_completion_pending: %d\n", (int)sc->is_completion_pending); 2279 db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending); 2280 db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running); 2281 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 2282 db_printf(" resetting: %d\n", (int)sc->resetting); 2283 2284 db_printf(" head: %u\n", sc->head); 2285 db_printf(" tail: %u\n", sc->tail); 2286 db_printf(" hw_head: %u\n", sc->hw_head); 2287 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2288 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2289 db_printf(" ring: %p\n", sc->ring); 2290 2291 db_printf(" ring[%u] (tail):\n", sc->tail % 2292 (1 << sc->ring_size_order)); 2293 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 2294 db_printf(" addr: 0x%lx\n", 2295 ioat_get_ring_entry(sc, sc->tail)->hw_desc_bus_addr); 2296 db_printf(" next: 0x%lx\n", 2297 ioat_get_ring_entry(sc, sc->tail)->u.generic->next); 2298 2299 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 2300 (1 << sc->ring_size_order)); 2301 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 2302 db_printf(" addr: 0x%lx\n", 2303 ioat_get_ring_entry(sc, sc->head - 1)->hw_desc_bus_addr); 2304 db_printf(" next: 0x%lx\n", 2305 ioat_get_ring_entry(sc, sc->head - 1)->u.generic->next); 2306 2307 db_printf(" ring[%u] (head):\n", (sc->head) % 2308 (1 << sc->ring_size_order)); 2309 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2310 db_printf(" addr: 0x%lx\n", 2311 ioat_get_ring_entry(sc, sc->head)->hw_desc_bus_addr); 2312 db_printf(" next: 0x%lx\n", 2313 ioat_get_ring_entry(sc, sc->head)->u.generic->next); 2314 2315 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2316 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2317 == ioat_get_ring_entry(sc, idx)->hw_desc_bus_addr) 2318 db_printf(" ring[%u] == hardware tail\n", idx); 2319 2320 db_printf(" cleanup_lock: "); 2321 db_show_lock(&sc->cleanup_lock); 2322 2323 db_printf(" refcnt: %u\n", sc->refcnt); 2324 #ifdef INVARIANTS 2325 CTASSERT(IOAT_NUM_REF_KINDS == 2); 2326 db_printf(" refkinds: [ENG=%u, DESCR=%u]\n", sc->refkinds[0], 2327 sc->refkinds[1]); 2328 #endif 2329 db_printf(" stats:\n"); 2330 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2331 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2332 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2333 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2334 2335 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2336 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2337 2338 if (db_pager_quit) 2339 return; 2340 2341 db_printf(" hw status:\n"); 2342 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2343 db_printf(" chanctrl: 0x%x\n", 2344 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2345 db_printf(" chancmd: 0x%x\n", 2346 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2347 db_printf(" dmacount: 0x%x\n", 2348 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2349 db_printf(" chainaddr: 0x%lx\n", 2350 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2351 db_printf(" chancmp: 0x%lx\n", 2352 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2353 db_printf(" chanerr: %b\n", 2354 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2355 return; 2356 usage: 2357 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2358 return; 2359 } 2360 #endif /* DDB */ 2361