1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/ioccom.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/sbuf.h> 42 #include <sys/sysctl.h> 43 #include <sys/taskqueue.h> 44 #include <sys/time.h> 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <machine/bus.h> 48 #include <machine/resource.h> 49 #include <machine/stdarg.h> 50 51 #include "ioat.h" 52 #include "ioat_hw.h" 53 #include "ioat_internal.h" 54 55 #define IOAT_INTR_TIMO (hz / 10) 56 #define IOAT_REFLK (&ioat->submit_lock) 57 58 static int ioat_probe(device_t device); 59 static int ioat_attach(device_t device); 60 static int ioat_detach(device_t device); 61 static int ioat_setup_intr(struct ioat_softc *ioat); 62 static int ioat_teardown_intr(struct ioat_softc *ioat); 63 static int ioat3_attach(device_t device); 64 static int ioat_start_channel(struct ioat_softc *ioat); 65 static int ioat_map_pci_bar(struct ioat_softc *ioat); 66 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 67 int error); 68 static void ioat_interrupt_handler(void *arg); 69 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 70 static int chanerr_to_errno(uint32_t); 71 static void ioat_process_events(struct ioat_softc *ioat); 72 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 73 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 74 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 75 struct ioat_descriptor **); 76 static void ioat_free_ring_entry(struct ioat_softc *ioat, 77 struct ioat_descriptor *desc); 78 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 79 int mflags); 80 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 81 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 82 uint32_t index); 83 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 84 uint32_t size, boolean_t need_dscr, int mflags); 85 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 86 struct ioat_descriptor **); 87 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 88 struct ioat_descriptor **); 89 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 90 static void ioat_timer_callback(void *arg); 91 static void dump_descriptor(void *hw_desc); 92 static void ioat_submit_single(struct ioat_softc *ioat); 93 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 94 int error); 95 static int ioat_reset_hw(struct ioat_softc *ioat); 96 static void ioat_reset_hw_task(void *, int); 97 static void ioat_setup_sysctl(device_t device); 98 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 99 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 100 enum ioat_ref_kind); 101 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 102 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 103 enum ioat_ref_kind, boolean_t); 104 static inline void ioat_putn(struct ioat_softc *, uint32_t, 105 enum ioat_ref_kind); 106 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 107 enum ioat_ref_kind); 108 static void ioat_drain_locked(struct ioat_softc *); 109 110 #define ioat_log_message(v, ...) do { \ 111 if ((v) <= g_ioat_debug_level) { \ 112 device_printf(ioat->device, __VA_ARGS__); \ 113 } \ 114 } while (0) 115 116 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 117 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 118 119 static int g_force_legacy_interrupts; 120 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 121 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 122 123 int g_ioat_debug_level = 0; 124 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 125 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 126 127 /* 128 * OS <-> Driver interface structures 129 */ 130 static device_method_t ioat_pci_methods[] = { 131 /* Device interface */ 132 DEVMETHOD(device_probe, ioat_probe), 133 DEVMETHOD(device_attach, ioat_attach), 134 DEVMETHOD(device_detach, ioat_detach), 135 { 0, 0 } 136 }; 137 138 static driver_t ioat_pci_driver = { 139 "ioat", 140 ioat_pci_methods, 141 sizeof(struct ioat_softc), 142 }; 143 144 static devclass_t ioat_devclass; 145 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 146 MODULE_VERSION(ioat, 1); 147 148 /* 149 * Private data structures 150 */ 151 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 152 static int ioat_channel_index = 0; 153 SYSCTL_INT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 154 "Number of IOAT channels attached"); 155 156 static struct _pcsid 157 { 158 u_int32_t type; 159 const char *desc; 160 } pci_ids[] = { 161 { 0x34308086, "TBG IOAT Ch0" }, 162 { 0x34318086, "TBG IOAT Ch1" }, 163 { 0x34328086, "TBG IOAT Ch2" }, 164 { 0x34338086, "TBG IOAT Ch3" }, 165 { 0x34298086, "TBG IOAT Ch4" }, 166 { 0x342a8086, "TBG IOAT Ch5" }, 167 { 0x342b8086, "TBG IOAT Ch6" }, 168 { 0x342c8086, "TBG IOAT Ch7" }, 169 170 { 0x37108086, "JSF IOAT Ch0" }, 171 { 0x37118086, "JSF IOAT Ch1" }, 172 { 0x37128086, "JSF IOAT Ch2" }, 173 { 0x37138086, "JSF IOAT Ch3" }, 174 { 0x37148086, "JSF IOAT Ch4" }, 175 { 0x37158086, "JSF IOAT Ch5" }, 176 { 0x37168086, "JSF IOAT Ch6" }, 177 { 0x37178086, "JSF IOAT Ch7" }, 178 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 179 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 180 181 { 0x3c208086, "SNB IOAT Ch0" }, 182 { 0x3c218086, "SNB IOAT Ch1" }, 183 { 0x3c228086, "SNB IOAT Ch2" }, 184 { 0x3c238086, "SNB IOAT Ch3" }, 185 { 0x3c248086, "SNB IOAT Ch4" }, 186 { 0x3c258086, "SNB IOAT Ch5" }, 187 { 0x3c268086, "SNB IOAT Ch6" }, 188 { 0x3c278086, "SNB IOAT Ch7" }, 189 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 190 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 191 192 { 0x0e208086, "IVB IOAT Ch0" }, 193 { 0x0e218086, "IVB IOAT Ch1" }, 194 { 0x0e228086, "IVB IOAT Ch2" }, 195 { 0x0e238086, "IVB IOAT Ch3" }, 196 { 0x0e248086, "IVB IOAT Ch4" }, 197 { 0x0e258086, "IVB IOAT Ch5" }, 198 { 0x0e268086, "IVB IOAT Ch6" }, 199 { 0x0e278086, "IVB IOAT Ch7" }, 200 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 201 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 202 203 { 0x2f208086, "HSW IOAT Ch0" }, 204 { 0x2f218086, "HSW IOAT Ch1" }, 205 { 0x2f228086, "HSW IOAT Ch2" }, 206 { 0x2f238086, "HSW IOAT Ch3" }, 207 { 0x2f248086, "HSW IOAT Ch4" }, 208 { 0x2f258086, "HSW IOAT Ch5" }, 209 { 0x2f268086, "HSW IOAT Ch6" }, 210 { 0x2f278086, "HSW IOAT Ch7" }, 211 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 212 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 213 214 { 0x0c508086, "BWD IOAT Ch0" }, 215 { 0x0c518086, "BWD IOAT Ch1" }, 216 { 0x0c528086, "BWD IOAT Ch2" }, 217 { 0x0c538086, "BWD IOAT Ch3" }, 218 219 { 0x6f508086, "BDXDE IOAT Ch0" }, 220 { 0x6f518086, "BDXDE IOAT Ch1" }, 221 { 0x6f528086, "BDXDE IOAT Ch2" }, 222 { 0x6f538086, "BDXDE IOAT Ch3" }, 223 224 { 0x6f208086, "BDX IOAT Ch0" }, 225 { 0x6f218086, "BDX IOAT Ch1" }, 226 { 0x6f228086, "BDX IOAT Ch2" }, 227 { 0x6f238086, "BDX IOAT Ch3" }, 228 { 0x6f248086, "BDX IOAT Ch4" }, 229 { 0x6f258086, "BDX IOAT Ch5" }, 230 { 0x6f268086, "BDX IOAT Ch6" }, 231 { 0x6f278086, "BDX IOAT Ch7" }, 232 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 233 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 234 235 { 0x00000000, NULL } 236 }; 237 238 /* 239 * OS <-> Driver linkage functions 240 */ 241 static int 242 ioat_probe(device_t device) 243 { 244 struct _pcsid *ep; 245 u_int32_t type; 246 247 type = pci_get_devid(device); 248 for (ep = pci_ids; ep->type; ep++) { 249 if (ep->type == type) { 250 device_set_desc(device, ep->desc); 251 return (0); 252 } 253 } 254 return (ENXIO); 255 } 256 257 static int 258 ioat_attach(device_t device) 259 { 260 struct ioat_softc *ioat; 261 int error; 262 263 ioat = DEVICE2SOFTC(device); 264 ioat->device = device; 265 266 error = ioat_map_pci_bar(ioat); 267 if (error != 0) 268 goto err; 269 270 ioat->version = ioat_read_cbver(ioat); 271 if (ioat->version < IOAT_VER_3_0) { 272 error = ENODEV; 273 goto err; 274 } 275 276 error = ioat3_attach(device); 277 if (error != 0) 278 goto err; 279 280 error = pci_enable_busmaster(device); 281 if (error != 0) 282 goto err; 283 284 error = ioat_setup_intr(ioat); 285 if (error != 0) 286 goto err; 287 288 error = ioat_reset_hw(ioat); 289 if (error != 0) 290 goto err; 291 292 ioat_process_events(ioat); 293 ioat_setup_sysctl(device); 294 295 ioat->chan_idx = ioat_channel_index; 296 ioat_channel[ioat_channel_index++] = ioat; 297 ioat_test_attach(); 298 299 err: 300 if (error != 0) 301 ioat_detach(device); 302 return (error); 303 } 304 305 static int 306 ioat_detach(device_t device) 307 { 308 struct ioat_softc *ioat; 309 310 ioat = DEVICE2SOFTC(device); 311 312 ioat_test_detach(); 313 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 314 315 mtx_lock(IOAT_REFLK); 316 ioat->quiescing = TRUE; 317 ioat->destroying = TRUE; 318 wakeup(&ioat->quiescing); 319 320 ioat_channel[ioat->chan_idx] = NULL; 321 322 ioat_drain_locked(ioat); 323 mtx_unlock(IOAT_REFLK); 324 325 ioat_teardown_intr(ioat); 326 callout_drain(&ioat->timer); 327 328 pci_disable_busmaster(device); 329 330 if (ioat->pci_resource != NULL) 331 bus_release_resource(device, SYS_RES_MEMORY, 332 ioat->pci_resource_id, ioat->pci_resource); 333 334 if (ioat->ring != NULL) 335 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 336 337 if (ioat->comp_update != NULL) { 338 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 339 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 340 ioat->comp_update_map); 341 bus_dma_tag_destroy(ioat->comp_update_tag); 342 } 343 344 bus_dma_tag_destroy(ioat->hw_desc_tag); 345 346 return (0); 347 } 348 349 static int 350 ioat_teardown_intr(struct ioat_softc *ioat) 351 { 352 353 if (ioat->tag != NULL) 354 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 355 356 if (ioat->res != NULL) 357 bus_release_resource(ioat->device, SYS_RES_IRQ, 358 rman_get_rid(ioat->res), ioat->res); 359 360 pci_release_msi(ioat->device); 361 return (0); 362 } 363 364 static int 365 ioat_start_channel(struct ioat_softc *ioat) 366 { 367 uint64_t status; 368 uint32_t chanerr; 369 int i; 370 371 ioat_acquire(&ioat->dmaengine); 372 ioat_null(&ioat->dmaengine, NULL, NULL, 0); 373 ioat_release(&ioat->dmaengine); 374 375 for (i = 0; i < 100; i++) { 376 DELAY(1); 377 status = ioat_get_chansts(ioat); 378 if (is_ioat_idle(status)) 379 return (0); 380 } 381 382 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 383 ioat_log_message(0, "could not start channel: " 384 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 385 IOAT_CHANERR_STR); 386 return (ENXIO); 387 } 388 389 /* 390 * Initialize Hardware 391 */ 392 static int 393 ioat3_attach(device_t device) 394 { 395 struct ioat_softc *ioat; 396 struct ioat_descriptor **ring; 397 struct ioat_descriptor *next; 398 struct ioat_dma_hw_descriptor *dma_hw_desc; 399 int i, num_descriptors; 400 int error; 401 uint8_t xfercap; 402 403 error = 0; 404 ioat = DEVICE2SOFTC(device); 405 ioat->capabilities = ioat_read_dmacapability(ioat); 406 407 ioat_log_message(1, "Capabilities: %b\n", (int)ioat->capabilities, 408 IOAT_DMACAP_STR); 409 410 xfercap = ioat_read_xfercap(ioat); 411 ioat->max_xfer_size = 1 << xfercap; 412 413 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 414 IOAT_INTRDELAY_SUPPORTED) != 0; 415 if (ioat->intrdelay_supported) 416 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 417 418 /* TODO: need to check DCA here if we ever do XOR/PQ */ 419 420 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 421 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 422 callout_init(&ioat->timer, 1); 423 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 424 425 /* Establish lock order for Witness */ 426 mtx_lock(&ioat->submit_lock); 427 mtx_lock(&ioat->cleanup_lock); 428 mtx_unlock(&ioat->cleanup_lock); 429 mtx_unlock(&ioat->submit_lock); 430 431 ioat->is_resize_pending = FALSE; 432 ioat->is_completion_pending = FALSE; 433 ioat->is_reset_pending = FALSE; 434 ioat->is_channel_running = FALSE; 435 436 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 437 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 438 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 439 &ioat->comp_update_tag); 440 441 error = bus_dmamem_alloc(ioat->comp_update_tag, 442 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 443 if (ioat->comp_update == NULL) 444 return (ENOMEM); 445 446 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 447 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 448 0); 449 if (error != 0) 450 return (error); 451 452 ioat->ring_size_order = IOAT_MIN_ORDER; 453 454 num_descriptors = 1 << ioat->ring_size_order; 455 456 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 457 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 458 sizeof(struct ioat_dma_hw_descriptor), 1, 459 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 460 &ioat->hw_desc_tag); 461 462 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 463 M_ZERO | M_WAITOK); 464 if (ioat->ring == NULL) 465 return (ENOMEM); 466 467 ring = ioat->ring; 468 for (i = 0; i < num_descriptors; i++) { 469 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 470 if (ring[i] == NULL) 471 return (ENOMEM); 472 473 ring[i]->id = i; 474 } 475 476 for (i = 0; i < num_descriptors - 1; i++) { 477 next = ring[i + 1]; 478 dma_hw_desc = ring[i]->u.dma; 479 480 dma_hw_desc->next = next->hw_desc_bus_addr; 481 } 482 483 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 484 485 ioat->head = ioat->hw_head = 0; 486 ioat->tail = 0; 487 ioat->last_seen = 0; 488 return (0); 489 } 490 491 static int 492 ioat_map_pci_bar(struct ioat_softc *ioat) 493 { 494 495 ioat->pci_resource_id = PCIR_BAR(0); 496 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 497 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 498 499 if (ioat->pci_resource == NULL) { 500 ioat_log_message(0, "unable to allocate pci resource\n"); 501 return (ENODEV); 502 } 503 504 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 505 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 506 return (0); 507 } 508 509 static void 510 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 511 { 512 struct ioat_softc *ioat = arg; 513 514 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 515 ioat->comp_update_bus_addr = seg[0].ds_addr; 516 } 517 518 static void 519 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 520 { 521 bus_addr_t *baddr; 522 523 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 524 baddr = arg; 525 *baddr = segs->ds_addr; 526 } 527 528 /* 529 * Interrupt setup and handlers 530 */ 531 static int 532 ioat_setup_intr(struct ioat_softc *ioat) 533 { 534 uint32_t num_vectors; 535 int error; 536 boolean_t use_msix; 537 boolean_t force_legacy_interrupts; 538 539 use_msix = FALSE; 540 force_legacy_interrupts = FALSE; 541 542 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 543 num_vectors = 1; 544 pci_alloc_msix(ioat->device, &num_vectors); 545 if (num_vectors == 1) 546 use_msix = TRUE; 547 } 548 549 if (use_msix) { 550 ioat->rid = 1; 551 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 552 &ioat->rid, RF_ACTIVE); 553 } else { 554 ioat->rid = 0; 555 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 556 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 557 } 558 if (ioat->res == NULL) { 559 ioat_log_message(0, "bus_alloc_resource failed\n"); 560 return (ENOMEM); 561 } 562 563 ioat->tag = NULL; 564 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 565 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 566 if (error != 0) { 567 ioat_log_message(0, "bus_setup_intr failed\n"); 568 return (error); 569 } 570 571 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 572 return (0); 573 } 574 575 static boolean_t 576 ioat_model_resets_msix(struct ioat_softc *ioat) 577 { 578 u_int32_t pciid; 579 580 pciid = pci_get_devid(ioat->device); 581 switch (pciid) { 582 /* BWD: */ 583 case 0x0c508086: 584 case 0x0c518086: 585 case 0x0c528086: 586 case 0x0c538086: 587 /* BDXDE: */ 588 case 0x6f508086: 589 case 0x6f518086: 590 case 0x6f528086: 591 case 0x6f538086: 592 return (TRUE); 593 } 594 595 return (FALSE); 596 } 597 598 static void 599 ioat_interrupt_handler(void *arg) 600 { 601 struct ioat_softc *ioat = arg; 602 603 ioat->stats.interrupts++; 604 ioat_process_events(ioat); 605 } 606 607 static int 608 chanerr_to_errno(uint32_t chanerr) 609 { 610 611 if (chanerr == 0) 612 return (0); 613 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 614 return (EFAULT); 615 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 616 return (EIO); 617 /* This one is probably our fault: */ 618 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 619 return (EIO); 620 return (EIO); 621 } 622 623 static void 624 ioat_process_events(struct ioat_softc *ioat) 625 { 626 struct ioat_descriptor *desc; 627 struct bus_dmadesc *dmadesc; 628 uint64_t comp_update, status; 629 uint32_t completed, chanerr; 630 int error; 631 632 mtx_lock(&ioat->cleanup_lock); 633 634 completed = 0; 635 comp_update = *ioat->comp_update; 636 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 637 638 CTR0(KTR_IOAT, __func__); 639 640 if (status == ioat->last_seen) { 641 /* 642 * If we landed in process_events and nothing has been 643 * completed, check for a timeout due to channel halt. 644 */ 645 comp_update = ioat_get_chansts(ioat); 646 goto out; 647 } 648 649 while (1) { 650 desc = ioat_get_ring_entry(ioat, ioat->tail); 651 dmadesc = &desc->bus_dmadesc; 652 CTR1(KTR_IOAT, "completing desc %d", ioat->tail); 653 654 if (dmadesc->callback_fn != NULL) 655 dmadesc->callback_fn(dmadesc->callback_arg, 0); 656 657 completed++; 658 ioat->tail++; 659 if (desc->hw_desc_bus_addr == status) 660 break; 661 } 662 663 ioat->last_seen = desc->hw_desc_bus_addr; 664 665 if (ioat->head == ioat->tail) { 666 ioat->is_completion_pending = FALSE; 667 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 668 ioat_timer_callback, ioat); 669 } 670 671 ioat->stats.descriptors_processed += completed; 672 673 out: 674 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 675 mtx_unlock(&ioat->cleanup_lock); 676 677 if (completed != 0) { 678 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 679 wakeup(&ioat->tail); 680 } 681 682 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 683 return; 684 685 ioat->stats.channel_halts++; 686 687 /* 688 * Fatal programming error on this DMA channel. Flush any outstanding 689 * work with error status and restart the engine. 690 */ 691 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 692 mtx_lock(&ioat->submit_lock); 693 mtx_lock(&ioat->cleanup_lock); 694 ioat->quiescing = TRUE; 695 696 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 697 ioat_halted_debug(ioat, chanerr); 698 ioat->stats.last_halt_chanerr = chanerr; 699 700 while (ioat_get_active(ioat) > 0) { 701 desc = ioat_get_ring_entry(ioat, ioat->tail); 702 dmadesc = &desc->bus_dmadesc; 703 CTR1(KTR_IOAT, "completing err desc %d", ioat->tail); 704 705 if (dmadesc->callback_fn != NULL) 706 dmadesc->callback_fn(dmadesc->callback_arg, 707 chanerr_to_errno(chanerr)); 708 709 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 710 ioat->tail++; 711 ioat->stats.descriptors_processed++; 712 ioat->stats.descriptors_error++; 713 } 714 715 /* Clear error status */ 716 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 717 718 mtx_unlock(&ioat->cleanup_lock); 719 mtx_unlock(&ioat->submit_lock); 720 721 ioat_log_message(0, "Resetting channel to recover from error\n"); 722 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 723 KASSERT(error == 0, 724 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 725 } 726 727 static void 728 ioat_reset_hw_task(void *ctx, int pending __unused) 729 { 730 struct ioat_softc *ioat; 731 int error; 732 733 ioat = ctx; 734 ioat_log_message(1, "%s: Resetting channel\n", __func__); 735 736 error = ioat_reset_hw(ioat); 737 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 738 (void)error; 739 } 740 741 /* 742 * User API functions 743 */ 744 bus_dmaengine_t 745 ioat_get_dmaengine(uint32_t index, int flags) 746 { 747 struct ioat_softc *ioat; 748 749 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 750 ("invalid flags: 0x%08x", flags)); 751 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 752 ("invalid wait | nowait")); 753 754 if (index >= ioat_channel_index) 755 return (NULL); 756 757 ioat = ioat_channel[index]; 758 if (ioat == NULL || ioat->destroying) 759 return (NULL); 760 761 if (ioat->quiescing) { 762 if ((flags & M_NOWAIT) != 0) 763 return (NULL); 764 765 mtx_lock(IOAT_REFLK); 766 while (ioat->quiescing && !ioat->destroying) 767 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 768 mtx_unlock(IOAT_REFLK); 769 770 if (ioat->destroying) 771 return (NULL); 772 } 773 774 /* 775 * There's a race here between the quiescing check and HW reset or 776 * module destroy. 777 */ 778 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 779 } 780 781 void 782 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 783 { 784 struct ioat_softc *ioat; 785 786 ioat = to_ioat_softc(dmaengine); 787 ioat_put(ioat, IOAT_DMAENGINE_REF); 788 } 789 790 int 791 ioat_get_hwversion(bus_dmaengine_t dmaengine) 792 { 793 struct ioat_softc *ioat; 794 795 ioat = to_ioat_softc(dmaengine); 796 return (ioat->version); 797 } 798 799 size_t 800 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 801 { 802 struct ioat_softc *ioat; 803 804 ioat = to_ioat_softc(dmaengine); 805 return (ioat->max_xfer_size); 806 } 807 808 int 809 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 810 { 811 struct ioat_softc *ioat; 812 813 ioat = to_ioat_softc(dmaengine); 814 if (!ioat->intrdelay_supported) 815 return (ENODEV); 816 if (delay > ioat->intrdelay_max) 817 return (ERANGE); 818 819 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 820 ioat->cached_intrdelay = 821 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 822 return (0); 823 } 824 825 uint16_t 826 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 827 { 828 struct ioat_softc *ioat; 829 830 ioat = to_ioat_softc(dmaengine); 831 return (ioat->intrdelay_max); 832 } 833 834 void 835 ioat_acquire(bus_dmaengine_t dmaengine) 836 { 837 struct ioat_softc *ioat; 838 839 ioat = to_ioat_softc(dmaengine); 840 mtx_lock(&ioat->submit_lock); 841 CTR0(KTR_IOAT, __func__); 842 } 843 844 int 845 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 846 { 847 struct ioat_softc *ioat; 848 int error; 849 850 ioat = to_ioat_softc(dmaengine); 851 ioat_acquire(dmaengine); 852 853 error = ioat_reserve_space(ioat, n, mflags); 854 if (error != 0) 855 ioat_release(dmaengine); 856 return (error); 857 } 858 859 void 860 ioat_release(bus_dmaengine_t dmaengine) 861 { 862 struct ioat_softc *ioat; 863 864 ioat = to_ioat_softc(dmaengine); 865 CTR0(KTR_IOAT, __func__); 866 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 867 mtx_unlock(&ioat->submit_lock); 868 } 869 870 static struct ioat_descriptor * 871 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 872 uint32_t size, uint64_t src, uint64_t dst, 873 bus_dmaengine_callback_t callback_fn, void *callback_arg, 874 uint32_t flags) 875 { 876 struct ioat_generic_hw_descriptor *hw_desc; 877 struct ioat_descriptor *desc; 878 int mflags; 879 880 mtx_assert(&ioat->submit_lock, MA_OWNED); 881 882 KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x", 883 flags & ~DMA_ALL_FLAGS)); 884 if ((flags & DMA_NO_WAIT) != 0) 885 mflags = M_NOWAIT; 886 else 887 mflags = M_WAITOK; 888 889 if (size > ioat->max_xfer_size) { 890 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 891 __func__, ioat->max_xfer_size, (unsigned)size); 892 return (NULL); 893 } 894 895 if (ioat_reserve_space(ioat, 1, mflags) != 0) 896 return (NULL); 897 898 desc = ioat_get_ring_entry(ioat, ioat->head); 899 hw_desc = desc->u.generic; 900 901 hw_desc->u.control_raw = 0; 902 hw_desc->u.control_generic.op = op; 903 hw_desc->u.control_generic.completion_update = 1; 904 905 if ((flags & DMA_INT_EN) != 0) 906 hw_desc->u.control_generic.int_enable = 1; 907 if ((flags & DMA_FENCE) != 0) 908 hw_desc->u.control_generic.fence = 1; 909 910 hw_desc->size = size; 911 hw_desc->src_addr = src; 912 hw_desc->dest_addr = dst; 913 914 desc->bus_dmadesc.callback_fn = callback_fn; 915 desc->bus_dmadesc.callback_arg = callback_arg; 916 return (desc); 917 } 918 919 struct bus_dmadesc * 920 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 921 void *callback_arg, uint32_t flags) 922 { 923 struct ioat_dma_hw_descriptor *hw_desc; 924 struct ioat_descriptor *desc; 925 struct ioat_softc *ioat; 926 927 CTR0(KTR_IOAT, __func__); 928 ioat = to_ioat_softc(dmaengine); 929 930 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 931 callback_arg, flags); 932 if (desc == NULL) 933 return (NULL); 934 935 hw_desc = desc->u.dma; 936 hw_desc->u.control.null = 1; 937 ioat_submit_single(ioat); 938 return (&desc->bus_dmadesc); 939 } 940 941 struct bus_dmadesc * 942 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 943 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 944 void *callback_arg, uint32_t flags) 945 { 946 struct ioat_dma_hw_descriptor *hw_desc; 947 struct ioat_descriptor *desc; 948 struct ioat_softc *ioat; 949 950 CTR0(KTR_IOAT, __func__); 951 ioat = to_ioat_softc(dmaengine); 952 953 if (((src | dst) & (0xffffull << 48)) != 0) { 954 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 955 __func__); 956 return (NULL); 957 } 958 959 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 960 callback_arg, flags); 961 if (desc == NULL) 962 return (NULL); 963 964 hw_desc = desc->u.dma; 965 if (g_ioat_debug_level >= 3) 966 dump_descriptor(hw_desc); 967 968 ioat_submit_single(ioat); 969 return (&desc->bus_dmadesc); 970 } 971 972 struct bus_dmadesc * 973 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 974 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 975 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 976 { 977 struct ioat_dma_hw_descriptor *hw_desc; 978 struct ioat_descriptor *desc; 979 struct ioat_softc *ioat; 980 981 CTR0(KTR_IOAT, __func__); 982 ioat = to_ioat_softc(dmaengine); 983 984 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 985 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 986 __func__); 987 return (NULL); 988 } 989 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 990 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 991 __func__); 992 return (NULL); 993 } 994 995 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 996 callback_fn, callback_arg, flags); 997 if (desc == NULL) 998 return (NULL); 999 1000 hw_desc = desc->u.dma; 1001 if (src2 != src1 + PAGE_SIZE) { 1002 hw_desc->u.control.src_page_break = 1; 1003 hw_desc->next_src_addr = src2; 1004 } 1005 if (dst2 != dst1 + PAGE_SIZE) { 1006 hw_desc->u.control.dest_page_break = 1; 1007 hw_desc->next_dest_addr = dst2; 1008 } 1009 1010 if (g_ioat_debug_level >= 3) 1011 dump_descriptor(hw_desc); 1012 1013 ioat_submit_single(ioat); 1014 return (&desc->bus_dmadesc); 1015 } 1016 1017 struct bus_dmadesc * 1018 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1019 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1020 uint32_t flags) 1021 { 1022 struct ioat_fill_hw_descriptor *hw_desc; 1023 struct ioat_descriptor *desc; 1024 struct ioat_softc *ioat; 1025 1026 CTR0(KTR_IOAT, __func__); 1027 ioat = to_ioat_softc(dmaengine); 1028 1029 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1030 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1031 __func__); 1032 return (NULL); 1033 } 1034 1035 if ((dst & (0xffffull << 48)) != 0) { 1036 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1037 __func__); 1038 return (NULL); 1039 } 1040 1041 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1042 callback_fn, callback_arg, flags); 1043 if (desc == NULL) 1044 return (NULL); 1045 1046 hw_desc = desc->u.fill; 1047 if (g_ioat_debug_level >= 3) 1048 dump_descriptor(hw_desc); 1049 1050 ioat_submit_single(ioat); 1051 return (&desc->bus_dmadesc); 1052 } 1053 1054 /* 1055 * Ring Management 1056 */ 1057 static inline uint32_t 1058 ioat_get_active(struct ioat_softc *ioat) 1059 { 1060 1061 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1062 } 1063 1064 static inline uint32_t 1065 ioat_get_ring_space(struct ioat_softc *ioat) 1066 { 1067 1068 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1069 } 1070 1071 static struct ioat_descriptor * 1072 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 1073 { 1074 struct ioat_generic_hw_descriptor *hw_desc; 1075 struct ioat_descriptor *desc; 1076 int error, busdmaflag; 1077 1078 error = ENOMEM; 1079 hw_desc = NULL; 1080 1081 if ((mflags & M_WAITOK) != 0) 1082 busdmaflag = BUS_DMA_WAITOK; 1083 else 1084 busdmaflag = BUS_DMA_NOWAIT; 1085 1086 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1087 if (desc == NULL) 1088 goto out; 1089 1090 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1091 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1092 if (hw_desc == NULL) 1093 goto out; 1094 1095 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1096 desc->u.generic = hw_desc; 1097 1098 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1099 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1100 busdmaflag); 1101 if (error) 1102 goto out; 1103 1104 out: 1105 if (error) { 1106 ioat_free_ring_entry(ioat, desc); 1107 return (NULL); 1108 } 1109 return (desc); 1110 } 1111 1112 static void 1113 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1114 { 1115 1116 if (desc == NULL) 1117 return; 1118 1119 if (desc->u.generic) 1120 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1121 ioat->hw_desc_map); 1122 free(desc, M_IOAT); 1123 } 1124 1125 /* 1126 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1127 * for 'num_descs'. 1128 * 1129 * If mflags contains M_WAITOK, blocks until enough space is available. 1130 * 1131 * Returns zero on success, or an errno on error. If num_descs is beyond the 1132 * maximum ring size, returns EINVAl; if allocation would block and mflags 1133 * contains M_NOWAIT, returns EAGAIN. 1134 * 1135 * Must be called with the submit_lock held; returns with the lock held. The 1136 * lock may be dropped to allocate the ring. 1137 * 1138 * (The submit_lock is needed to add any entries to the ring, so callers are 1139 * assured enough room is available.) 1140 */ 1141 static int 1142 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1143 { 1144 struct ioat_descriptor **new_ring; 1145 uint32_t order; 1146 int error; 1147 1148 mtx_assert(&ioat->submit_lock, MA_OWNED); 1149 error = 0; 1150 1151 if (num_descs < 1 || num_descs > (1 << IOAT_MAX_ORDER)) { 1152 error = EINVAL; 1153 goto out; 1154 } 1155 if (ioat->quiescing) { 1156 error = ENXIO; 1157 goto out; 1158 } 1159 1160 for (;;) { 1161 if (ioat_get_ring_space(ioat) >= num_descs) 1162 goto out; 1163 1164 order = ioat->ring_size_order; 1165 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1166 if ((mflags & M_WAITOK) != 0) { 1167 msleep(&ioat->tail, &ioat->submit_lock, 0, 1168 "ioat_rsz", 0); 1169 continue; 1170 } 1171 1172 error = EAGAIN; 1173 break; 1174 } 1175 1176 ioat->is_resize_pending = TRUE; 1177 for (;;) { 1178 mtx_unlock(&ioat->submit_lock); 1179 1180 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1181 TRUE, mflags); 1182 1183 mtx_lock(&ioat->submit_lock); 1184 KASSERT(ioat->ring_size_order == order, 1185 ("is_resize_pending should protect order")); 1186 1187 if (new_ring == NULL) { 1188 KASSERT((mflags & M_WAITOK) == 0, 1189 ("allocation failed")); 1190 error = EAGAIN; 1191 break; 1192 } 1193 1194 error = ring_grow(ioat, order, new_ring); 1195 if (error == 0) 1196 break; 1197 } 1198 ioat->is_resize_pending = FALSE; 1199 wakeup(&ioat->tail); 1200 if (error) 1201 break; 1202 } 1203 1204 out: 1205 mtx_assert(&ioat->submit_lock, MA_OWNED); 1206 return (error); 1207 } 1208 1209 static struct ioat_descriptor ** 1210 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1211 int mflags) 1212 { 1213 struct ioat_descriptor **ring; 1214 uint32_t i; 1215 int error; 1216 1217 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1218 1219 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1220 if (ring == NULL) 1221 return (NULL); 1222 1223 if (need_dscr) { 1224 error = ENOMEM; 1225 for (i = size / 2; i < size; i++) { 1226 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1227 if (ring[i] == NULL) 1228 goto out; 1229 ring[i]->id = i; 1230 } 1231 } 1232 error = 0; 1233 1234 out: 1235 if (error != 0 && ring != NULL) { 1236 ioat_free_ring(ioat, size, ring); 1237 ring = NULL; 1238 } 1239 return (ring); 1240 } 1241 1242 static void 1243 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1244 struct ioat_descriptor **ring) 1245 { 1246 uint32_t i; 1247 1248 for (i = 0; i < size; i++) { 1249 if (ring[i] != NULL) 1250 ioat_free_ring_entry(ioat, ring[i]); 1251 } 1252 free(ring, M_IOAT); 1253 } 1254 1255 static struct ioat_descriptor * 1256 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1257 { 1258 1259 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1260 } 1261 1262 static int 1263 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1264 struct ioat_descriptor **newring) 1265 { 1266 struct ioat_descriptor *tmp, *next; 1267 struct ioat_dma_hw_descriptor *hw; 1268 uint32_t oldsize, newsize, head, tail, i, end; 1269 int error; 1270 1271 CTR0(KTR_IOAT, __func__); 1272 1273 mtx_assert(&ioat->submit_lock, MA_OWNED); 1274 1275 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1276 error = EINVAL; 1277 goto out; 1278 } 1279 1280 oldsize = (1 << oldorder); 1281 newsize = (1 << (oldorder + 1)); 1282 1283 mtx_lock(&ioat->cleanup_lock); 1284 1285 head = ioat->head & (oldsize - 1); 1286 tail = ioat->tail & (oldsize - 1); 1287 1288 /* Copy old descriptors to new ring */ 1289 for (i = 0; i < oldsize; i++) 1290 newring[i] = ioat->ring[i]; 1291 1292 /* 1293 * If head has wrapped but tail hasn't, we must swap some descriptors 1294 * around so that tail can increment directly to head. 1295 */ 1296 if (head < tail) { 1297 for (i = 0; i <= head; i++) { 1298 tmp = newring[oldsize + i]; 1299 1300 newring[oldsize + i] = newring[i]; 1301 newring[oldsize + i]->id = oldsize + i; 1302 1303 newring[i] = tmp; 1304 newring[i]->id = i; 1305 } 1306 head += oldsize; 1307 } 1308 1309 KASSERT(head >= tail, ("invariants")); 1310 1311 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1312 if (head < oldsize) { 1313 i = oldsize - 1; 1314 end = newsize; 1315 } else { 1316 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1317 i = head; 1318 end = newsize + (head - oldsize) + 1; 1319 } 1320 1321 /* 1322 * Fix up hardware ring, being careful not to trample the active 1323 * section (tail -> head). 1324 */ 1325 for (; i < end; i++) { 1326 KASSERT((i & (newsize - 1)) < tail || 1327 (i & (newsize - 1)) >= head, ("trampling snake")); 1328 1329 next = newring[(i + 1) & (newsize - 1)]; 1330 hw = newring[i & (newsize - 1)]->u.dma; 1331 hw->next = next->hw_desc_bus_addr; 1332 } 1333 1334 free(ioat->ring, M_IOAT); 1335 ioat->ring = newring; 1336 ioat->ring_size_order = oldorder + 1; 1337 ioat->tail = tail; 1338 ioat->head = head; 1339 error = 0; 1340 1341 mtx_unlock(&ioat->cleanup_lock); 1342 out: 1343 if (error) 1344 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1345 return (error); 1346 } 1347 1348 static int 1349 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1350 struct ioat_descriptor **newring) 1351 { 1352 struct ioat_dma_hw_descriptor *hw; 1353 struct ioat_descriptor *ent, *next; 1354 uint32_t oldsize, newsize, current_idx, new_idx, i; 1355 int error; 1356 1357 CTR0(KTR_IOAT, __func__); 1358 1359 mtx_assert(&ioat->submit_lock, MA_OWNED); 1360 1361 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1362 error = EINVAL; 1363 goto out_unlocked; 1364 } 1365 1366 oldsize = (1 << oldorder); 1367 newsize = (1 << (oldorder - 1)); 1368 1369 mtx_lock(&ioat->cleanup_lock); 1370 1371 /* Can't shrink below current active set! */ 1372 if (ioat_get_active(ioat) >= newsize) { 1373 error = ENOMEM; 1374 goto out; 1375 } 1376 1377 /* 1378 * Copy current descriptors to the new ring, dropping the removed 1379 * descriptors. 1380 */ 1381 for (i = 0; i < newsize; i++) { 1382 current_idx = (ioat->tail + i) & (oldsize - 1); 1383 new_idx = (ioat->tail + i) & (newsize - 1); 1384 1385 newring[new_idx] = ioat->ring[current_idx]; 1386 newring[new_idx]->id = new_idx; 1387 } 1388 1389 /* Free deleted descriptors */ 1390 for (i = newsize; i < oldsize; i++) { 1391 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1392 ioat_free_ring_entry(ioat, ent); 1393 } 1394 1395 /* Fix up hardware ring. */ 1396 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1397 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1398 hw->next = next->hw_desc_bus_addr; 1399 1400 free(ioat->ring, M_IOAT); 1401 ioat->ring = newring; 1402 ioat->ring_size_order = oldorder - 1; 1403 error = 0; 1404 1405 out: 1406 mtx_unlock(&ioat->cleanup_lock); 1407 out_unlocked: 1408 if (error) 1409 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1410 return (error); 1411 } 1412 1413 static void 1414 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1415 { 1416 struct ioat_descriptor *desc; 1417 1418 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1419 IOAT_CHANERR_STR); 1420 if (chanerr == 0) 1421 return; 1422 1423 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1424 1425 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1426 dump_descriptor(desc->u.raw); 1427 1428 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1429 dump_descriptor(desc->u.raw); 1430 } 1431 1432 static void 1433 ioat_timer_callback(void *arg) 1434 { 1435 struct ioat_descriptor **newring; 1436 struct ioat_softc *ioat; 1437 uint32_t order; 1438 1439 ioat = arg; 1440 ioat_log_message(1, "%s\n", __func__); 1441 1442 if (ioat->is_completion_pending) { 1443 ioat_process_events(ioat); 1444 return; 1445 } 1446 1447 /* Slowly scale the ring down if idle. */ 1448 mtx_lock(&ioat->submit_lock); 1449 order = ioat->ring_size_order; 1450 if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) { 1451 mtx_unlock(&ioat->submit_lock); 1452 goto out; 1453 } 1454 ioat->is_resize_pending = TRUE; 1455 mtx_unlock(&ioat->submit_lock); 1456 1457 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1458 M_NOWAIT); 1459 1460 mtx_lock(&ioat->submit_lock); 1461 KASSERT(ioat->ring_size_order == order, 1462 ("resize_pending protects order")); 1463 1464 if (newring != NULL) 1465 ring_shrink(ioat, order, newring); 1466 1467 ioat->is_resize_pending = FALSE; 1468 mtx_unlock(&ioat->submit_lock); 1469 1470 out: 1471 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1472 callout_reset(&ioat->timer, 10 * hz, 1473 ioat_timer_callback, ioat); 1474 } 1475 1476 /* 1477 * Support Functions 1478 */ 1479 static void 1480 ioat_submit_single(struct ioat_softc *ioat) 1481 { 1482 1483 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1484 atomic_add_rel_int(&ioat->head, 1); 1485 atomic_add_rel_int(&ioat->hw_head, 1); 1486 1487 if (!ioat->is_completion_pending) { 1488 ioat->is_completion_pending = TRUE; 1489 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 1490 ioat_timer_callback, ioat); 1491 } 1492 1493 ioat->stats.descriptors_submitted++; 1494 } 1495 1496 static int 1497 ioat_reset_hw(struct ioat_softc *ioat) 1498 { 1499 uint64_t status; 1500 uint32_t chanerr; 1501 unsigned timeout; 1502 int error; 1503 1504 mtx_lock(IOAT_REFLK); 1505 ioat->quiescing = TRUE; 1506 ioat_drain_locked(ioat); 1507 mtx_unlock(IOAT_REFLK); 1508 1509 status = ioat_get_chansts(ioat); 1510 if (is_ioat_active(status) || is_ioat_idle(status)) 1511 ioat_suspend(ioat); 1512 1513 /* Wait at most 20 ms */ 1514 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1515 timeout < 20; timeout++) { 1516 DELAY(1000); 1517 status = ioat_get_chansts(ioat); 1518 } 1519 if (timeout == 20) { 1520 error = ETIMEDOUT; 1521 goto out; 1522 } 1523 1524 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1525 1526 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1527 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1528 1529 /* 1530 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1531 * that can cause stability issues for IOAT v3. 1532 */ 1533 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1534 4); 1535 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1536 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1537 1538 /* 1539 * BDXDE and BWD models reset MSI-X registers on device reset. 1540 * Save/restore their contents manually. 1541 */ 1542 if (ioat_model_resets_msix(ioat)) { 1543 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1544 pci_save_state(ioat->device); 1545 } 1546 1547 ioat_reset(ioat); 1548 1549 /* Wait at most 20 ms */ 1550 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1551 DELAY(1000); 1552 if (timeout == 20) { 1553 error = ETIMEDOUT; 1554 goto out; 1555 } 1556 1557 if (ioat_model_resets_msix(ioat)) { 1558 ioat_log_message(1, "device resets registers; restored\n"); 1559 pci_restore_state(ioat->device); 1560 } 1561 1562 /* Reset attempts to return the hardware to "halted." */ 1563 status = ioat_get_chansts(ioat); 1564 if (is_ioat_active(status) || is_ioat_idle(status)) { 1565 /* So this really shouldn't happen... */ 1566 ioat_log_message(0, "Device is active after a reset?\n"); 1567 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1568 error = 0; 1569 goto out; 1570 } 1571 1572 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1573 if (chanerr != 0) { 1574 mtx_lock(&ioat->cleanup_lock); 1575 ioat_halted_debug(ioat, chanerr); 1576 mtx_unlock(&ioat->cleanup_lock); 1577 error = EIO; 1578 goto out; 1579 } 1580 1581 /* 1582 * Bring device back online after reset. Writing CHAINADDR brings the 1583 * device back to active. 1584 * 1585 * The internal ring counter resets to zero, so we have to start over 1586 * at zero as well. 1587 */ 1588 ioat->tail = ioat->head = ioat->hw_head = 0; 1589 ioat->last_seen = 0; 1590 1591 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1592 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1593 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1594 error = 0; 1595 1596 out: 1597 mtx_lock(IOAT_REFLK); 1598 ioat->quiescing = FALSE; 1599 wakeup(&ioat->quiescing); 1600 mtx_unlock(IOAT_REFLK); 1601 1602 if (error == 0) 1603 error = ioat_start_channel(ioat); 1604 1605 return (error); 1606 } 1607 1608 static int 1609 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1610 { 1611 struct ioat_softc *ioat; 1612 struct sbuf sb; 1613 uint64_t status; 1614 int error; 1615 1616 ioat = arg1; 1617 1618 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1619 1620 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1621 switch (status) { 1622 case IOAT_CHANSTS_ACTIVE: 1623 sbuf_printf(&sb, "ACTIVE"); 1624 break; 1625 case IOAT_CHANSTS_IDLE: 1626 sbuf_printf(&sb, "IDLE"); 1627 break; 1628 case IOAT_CHANSTS_SUSPENDED: 1629 sbuf_printf(&sb, "SUSPENDED"); 1630 break; 1631 case IOAT_CHANSTS_HALTED: 1632 sbuf_printf(&sb, "HALTED"); 1633 break; 1634 case IOAT_CHANSTS_ARMED: 1635 sbuf_printf(&sb, "ARMED"); 1636 break; 1637 default: 1638 sbuf_printf(&sb, "UNKNOWN"); 1639 break; 1640 } 1641 error = sbuf_finish(&sb); 1642 sbuf_delete(&sb); 1643 1644 if (error != 0 || req->newptr == NULL) 1645 return (error); 1646 return (EINVAL); 1647 } 1648 1649 static int 1650 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1651 { 1652 struct ioat_softc *ioat; 1653 struct sbuf sb; 1654 #define PRECISION "1" 1655 const uintmax_t factor = 10; 1656 uintmax_t rate; 1657 int error; 1658 1659 ioat = arg1; 1660 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1661 1662 if (ioat->stats.interrupts == 0) { 1663 sbuf_printf(&sb, "NaN"); 1664 goto out; 1665 } 1666 rate = ioat->stats.descriptors_processed * factor / 1667 ioat->stats.interrupts; 1668 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1669 rate % factor); 1670 #undef PRECISION 1671 out: 1672 error = sbuf_finish(&sb); 1673 sbuf_delete(&sb); 1674 if (error != 0 || req->newptr == NULL) 1675 return (error); 1676 return (EINVAL); 1677 } 1678 1679 static int 1680 sysctl_handle_error(SYSCTL_HANDLER_ARGS) 1681 { 1682 struct ioat_descriptor *desc; 1683 struct ioat_softc *ioat; 1684 int error, arg; 1685 1686 ioat = arg1; 1687 1688 arg = 0; 1689 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1690 if (error != 0 || req->newptr == NULL) 1691 return (error); 1692 1693 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1694 if (error != 0) 1695 return (error); 1696 1697 if (arg != 0) { 1698 ioat_acquire(&ioat->dmaengine); 1699 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 1, 1700 0xffff000000000000ull, 0xffff000000000000ull, NULL, NULL, 1701 0); 1702 if (desc == NULL) 1703 error = ENOMEM; 1704 else 1705 ioat_submit_single(ioat); 1706 ioat_release(&ioat->dmaengine); 1707 } 1708 return (error); 1709 } 1710 1711 static int 1712 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1713 { 1714 struct ioat_softc *ioat; 1715 int error, arg; 1716 1717 ioat = arg1; 1718 1719 arg = 0; 1720 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1721 if (error != 0 || req->newptr == NULL) 1722 return (error); 1723 1724 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1725 if (error != 0) 1726 return (error); 1727 1728 if (arg != 0) 1729 error = ioat_reset_hw(ioat); 1730 1731 return (error); 1732 } 1733 1734 static void 1735 dump_descriptor(void *hw_desc) 1736 { 1737 int i, j; 1738 1739 for (i = 0; i < 2; i++) { 1740 for (j = 0; j < 8; j++) 1741 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1742 printf("\n"); 1743 } 1744 } 1745 1746 static void 1747 ioat_setup_sysctl(device_t device) 1748 { 1749 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1750 struct sysctl_ctx_list *ctx; 1751 struct sysctl_oid *tree, *tmp; 1752 struct ioat_softc *ioat; 1753 1754 ioat = DEVICE2SOFTC(device); 1755 ctx = device_get_sysctl_ctx(device); 1756 tree = device_get_sysctl_tree(device); 1757 par = SYSCTL_CHILDREN(tree); 1758 1759 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1760 &ioat->version, 0, "HW version (0xMM form)"); 1761 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1762 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1763 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1764 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1765 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1766 &ioat->intrdelay_max, 0, 1767 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1768 1769 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 1770 "IOAT channel internal state"); 1771 state = SYSCTL_CHILDREN(tmp); 1772 1773 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1774 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1775 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1776 0, "SW descriptor head pointer index"); 1777 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1778 0, "SW descriptor tail pointer index"); 1779 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 1780 &ioat->hw_head, 0, "HW DMACOUNT"); 1781 1782 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1783 ioat->comp_update, "HW addr of last completion"); 1784 1785 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 1786 &ioat->is_resize_pending, 0, "resize pending"); 1787 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 1788 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 1789 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1790 &ioat->is_reset_pending, 0, "reset pending"); 1791 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1792 &ioat->is_channel_running, 0, "channel running"); 1793 1794 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1795 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1796 "String of the channel status"); 1797 1798 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1799 &ioat->cached_intrdelay, 0, 1800 "Current INTRDELAY on this channel (cached, microseconds)"); 1801 1802 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 1803 "Big hammers (mostly for testing)"); 1804 hammer = SYSCTL_CHILDREN(tmp); 1805 1806 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1807 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1808 "Set to non-zero to reset the hardware"); 1809 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_error", 1810 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_error, "I", 1811 "Set to non-zero to inject a recoverable hardware error"); 1812 1813 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 1814 "IOAT channel statistics"); 1815 statpar = SYSCTL_CHILDREN(tmp); 1816 1817 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 1818 &ioat->stats.interrupts, 1819 "Number of interrupts processed on this channel"); 1820 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 1821 &ioat->stats.descriptors_processed, 1822 "Number of descriptors processed on this channel"); 1823 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 1824 &ioat->stats.descriptors_submitted, 1825 "Number of descriptors submitted to this channel"); 1826 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 1827 &ioat->stats.descriptors_error, 1828 "Number of descriptors failed by channel errors"); 1829 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 1830 &ioat->stats.channel_halts, 0, 1831 "Number of times the channel has halted"); 1832 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 1833 &ioat->stats.last_halt_chanerr, 0, 1834 "The raw CHANERR when the channel was last halted"); 1835 1836 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 1837 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 1838 "Descriptors per interrupt"); 1839 } 1840 1841 static inline struct ioat_softc * 1842 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1843 { 1844 uint32_t old; 1845 1846 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1847 1848 old = atomic_fetchadd_32(&ioat->refcnt, 1); 1849 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 1850 1851 #ifdef INVARIANTS 1852 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 1853 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 1854 #endif 1855 1856 return (ioat); 1857 } 1858 1859 static inline void 1860 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1861 { 1862 1863 _ioat_putn(ioat, n, kind, FALSE); 1864 } 1865 1866 static inline void 1867 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1868 { 1869 1870 _ioat_putn(ioat, n, kind, TRUE); 1871 } 1872 1873 static inline void 1874 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 1875 boolean_t locked) 1876 { 1877 uint32_t old; 1878 1879 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1880 1881 if (n == 0) 1882 return; 1883 1884 #ifdef INVARIANTS 1885 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 1886 KASSERT(old >= n, ("refcnt kind underflow")); 1887 #endif 1888 1889 /* Skip acquiring the lock if resulting refcnt > 0. */ 1890 for (;;) { 1891 old = ioat->refcnt; 1892 if (old <= n) 1893 break; 1894 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 1895 return; 1896 } 1897 1898 if (locked) 1899 mtx_assert(IOAT_REFLK, MA_OWNED); 1900 else 1901 mtx_lock(IOAT_REFLK); 1902 1903 old = atomic_fetchadd_32(&ioat->refcnt, -n); 1904 KASSERT(old >= n, ("refcnt error")); 1905 1906 if (old == n) 1907 wakeup(IOAT_REFLK); 1908 if (!locked) 1909 mtx_unlock(IOAT_REFLK); 1910 } 1911 1912 static inline void 1913 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1914 { 1915 1916 ioat_putn(ioat, 1, kind); 1917 } 1918 1919 static void 1920 ioat_drain_locked(struct ioat_softc *ioat) 1921 { 1922 1923 mtx_assert(IOAT_REFLK, MA_OWNED); 1924 while (ioat->refcnt > 0) 1925 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 1926 } 1927