1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * Copyright (C) 2018 Alexander Motin <mav@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_ddb.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/domainset.h> 38 #include <sys/fail.h> 39 #include <sys/ioccom.h> 40 #include <sys/kernel.h> 41 #include <sys/ktr.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/sbuf.h> 48 #include <sys/smp.h> 49 #include <sys/sysctl.h> 50 #include <sys/taskqueue.h> 51 #include <sys/time.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 #include <machine/stdarg.h> 57 58 #ifdef DDB 59 #include <ddb/ddb.h> 60 #endif 61 62 #include "ioat.h" 63 #include "ioat_hw.h" 64 #include "ioat_internal.h" 65 66 #ifndef BUS_SPACE_MAXADDR_40BIT 67 #define BUS_SPACE_MAXADDR_40BIT MIN(BUS_SPACE_MAXADDR, 0xFFFFFFFFFFULL) 68 #endif 69 #ifndef BUS_SPACE_MAXADDR_46BIT 70 #define BUS_SPACE_MAXADDR_46BIT MIN(BUS_SPACE_MAXADDR, 0x3FFFFFFFFFFFULL) 71 #endif 72 73 static int ioat_probe(device_t device); 74 static int ioat_attach(device_t device); 75 static int ioat_detach(device_t device); 76 static int ioat_setup_intr(struct ioat_softc *ioat); 77 static int ioat_teardown_intr(struct ioat_softc *ioat); 78 static int ioat3_attach(device_t device); 79 static int ioat_start_channel(struct ioat_softc *ioat); 80 static int ioat_map_pci_bar(struct ioat_softc *ioat); 81 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 82 int error); 83 static void ioat_interrupt_handler(void *arg); 84 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 85 static int chanerr_to_errno(uint32_t); 86 static void ioat_process_events(struct ioat_softc *ioat, boolean_t intr); 87 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 88 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 89 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 90 struct ioat_descriptor *); 91 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 92 static union ioat_hw_descriptor *ioat_get_descriptor(struct ioat_softc *, 93 uint32_t index); 94 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *, 95 uint32_t index); 96 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 97 static void ioat_poll_timer_callback(void *arg); 98 static void dump_descriptor(void *hw_desc); 99 static void ioat_submit_single(struct ioat_softc *ioat); 100 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 101 int error); 102 static int ioat_reset_hw(struct ioat_softc *ioat); 103 static void ioat_reset_hw_task(void *, int); 104 static void ioat_setup_sysctl(device_t device); 105 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 106 static void ioat_get(struct ioat_softc *); 107 static void ioat_put(struct ioat_softc *); 108 static void ioat_drain_locked(struct ioat_softc *); 109 110 #define ioat_log_message(v, ...) do { \ 111 if ((v) <= g_ioat_debug_level) { \ 112 device_printf(ioat->device, __VA_ARGS__); \ 113 } \ 114 } while (0) 115 116 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 117 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 118 119 static int g_force_legacy_interrupts; 120 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 121 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 122 123 int g_ioat_debug_level = 0; 124 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 125 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 126 127 unsigned g_ioat_ring_order = 13; 128 SYSCTL_UINT(_hw_ioat, OID_AUTO, ring_order, CTLFLAG_RDTUN, &g_ioat_ring_order, 129 0, "Set IOAT ring order. (1 << this) == ring size."); 130 131 /* 132 * OS <-> Driver interface structures 133 */ 134 static device_method_t ioat_pci_methods[] = { 135 /* Device interface */ 136 DEVMETHOD(device_probe, ioat_probe), 137 DEVMETHOD(device_attach, ioat_attach), 138 DEVMETHOD(device_detach, ioat_detach), 139 DEVMETHOD_END 140 }; 141 142 static driver_t ioat_pci_driver = { 143 "ioat", 144 ioat_pci_methods, 145 sizeof(struct ioat_softc), 146 }; 147 148 static devclass_t ioat_devclass; 149 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 150 MODULE_VERSION(ioat, 1); 151 152 /* 153 * Private data structures 154 */ 155 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 156 static unsigned ioat_channel_index = 0; 157 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 158 "Number of IOAT channels attached"); 159 static struct mtx ioat_list_mtx; 160 MTX_SYSINIT(ioat_list_mtx, &ioat_list_mtx, "ioat list mtx", MTX_DEF); 161 162 static struct _pcsid 163 { 164 u_int32_t type; 165 const char *desc; 166 } pci_ids[] = { 167 { 0x34308086, "TBG IOAT Ch0" }, 168 { 0x34318086, "TBG IOAT Ch1" }, 169 { 0x34328086, "TBG IOAT Ch2" }, 170 { 0x34338086, "TBG IOAT Ch3" }, 171 { 0x34298086, "TBG IOAT Ch4" }, 172 { 0x342a8086, "TBG IOAT Ch5" }, 173 { 0x342b8086, "TBG IOAT Ch6" }, 174 { 0x342c8086, "TBG IOAT Ch7" }, 175 176 { 0x37108086, "JSF IOAT Ch0" }, 177 { 0x37118086, "JSF IOAT Ch1" }, 178 { 0x37128086, "JSF IOAT Ch2" }, 179 { 0x37138086, "JSF IOAT Ch3" }, 180 { 0x37148086, "JSF IOAT Ch4" }, 181 { 0x37158086, "JSF IOAT Ch5" }, 182 { 0x37168086, "JSF IOAT Ch6" }, 183 { 0x37178086, "JSF IOAT Ch7" }, 184 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 185 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 186 187 { 0x3c208086, "SNB IOAT Ch0" }, 188 { 0x3c218086, "SNB IOAT Ch1" }, 189 { 0x3c228086, "SNB IOAT Ch2" }, 190 { 0x3c238086, "SNB IOAT Ch3" }, 191 { 0x3c248086, "SNB IOAT Ch4" }, 192 { 0x3c258086, "SNB IOAT Ch5" }, 193 { 0x3c268086, "SNB IOAT Ch6" }, 194 { 0x3c278086, "SNB IOAT Ch7" }, 195 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 196 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 197 198 { 0x0e208086, "IVB IOAT Ch0" }, 199 { 0x0e218086, "IVB IOAT Ch1" }, 200 { 0x0e228086, "IVB IOAT Ch2" }, 201 { 0x0e238086, "IVB IOAT Ch3" }, 202 { 0x0e248086, "IVB IOAT Ch4" }, 203 { 0x0e258086, "IVB IOAT Ch5" }, 204 { 0x0e268086, "IVB IOAT Ch6" }, 205 { 0x0e278086, "IVB IOAT Ch7" }, 206 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 207 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 208 209 { 0x2f208086, "HSW IOAT Ch0" }, 210 { 0x2f218086, "HSW IOAT Ch1" }, 211 { 0x2f228086, "HSW IOAT Ch2" }, 212 { 0x2f238086, "HSW IOAT Ch3" }, 213 { 0x2f248086, "HSW IOAT Ch4" }, 214 { 0x2f258086, "HSW IOAT Ch5" }, 215 { 0x2f268086, "HSW IOAT Ch6" }, 216 { 0x2f278086, "HSW IOAT Ch7" }, 217 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 218 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 219 220 { 0x0c508086, "BWD IOAT Ch0" }, 221 { 0x0c518086, "BWD IOAT Ch1" }, 222 { 0x0c528086, "BWD IOAT Ch2" }, 223 { 0x0c538086, "BWD IOAT Ch3" }, 224 225 { 0x6f508086, "BDXDE IOAT Ch0" }, 226 { 0x6f518086, "BDXDE IOAT Ch1" }, 227 { 0x6f528086, "BDXDE IOAT Ch2" }, 228 { 0x6f538086, "BDXDE IOAT Ch3" }, 229 230 { 0x6f208086, "BDX IOAT Ch0" }, 231 { 0x6f218086, "BDX IOAT Ch1" }, 232 { 0x6f228086, "BDX IOAT Ch2" }, 233 { 0x6f238086, "BDX IOAT Ch3" }, 234 { 0x6f248086, "BDX IOAT Ch4" }, 235 { 0x6f258086, "BDX IOAT Ch5" }, 236 { 0x6f268086, "BDX IOAT Ch6" }, 237 { 0x6f278086, "BDX IOAT Ch7" }, 238 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 239 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 240 241 { 0x20218086, "SKX IOAT" }, 242 }; 243 244 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, ioat, pci_ids, 245 nitems(pci_ids)); 246 247 /* 248 * OS <-> Driver linkage functions 249 */ 250 static int 251 ioat_probe(device_t device) 252 { 253 struct _pcsid *ep; 254 u_int32_t type; 255 256 type = pci_get_devid(device); 257 for (ep = pci_ids; ep < &pci_ids[nitems(pci_ids)]; ep++) { 258 if (ep->type == type) { 259 device_set_desc(device, ep->desc); 260 return (0); 261 } 262 } 263 return (ENXIO); 264 } 265 266 static int 267 ioat_attach(device_t device) 268 { 269 struct ioat_softc *ioat; 270 int error, i; 271 272 ioat = DEVICE2SOFTC(device); 273 ioat->device = device; 274 if (bus_get_domain(device, &ioat->domain) != 0) 275 ioat->domain = 0; 276 ioat->cpu = CPU_FFS(&cpuset_domain[ioat->domain]) - 1; 277 if (ioat->cpu < 0) 278 ioat->cpu = CPU_FIRST(); 279 280 error = ioat_map_pci_bar(ioat); 281 if (error != 0) 282 goto err; 283 284 ioat->version = ioat_read_cbver(ioat); 285 if (ioat->version < IOAT_VER_3_0) { 286 error = ENODEV; 287 goto err; 288 } 289 290 error = ioat3_attach(device); 291 if (error != 0) 292 goto err; 293 294 error = pci_enable_busmaster(device); 295 if (error != 0) 296 goto err; 297 298 error = ioat_setup_intr(ioat); 299 if (error != 0) 300 goto err; 301 302 error = ioat_reset_hw(ioat); 303 if (error != 0) 304 goto err; 305 306 ioat_process_events(ioat, FALSE); 307 ioat_setup_sysctl(device); 308 309 mtx_lock(&ioat_list_mtx); 310 for (i = 0; i < IOAT_MAX_CHANNELS; i++) { 311 if (ioat_channel[i] == NULL) 312 break; 313 } 314 if (i >= IOAT_MAX_CHANNELS) { 315 mtx_unlock(&ioat_list_mtx); 316 device_printf(device, "Too many I/OAT devices in system\n"); 317 error = ENXIO; 318 goto err; 319 } 320 ioat->chan_idx = i; 321 ioat_channel[i] = ioat; 322 if (i >= ioat_channel_index) 323 ioat_channel_index = i + 1; 324 mtx_unlock(&ioat_list_mtx); 325 326 ioat_test_attach(); 327 328 err: 329 if (error != 0) 330 ioat_detach(device); 331 return (error); 332 } 333 334 static inline int 335 ioat_bus_dmamap_destroy(struct ioat_softc *ioat, const char *func, 336 bus_dma_tag_t dmat, bus_dmamap_t map) 337 { 338 int error; 339 340 error = bus_dmamap_destroy(dmat, map); 341 if (error != 0) { 342 ioat_log_message(0, 343 "%s: bus_dmamap_destroy failed %d\n", func, error); 344 } 345 346 return (error); 347 } 348 349 static int 350 ioat_detach(device_t device) 351 { 352 struct ioat_softc *ioat; 353 int i, error; 354 355 ioat = DEVICE2SOFTC(device); 356 357 mtx_lock(&ioat_list_mtx); 358 ioat_channel[ioat->chan_idx] = NULL; 359 while (ioat_channel_index > 0 && 360 ioat_channel[ioat_channel_index - 1] == NULL) 361 ioat_channel_index--; 362 mtx_unlock(&ioat_list_mtx); 363 364 ioat_test_detach(); 365 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 366 367 mtx_lock(&ioat->submit_lock); 368 ioat->quiescing = TRUE; 369 ioat->destroying = TRUE; 370 wakeup(&ioat->quiescing); 371 wakeup(&ioat->resetting); 372 373 ioat_drain_locked(ioat); 374 mtx_unlock(&ioat->submit_lock); 375 mtx_lock(&ioat->cleanup_lock); 376 while (ioat_get_active(ioat) > 0) 377 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1); 378 mtx_unlock(&ioat->cleanup_lock); 379 380 ioat_teardown_intr(ioat); 381 callout_drain(&ioat->poll_timer); 382 383 pci_disable_busmaster(device); 384 385 if (ioat->pci_resource != NULL) 386 bus_release_resource(device, SYS_RES_MEMORY, 387 ioat->pci_resource_id, ioat->pci_resource); 388 389 if (ioat->data_tag != NULL) { 390 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 391 error = ioat_bus_dmamap_destroy(ioat, __func__, 392 ioat->data_tag, ioat->ring[i].src_dmamap); 393 if (error != 0) 394 return (error); 395 } 396 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 397 error = ioat_bus_dmamap_destroy(ioat, __func__, 398 ioat->data_tag, ioat->ring[i].dst_dmamap); 399 if (error != 0) 400 return (error); 401 } 402 403 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 404 error = ioat_bus_dmamap_destroy(ioat, __func__, 405 ioat->data_tag, ioat->ring[i].src2_dmamap); 406 if (error != 0) 407 return (error); 408 } 409 for (i = 0; i < 1 << ioat->ring_size_order; i++) { 410 error = ioat_bus_dmamap_destroy(ioat, __func__, 411 ioat->data_tag, ioat->ring[i].dst2_dmamap); 412 if (error != 0) 413 return (error); 414 } 415 416 bus_dma_tag_destroy(ioat->data_tag); 417 } 418 419 if (ioat->ring != NULL) 420 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 421 422 if (ioat->comp_update != NULL) { 423 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 424 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 425 ioat->comp_update_map); 426 bus_dma_tag_destroy(ioat->comp_update_tag); 427 } 428 429 if (ioat->hw_desc_ring != NULL) { 430 bus_dmamap_unload(ioat->hw_desc_tag, ioat->hw_desc_map); 431 bus_dmamem_free(ioat->hw_desc_tag, ioat->hw_desc_ring, 432 ioat->hw_desc_map); 433 bus_dma_tag_destroy(ioat->hw_desc_tag); 434 } 435 436 return (0); 437 } 438 439 static int 440 ioat_teardown_intr(struct ioat_softc *ioat) 441 { 442 443 if (ioat->tag != NULL) 444 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 445 446 if (ioat->res != NULL) 447 bus_release_resource(ioat->device, SYS_RES_IRQ, 448 rman_get_rid(ioat->res), ioat->res); 449 450 pci_release_msi(ioat->device); 451 return (0); 452 } 453 454 static int 455 ioat_start_channel(struct ioat_softc *ioat) 456 { 457 struct ioat_dma_hw_descriptor *hw_desc; 458 struct ioat_descriptor *desc; 459 struct bus_dmadesc *dmadesc; 460 uint64_t status; 461 uint32_t chanerr; 462 int i; 463 464 ioat_acquire(&ioat->dmaengine); 465 466 /* Submit 'NULL' operation manually to avoid quiescing flag */ 467 desc = ioat_get_ring_entry(ioat, ioat->head); 468 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->dma; 469 dmadesc = &desc->bus_dmadesc; 470 471 dmadesc->callback_fn = NULL; 472 dmadesc->callback_arg = NULL; 473 474 hw_desc->u.control_raw = 0; 475 hw_desc->u.control_generic.op = IOAT_OP_COPY; 476 hw_desc->u.control_generic.completion_update = 1; 477 hw_desc->size = 8; 478 hw_desc->src_addr = 0; 479 hw_desc->dest_addr = 0; 480 hw_desc->u.control.null = 1; 481 482 ioat_submit_single(ioat); 483 ioat_release(&ioat->dmaengine); 484 485 for (i = 0; i < 100; i++) { 486 DELAY(1); 487 status = ioat_get_chansts(ioat); 488 if (is_ioat_idle(status)) 489 return (0); 490 } 491 492 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 493 ioat_log_message(0, "could not start channel: " 494 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 495 IOAT_CHANERR_STR); 496 return (ENXIO); 497 } 498 499 /* 500 * Initialize Hardware 501 */ 502 static int 503 ioat3_attach(device_t device) 504 { 505 struct ioat_softc *ioat; 506 struct ioat_descriptor *ring; 507 struct ioat_dma_hw_descriptor *dma_hw_desc; 508 void *hw_desc; 509 bus_addr_t lowaddr; 510 size_t ringsz; 511 int i, num_descriptors; 512 int error; 513 uint8_t xfercap; 514 515 error = 0; 516 ioat = DEVICE2SOFTC(device); 517 ioat->capabilities = ioat_read_dmacapability(ioat); 518 519 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 520 IOAT_DMACAP_STR); 521 522 xfercap = ioat_read_xfercap(ioat); 523 ioat->max_xfer_size = 1 << xfercap; 524 525 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 526 IOAT_INTRDELAY_SUPPORTED) != 0; 527 if (ioat->intrdelay_supported) 528 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 529 530 /* TODO: need to check DCA here if we ever do XOR/PQ */ 531 532 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 533 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 534 callout_init(&ioat->poll_timer, 1); 535 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 536 537 /* Establish lock order for Witness */ 538 mtx_lock(&ioat->cleanup_lock); 539 mtx_lock(&ioat->submit_lock); 540 mtx_unlock(&ioat->submit_lock); 541 mtx_unlock(&ioat->cleanup_lock); 542 543 ioat->is_submitter_processing = FALSE; 544 545 if (ioat->version >= IOAT_VER_3_3) 546 lowaddr = BUS_SPACE_MAXADDR_48BIT; 547 else if (ioat->version >= IOAT_VER_3_2) 548 lowaddr = BUS_SPACE_MAXADDR_46BIT; 549 else 550 lowaddr = BUS_SPACE_MAXADDR_40BIT; 551 552 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 553 sizeof(uint64_t), 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 554 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 555 &ioat->comp_update_tag); 556 if (error != 0) 557 return (error); 558 559 error = bus_dmamem_alloc(ioat->comp_update_tag, 560 (void **)&ioat->comp_update, BUS_DMA_ZERO | BUS_DMA_WAITOK, 561 &ioat->comp_update_map); 562 if (error != 0) 563 return (error); 564 565 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 566 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 567 BUS_DMA_NOWAIT); 568 if (error != 0) 569 return (error); 570 571 ioat->ring_size_order = g_ioat_ring_order; 572 num_descriptors = 1 << ioat->ring_size_order; 573 ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors; 574 575 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 576 2 * 1024 * 1024, 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 577 ringsz, 1, ringsz, 0, NULL, NULL, &ioat->hw_desc_tag); 578 if (error != 0) 579 return (error); 580 581 error = bus_dmamem_alloc(ioat->hw_desc_tag, &hw_desc, 582 BUS_DMA_ZERO | BUS_DMA_WAITOK, &ioat->hw_desc_map); 583 if (error != 0) 584 return (error); 585 586 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 587 ringsz, ioat_dmamap_cb, &ioat->hw_desc_bus_addr, BUS_DMA_NOWAIT); 588 if (error) 589 return (error); 590 591 ioat->hw_desc_ring = hw_desc; 592 593 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 594 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 595 ioat->max_xfer_size, 1, ioat->max_xfer_size, 0, NULL, NULL, 596 &ioat->data_tag); 597 if (error != 0) 598 return (error); 599 ioat->ring = malloc_domainset(num_descriptors * sizeof(*ring), M_IOAT, 600 DOMAINSET_PREF(ioat->domain), M_ZERO | M_WAITOK); 601 602 ring = ioat->ring; 603 for (i = 0; i < num_descriptors; i++) { 604 memset(&ring[i].bus_dmadesc, 0, sizeof(ring[i].bus_dmadesc)); 605 ring[i].id = i; 606 error = bus_dmamap_create(ioat->data_tag, 0, 607 &ring[i].src_dmamap); 608 if (error != 0) { 609 ioat_log_message(0, 610 "%s: bus_dmamap_create failed %d\n", __func__, 611 error); 612 return (error); 613 } 614 error = bus_dmamap_create(ioat->data_tag, 0, 615 &ring[i].dst_dmamap); 616 if (error != 0) { 617 ioat_log_message(0, 618 "%s: bus_dmamap_create failed %d\n", __func__, 619 error); 620 return (error); 621 } 622 error = bus_dmamap_create(ioat->data_tag, 0, 623 &ring[i].src2_dmamap); 624 if (error != 0) { 625 ioat_log_message(0, 626 "%s: bus_dmamap_create failed %d\n", __func__, 627 error); 628 return (error); 629 } 630 error = bus_dmamap_create(ioat->data_tag, 0, 631 &ring[i].dst2_dmamap); 632 if (error != 0) { 633 ioat_log_message(0, 634 "%s: bus_dmamap_create failed %d\n", __func__, 635 error); 636 return (error); 637 } 638 } 639 640 for (i = 0; i < num_descriptors; i++) { 641 dma_hw_desc = &ioat->hw_desc_ring[i].dma; 642 dma_hw_desc->next = RING_PHYS_ADDR(ioat, i + 1); 643 } 644 645 ioat->tail = ioat->head = 0; 646 *ioat->comp_update = ioat->last_seen = 647 RING_PHYS_ADDR(ioat, ioat->tail - 1); 648 return (0); 649 } 650 651 static int 652 ioat_map_pci_bar(struct ioat_softc *ioat) 653 { 654 655 ioat->pci_resource_id = PCIR_BAR(0); 656 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 657 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 658 659 if (ioat->pci_resource == NULL) { 660 ioat_log_message(0, "unable to allocate pci resource\n"); 661 return (ENODEV); 662 } 663 664 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 665 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 666 return (0); 667 } 668 669 static void 670 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 671 { 672 struct ioat_softc *ioat = arg; 673 674 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 675 ioat->comp_update_bus_addr = seg[0].ds_addr; 676 } 677 678 static void 679 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 680 { 681 bus_addr_t *baddr; 682 683 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 684 baddr = arg; 685 *baddr = segs->ds_addr; 686 } 687 688 /* 689 * Interrupt setup and handlers 690 */ 691 static int 692 ioat_setup_intr(struct ioat_softc *ioat) 693 { 694 uint32_t num_vectors; 695 int error; 696 boolean_t use_msix; 697 boolean_t force_legacy_interrupts; 698 699 use_msix = FALSE; 700 force_legacy_interrupts = FALSE; 701 702 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 703 num_vectors = 1; 704 pci_alloc_msix(ioat->device, &num_vectors); 705 if (num_vectors == 1) 706 use_msix = TRUE; 707 } 708 709 if (use_msix) { 710 ioat->rid = 1; 711 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 712 &ioat->rid, RF_ACTIVE); 713 } else { 714 ioat->rid = 0; 715 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 716 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 717 } 718 if (ioat->res == NULL) { 719 ioat_log_message(0, "bus_alloc_resource failed\n"); 720 return (ENOMEM); 721 } 722 723 ioat->tag = NULL; 724 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 725 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 726 if (error != 0) { 727 ioat_log_message(0, "bus_setup_intr failed\n"); 728 return (error); 729 } 730 731 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 732 return (0); 733 } 734 735 static boolean_t 736 ioat_model_resets_msix(struct ioat_softc *ioat) 737 { 738 u_int32_t pciid; 739 740 pciid = pci_get_devid(ioat->device); 741 switch (pciid) { 742 /* BWD: */ 743 case 0x0c508086: 744 case 0x0c518086: 745 case 0x0c528086: 746 case 0x0c538086: 747 /* BDXDE: */ 748 case 0x6f508086: 749 case 0x6f518086: 750 case 0x6f528086: 751 case 0x6f538086: 752 return (TRUE); 753 } 754 755 return (FALSE); 756 } 757 758 static void 759 ioat_interrupt_handler(void *arg) 760 { 761 struct ioat_softc *ioat = arg; 762 763 ioat->stats.interrupts++; 764 ioat_process_events(ioat, TRUE); 765 } 766 767 static int 768 chanerr_to_errno(uint32_t chanerr) 769 { 770 771 if (chanerr == 0) 772 return (0); 773 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 774 return (EFAULT); 775 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 776 return (EIO); 777 /* This one is probably our fault: */ 778 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 779 return (EIO); 780 return (EIO); 781 } 782 783 static void 784 ioat_process_events(struct ioat_softc *ioat, boolean_t intr) 785 { 786 struct ioat_descriptor *desc; 787 struct bus_dmadesc *dmadesc; 788 uint64_t comp_update, status; 789 uint32_t completed, chanerr; 790 int error; 791 792 mtx_lock(&ioat->cleanup_lock); 793 794 /* 795 * Don't run while the hardware is being reset. Reset is responsible 796 * for blocking new work and draining & completing existing work, so 797 * there is nothing to do until new work is queued after reset anyway. 798 */ 799 if (ioat->resetting_cleanup) { 800 mtx_unlock(&ioat->cleanup_lock); 801 return; 802 } 803 804 completed = 0; 805 comp_update = *ioat->comp_update; 806 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 807 808 if (status < ioat->hw_desc_bus_addr || 809 status >= ioat->hw_desc_bus_addr + (1 << ioat->ring_size_order) * 810 sizeof(struct ioat_generic_hw_descriptor)) 811 panic("Bogus completion address %jx (channel %u)", 812 (uintmax_t)status, ioat->chan_idx); 813 814 if (status == ioat->last_seen) { 815 /* 816 * If we landed in process_events and nothing has been 817 * completed, check for a timeout due to channel halt. 818 */ 819 goto out; 820 } 821 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx", 822 __func__, ioat->chan_idx, comp_update, ioat->last_seen); 823 824 while (RING_PHYS_ADDR(ioat, ioat->tail - 1) != status) { 825 desc = ioat_get_ring_entry(ioat, ioat->tail); 826 dmadesc = &desc->bus_dmadesc; 827 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) ok cb %p(%p)", 828 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 829 dmadesc->callback_arg); 830 831 bus_dmamap_unload(ioat->data_tag, desc->src_dmamap); 832 bus_dmamap_unload(ioat->data_tag, desc->dst_dmamap); 833 bus_dmamap_unload(ioat->data_tag, desc->src2_dmamap); 834 bus_dmamap_unload(ioat->data_tag, desc->dst2_dmamap); 835 836 if (dmadesc->callback_fn != NULL) 837 dmadesc->callback_fn(dmadesc->callback_arg, 0); 838 839 completed++; 840 ioat->tail++; 841 } 842 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 843 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 844 845 if (completed != 0) { 846 ioat->last_seen = RING_PHYS_ADDR(ioat, ioat->tail - 1); 847 ioat->stats.descriptors_processed += completed; 848 wakeup(&ioat->tail); 849 } 850 851 out: 852 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 853 mtx_unlock(&ioat->cleanup_lock); 854 855 /* 856 * The device doesn't seem to reliably push suspend/halt statuses to 857 * the channel completion memory address, so poll the device register 858 * here. For performance reasons skip it on interrupts, do it only 859 * on much more rare polling events. 860 */ 861 if (!intr) 862 comp_update = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 863 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 864 return; 865 866 ioat->stats.channel_halts++; 867 868 /* 869 * Fatal programming error on this DMA channel. Flush any outstanding 870 * work with error status and restart the engine. 871 */ 872 mtx_lock(&ioat->submit_lock); 873 ioat->quiescing = TRUE; 874 mtx_unlock(&ioat->submit_lock); 875 876 /* 877 * This is safe to do here because the submit queue is quiesced. We 878 * know that we will drain all outstanding events, so ioat_reset_hw 879 * can't deadlock. It is necessary to protect other ioat_process_event 880 * threads from racing ioat_reset_hw, reading an indeterminate hw 881 * state, and attempting to continue issuing completions. 882 */ 883 mtx_lock(&ioat->cleanup_lock); 884 ioat->resetting_cleanup = TRUE; 885 886 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 887 if (1 <= g_ioat_debug_level) 888 ioat_halted_debug(ioat, chanerr); 889 ioat->stats.last_halt_chanerr = chanerr; 890 891 while (ioat_get_active(ioat) > 0) { 892 desc = ioat_get_ring_entry(ioat, ioat->tail); 893 dmadesc = &desc->bus_dmadesc; 894 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) err cb %p(%p)", 895 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 896 dmadesc->callback_arg); 897 898 if (dmadesc->callback_fn != NULL) 899 dmadesc->callback_fn(dmadesc->callback_arg, 900 chanerr_to_errno(chanerr)); 901 902 ioat->tail++; 903 ioat->stats.descriptors_processed++; 904 ioat->stats.descriptors_error++; 905 } 906 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 907 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 908 909 /* Clear error status */ 910 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 911 912 mtx_unlock(&ioat->cleanup_lock); 913 914 ioat_log_message(0, "Resetting channel to recover from error\n"); 915 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 916 KASSERT(error == 0, 917 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 918 } 919 920 static void 921 ioat_reset_hw_task(void *ctx, int pending __unused) 922 { 923 struct ioat_softc *ioat; 924 int error; 925 926 ioat = ctx; 927 ioat_log_message(1, "%s: Resetting channel\n", __func__); 928 929 error = ioat_reset_hw(ioat); 930 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 931 (void)error; 932 } 933 934 /* 935 * User API functions 936 */ 937 unsigned 938 ioat_get_nchannels(void) 939 { 940 941 return (ioat_channel_index); 942 } 943 944 bus_dmaengine_t 945 ioat_get_dmaengine(uint32_t index, int flags) 946 { 947 struct ioat_softc *ioat; 948 949 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 950 ("invalid flags: 0x%08x", flags)); 951 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 952 ("invalid wait | nowait")); 953 954 mtx_lock(&ioat_list_mtx); 955 if (index >= ioat_channel_index || 956 (ioat = ioat_channel[index]) == NULL) { 957 mtx_unlock(&ioat_list_mtx); 958 return (NULL); 959 } 960 mtx_lock(&ioat->submit_lock); 961 mtx_unlock(&ioat_list_mtx); 962 963 if (ioat->destroying) { 964 mtx_unlock(&ioat->submit_lock); 965 return (NULL); 966 } 967 968 ioat_get(ioat); 969 if (ioat->quiescing) { 970 if ((flags & M_NOWAIT) != 0) { 971 ioat_put(ioat); 972 mtx_unlock(&ioat->submit_lock); 973 return (NULL); 974 } 975 976 while (ioat->quiescing && !ioat->destroying) 977 msleep(&ioat->quiescing, &ioat->submit_lock, 0, "getdma", 0); 978 979 if (ioat->destroying) { 980 ioat_put(ioat); 981 mtx_unlock(&ioat->submit_lock); 982 return (NULL); 983 } 984 } 985 mtx_unlock(&ioat->submit_lock); 986 return (&ioat->dmaengine); 987 } 988 989 void 990 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 991 { 992 struct ioat_softc *ioat; 993 994 ioat = to_ioat_softc(dmaengine); 995 mtx_lock(&ioat->submit_lock); 996 ioat_put(ioat); 997 mtx_unlock(&ioat->submit_lock); 998 } 999 1000 int 1001 ioat_get_hwversion(bus_dmaengine_t dmaengine) 1002 { 1003 struct ioat_softc *ioat; 1004 1005 ioat = to_ioat_softc(dmaengine); 1006 return (ioat->version); 1007 } 1008 1009 size_t 1010 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 1011 { 1012 struct ioat_softc *ioat; 1013 1014 ioat = to_ioat_softc(dmaengine); 1015 return (ioat->max_xfer_size); 1016 } 1017 1018 uint32_t 1019 ioat_get_capabilities(bus_dmaengine_t dmaengine) 1020 { 1021 struct ioat_softc *ioat; 1022 1023 ioat = to_ioat_softc(dmaengine); 1024 return (ioat->capabilities); 1025 } 1026 1027 int 1028 ioat_get_domain(bus_dmaengine_t dmaengine, int *domain) 1029 { 1030 struct ioat_softc *ioat; 1031 1032 ioat = to_ioat_softc(dmaengine); 1033 return (bus_get_domain(ioat->device, domain)); 1034 } 1035 1036 int 1037 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 1038 { 1039 struct ioat_softc *ioat; 1040 1041 ioat = to_ioat_softc(dmaengine); 1042 if (!ioat->intrdelay_supported) 1043 return (ENODEV); 1044 if (delay > ioat->intrdelay_max) 1045 return (ERANGE); 1046 1047 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 1048 ioat->cached_intrdelay = 1049 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 1050 return (0); 1051 } 1052 1053 uint16_t 1054 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 1055 { 1056 struct ioat_softc *ioat; 1057 1058 ioat = to_ioat_softc(dmaengine); 1059 return (ioat->intrdelay_max); 1060 } 1061 1062 void 1063 ioat_acquire(bus_dmaengine_t dmaengine) 1064 { 1065 struct ioat_softc *ioat; 1066 1067 ioat = to_ioat_softc(dmaengine); 1068 mtx_lock(&ioat->submit_lock); 1069 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1070 ioat->acq_head = ioat->head; 1071 } 1072 1073 int 1074 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 1075 { 1076 struct ioat_softc *ioat; 1077 int error; 1078 1079 ioat = to_ioat_softc(dmaengine); 1080 ioat_acquire(dmaengine); 1081 1082 error = ioat_reserve_space(ioat, n, mflags); 1083 if (error != 0) 1084 ioat_release(dmaengine); 1085 return (error); 1086 } 1087 1088 void 1089 ioat_release(bus_dmaengine_t dmaengine) 1090 { 1091 struct ioat_softc *ioat; 1092 1093 ioat = to_ioat_softc(dmaengine); 1094 CTR3(KTR_IOAT, "%s channel=%u dispatch1 head=%u", __func__, 1095 ioat->chan_idx, ioat->head); 1096 KFAIL_POINT_CODE(DEBUG_FP, ioat_release, /* do nothing */); 1097 CTR3(KTR_IOAT, "%s channel=%u dispatch2 head=%u", __func__, 1098 ioat->chan_idx, ioat->head); 1099 1100 if (ioat->acq_head != ioat->head) { 1101 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, 1102 (uint16_t)ioat->head); 1103 1104 if (!callout_pending(&ioat->poll_timer)) { 1105 callout_reset_on(&ioat->poll_timer, 1, 1106 ioat_poll_timer_callback, ioat, ioat->cpu); 1107 } 1108 } 1109 mtx_unlock(&ioat->submit_lock); 1110 } 1111 1112 static struct ioat_descriptor * 1113 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 1114 uint32_t size, uint64_t src, uint64_t dst, 1115 bus_dmaengine_callback_t callback_fn, void *callback_arg, 1116 uint32_t flags) 1117 { 1118 struct ioat_generic_hw_descriptor *hw_desc; 1119 struct ioat_descriptor *desc; 1120 bus_dma_segment_t seg; 1121 int mflags, nseg, error; 1122 1123 mtx_assert(&ioat->submit_lock, MA_OWNED); 1124 1125 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 1126 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 1127 KASSERT(size <= ioat->max_xfer_size, ("%s: size too big (%u > %u)", 1128 __func__, (unsigned)size, ioat->max_xfer_size)); 1129 1130 if ((flags & DMA_NO_WAIT) != 0) 1131 mflags = M_NOWAIT; 1132 else 1133 mflags = M_WAITOK; 1134 1135 if (ioat_reserve_space(ioat, 1, mflags) != 0) 1136 return (NULL); 1137 1138 desc = ioat_get_ring_entry(ioat, ioat->head); 1139 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->generic; 1140 1141 hw_desc->u.control_raw = 0; 1142 hw_desc->u.control_generic.op = op; 1143 hw_desc->u.control_generic.completion_update = 1; 1144 1145 if ((flags & DMA_INT_EN) != 0) 1146 hw_desc->u.control_generic.int_enable = 1; 1147 if ((flags & DMA_FENCE) != 0) 1148 hw_desc->u.control_generic.fence = 1; 1149 1150 hw_desc->size = size; 1151 1152 if (src != 0) { 1153 nseg = -1; 1154 error = _bus_dmamap_load_phys(ioat->data_tag, desc->src_dmamap, 1155 src, size, 0, &seg, &nseg); 1156 if (error != 0) { 1157 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1158 " failed %d\n", __func__, error); 1159 return (NULL); 1160 } 1161 hw_desc->src_addr = seg.ds_addr; 1162 } 1163 1164 if (dst != 0) { 1165 nseg = -1; 1166 error = _bus_dmamap_load_phys(ioat->data_tag, desc->dst_dmamap, 1167 dst, size, 0, &seg, &nseg); 1168 if (error != 0) { 1169 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1170 " failed %d\n", __func__, error); 1171 return (NULL); 1172 } 1173 hw_desc->dest_addr = seg.ds_addr; 1174 } 1175 1176 desc->bus_dmadesc.callback_fn = callback_fn; 1177 desc->bus_dmadesc.callback_arg = callback_arg; 1178 return (desc); 1179 } 1180 1181 struct bus_dmadesc * 1182 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1183 void *callback_arg, uint32_t flags) 1184 { 1185 struct ioat_dma_hw_descriptor *hw_desc; 1186 struct ioat_descriptor *desc; 1187 struct ioat_softc *ioat; 1188 1189 ioat = to_ioat_softc(dmaengine); 1190 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1191 1192 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1193 callback_arg, flags); 1194 if (desc == NULL) 1195 return (NULL); 1196 1197 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1198 hw_desc->u.control.null = 1; 1199 ioat_submit_single(ioat); 1200 return (&desc->bus_dmadesc); 1201 } 1202 1203 struct bus_dmadesc * 1204 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1205 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1206 void *callback_arg, uint32_t flags) 1207 { 1208 struct ioat_dma_hw_descriptor *hw_desc; 1209 struct ioat_descriptor *desc; 1210 struct ioat_softc *ioat; 1211 1212 ioat = to_ioat_softc(dmaengine); 1213 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1214 callback_arg, flags); 1215 if (desc == NULL) 1216 return (NULL); 1217 1218 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1219 if (g_ioat_debug_level >= 3) 1220 dump_descriptor(hw_desc); 1221 1222 ioat_submit_single(ioat); 1223 CTR6(KTR_IOAT, "%s channel=%u desc=%p dest=%lx src=%lx len=%lx", 1224 __func__, ioat->chan_idx, &desc->bus_dmadesc, dst, src, len); 1225 return (&desc->bus_dmadesc); 1226 } 1227 1228 struct bus_dmadesc * 1229 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1230 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1231 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1232 { 1233 struct ioat_dma_hw_descriptor *hw_desc; 1234 struct ioat_descriptor *desc; 1235 struct ioat_softc *ioat; 1236 bus_size_t src1_len, dst1_len; 1237 bus_dma_segment_t seg; 1238 int nseg, error; 1239 1240 ioat = to_ioat_softc(dmaengine); 1241 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1242 1243 KASSERT(((src1 | src2 | dst1 | dst2) & PAGE_MASK) == 0, 1244 ("%s: addresses are not page-aligned", __func__)); 1245 1246 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, 0, 0, 1247 callback_fn, callback_arg, flags); 1248 if (desc == NULL) 1249 return (NULL); 1250 1251 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1252 1253 src1_len = (src2 != src1 + PAGE_SIZE) ? PAGE_SIZE : 2 * PAGE_SIZE; 1254 nseg = -1; 1255 error = _bus_dmamap_load_phys(ioat->data_tag, 1256 desc->src_dmamap, src1, src1_len, 0, &seg, &nseg); 1257 if (error != 0) { 1258 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1259 " failed %d\n", __func__, error); 1260 return (NULL); 1261 } 1262 hw_desc->src_addr = seg.ds_addr; 1263 if (src1_len != 2 * PAGE_SIZE) { 1264 hw_desc->u.control.src_page_break = 1; 1265 nseg = -1; 1266 error = _bus_dmamap_load_phys(ioat->data_tag, 1267 desc->src2_dmamap, src2, PAGE_SIZE, 0, &seg, &nseg); 1268 if (error != 0) { 1269 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1270 " failed %d\n", __func__, error); 1271 return (NULL); 1272 } 1273 hw_desc->next_src_addr = seg.ds_addr; 1274 } 1275 1276 dst1_len = (dst2 != dst1 + PAGE_SIZE) ? PAGE_SIZE : 2 * PAGE_SIZE; 1277 nseg = -1; 1278 error = _bus_dmamap_load_phys(ioat->data_tag, 1279 desc->dst_dmamap, dst1, dst1_len, 0, &seg, &nseg); 1280 if (error != 0) { 1281 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1282 " failed %d\n", __func__, error); 1283 return (NULL); 1284 } 1285 hw_desc->dest_addr = seg.ds_addr; 1286 if (dst1_len != 2 * PAGE_SIZE) { 1287 hw_desc->u.control.dest_page_break = 1; 1288 nseg = -1; 1289 error = _bus_dmamap_load_phys(ioat->data_tag, 1290 desc->dst2_dmamap, dst2, PAGE_SIZE, 0, &seg, &nseg); 1291 if (error != 0) { 1292 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1293 " failed %d\n", __func__, error); 1294 return (NULL); 1295 } 1296 hw_desc->next_dest_addr = seg.ds_addr; 1297 } 1298 1299 if (g_ioat_debug_level >= 3) 1300 dump_descriptor(hw_desc); 1301 1302 ioat_submit_single(ioat); 1303 return (&desc->bus_dmadesc); 1304 } 1305 1306 struct bus_dmadesc * 1307 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1308 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1309 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1310 { 1311 struct ioat_crc32_hw_descriptor *hw_desc; 1312 struct ioat_descriptor *desc; 1313 struct ioat_softc *ioat; 1314 uint32_t teststore; 1315 uint8_t op; 1316 bus_dma_segment_t seg; 1317 int nseg, error; 1318 1319 ioat = to_ioat_softc(dmaengine); 1320 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1321 1322 KASSERT((ioat->capabilities & IOAT_DMACAP_MOVECRC) != 0, 1323 ("%s: device lacks MOVECRC capability", __func__)); 1324 teststore = (flags & _DMA_CRC_TESTSTORE); 1325 KASSERT(teststore != _DMA_CRC_TESTSTORE, 1326 ("%s: TEST and STORE invalid", __func__)); 1327 KASSERT(teststore != 0 || (flags & DMA_CRC_INLINE) == 0, 1328 ("%s: INLINE invalid without TEST or STORE", __func__)); 1329 1330 switch (teststore) { 1331 case DMA_CRC_STORE: 1332 op = IOAT_OP_MOVECRC_STORE; 1333 break; 1334 case DMA_CRC_TEST: 1335 op = IOAT_OP_MOVECRC_TEST; 1336 break; 1337 default: 1338 KASSERT(teststore == 0, ("bogus")); 1339 op = IOAT_OP_MOVECRC; 1340 break; 1341 } 1342 1343 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1344 callback_arg, flags & ~_DMA_CRC_FLAGS); 1345 if (desc == NULL) 1346 return (NULL); 1347 1348 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1349 1350 if ((flags & DMA_CRC_INLINE) == 0) { 1351 nseg = -1; 1352 error = _bus_dmamap_load_phys(ioat->data_tag, 1353 desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0, 1354 &seg, &nseg); 1355 if (error != 0) { 1356 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1357 " failed %d\n", __func__, error); 1358 return (NULL); 1359 } 1360 hw_desc->crc_address = seg.ds_addr; 1361 } else 1362 hw_desc->u.control.crc_location = 1; 1363 1364 if (initialseed != NULL) { 1365 hw_desc->u.control.use_seed = 1; 1366 hw_desc->seed = *initialseed; 1367 } 1368 1369 if (g_ioat_debug_level >= 3) 1370 dump_descriptor(hw_desc); 1371 1372 ioat_submit_single(ioat); 1373 return (&desc->bus_dmadesc); 1374 } 1375 1376 struct bus_dmadesc * 1377 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1378 uint32_t *initialseed, bus_addr_t crcptr, 1379 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1380 { 1381 struct ioat_crc32_hw_descriptor *hw_desc; 1382 struct ioat_descriptor *desc; 1383 struct ioat_softc *ioat; 1384 uint32_t teststore; 1385 uint8_t op; 1386 bus_dma_segment_t seg; 1387 int nseg, error; 1388 1389 ioat = to_ioat_softc(dmaengine); 1390 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1391 1392 KASSERT((ioat->capabilities & IOAT_DMACAP_CRC) != 0, 1393 ("%s: device lacks CRC capability", __func__)); 1394 teststore = (flags & _DMA_CRC_TESTSTORE); 1395 KASSERT(teststore != _DMA_CRC_TESTSTORE, 1396 ("%s: TEST and STORE invalid", __func__)); 1397 KASSERT(teststore != 0 || (flags & DMA_CRC_INLINE) == 0, 1398 ("%s: INLINE invalid without TEST or STORE", __func__)); 1399 1400 switch (teststore) { 1401 case DMA_CRC_STORE: 1402 op = IOAT_OP_CRC_STORE; 1403 break; 1404 case DMA_CRC_TEST: 1405 op = IOAT_OP_CRC_TEST; 1406 break; 1407 default: 1408 KASSERT(teststore == 0, ("bogus")); 1409 op = IOAT_OP_CRC; 1410 break; 1411 } 1412 1413 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1414 callback_arg, flags & ~_DMA_CRC_FLAGS); 1415 if (desc == NULL) 1416 return (NULL); 1417 1418 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1419 1420 if ((flags & DMA_CRC_INLINE) == 0) { 1421 nseg = -1; 1422 error = _bus_dmamap_load_phys(ioat->data_tag, 1423 desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0, 1424 &seg, &nseg); 1425 if (error != 0) { 1426 ioat_log_message(0, "%s: _bus_dmamap_load_phys" 1427 " failed %d\n", __func__, error); 1428 return (NULL); 1429 } 1430 hw_desc->crc_address = seg.ds_addr; 1431 } else 1432 hw_desc->u.control.crc_location = 1; 1433 1434 if (initialseed != NULL) { 1435 hw_desc->u.control.use_seed = 1; 1436 hw_desc->seed = *initialseed; 1437 } 1438 1439 if (g_ioat_debug_level >= 3) 1440 dump_descriptor(hw_desc); 1441 1442 ioat_submit_single(ioat); 1443 return (&desc->bus_dmadesc); 1444 } 1445 1446 struct bus_dmadesc * 1447 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1448 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1449 uint32_t flags) 1450 { 1451 struct ioat_fill_hw_descriptor *hw_desc; 1452 struct ioat_descriptor *desc; 1453 struct ioat_softc *ioat; 1454 1455 ioat = to_ioat_softc(dmaengine); 1456 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1457 1458 KASSERT((ioat->capabilities & IOAT_DMACAP_BFILL) != 0, 1459 ("%s: device lacks BFILL capability", __func__)); 1460 1461 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, 0, dst, 1462 callback_fn, callback_arg, flags); 1463 if (desc == NULL) 1464 return (NULL); 1465 1466 hw_desc = &ioat_get_descriptor(ioat, desc->id)->fill; 1467 hw_desc->src_data = fillpattern; 1468 if (g_ioat_debug_level >= 3) 1469 dump_descriptor(hw_desc); 1470 1471 ioat_submit_single(ioat); 1472 return (&desc->bus_dmadesc); 1473 } 1474 1475 /* 1476 * Ring Management 1477 */ 1478 static inline uint32_t 1479 ioat_get_active(struct ioat_softc *ioat) 1480 { 1481 1482 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1483 } 1484 1485 static inline uint32_t 1486 ioat_get_ring_space(struct ioat_softc *ioat) 1487 { 1488 1489 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1490 } 1491 1492 /* 1493 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1494 * for 'num_descs'. 1495 * 1496 * If mflags contains M_WAITOK, blocks until enough space is available. 1497 * 1498 * Returns zero on success, or an errno on error. If num_descs is beyond the 1499 * maximum ring size, returns EINVAl; if allocation would block and mflags 1500 * contains M_NOWAIT, returns EAGAIN. 1501 * 1502 * Must be called with the submit_lock held; returns with the lock held. The 1503 * lock may be dropped to allocate the ring. 1504 * 1505 * (The submit_lock is needed to add any entries to the ring, so callers are 1506 * assured enough room is available.) 1507 */ 1508 static int 1509 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1510 { 1511 boolean_t dug; 1512 int error; 1513 1514 mtx_assert(&ioat->submit_lock, MA_OWNED); 1515 error = 0; 1516 dug = FALSE; 1517 1518 if (num_descs < 1 || num_descs >= (1 << ioat->ring_size_order)) { 1519 error = EINVAL; 1520 goto out; 1521 } 1522 1523 for (;;) { 1524 if (ioat->quiescing) { 1525 error = ENXIO; 1526 goto out; 1527 } 1528 1529 if (ioat_get_ring_space(ioat) >= num_descs) 1530 goto out; 1531 1532 CTR3(KTR_IOAT, "%s channel=%u starved (%u)", __func__, 1533 ioat->chan_idx, num_descs); 1534 1535 if (!dug && !ioat->is_submitter_processing) { 1536 ioat->is_submitter_processing = TRUE; 1537 mtx_unlock(&ioat->submit_lock); 1538 1539 CTR2(KTR_IOAT, "%s channel=%u attempting to process events", 1540 __func__, ioat->chan_idx); 1541 ioat_process_events(ioat, FALSE); 1542 1543 mtx_lock(&ioat->submit_lock); 1544 dug = TRUE; 1545 KASSERT(ioat->is_submitter_processing == TRUE, 1546 ("is_submitter_processing")); 1547 ioat->is_submitter_processing = FALSE; 1548 wakeup(&ioat->tail); 1549 continue; 1550 } 1551 1552 if ((mflags & M_WAITOK) == 0) { 1553 error = EAGAIN; 1554 break; 1555 } 1556 CTR2(KTR_IOAT, "%s channel=%u blocking on completions", 1557 __func__, ioat->chan_idx); 1558 msleep(&ioat->tail, &ioat->submit_lock, 0, 1559 "ioat_full", 0); 1560 continue; 1561 } 1562 1563 out: 1564 mtx_assert(&ioat->submit_lock, MA_OWNED); 1565 KASSERT(!ioat->quiescing || error == ENXIO, 1566 ("reserved during quiesce")); 1567 return (error); 1568 } 1569 1570 static void 1571 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1572 struct ioat_descriptor *ring) 1573 { 1574 1575 free_domain(ring, M_IOAT); 1576 } 1577 1578 static struct ioat_descriptor * 1579 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1580 { 1581 1582 return (&ioat->ring[index % (1 << ioat->ring_size_order)]); 1583 } 1584 1585 static union ioat_hw_descriptor * 1586 ioat_get_descriptor(struct ioat_softc *ioat, uint32_t index) 1587 { 1588 1589 return (&ioat->hw_desc_ring[index % (1 << ioat->ring_size_order)]); 1590 } 1591 1592 static void 1593 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1594 { 1595 union ioat_hw_descriptor *desc; 1596 1597 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1598 IOAT_CHANERR_STR); 1599 if (chanerr == 0) 1600 return; 1601 1602 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1603 1604 desc = ioat_get_descriptor(ioat, ioat->tail + 0); 1605 dump_descriptor(desc); 1606 1607 desc = ioat_get_descriptor(ioat, ioat->tail + 1); 1608 dump_descriptor(desc); 1609 } 1610 1611 static void 1612 ioat_poll_timer_callback(void *arg) 1613 { 1614 struct ioat_softc *ioat; 1615 1616 ioat = arg; 1617 CTR1(KTR_IOAT, "%s", __func__); 1618 1619 ioat_process_events(ioat, FALSE); 1620 1621 mtx_lock(&ioat->submit_lock); 1622 if (ioat_get_active(ioat) > 0) 1623 callout_schedule(&ioat->poll_timer, 1); 1624 mtx_unlock(&ioat->submit_lock); 1625 } 1626 1627 /* 1628 * Support Functions 1629 */ 1630 static void 1631 ioat_submit_single(struct ioat_softc *ioat) 1632 { 1633 1634 mtx_assert(&ioat->submit_lock, MA_OWNED); 1635 1636 ioat->head++; 1637 CTR4(KTR_IOAT, "%s channel=%u head=%u tail=%u", __func__, 1638 ioat->chan_idx, ioat->head, ioat->tail); 1639 1640 ioat->stats.descriptors_submitted++; 1641 } 1642 1643 static int 1644 ioat_reset_hw(struct ioat_softc *ioat) 1645 { 1646 uint64_t status; 1647 uint32_t chanerr; 1648 unsigned timeout; 1649 int error; 1650 1651 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1652 1653 mtx_lock(&ioat->submit_lock); 1654 while (ioat->resetting && !ioat->destroying) 1655 msleep(&ioat->resetting, &ioat->submit_lock, 0, "IRH_drain", 0); 1656 if (ioat->destroying) { 1657 mtx_unlock(&ioat->submit_lock); 1658 return (ENXIO); 1659 } 1660 ioat->resetting = TRUE; 1661 ioat->quiescing = TRUE; 1662 mtx_unlock(&ioat->submit_lock); 1663 mtx_lock(&ioat->cleanup_lock); 1664 while (ioat_get_active(ioat) > 0) 1665 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1); 1666 1667 /* 1668 * Suspend ioat_process_events while the hardware and softc are in an 1669 * indeterminate state. 1670 */ 1671 ioat->resetting_cleanup = TRUE; 1672 mtx_unlock(&ioat->cleanup_lock); 1673 1674 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__, 1675 ioat->chan_idx); 1676 1677 status = ioat_get_chansts(ioat); 1678 if (is_ioat_active(status) || is_ioat_idle(status)) 1679 ioat_suspend(ioat); 1680 1681 /* Wait at most 20 ms */ 1682 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1683 timeout < 20; timeout++) { 1684 DELAY(1000); 1685 status = ioat_get_chansts(ioat); 1686 } 1687 if (timeout == 20) { 1688 error = ETIMEDOUT; 1689 goto out; 1690 } 1691 1692 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1693 1694 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1695 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1696 1697 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__, 1698 ioat->chan_idx); 1699 1700 /* 1701 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1702 * that can cause stability issues for IOAT v3. 1703 */ 1704 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1705 4); 1706 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1707 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1708 1709 /* 1710 * BDXDE and BWD models reset MSI-X registers on device reset. 1711 * Save/restore their contents manually. 1712 */ 1713 if (ioat_model_resets_msix(ioat)) { 1714 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1715 pci_save_state(ioat->device); 1716 } 1717 1718 ioat_reset(ioat); 1719 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__, 1720 ioat->chan_idx); 1721 1722 /* Wait at most 20 ms */ 1723 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1724 DELAY(1000); 1725 if (timeout == 20) { 1726 error = ETIMEDOUT; 1727 goto out; 1728 } 1729 1730 if (ioat_model_resets_msix(ioat)) { 1731 ioat_log_message(1, "device resets registers; restored\n"); 1732 pci_restore_state(ioat->device); 1733 } 1734 1735 /* Reset attempts to return the hardware to "halted." */ 1736 status = ioat_get_chansts(ioat); 1737 if (is_ioat_active(status) || is_ioat_idle(status)) { 1738 /* So this really shouldn't happen... */ 1739 ioat_log_message(0, "Device is active after a reset?\n"); 1740 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1741 error = 0; 1742 goto out; 1743 } 1744 1745 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1746 if (chanerr != 0) { 1747 mtx_lock(&ioat->cleanup_lock); 1748 ioat_halted_debug(ioat, chanerr); 1749 mtx_unlock(&ioat->cleanup_lock); 1750 error = EIO; 1751 goto out; 1752 } 1753 1754 /* 1755 * Bring device back online after reset. Writing CHAINADDR brings the 1756 * device back to active. 1757 * 1758 * The internal ring counter resets to zero, so we have to start over 1759 * at zero as well. 1760 */ 1761 ioat->tail = ioat->head = 0; 1762 *ioat->comp_update = ioat->last_seen = 1763 RING_PHYS_ADDR(ioat, ioat->tail - 1); 1764 1765 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1766 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1767 ioat_write_chainaddr(ioat, RING_PHYS_ADDR(ioat, 0)); 1768 error = 0; 1769 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__, 1770 ioat->chan_idx); 1771 1772 out: 1773 /* Enqueues a null operation and ensures it completes. */ 1774 if (error == 0) { 1775 error = ioat_start_channel(ioat); 1776 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__, 1777 ioat->chan_idx); 1778 } 1779 1780 /* 1781 * Resume completions now that ring state is consistent. 1782 */ 1783 mtx_lock(&ioat->cleanup_lock); 1784 ioat->resetting_cleanup = FALSE; 1785 mtx_unlock(&ioat->cleanup_lock); 1786 1787 /* Unblock submission of new work */ 1788 mtx_lock(&ioat->submit_lock); 1789 ioat->quiescing = FALSE; 1790 wakeup(&ioat->quiescing); 1791 1792 ioat->resetting = FALSE; 1793 wakeup(&ioat->resetting); 1794 1795 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx); 1796 mtx_unlock(&ioat->submit_lock); 1797 1798 return (error); 1799 } 1800 1801 static int 1802 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1803 { 1804 struct ioat_softc *ioat; 1805 struct sbuf sb; 1806 uint64_t status; 1807 int error; 1808 1809 ioat = arg1; 1810 1811 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1812 1813 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1814 switch (status) { 1815 case IOAT_CHANSTS_ACTIVE: 1816 sbuf_printf(&sb, "ACTIVE"); 1817 break; 1818 case IOAT_CHANSTS_IDLE: 1819 sbuf_printf(&sb, "IDLE"); 1820 break; 1821 case IOAT_CHANSTS_SUSPENDED: 1822 sbuf_printf(&sb, "SUSPENDED"); 1823 break; 1824 case IOAT_CHANSTS_HALTED: 1825 sbuf_printf(&sb, "HALTED"); 1826 break; 1827 case IOAT_CHANSTS_ARMED: 1828 sbuf_printf(&sb, "ARMED"); 1829 break; 1830 default: 1831 sbuf_printf(&sb, "UNKNOWN"); 1832 break; 1833 } 1834 error = sbuf_finish(&sb); 1835 sbuf_delete(&sb); 1836 1837 if (error != 0 || req->newptr == NULL) 1838 return (error); 1839 return (EINVAL); 1840 } 1841 1842 static int 1843 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1844 { 1845 struct ioat_softc *ioat; 1846 struct sbuf sb; 1847 #define PRECISION "1" 1848 const uintmax_t factor = 10; 1849 uintmax_t rate; 1850 int error; 1851 1852 ioat = arg1; 1853 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1854 1855 if (ioat->stats.interrupts == 0) { 1856 sbuf_printf(&sb, "NaN"); 1857 goto out; 1858 } 1859 rate = ioat->stats.descriptors_processed * factor / 1860 ioat->stats.interrupts; 1861 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1862 rate % factor); 1863 #undef PRECISION 1864 out: 1865 error = sbuf_finish(&sb); 1866 sbuf_delete(&sb); 1867 if (error != 0 || req->newptr == NULL) 1868 return (error); 1869 return (EINVAL); 1870 } 1871 1872 static int 1873 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1874 { 1875 struct ioat_softc *ioat; 1876 int error, arg; 1877 1878 ioat = arg1; 1879 1880 arg = 0; 1881 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1882 if (error != 0 || req->newptr == NULL) 1883 return (error); 1884 1885 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1886 if (error != 0) 1887 return (error); 1888 1889 if (arg != 0) 1890 error = ioat_reset_hw(ioat); 1891 1892 return (error); 1893 } 1894 1895 static void 1896 dump_descriptor(void *hw_desc) 1897 { 1898 int i, j; 1899 1900 for (i = 0; i < 2; i++) { 1901 for (j = 0; j < 8; j++) 1902 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1903 printf("\n"); 1904 } 1905 } 1906 1907 static void 1908 ioat_setup_sysctl(device_t device) 1909 { 1910 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1911 struct sysctl_ctx_list *ctx; 1912 struct sysctl_oid *tree, *tmp; 1913 struct ioat_softc *ioat; 1914 1915 ioat = DEVICE2SOFTC(device); 1916 ctx = device_get_sysctl_ctx(device); 1917 tree = device_get_sysctl_tree(device); 1918 par = SYSCTL_CHILDREN(tree); 1919 1920 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1921 &ioat->version, 0, "HW version (0xMM form)"); 1922 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1923 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1924 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1925 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1926 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1927 &ioat->intrdelay_max, 0, 1928 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1929 1930 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 1931 "IOAT channel internal state"); 1932 state = SYSCTL_CHILDREN(tmp); 1933 1934 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1935 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1936 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1937 0, "SW descriptor head pointer index"); 1938 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1939 0, "SW descriptor tail pointer index"); 1940 1941 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1942 ioat->comp_update, "HW addr of last completion"); 1943 1944 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 1945 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 1946 "submitter processing"); 1947 1948 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1949 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1950 "String of the channel status"); 1951 1952 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1953 &ioat->cached_intrdelay, 0, 1954 "Current INTRDELAY on this channel (cached, microseconds)"); 1955 1956 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 1957 "Big hammers (mostly for testing)"); 1958 hammer = SYSCTL_CHILDREN(tmp); 1959 1960 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1961 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1962 "Set to non-zero to reset the hardware"); 1963 1964 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 1965 "IOAT channel statistics"); 1966 statpar = SYSCTL_CHILDREN(tmp); 1967 1968 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", 1969 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.interrupts, 1970 "Number of interrupts processed on this channel"); 1971 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", 1972 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_processed, 1973 "Number of descriptors processed on this channel"); 1974 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", 1975 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_submitted, 1976 "Number of descriptors submitted to this channel"); 1977 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", 1978 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_error, 1979 "Number of descriptors failed by channel errors"); 1980 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", 1981 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.channel_halts, 0, 1982 "Number of times the channel has halted"); 1983 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", 1984 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.last_halt_chanerr, 0, 1985 "The raw CHANERR when the channel was last halted"); 1986 1987 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 1988 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 1989 "Descriptors per interrupt"); 1990 } 1991 1992 static void 1993 ioat_get(struct ioat_softc *ioat) 1994 { 1995 1996 mtx_assert(&ioat->submit_lock, MA_OWNED); 1997 KASSERT(ioat->refcnt < UINT32_MAX, ("refcnt overflow")); 1998 1999 ioat->refcnt++; 2000 } 2001 2002 static void 2003 ioat_put(struct ioat_softc *ioat) 2004 { 2005 2006 mtx_assert(&ioat->submit_lock, MA_OWNED); 2007 KASSERT(ioat->refcnt >= 1, ("refcnt error")); 2008 2009 if (--ioat->refcnt == 0) 2010 wakeup(&ioat->refcnt); 2011 } 2012 2013 static void 2014 ioat_drain_locked(struct ioat_softc *ioat) 2015 { 2016 2017 mtx_assert(&ioat->submit_lock, MA_OWNED); 2018 2019 while (ioat->refcnt > 0) 2020 msleep(&ioat->refcnt, &ioat->submit_lock, 0, "ioat_drain", 0); 2021 } 2022 2023 #ifdef DDB 2024 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 2025 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 2026 DB_SHOW_COMMAND(ioat, db_show_ioat) 2027 { 2028 struct ioat_softc *sc; 2029 unsigned idx; 2030 2031 if (!have_addr) 2032 goto usage; 2033 idx = (unsigned)addr; 2034 if (idx >= ioat_channel_index) 2035 goto usage; 2036 2037 sc = ioat_channel[idx]; 2038 db_printf("ioat softc at %p\n", sc); 2039 if (sc == NULL) 2040 return; 2041 2042 db_printf(" version: %d\n", sc->version); 2043 db_printf(" chan_idx: %u\n", sc->chan_idx); 2044 db_printf(" submit_lock: "); 2045 db_show_lock(&sc->submit_lock); 2046 2047 db_printf(" capabilities: %b\n", (int)sc->capabilities, 2048 IOAT_DMACAP_STR); 2049 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 2050 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 2051 2052 db_printf(" poll_timer:\n"); 2053 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 2054 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 2055 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 2056 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 2057 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 2058 2059 db_printf(" quiescing: %d\n", (int)sc->quiescing); 2060 db_printf(" destroying: %d\n", (int)sc->destroying); 2061 db_printf(" is_submitter_processing: %d\n", 2062 (int)sc->is_submitter_processing); 2063 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 2064 db_printf(" resetting: %d\n", (int)sc->resetting); 2065 2066 db_printf(" head: %u\n", sc->head); 2067 db_printf(" tail: %u\n", sc->tail); 2068 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2069 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2070 db_printf(" ring: %p\n", sc->ring); 2071 db_printf(" descriptors: %p\n", sc->hw_desc_ring); 2072 db_printf(" descriptors (phys): 0x%jx\n", 2073 (uintmax_t)sc->hw_desc_bus_addr); 2074 2075 db_printf(" ring[%u] (tail):\n", sc->tail % 2076 (1 << sc->ring_size_order)); 2077 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 2078 db_printf(" addr: 0x%lx\n", 2079 RING_PHYS_ADDR(sc, sc->tail)); 2080 db_printf(" next: 0x%lx\n", 2081 ioat_get_descriptor(sc, sc->tail)->generic.next); 2082 2083 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 2084 (1 << sc->ring_size_order)); 2085 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 2086 db_printf(" addr: 0x%lx\n", 2087 RING_PHYS_ADDR(sc, sc->head - 1)); 2088 db_printf(" next: 0x%lx\n", 2089 ioat_get_descriptor(sc, sc->head - 1)->generic.next); 2090 2091 db_printf(" ring[%u] (head):\n", (sc->head) % 2092 (1 << sc->ring_size_order)); 2093 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2094 db_printf(" addr: 0x%lx\n", 2095 RING_PHYS_ADDR(sc, sc->head)); 2096 db_printf(" next: 0x%lx\n", 2097 ioat_get_descriptor(sc, sc->head)->generic.next); 2098 2099 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2100 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2101 == RING_PHYS_ADDR(sc, idx)) 2102 db_printf(" ring[%u] == hardware tail\n", idx); 2103 2104 db_printf(" cleanup_lock: "); 2105 db_show_lock(&sc->cleanup_lock); 2106 2107 db_printf(" refcnt: %u\n", sc->refcnt); 2108 db_printf(" stats:\n"); 2109 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2110 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2111 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2112 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2113 2114 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2115 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2116 2117 if (db_pager_quit) 2118 return; 2119 2120 db_printf(" hw status:\n"); 2121 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2122 db_printf(" chanctrl: 0x%x\n", 2123 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2124 db_printf(" chancmd: 0x%x\n", 2125 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2126 db_printf(" dmacount: 0x%x\n", 2127 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2128 db_printf(" chainaddr: 0x%lx\n", 2129 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2130 db_printf(" chancmp: 0x%lx\n", 2131 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2132 db_printf(" chanerr: %b\n", 2133 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2134 return; 2135 usage: 2136 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2137 return; 2138 } 2139 #endif /* DDB */ 2140