1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ddb.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/fail.h> 37 #include <sys/ioccom.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/sbuf.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 #include <sys/time.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <machine/stdarg.h> 53 54 #ifdef DDB 55 #include <ddb/ddb.h> 56 #endif 57 58 #include "ioat.h" 59 #include "ioat_hw.h" 60 #include "ioat_internal.h" 61 62 #ifndef BUS_SPACE_MAXADDR_40BIT 63 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 64 #endif 65 #define IOAT_REFLK (&ioat->submit_lock) 66 #define IOAT_SHRINK_PERIOD (10 * hz) 67 68 static int ioat_probe(device_t device); 69 static int ioat_attach(device_t device); 70 static int ioat_detach(device_t device); 71 static int ioat_setup_intr(struct ioat_softc *ioat); 72 static int ioat_teardown_intr(struct ioat_softc *ioat); 73 static int ioat3_attach(device_t device); 74 static int ioat_start_channel(struct ioat_softc *ioat); 75 static int ioat_map_pci_bar(struct ioat_softc *ioat); 76 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 77 int error); 78 static void ioat_interrupt_handler(void *arg); 79 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 80 static int chanerr_to_errno(uint32_t); 81 static void ioat_process_events(struct ioat_softc *ioat); 82 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 83 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 84 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 85 struct ioat_descriptor **); 86 static void ioat_free_ring_entry(struct ioat_softc *ioat, 87 struct ioat_descriptor *desc); 88 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 89 int mflags); 90 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 91 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 92 uint32_t index); 93 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 94 uint32_t size, boolean_t need_dscr, int mflags); 95 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 96 struct ioat_descriptor **); 97 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 98 struct ioat_descriptor **); 99 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 100 static void ioat_poll_timer_callback(void *arg); 101 static void ioat_shrink_timer_callback(void *arg); 102 static void dump_descriptor(void *hw_desc); 103 static void ioat_submit_single(struct ioat_softc *ioat); 104 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 105 int error); 106 static int ioat_reset_hw(struct ioat_softc *ioat); 107 static void ioat_reset_hw_task(void *, int); 108 static void ioat_setup_sysctl(device_t device); 109 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 110 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 111 enum ioat_ref_kind); 112 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 113 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 114 enum ioat_ref_kind, boolean_t); 115 static inline void ioat_putn(struct ioat_softc *, uint32_t, 116 enum ioat_ref_kind); 117 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 118 enum ioat_ref_kind); 119 static void ioat_drain_locked(struct ioat_softc *); 120 121 #define ioat_log_message(v, ...) do { \ 122 if ((v) <= g_ioat_debug_level) { \ 123 device_printf(ioat->device, __VA_ARGS__); \ 124 } \ 125 } while (0) 126 127 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 128 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 129 130 static int g_force_legacy_interrupts; 131 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 132 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 133 134 int g_ioat_debug_level = 0; 135 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 136 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 137 138 /* 139 * OS <-> Driver interface structures 140 */ 141 static device_method_t ioat_pci_methods[] = { 142 /* Device interface */ 143 DEVMETHOD(device_probe, ioat_probe), 144 DEVMETHOD(device_attach, ioat_attach), 145 DEVMETHOD(device_detach, ioat_detach), 146 DEVMETHOD_END 147 }; 148 149 static driver_t ioat_pci_driver = { 150 "ioat", 151 ioat_pci_methods, 152 sizeof(struct ioat_softc), 153 }; 154 155 static devclass_t ioat_devclass; 156 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 157 MODULE_VERSION(ioat, 1); 158 159 /* 160 * Private data structures 161 */ 162 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 163 static unsigned ioat_channel_index = 0; 164 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 165 "Number of IOAT channels attached"); 166 167 static struct _pcsid 168 { 169 u_int32_t type; 170 const char *desc; 171 } pci_ids[] = { 172 { 0x34308086, "TBG IOAT Ch0" }, 173 { 0x34318086, "TBG IOAT Ch1" }, 174 { 0x34328086, "TBG IOAT Ch2" }, 175 { 0x34338086, "TBG IOAT Ch3" }, 176 { 0x34298086, "TBG IOAT Ch4" }, 177 { 0x342a8086, "TBG IOAT Ch5" }, 178 { 0x342b8086, "TBG IOAT Ch6" }, 179 { 0x342c8086, "TBG IOAT Ch7" }, 180 181 { 0x37108086, "JSF IOAT Ch0" }, 182 { 0x37118086, "JSF IOAT Ch1" }, 183 { 0x37128086, "JSF IOAT Ch2" }, 184 { 0x37138086, "JSF IOAT Ch3" }, 185 { 0x37148086, "JSF IOAT Ch4" }, 186 { 0x37158086, "JSF IOAT Ch5" }, 187 { 0x37168086, "JSF IOAT Ch6" }, 188 { 0x37178086, "JSF IOAT Ch7" }, 189 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 190 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 191 192 { 0x3c208086, "SNB IOAT Ch0" }, 193 { 0x3c218086, "SNB IOAT Ch1" }, 194 { 0x3c228086, "SNB IOAT Ch2" }, 195 { 0x3c238086, "SNB IOAT Ch3" }, 196 { 0x3c248086, "SNB IOAT Ch4" }, 197 { 0x3c258086, "SNB IOAT Ch5" }, 198 { 0x3c268086, "SNB IOAT Ch6" }, 199 { 0x3c278086, "SNB IOAT Ch7" }, 200 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 201 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 202 203 { 0x0e208086, "IVB IOAT Ch0" }, 204 { 0x0e218086, "IVB IOAT Ch1" }, 205 { 0x0e228086, "IVB IOAT Ch2" }, 206 { 0x0e238086, "IVB IOAT Ch3" }, 207 { 0x0e248086, "IVB IOAT Ch4" }, 208 { 0x0e258086, "IVB IOAT Ch5" }, 209 { 0x0e268086, "IVB IOAT Ch6" }, 210 { 0x0e278086, "IVB IOAT Ch7" }, 211 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 212 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 213 214 { 0x2f208086, "HSW IOAT Ch0" }, 215 { 0x2f218086, "HSW IOAT Ch1" }, 216 { 0x2f228086, "HSW IOAT Ch2" }, 217 { 0x2f238086, "HSW IOAT Ch3" }, 218 { 0x2f248086, "HSW IOAT Ch4" }, 219 { 0x2f258086, "HSW IOAT Ch5" }, 220 { 0x2f268086, "HSW IOAT Ch6" }, 221 { 0x2f278086, "HSW IOAT Ch7" }, 222 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 223 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 224 225 { 0x0c508086, "BWD IOAT Ch0" }, 226 { 0x0c518086, "BWD IOAT Ch1" }, 227 { 0x0c528086, "BWD IOAT Ch2" }, 228 { 0x0c538086, "BWD IOAT Ch3" }, 229 230 { 0x6f508086, "BDXDE IOAT Ch0" }, 231 { 0x6f518086, "BDXDE IOAT Ch1" }, 232 { 0x6f528086, "BDXDE IOAT Ch2" }, 233 { 0x6f538086, "BDXDE IOAT Ch3" }, 234 235 { 0x6f208086, "BDX IOAT Ch0" }, 236 { 0x6f218086, "BDX IOAT Ch1" }, 237 { 0x6f228086, "BDX IOAT Ch2" }, 238 { 0x6f238086, "BDX IOAT Ch3" }, 239 { 0x6f248086, "BDX IOAT Ch4" }, 240 { 0x6f258086, "BDX IOAT Ch5" }, 241 { 0x6f268086, "BDX IOAT Ch6" }, 242 { 0x6f278086, "BDX IOAT Ch7" }, 243 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 244 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 245 246 { 0x00000000, NULL } 247 }; 248 249 /* 250 * OS <-> Driver linkage functions 251 */ 252 static int 253 ioat_probe(device_t device) 254 { 255 struct _pcsid *ep; 256 u_int32_t type; 257 258 type = pci_get_devid(device); 259 for (ep = pci_ids; ep->type; ep++) { 260 if (ep->type == type) { 261 device_set_desc(device, ep->desc); 262 return (0); 263 } 264 } 265 return (ENXIO); 266 } 267 268 static int 269 ioat_attach(device_t device) 270 { 271 struct ioat_softc *ioat; 272 int error; 273 274 ioat = DEVICE2SOFTC(device); 275 ioat->device = device; 276 277 error = ioat_map_pci_bar(ioat); 278 if (error != 0) 279 goto err; 280 281 ioat->version = ioat_read_cbver(ioat); 282 if (ioat->version < IOAT_VER_3_0) { 283 error = ENODEV; 284 goto err; 285 } 286 287 error = ioat3_attach(device); 288 if (error != 0) 289 goto err; 290 291 error = pci_enable_busmaster(device); 292 if (error != 0) 293 goto err; 294 295 error = ioat_setup_intr(ioat); 296 if (error != 0) 297 goto err; 298 299 error = ioat_reset_hw(ioat); 300 if (error != 0) 301 goto err; 302 303 ioat_process_events(ioat); 304 ioat_setup_sysctl(device); 305 306 ioat->chan_idx = ioat_channel_index; 307 ioat_channel[ioat_channel_index++] = ioat; 308 ioat_test_attach(); 309 310 err: 311 if (error != 0) 312 ioat_detach(device); 313 return (error); 314 } 315 316 static int 317 ioat_detach(device_t device) 318 { 319 struct ioat_softc *ioat; 320 321 ioat = DEVICE2SOFTC(device); 322 323 ioat_test_detach(); 324 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 325 326 mtx_lock(IOAT_REFLK); 327 ioat->quiescing = TRUE; 328 ioat->destroying = TRUE; 329 wakeup(&ioat->quiescing); 330 wakeup(&ioat->resetting); 331 332 ioat_channel[ioat->chan_idx] = NULL; 333 334 ioat_drain_locked(ioat); 335 mtx_unlock(IOAT_REFLK); 336 337 ioat_teardown_intr(ioat); 338 callout_drain(&ioat->poll_timer); 339 callout_drain(&ioat->shrink_timer); 340 341 pci_disable_busmaster(device); 342 343 if (ioat->pci_resource != NULL) 344 bus_release_resource(device, SYS_RES_MEMORY, 345 ioat->pci_resource_id, ioat->pci_resource); 346 347 if (ioat->ring != NULL) 348 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 349 350 if (ioat->comp_update != NULL) { 351 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 352 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 353 ioat->comp_update_map); 354 bus_dma_tag_destroy(ioat->comp_update_tag); 355 } 356 357 bus_dma_tag_destroy(ioat->hw_desc_tag); 358 359 return (0); 360 } 361 362 static int 363 ioat_teardown_intr(struct ioat_softc *ioat) 364 { 365 366 if (ioat->tag != NULL) 367 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 368 369 if (ioat->res != NULL) 370 bus_release_resource(ioat->device, SYS_RES_IRQ, 371 rman_get_rid(ioat->res), ioat->res); 372 373 pci_release_msi(ioat->device); 374 return (0); 375 } 376 377 static int 378 ioat_start_channel(struct ioat_softc *ioat) 379 { 380 struct ioat_dma_hw_descriptor *hw_desc; 381 struct ioat_descriptor *desc; 382 struct bus_dmadesc *dmadesc; 383 uint64_t status; 384 uint32_t chanerr; 385 int i; 386 387 ioat_acquire(&ioat->dmaengine); 388 389 /* Submit 'NULL' operation manually to avoid quiescing flag */ 390 desc = ioat_get_ring_entry(ioat, ioat->head); 391 dmadesc = &desc->bus_dmadesc; 392 hw_desc = desc->u.dma; 393 394 dmadesc->callback_fn = NULL; 395 dmadesc->callback_arg = NULL; 396 397 hw_desc->u.control_raw = 0; 398 hw_desc->u.control_generic.op = IOAT_OP_COPY; 399 hw_desc->u.control_generic.completion_update = 1; 400 hw_desc->size = 8; 401 hw_desc->src_addr = 0; 402 hw_desc->dest_addr = 0; 403 hw_desc->u.control.null = 1; 404 405 ioat_submit_single(ioat); 406 ioat_release(&ioat->dmaengine); 407 408 for (i = 0; i < 100; i++) { 409 DELAY(1); 410 status = ioat_get_chansts(ioat); 411 if (is_ioat_idle(status)) 412 return (0); 413 } 414 415 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 416 ioat_log_message(0, "could not start channel: " 417 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 418 IOAT_CHANERR_STR); 419 return (ENXIO); 420 } 421 422 /* 423 * Initialize Hardware 424 */ 425 static int 426 ioat3_attach(device_t device) 427 { 428 struct ioat_softc *ioat; 429 struct ioat_descriptor **ring; 430 struct ioat_descriptor *next; 431 struct ioat_dma_hw_descriptor *dma_hw_desc; 432 int i, num_descriptors; 433 int error; 434 uint8_t xfercap; 435 436 error = 0; 437 ioat = DEVICE2SOFTC(device); 438 ioat->capabilities = ioat_read_dmacapability(ioat); 439 440 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 441 IOAT_DMACAP_STR); 442 443 xfercap = ioat_read_xfercap(ioat); 444 ioat->max_xfer_size = 1 << xfercap; 445 446 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 447 IOAT_INTRDELAY_SUPPORTED) != 0; 448 if (ioat->intrdelay_supported) 449 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 450 451 /* TODO: need to check DCA here if we ever do XOR/PQ */ 452 453 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 454 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 455 callout_init(&ioat->poll_timer, 1); 456 callout_init(&ioat->shrink_timer, 1); 457 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 458 459 /* Establish lock order for Witness */ 460 mtx_lock(&ioat->submit_lock); 461 mtx_lock(&ioat->cleanup_lock); 462 mtx_unlock(&ioat->cleanup_lock); 463 mtx_unlock(&ioat->submit_lock); 464 465 ioat->is_resize_pending = FALSE; 466 ioat->is_submitter_processing = FALSE; 467 ioat->is_completion_pending = FALSE; 468 ioat->is_reset_pending = FALSE; 469 ioat->is_channel_running = FALSE; 470 471 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 472 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 473 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 474 &ioat->comp_update_tag); 475 476 error = bus_dmamem_alloc(ioat->comp_update_tag, 477 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 478 if (ioat->comp_update == NULL) 479 return (ENOMEM); 480 481 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 482 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 483 0); 484 if (error != 0) 485 return (error); 486 487 ioat->ring_size_order = IOAT_MIN_ORDER; 488 489 num_descriptors = 1 << ioat->ring_size_order; 490 491 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 492 BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL, 493 sizeof(struct ioat_dma_hw_descriptor), 1, 494 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 495 &ioat->hw_desc_tag); 496 497 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 498 M_ZERO | M_WAITOK); 499 500 ring = ioat->ring; 501 for (i = 0; i < num_descriptors; i++) { 502 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 503 if (ring[i] == NULL) 504 return (ENOMEM); 505 506 ring[i]->id = i; 507 } 508 509 for (i = 0; i < num_descriptors - 1; i++) { 510 next = ring[i + 1]; 511 dma_hw_desc = ring[i]->u.dma; 512 513 dma_hw_desc->next = next->hw_desc_bus_addr; 514 } 515 516 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 517 518 ioat->head = ioat->hw_head = 0; 519 ioat->tail = 0; 520 ioat->last_seen = 0; 521 *ioat->comp_update = 0; 522 return (0); 523 } 524 525 static int 526 ioat_map_pci_bar(struct ioat_softc *ioat) 527 { 528 529 ioat->pci_resource_id = PCIR_BAR(0); 530 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 531 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 532 533 if (ioat->pci_resource == NULL) { 534 ioat_log_message(0, "unable to allocate pci resource\n"); 535 return (ENODEV); 536 } 537 538 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 539 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 540 return (0); 541 } 542 543 static void 544 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 545 { 546 struct ioat_softc *ioat = arg; 547 548 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 549 ioat->comp_update_bus_addr = seg[0].ds_addr; 550 } 551 552 static void 553 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 554 { 555 bus_addr_t *baddr; 556 557 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 558 baddr = arg; 559 *baddr = segs->ds_addr; 560 } 561 562 /* 563 * Interrupt setup and handlers 564 */ 565 static int 566 ioat_setup_intr(struct ioat_softc *ioat) 567 { 568 uint32_t num_vectors; 569 int error; 570 boolean_t use_msix; 571 boolean_t force_legacy_interrupts; 572 573 use_msix = FALSE; 574 force_legacy_interrupts = FALSE; 575 576 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 577 num_vectors = 1; 578 pci_alloc_msix(ioat->device, &num_vectors); 579 if (num_vectors == 1) 580 use_msix = TRUE; 581 } 582 583 if (use_msix) { 584 ioat->rid = 1; 585 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 586 &ioat->rid, RF_ACTIVE); 587 } else { 588 ioat->rid = 0; 589 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 590 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 591 } 592 if (ioat->res == NULL) { 593 ioat_log_message(0, "bus_alloc_resource failed\n"); 594 return (ENOMEM); 595 } 596 597 ioat->tag = NULL; 598 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 599 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 600 if (error != 0) { 601 ioat_log_message(0, "bus_setup_intr failed\n"); 602 return (error); 603 } 604 605 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 606 return (0); 607 } 608 609 static boolean_t 610 ioat_model_resets_msix(struct ioat_softc *ioat) 611 { 612 u_int32_t pciid; 613 614 pciid = pci_get_devid(ioat->device); 615 switch (pciid) { 616 /* BWD: */ 617 case 0x0c508086: 618 case 0x0c518086: 619 case 0x0c528086: 620 case 0x0c538086: 621 /* BDXDE: */ 622 case 0x6f508086: 623 case 0x6f518086: 624 case 0x6f528086: 625 case 0x6f538086: 626 return (TRUE); 627 } 628 629 return (FALSE); 630 } 631 632 static void 633 ioat_interrupt_handler(void *arg) 634 { 635 struct ioat_softc *ioat = arg; 636 637 ioat->stats.interrupts++; 638 ioat_process_events(ioat); 639 } 640 641 static int 642 chanerr_to_errno(uint32_t chanerr) 643 { 644 645 if (chanerr == 0) 646 return (0); 647 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 648 return (EFAULT); 649 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 650 return (EIO); 651 /* This one is probably our fault: */ 652 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 653 return (EIO); 654 return (EIO); 655 } 656 657 static void 658 ioat_process_events(struct ioat_softc *ioat) 659 { 660 struct ioat_descriptor *desc; 661 struct bus_dmadesc *dmadesc; 662 uint64_t comp_update, status; 663 uint32_t completed, chanerr; 664 boolean_t pending; 665 int error; 666 667 mtx_lock(&ioat->cleanup_lock); 668 669 /* 670 * Don't run while the hardware is being reset. Reset is responsible 671 * for blocking new work and draining & completing existing work, so 672 * there is nothing to do until new work is queued after reset anyway. 673 */ 674 if (ioat->resetting_cleanup) { 675 mtx_unlock(&ioat->cleanup_lock); 676 return; 677 } 678 679 completed = 0; 680 comp_update = *ioat->comp_update; 681 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 682 683 if (status == ioat->last_seen) { 684 /* 685 * If we landed in process_events and nothing has been 686 * completed, check for a timeout due to channel halt. 687 */ 688 goto out; 689 } 690 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx", 691 __func__, ioat->chan_idx, comp_update, ioat->last_seen); 692 693 desc = ioat_get_ring_entry(ioat, ioat->tail - 1); 694 while (desc->hw_desc_bus_addr != status) { 695 desc = ioat_get_ring_entry(ioat, ioat->tail); 696 dmadesc = &desc->bus_dmadesc; 697 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) ok cb %p(%p)", 698 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 699 dmadesc->callback_arg); 700 701 if (dmadesc->callback_fn != NULL) 702 dmadesc->callback_fn(dmadesc->callback_arg, 0); 703 704 completed++; 705 ioat->tail++; 706 } 707 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 708 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 709 710 if (completed != 0) { 711 ioat->last_seen = desc->hw_desc_bus_addr; 712 ioat->stats.descriptors_processed += completed; 713 } 714 715 out: 716 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 717 718 /* Perform a racy check first; only take the locks if it passes. */ 719 pending = (ioat_get_active(ioat) != 0); 720 if (!pending && ioat->is_completion_pending) { 721 mtx_unlock(&ioat->cleanup_lock); 722 mtx_lock(&ioat->submit_lock); 723 mtx_lock(&ioat->cleanup_lock); 724 725 pending = (ioat_get_active(ioat) != 0); 726 if (!pending && ioat->is_completion_pending) { 727 ioat->is_completion_pending = FALSE; 728 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 729 ioat_shrink_timer_callback, ioat); 730 callout_stop(&ioat->poll_timer); 731 } 732 mtx_unlock(&ioat->submit_lock); 733 } 734 mtx_unlock(&ioat->cleanup_lock); 735 736 if (pending) 737 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 738 ioat); 739 740 if (completed != 0) { 741 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 742 wakeup(&ioat->tail); 743 } 744 745 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 746 return; 747 748 ioat->stats.channel_halts++; 749 750 /* 751 * Fatal programming error on this DMA channel. Flush any outstanding 752 * work with error status and restart the engine. 753 */ 754 mtx_lock(&ioat->submit_lock); 755 mtx_lock(&ioat->cleanup_lock); 756 ioat->quiescing = TRUE; 757 758 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 759 if (1 <= g_ioat_debug_level) 760 ioat_halted_debug(ioat, chanerr); 761 ioat->stats.last_halt_chanerr = chanerr; 762 763 while (ioat_get_active(ioat) > 0) { 764 desc = ioat_get_ring_entry(ioat, ioat->tail); 765 dmadesc = &desc->bus_dmadesc; 766 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) err cb %p(%p)", 767 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 768 dmadesc->callback_arg); 769 770 if (dmadesc->callback_fn != NULL) 771 dmadesc->callback_fn(dmadesc->callback_arg, 772 chanerr_to_errno(chanerr)); 773 774 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 775 ioat->tail++; 776 ioat->stats.descriptors_processed++; 777 ioat->stats.descriptors_error++; 778 } 779 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 780 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 781 782 if (ioat->is_completion_pending) { 783 ioat->is_completion_pending = FALSE; 784 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 785 ioat_shrink_timer_callback, ioat); 786 callout_stop(&ioat->poll_timer); 787 } 788 789 /* Clear error status */ 790 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 791 792 mtx_unlock(&ioat->cleanup_lock); 793 mtx_unlock(&ioat->submit_lock); 794 795 ioat_log_message(0, "Resetting channel to recover from error\n"); 796 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 797 KASSERT(error == 0, 798 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 799 } 800 801 static void 802 ioat_reset_hw_task(void *ctx, int pending __unused) 803 { 804 struct ioat_softc *ioat; 805 int error; 806 807 ioat = ctx; 808 ioat_log_message(1, "%s: Resetting channel\n", __func__); 809 810 error = ioat_reset_hw(ioat); 811 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 812 (void)error; 813 } 814 815 /* 816 * User API functions 817 */ 818 unsigned 819 ioat_get_nchannels(void) 820 { 821 822 return (ioat_channel_index); 823 } 824 825 bus_dmaengine_t 826 ioat_get_dmaengine(uint32_t index, int flags) 827 { 828 struct ioat_softc *ioat; 829 830 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 831 ("invalid flags: 0x%08x", flags)); 832 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 833 ("invalid wait | nowait")); 834 835 if (index >= ioat_channel_index) 836 return (NULL); 837 838 ioat = ioat_channel[index]; 839 if (ioat == NULL || ioat->destroying) 840 return (NULL); 841 842 if (ioat->quiescing) { 843 if ((flags & M_NOWAIT) != 0) 844 return (NULL); 845 846 mtx_lock(IOAT_REFLK); 847 while (ioat->quiescing && !ioat->destroying) 848 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 849 mtx_unlock(IOAT_REFLK); 850 851 if (ioat->destroying) 852 return (NULL); 853 } 854 855 /* 856 * There's a race here between the quiescing check and HW reset or 857 * module destroy. 858 */ 859 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 860 } 861 862 void 863 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 864 { 865 struct ioat_softc *ioat; 866 867 ioat = to_ioat_softc(dmaengine); 868 ioat_put(ioat, IOAT_DMAENGINE_REF); 869 } 870 871 int 872 ioat_get_hwversion(bus_dmaengine_t dmaengine) 873 { 874 struct ioat_softc *ioat; 875 876 ioat = to_ioat_softc(dmaengine); 877 return (ioat->version); 878 } 879 880 size_t 881 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 882 { 883 struct ioat_softc *ioat; 884 885 ioat = to_ioat_softc(dmaengine); 886 return (ioat->max_xfer_size); 887 } 888 889 uint32_t 890 ioat_get_capabilities(bus_dmaengine_t dmaengine) 891 { 892 struct ioat_softc *ioat; 893 894 ioat = to_ioat_softc(dmaengine); 895 return (ioat->capabilities); 896 } 897 898 int 899 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 900 { 901 struct ioat_softc *ioat; 902 903 ioat = to_ioat_softc(dmaengine); 904 if (!ioat->intrdelay_supported) 905 return (ENODEV); 906 if (delay > ioat->intrdelay_max) 907 return (ERANGE); 908 909 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 910 ioat->cached_intrdelay = 911 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 912 return (0); 913 } 914 915 uint16_t 916 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 917 { 918 struct ioat_softc *ioat; 919 920 ioat = to_ioat_softc(dmaengine); 921 return (ioat->intrdelay_max); 922 } 923 924 void 925 ioat_acquire(bus_dmaengine_t dmaengine) 926 { 927 struct ioat_softc *ioat; 928 929 ioat = to_ioat_softc(dmaengine); 930 mtx_lock(&ioat->submit_lock); 931 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 932 } 933 934 int 935 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 936 { 937 struct ioat_softc *ioat; 938 int error; 939 940 ioat = to_ioat_softc(dmaengine); 941 ioat_acquire(dmaengine); 942 943 error = ioat_reserve_space(ioat, n, mflags); 944 if (error != 0) 945 ioat_release(dmaengine); 946 return (error); 947 } 948 949 void 950 ioat_release(bus_dmaengine_t dmaengine) 951 { 952 struct ioat_softc *ioat; 953 954 ioat = to_ioat_softc(dmaengine); 955 CTR4(KTR_IOAT, "%s channel=%u dispatch1 hw_head=%u head=%u", __func__, 956 ioat->chan_idx, ioat->hw_head & UINT16_MAX, ioat->head); 957 KFAIL_POINT_CODE(DEBUG_FP, ioat_release, /* do nothing */); 958 CTR4(KTR_IOAT, "%s channel=%u dispatch2 hw_head=%u head=%u", __func__, 959 ioat->chan_idx, ioat->hw_head & UINT16_MAX, ioat->head); 960 961 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 962 963 if (!ioat->is_completion_pending) { 964 ioat->is_completion_pending = TRUE; 965 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 966 ioat); 967 callout_stop(&ioat->shrink_timer); 968 } 969 mtx_unlock(&ioat->submit_lock); 970 } 971 972 static struct ioat_descriptor * 973 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 974 uint32_t size, uint64_t src, uint64_t dst, 975 bus_dmaengine_callback_t callback_fn, void *callback_arg, 976 uint32_t flags) 977 { 978 struct ioat_generic_hw_descriptor *hw_desc; 979 struct ioat_descriptor *desc; 980 int mflags; 981 982 mtx_assert(&ioat->submit_lock, MA_OWNED); 983 984 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 985 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 986 if ((flags & DMA_NO_WAIT) != 0) 987 mflags = M_NOWAIT; 988 else 989 mflags = M_WAITOK; 990 991 if (size > ioat->max_xfer_size) { 992 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 993 __func__, ioat->max_xfer_size, (unsigned)size); 994 return (NULL); 995 } 996 997 if (ioat_reserve_space(ioat, 1, mflags) != 0) 998 return (NULL); 999 1000 desc = ioat_get_ring_entry(ioat, ioat->head); 1001 hw_desc = desc->u.generic; 1002 1003 hw_desc->u.control_raw = 0; 1004 hw_desc->u.control_generic.op = op; 1005 hw_desc->u.control_generic.completion_update = 1; 1006 1007 if ((flags & DMA_INT_EN) != 0) 1008 hw_desc->u.control_generic.int_enable = 1; 1009 if ((flags & DMA_FENCE) != 0) 1010 hw_desc->u.control_generic.fence = 1; 1011 1012 hw_desc->size = size; 1013 hw_desc->src_addr = src; 1014 hw_desc->dest_addr = dst; 1015 1016 desc->bus_dmadesc.callback_fn = callback_fn; 1017 desc->bus_dmadesc.callback_arg = callback_arg; 1018 return (desc); 1019 } 1020 1021 struct bus_dmadesc * 1022 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1023 void *callback_arg, uint32_t flags) 1024 { 1025 struct ioat_dma_hw_descriptor *hw_desc; 1026 struct ioat_descriptor *desc; 1027 struct ioat_softc *ioat; 1028 1029 ioat = to_ioat_softc(dmaengine); 1030 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1031 1032 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1033 callback_arg, flags); 1034 if (desc == NULL) 1035 return (NULL); 1036 1037 hw_desc = desc->u.dma; 1038 hw_desc->u.control.null = 1; 1039 ioat_submit_single(ioat); 1040 return (&desc->bus_dmadesc); 1041 } 1042 1043 struct bus_dmadesc * 1044 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1045 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1046 void *callback_arg, uint32_t flags) 1047 { 1048 struct ioat_dma_hw_descriptor *hw_desc; 1049 struct ioat_descriptor *desc; 1050 struct ioat_softc *ioat; 1051 1052 ioat = to_ioat_softc(dmaengine); 1053 1054 if (((src | dst) & (0xffffull << 48)) != 0) { 1055 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1056 __func__); 1057 return (NULL); 1058 } 1059 1060 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1061 callback_arg, flags); 1062 if (desc == NULL) 1063 return (NULL); 1064 1065 hw_desc = desc->u.dma; 1066 if (g_ioat_debug_level >= 3) 1067 dump_descriptor(hw_desc); 1068 1069 ioat_submit_single(ioat); 1070 CTR6(KTR_IOAT, "%s channel=%u desc=%p dest=%lx src=%lx len=%lx", 1071 __func__, ioat->chan_idx, &desc->bus_dmadesc, dst, src, len); 1072 return (&desc->bus_dmadesc); 1073 } 1074 1075 struct bus_dmadesc * 1076 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1077 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1078 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1079 { 1080 struct ioat_dma_hw_descriptor *hw_desc; 1081 struct ioat_descriptor *desc; 1082 struct ioat_softc *ioat; 1083 1084 ioat = to_ioat_softc(dmaengine); 1085 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1086 1087 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 1088 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1089 __func__); 1090 return (NULL); 1091 } 1092 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 1093 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 1094 __func__); 1095 return (NULL); 1096 } 1097 1098 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 1099 callback_fn, callback_arg, flags); 1100 if (desc == NULL) 1101 return (NULL); 1102 1103 hw_desc = desc->u.dma; 1104 if (src2 != src1 + PAGE_SIZE) { 1105 hw_desc->u.control.src_page_break = 1; 1106 hw_desc->next_src_addr = src2; 1107 } 1108 if (dst2 != dst1 + PAGE_SIZE) { 1109 hw_desc->u.control.dest_page_break = 1; 1110 hw_desc->next_dest_addr = dst2; 1111 } 1112 1113 if (g_ioat_debug_level >= 3) 1114 dump_descriptor(hw_desc); 1115 1116 ioat_submit_single(ioat); 1117 return (&desc->bus_dmadesc); 1118 } 1119 1120 struct bus_dmadesc * 1121 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1122 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1123 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1124 { 1125 struct ioat_crc32_hw_descriptor *hw_desc; 1126 struct ioat_descriptor *desc; 1127 struct ioat_softc *ioat; 1128 uint32_t teststore; 1129 uint8_t op; 1130 1131 ioat = to_ioat_softc(dmaengine); 1132 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1133 1134 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1135 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1136 __func__); 1137 return (NULL); 1138 } 1139 if (((src | dst) & (0xffffffull << 40)) != 0) { 1140 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1141 __func__); 1142 return (NULL); 1143 } 1144 teststore = (flags & _DMA_CRC_TESTSTORE); 1145 if (teststore == _DMA_CRC_TESTSTORE) { 1146 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1147 return (NULL); 1148 } 1149 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1150 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1151 __func__); 1152 return (NULL); 1153 } 1154 1155 switch (teststore) { 1156 case DMA_CRC_STORE: 1157 op = IOAT_OP_MOVECRC_STORE; 1158 break; 1159 case DMA_CRC_TEST: 1160 op = IOAT_OP_MOVECRC_TEST; 1161 break; 1162 default: 1163 KASSERT(teststore == 0, ("bogus")); 1164 op = IOAT_OP_MOVECRC; 1165 break; 1166 } 1167 1168 if ((flags & DMA_CRC_INLINE) == 0 && 1169 (crcptr & (0xffffffull << 40)) != 0) { 1170 ioat_log_message(0, 1171 "%s: High 24 bits of crcptr invalid\n", __func__); 1172 return (NULL); 1173 } 1174 1175 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1176 callback_arg, flags & ~_DMA_CRC_FLAGS); 1177 if (desc == NULL) 1178 return (NULL); 1179 1180 hw_desc = desc->u.crc32; 1181 1182 if ((flags & DMA_CRC_INLINE) == 0) 1183 hw_desc->crc_address = crcptr; 1184 else 1185 hw_desc->u.control.crc_location = 1; 1186 1187 if (initialseed != NULL) { 1188 hw_desc->u.control.use_seed = 1; 1189 hw_desc->seed = *initialseed; 1190 } 1191 1192 if (g_ioat_debug_level >= 3) 1193 dump_descriptor(hw_desc); 1194 1195 ioat_submit_single(ioat); 1196 return (&desc->bus_dmadesc); 1197 } 1198 1199 struct bus_dmadesc * 1200 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1201 uint32_t *initialseed, bus_addr_t crcptr, 1202 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1203 { 1204 struct ioat_crc32_hw_descriptor *hw_desc; 1205 struct ioat_descriptor *desc; 1206 struct ioat_softc *ioat; 1207 uint32_t teststore; 1208 uint8_t op; 1209 1210 ioat = to_ioat_softc(dmaengine); 1211 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1212 1213 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1214 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1215 __func__); 1216 return (NULL); 1217 } 1218 if ((src & (0xffffffull << 40)) != 0) { 1219 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1220 __func__); 1221 return (NULL); 1222 } 1223 teststore = (flags & _DMA_CRC_TESTSTORE); 1224 if (teststore == _DMA_CRC_TESTSTORE) { 1225 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1226 return (NULL); 1227 } 1228 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1229 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1230 __func__); 1231 return (NULL); 1232 } 1233 1234 switch (teststore) { 1235 case DMA_CRC_STORE: 1236 op = IOAT_OP_CRC_STORE; 1237 break; 1238 case DMA_CRC_TEST: 1239 op = IOAT_OP_CRC_TEST; 1240 break; 1241 default: 1242 KASSERT(teststore == 0, ("bogus")); 1243 op = IOAT_OP_CRC; 1244 break; 1245 } 1246 1247 if ((flags & DMA_CRC_INLINE) == 0 && 1248 (crcptr & (0xffffffull << 40)) != 0) { 1249 ioat_log_message(0, 1250 "%s: High 24 bits of crcptr invalid\n", __func__); 1251 return (NULL); 1252 } 1253 1254 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1255 callback_arg, flags & ~_DMA_CRC_FLAGS); 1256 if (desc == NULL) 1257 return (NULL); 1258 1259 hw_desc = desc->u.crc32; 1260 1261 if ((flags & DMA_CRC_INLINE) == 0) 1262 hw_desc->crc_address = crcptr; 1263 else 1264 hw_desc->u.control.crc_location = 1; 1265 1266 if (initialseed != NULL) { 1267 hw_desc->u.control.use_seed = 1; 1268 hw_desc->seed = *initialseed; 1269 } 1270 1271 if (g_ioat_debug_level >= 3) 1272 dump_descriptor(hw_desc); 1273 1274 ioat_submit_single(ioat); 1275 return (&desc->bus_dmadesc); 1276 } 1277 1278 struct bus_dmadesc * 1279 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1280 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1281 uint32_t flags) 1282 { 1283 struct ioat_fill_hw_descriptor *hw_desc; 1284 struct ioat_descriptor *desc; 1285 struct ioat_softc *ioat; 1286 1287 ioat = to_ioat_softc(dmaengine); 1288 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1289 1290 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1291 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1292 __func__); 1293 return (NULL); 1294 } 1295 1296 if ((dst & (0xffffull << 48)) != 0) { 1297 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1298 __func__); 1299 return (NULL); 1300 } 1301 1302 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1303 callback_fn, callback_arg, flags); 1304 if (desc == NULL) 1305 return (NULL); 1306 1307 hw_desc = desc->u.fill; 1308 if (g_ioat_debug_level >= 3) 1309 dump_descriptor(hw_desc); 1310 1311 ioat_submit_single(ioat); 1312 return (&desc->bus_dmadesc); 1313 } 1314 1315 /* 1316 * Ring Management 1317 */ 1318 static inline uint32_t 1319 ioat_get_active(struct ioat_softc *ioat) 1320 { 1321 1322 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1323 } 1324 1325 static inline uint32_t 1326 ioat_get_ring_space(struct ioat_softc *ioat) 1327 { 1328 1329 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1330 } 1331 1332 static struct ioat_descriptor * 1333 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 1334 { 1335 struct ioat_generic_hw_descriptor *hw_desc; 1336 struct ioat_descriptor *desc; 1337 int error, busdmaflag; 1338 1339 error = ENOMEM; 1340 hw_desc = NULL; 1341 1342 if ((mflags & M_WAITOK) != 0) 1343 busdmaflag = BUS_DMA_WAITOK; 1344 else 1345 busdmaflag = BUS_DMA_NOWAIT; 1346 1347 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1348 if (desc == NULL) 1349 goto out; 1350 1351 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1352 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1353 if (hw_desc == NULL) 1354 goto out; 1355 1356 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1357 desc->u.generic = hw_desc; 1358 1359 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1360 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1361 busdmaflag); 1362 if (error) 1363 goto out; 1364 1365 out: 1366 if (error) { 1367 ioat_free_ring_entry(ioat, desc); 1368 return (NULL); 1369 } 1370 return (desc); 1371 } 1372 1373 static void 1374 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1375 { 1376 1377 if (desc == NULL) 1378 return; 1379 1380 if (desc->u.generic) 1381 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1382 ioat->hw_desc_map); 1383 free(desc, M_IOAT); 1384 } 1385 1386 /* 1387 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1388 * for 'num_descs'. 1389 * 1390 * If mflags contains M_WAITOK, blocks until enough space is available. 1391 * 1392 * Returns zero on success, or an errno on error. If num_descs is beyond the 1393 * maximum ring size, returns EINVAl; if allocation would block and mflags 1394 * contains M_NOWAIT, returns EAGAIN. 1395 * 1396 * Must be called with the submit_lock held; returns with the lock held. The 1397 * lock may be dropped to allocate the ring. 1398 * 1399 * (The submit_lock is needed to add any entries to the ring, so callers are 1400 * assured enough room is available.) 1401 */ 1402 static int 1403 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1404 { 1405 struct ioat_descriptor **new_ring; 1406 uint32_t order; 1407 boolean_t dug; 1408 int error; 1409 1410 mtx_assert(&ioat->submit_lock, MA_OWNED); 1411 error = 0; 1412 dug = FALSE; 1413 1414 if (num_descs < 1 || num_descs >= (1 << IOAT_MAX_ORDER)) { 1415 error = EINVAL; 1416 goto out; 1417 } 1418 1419 for (;;) { 1420 if (ioat->quiescing) { 1421 error = ENXIO; 1422 goto out; 1423 } 1424 1425 if (ioat_get_ring_space(ioat) >= num_descs) 1426 goto out; 1427 1428 CTR3(KTR_IOAT, "%s channel=%u starved (%u)", __func__, 1429 ioat->chan_idx, num_descs); 1430 1431 if (!dug && !ioat->is_submitter_processing && 1432 (1 << ioat->ring_size_order) > num_descs) { 1433 ioat->is_submitter_processing = TRUE; 1434 mtx_unlock(&ioat->submit_lock); 1435 1436 CTR2(KTR_IOAT, "%s channel=%u attempting to process events", 1437 __func__, ioat->chan_idx); 1438 ioat_process_events(ioat); 1439 1440 mtx_lock(&ioat->submit_lock); 1441 dug = TRUE; 1442 KASSERT(ioat->is_submitter_processing == TRUE, 1443 ("is_submitter_processing")); 1444 ioat->is_submitter_processing = FALSE; 1445 wakeup(&ioat->tail); 1446 continue; 1447 } 1448 1449 order = ioat->ring_size_order; 1450 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1451 if ((mflags & M_WAITOK) != 0) { 1452 CTR2(KTR_IOAT, "%s channel=%u blocking on completions", 1453 __func__, ioat->chan_idx); 1454 msleep(&ioat->tail, &ioat->submit_lock, 0, 1455 "ioat_rsz", 0); 1456 continue; 1457 } 1458 1459 error = EAGAIN; 1460 break; 1461 } 1462 1463 ioat->is_resize_pending = TRUE; 1464 for (;;) { 1465 mtx_unlock(&ioat->submit_lock); 1466 1467 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1468 TRUE, mflags); 1469 1470 mtx_lock(&ioat->submit_lock); 1471 KASSERT(ioat->ring_size_order == order, 1472 ("is_resize_pending should protect order")); 1473 1474 if (new_ring == NULL) { 1475 KASSERT((mflags & M_WAITOK) == 0, 1476 ("allocation failed")); 1477 error = EAGAIN; 1478 break; 1479 } 1480 1481 error = ring_grow(ioat, order, new_ring); 1482 if (error == 0) 1483 break; 1484 } 1485 ioat->is_resize_pending = FALSE; 1486 wakeup(&ioat->tail); 1487 if (error) 1488 break; 1489 } 1490 1491 out: 1492 mtx_assert(&ioat->submit_lock, MA_OWNED); 1493 KASSERT(!ioat->quiescing || error == ENXIO, 1494 ("reserved during quiesce")); 1495 return (error); 1496 } 1497 1498 static struct ioat_descriptor ** 1499 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1500 int mflags) 1501 { 1502 struct ioat_descriptor **ring; 1503 uint32_t i; 1504 int error; 1505 1506 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1507 1508 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1509 if (ring == NULL) 1510 return (NULL); 1511 1512 if (need_dscr) { 1513 error = ENOMEM; 1514 for (i = size / 2; i < size; i++) { 1515 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1516 if (ring[i] == NULL) 1517 goto out; 1518 ring[i]->id = i; 1519 } 1520 } 1521 error = 0; 1522 1523 out: 1524 if (error != 0 && ring != NULL) { 1525 ioat_free_ring(ioat, size, ring); 1526 ring = NULL; 1527 } 1528 return (ring); 1529 } 1530 1531 static void 1532 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1533 struct ioat_descriptor **ring) 1534 { 1535 uint32_t i; 1536 1537 for (i = 0; i < size; i++) { 1538 if (ring[i] != NULL) 1539 ioat_free_ring_entry(ioat, ring[i]); 1540 } 1541 free(ring, M_IOAT); 1542 } 1543 1544 static struct ioat_descriptor * 1545 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1546 { 1547 1548 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1549 } 1550 1551 static int 1552 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1553 struct ioat_descriptor **newring) 1554 { 1555 struct ioat_descriptor *tmp, *next; 1556 struct ioat_dma_hw_descriptor *hw; 1557 uint32_t oldsize, newsize, head, tail, i, end; 1558 int error; 1559 1560 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1561 1562 mtx_assert(&ioat->submit_lock, MA_OWNED); 1563 1564 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1565 error = EINVAL; 1566 goto out; 1567 } 1568 1569 oldsize = (1 << oldorder); 1570 newsize = (1 << (oldorder + 1)); 1571 1572 mtx_lock(&ioat->cleanup_lock); 1573 1574 head = ioat->head & (oldsize - 1); 1575 tail = ioat->tail & (oldsize - 1); 1576 1577 /* Copy old descriptors to new ring */ 1578 for (i = 0; i < oldsize; i++) 1579 newring[i] = ioat->ring[i]; 1580 1581 /* 1582 * If head has wrapped but tail hasn't, we must swap some descriptors 1583 * around so that tail can increment directly to head. 1584 */ 1585 if (head < tail) { 1586 for (i = 0; i <= head; i++) { 1587 tmp = newring[oldsize + i]; 1588 1589 newring[oldsize + i] = newring[i]; 1590 newring[oldsize + i]->id = oldsize + i; 1591 1592 newring[i] = tmp; 1593 newring[i]->id = i; 1594 } 1595 head += oldsize; 1596 } 1597 1598 KASSERT(head >= tail, ("invariants")); 1599 1600 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1601 if (head < oldsize) { 1602 i = oldsize - 1; 1603 end = newsize; 1604 } else { 1605 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1606 i = head; 1607 end = newsize + (head - oldsize) + 1; 1608 } 1609 1610 /* 1611 * Fix up hardware ring, being careful not to trample the active 1612 * section (tail -> head). 1613 */ 1614 for (; i < end; i++) { 1615 KASSERT((i & (newsize - 1)) < tail || 1616 (i & (newsize - 1)) >= head, ("trampling snake")); 1617 1618 next = newring[(i + 1) & (newsize - 1)]; 1619 hw = newring[i & (newsize - 1)]->u.dma; 1620 hw->next = next->hw_desc_bus_addr; 1621 } 1622 1623 #ifdef INVARIANTS 1624 for (i = 0; i < newsize; i++) { 1625 next = newring[(i + 1) & (newsize - 1)]; 1626 hw = newring[i & (newsize - 1)]->u.dma; 1627 1628 KASSERT(hw->next == next->hw_desc_bus_addr, 1629 ("mismatch at i:%u (oldsize:%u); next=%p nextaddr=0x%lx" 1630 " (tail:%u)", i, oldsize, next, next->hw_desc_bus_addr, 1631 tail)); 1632 } 1633 #endif 1634 1635 free(ioat->ring, M_IOAT); 1636 ioat->ring = newring; 1637 ioat->ring_size_order = oldorder + 1; 1638 ioat->tail = tail; 1639 ioat->head = head; 1640 error = 0; 1641 1642 mtx_unlock(&ioat->cleanup_lock); 1643 out: 1644 if (error) 1645 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1646 return (error); 1647 } 1648 1649 static int 1650 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1651 struct ioat_descriptor **newring) 1652 { 1653 struct ioat_dma_hw_descriptor *hw; 1654 struct ioat_descriptor *ent, *next; 1655 uint32_t oldsize, newsize, current_idx, new_idx, i; 1656 int error; 1657 1658 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1659 1660 mtx_assert(&ioat->submit_lock, MA_OWNED); 1661 1662 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1663 error = EINVAL; 1664 goto out_unlocked; 1665 } 1666 1667 oldsize = (1 << oldorder); 1668 newsize = (1 << (oldorder - 1)); 1669 1670 mtx_lock(&ioat->cleanup_lock); 1671 1672 /* Can't shrink below current active set! */ 1673 if (ioat_get_active(ioat) >= newsize) { 1674 error = ENOMEM; 1675 goto out; 1676 } 1677 1678 /* 1679 * Copy current descriptors to the new ring, dropping the removed 1680 * descriptors. 1681 */ 1682 for (i = 0; i < newsize; i++) { 1683 current_idx = (ioat->tail + i) & (oldsize - 1); 1684 new_idx = (ioat->tail + i) & (newsize - 1); 1685 1686 newring[new_idx] = ioat->ring[current_idx]; 1687 newring[new_idx]->id = new_idx; 1688 } 1689 1690 /* Free deleted descriptors */ 1691 for (i = newsize; i < oldsize; i++) { 1692 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1693 ioat_free_ring_entry(ioat, ent); 1694 } 1695 1696 /* Fix up hardware ring. */ 1697 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1698 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1699 hw->next = next->hw_desc_bus_addr; 1700 1701 #ifdef INVARIANTS 1702 for (i = 0; i < newsize; i++) { 1703 next = newring[(i + 1) & (newsize - 1)]; 1704 hw = newring[i & (newsize - 1)]->u.dma; 1705 1706 KASSERT(hw->next == next->hw_desc_bus_addr, 1707 ("mismatch at i:%u (newsize:%u); next=%p nextaddr=0x%lx " 1708 "(tail:%u)", i, newsize, next, next->hw_desc_bus_addr, 1709 ioat->tail)); 1710 } 1711 #endif 1712 1713 free(ioat->ring, M_IOAT); 1714 ioat->ring = newring; 1715 ioat->ring_size_order = oldorder - 1; 1716 error = 0; 1717 1718 out: 1719 mtx_unlock(&ioat->cleanup_lock); 1720 out_unlocked: 1721 if (error) 1722 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1723 return (error); 1724 } 1725 1726 static void 1727 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1728 { 1729 struct ioat_descriptor *desc; 1730 1731 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1732 IOAT_CHANERR_STR); 1733 if (chanerr == 0) 1734 return; 1735 1736 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1737 1738 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1739 dump_descriptor(desc->u.raw); 1740 1741 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1742 dump_descriptor(desc->u.raw); 1743 } 1744 1745 static void 1746 ioat_poll_timer_callback(void *arg) 1747 { 1748 struct ioat_softc *ioat; 1749 1750 ioat = arg; 1751 ioat_log_message(3, "%s\n", __func__); 1752 1753 ioat_process_events(ioat); 1754 } 1755 1756 static void 1757 ioat_shrink_timer_callback(void *arg) 1758 { 1759 struct ioat_descriptor **newring; 1760 struct ioat_softc *ioat; 1761 uint32_t order; 1762 1763 ioat = arg; 1764 ioat_log_message(1, "%s\n", __func__); 1765 1766 /* Slowly scale the ring down if idle. */ 1767 mtx_lock(&ioat->submit_lock); 1768 1769 /* Don't run while the hardware is being reset. */ 1770 if (ioat->resetting) { 1771 mtx_unlock(&ioat->submit_lock); 1772 return; 1773 } 1774 1775 order = ioat->ring_size_order; 1776 if (ioat->is_completion_pending || ioat->is_resize_pending || 1777 order == IOAT_MIN_ORDER) { 1778 mtx_unlock(&ioat->submit_lock); 1779 goto out; 1780 } 1781 ioat->is_resize_pending = TRUE; 1782 mtx_unlock(&ioat->submit_lock); 1783 1784 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1785 M_NOWAIT); 1786 1787 mtx_lock(&ioat->submit_lock); 1788 KASSERT(ioat->ring_size_order == order, 1789 ("resize_pending protects order")); 1790 1791 if (newring != NULL && !ioat->is_completion_pending) 1792 ring_shrink(ioat, order, newring); 1793 else if (newring != NULL) 1794 ioat_free_ring(ioat, (1 << (order - 1)), newring); 1795 1796 ioat->is_resize_pending = FALSE; 1797 mtx_unlock(&ioat->submit_lock); 1798 1799 out: 1800 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1801 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 1802 ioat_shrink_timer_callback, ioat); 1803 } 1804 1805 /* 1806 * Support Functions 1807 */ 1808 static void 1809 ioat_submit_single(struct ioat_softc *ioat) 1810 { 1811 1812 mtx_assert(&ioat->submit_lock, MA_OWNED); 1813 1814 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1815 atomic_add_rel_int(&ioat->head, 1); 1816 atomic_add_rel_int(&ioat->hw_head, 1); 1817 CTR5(KTR_IOAT, "%s channel=%u head=%u hw_head=%u tail=%u", __func__, 1818 ioat->chan_idx, ioat->head, ioat->hw_head & UINT16_MAX, 1819 ioat->tail); 1820 1821 ioat->stats.descriptors_submitted++; 1822 } 1823 1824 static int 1825 ioat_reset_hw(struct ioat_softc *ioat) 1826 { 1827 uint64_t status; 1828 uint32_t chanerr; 1829 unsigned timeout; 1830 int error; 1831 1832 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1833 1834 mtx_lock(IOAT_REFLK); 1835 while (ioat->resetting && !ioat->destroying) 1836 msleep(&ioat->resetting, IOAT_REFLK, 0, "IRH_drain", 0); 1837 if (ioat->destroying) { 1838 mtx_unlock(IOAT_REFLK); 1839 return (ENXIO); 1840 } 1841 ioat->resetting = TRUE; 1842 1843 ioat->quiescing = TRUE; 1844 ioat_drain_locked(ioat); 1845 mtx_unlock(IOAT_REFLK); 1846 1847 /* 1848 * Suspend ioat_process_events while the hardware and softc are in an 1849 * indeterminate state. 1850 */ 1851 mtx_lock(&ioat->cleanup_lock); 1852 ioat->resetting_cleanup = TRUE; 1853 mtx_unlock(&ioat->cleanup_lock); 1854 1855 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__, 1856 ioat->chan_idx); 1857 1858 status = ioat_get_chansts(ioat); 1859 if (is_ioat_active(status) || is_ioat_idle(status)) 1860 ioat_suspend(ioat); 1861 1862 /* Wait at most 20 ms */ 1863 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1864 timeout < 20; timeout++) { 1865 DELAY(1000); 1866 status = ioat_get_chansts(ioat); 1867 } 1868 if (timeout == 20) { 1869 error = ETIMEDOUT; 1870 goto out; 1871 } 1872 1873 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1874 1875 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1876 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1877 1878 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__, 1879 ioat->chan_idx); 1880 1881 /* 1882 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1883 * that can cause stability issues for IOAT v3. 1884 */ 1885 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1886 4); 1887 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1888 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1889 1890 /* 1891 * BDXDE and BWD models reset MSI-X registers on device reset. 1892 * Save/restore their contents manually. 1893 */ 1894 if (ioat_model_resets_msix(ioat)) { 1895 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1896 pci_save_state(ioat->device); 1897 } 1898 1899 ioat_reset(ioat); 1900 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__, 1901 ioat->chan_idx); 1902 1903 /* Wait at most 20 ms */ 1904 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1905 DELAY(1000); 1906 if (timeout == 20) { 1907 error = ETIMEDOUT; 1908 goto out; 1909 } 1910 1911 if (ioat_model_resets_msix(ioat)) { 1912 ioat_log_message(1, "device resets registers; restored\n"); 1913 pci_restore_state(ioat->device); 1914 } 1915 1916 /* Reset attempts to return the hardware to "halted." */ 1917 status = ioat_get_chansts(ioat); 1918 if (is_ioat_active(status) || is_ioat_idle(status)) { 1919 /* So this really shouldn't happen... */ 1920 ioat_log_message(0, "Device is active after a reset?\n"); 1921 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1922 error = 0; 1923 goto out; 1924 } 1925 1926 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1927 if (chanerr != 0) { 1928 mtx_lock(&ioat->cleanup_lock); 1929 ioat_halted_debug(ioat, chanerr); 1930 mtx_unlock(&ioat->cleanup_lock); 1931 error = EIO; 1932 goto out; 1933 } 1934 1935 /* 1936 * Bring device back online after reset. Writing CHAINADDR brings the 1937 * device back to active. 1938 * 1939 * The internal ring counter resets to zero, so we have to start over 1940 * at zero as well. 1941 */ 1942 ioat->tail = ioat->head = ioat->hw_head = 0; 1943 ioat->last_seen = 0; 1944 *ioat->comp_update = 0; 1945 KASSERT(!ioat->is_completion_pending, ("bogus completion_pending")); 1946 1947 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1948 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1949 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1950 error = 0; 1951 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__, 1952 ioat->chan_idx); 1953 1954 out: 1955 /* Enqueues a null operation and ensures it completes. */ 1956 if (error == 0) { 1957 error = ioat_start_channel(ioat); 1958 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__, 1959 ioat->chan_idx); 1960 } 1961 1962 /* 1963 * Resume completions now that ring state is consistent. 1964 */ 1965 mtx_lock(&ioat->cleanup_lock); 1966 ioat->resetting_cleanup = FALSE; 1967 mtx_unlock(&ioat->cleanup_lock); 1968 1969 /* Unblock submission of new work */ 1970 mtx_lock(IOAT_REFLK); 1971 ioat->quiescing = FALSE; 1972 wakeup(&ioat->quiescing); 1973 1974 ioat->resetting = FALSE; 1975 wakeup(&ioat->resetting); 1976 1977 if (ioat->is_completion_pending) 1978 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 1979 ioat); 1980 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx); 1981 mtx_unlock(IOAT_REFLK); 1982 1983 return (error); 1984 } 1985 1986 static int 1987 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1988 { 1989 struct ioat_softc *ioat; 1990 struct sbuf sb; 1991 uint64_t status; 1992 int error; 1993 1994 ioat = arg1; 1995 1996 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1997 1998 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1999 switch (status) { 2000 case IOAT_CHANSTS_ACTIVE: 2001 sbuf_printf(&sb, "ACTIVE"); 2002 break; 2003 case IOAT_CHANSTS_IDLE: 2004 sbuf_printf(&sb, "IDLE"); 2005 break; 2006 case IOAT_CHANSTS_SUSPENDED: 2007 sbuf_printf(&sb, "SUSPENDED"); 2008 break; 2009 case IOAT_CHANSTS_HALTED: 2010 sbuf_printf(&sb, "HALTED"); 2011 break; 2012 case IOAT_CHANSTS_ARMED: 2013 sbuf_printf(&sb, "ARMED"); 2014 break; 2015 default: 2016 sbuf_printf(&sb, "UNKNOWN"); 2017 break; 2018 } 2019 error = sbuf_finish(&sb); 2020 sbuf_delete(&sb); 2021 2022 if (error != 0 || req->newptr == NULL) 2023 return (error); 2024 return (EINVAL); 2025 } 2026 2027 static int 2028 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 2029 { 2030 struct ioat_softc *ioat; 2031 struct sbuf sb; 2032 #define PRECISION "1" 2033 const uintmax_t factor = 10; 2034 uintmax_t rate; 2035 int error; 2036 2037 ioat = arg1; 2038 sbuf_new_for_sysctl(&sb, NULL, 16, req); 2039 2040 if (ioat->stats.interrupts == 0) { 2041 sbuf_printf(&sb, "NaN"); 2042 goto out; 2043 } 2044 rate = ioat->stats.descriptors_processed * factor / 2045 ioat->stats.interrupts; 2046 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 2047 rate % factor); 2048 #undef PRECISION 2049 out: 2050 error = sbuf_finish(&sb); 2051 sbuf_delete(&sb); 2052 if (error != 0 || req->newptr == NULL) 2053 return (error); 2054 return (EINVAL); 2055 } 2056 2057 static int 2058 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 2059 { 2060 struct ioat_softc *ioat; 2061 int error, arg; 2062 2063 ioat = arg1; 2064 2065 arg = 0; 2066 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 2067 if (error != 0 || req->newptr == NULL) 2068 return (error); 2069 2070 error = SYSCTL_IN(req, &arg, sizeof(arg)); 2071 if (error != 0) 2072 return (error); 2073 2074 if (arg != 0) 2075 error = ioat_reset_hw(ioat); 2076 2077 return (error); 2078 } 2079 2080 static void 2081 dump_descriptor(void *hw_desc) 2082 { 2083 int i, j; 2084 2085 for (i = 0; i < 2; i++) { 2086 for (j = 0; j < 8; j++) 2087 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 2088 printf("\n"); 2089 } 2090 } 2091 2092 static void 2093 ioat_setup_sysctl(device_t device) 2094 { 2095 struct sysctl_oid_list *par, *statpar, *state, *hammer; 2096 struct sysctl_ctx_list *ctx; 2097 struct sysctl_oid *tree, *tmp; 2098 struct ioat_softc *ioat; 2099 2100 ioat = DEVICE2SOFTC(device); 2101 ctx = device_get_sysctl_ctx(device); 2102 tree = device_get_sysctl_tree(device); 2103 par = SYSCTL_CHILDREN(tree); 2104 2105 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 2106 &ioat->version, 0, "HW version (0xMM form)"); 2107 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 2108 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 2109 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 2110 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 2111 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 2112 &ioat->intrdelay_max, 0, 2113 "Maximum configurable INTRDELAY on this channel (microseconds)"); 2114 2115 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 2116 "IOAT channel internal state"); 2117 state = SYSCTL_CHILDREN(tmp); 2118 2119 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 2120 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 2121 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 2122 0, "SW descriptor head pointer index"); 2123 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 2124 0, "SW descriptor tail pointer index"); 2125 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 2126 &ioat->hw_head, 0, "HW DMACOUNT"); 2127 2128 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 2129 ioat->comp_update, "HW addr of last completion"); 2130 2131 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 2132 &ioat->is_resize_pending, 0, "resize pending"); 2133 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 2134 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 2135 "submitter processing"); 2136 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 2137 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 2138 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 2139 &ioat->is_reset_pending, 0, "reset pending"); 2140 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 2141 &ioat->is_channel_running, 0, "channel running"); 2142 2143 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 2144 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 2145 "String of the channel status"); 2146 2147 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 2148 &ioat->cached_intrdelay, 0, 2149 "Current INTRDELAY on this channel (cached, microseconds)"); 2150 2151 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 2152 "Big hammers (mostly for testing)"); 2153 hammer = SYSCTL_CHILDREN(tmp); 2154 2155 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 2156 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 2157 "Set to non-zero to reset the hardware"); 2158 2159 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 2160 "IOAT channel statistics"); 2161 statpar = SYSCTL_CHILDREN(tmp); 2162 2163 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 2164 &ioat->stats.interrupts, 2165 "Number of interrupts processed on this channel"); 2166 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 2167 &ioat->stats.descriptors_processed, 2168 "Number of descriptors processed on this channel"); 2169 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 2170 &ioat->stats.descriptors_submitted, 2171 "Number of descriptors submitted to this channel"); 2172 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 2173 &ioat->stats.descriptors_error, 2174 "Number of descriptors failed by channel errors"); 2175 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 2176 &ioat->stats.channel_halts, 0, 2177 "Number of times the channel has halted"); 2178 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 2179 &ioat->stats.last_halt_chanerr, 0, 2180 "The raw CHANERR when the channel was last halted"); 2181 2182 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 2183 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 2184 "Descriptors per interrupt"); 2185 } 2186 2187 static inline struct ioat_softc * 2188 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2189 { 2190 uint32_t old; 2191 2192 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2193 2194 old = atomic_fetchadd_32(&ioat->refcnt, 1); 2195 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 2196 2197 #ifdef INVARIANTS 2198 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 2199 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 2200 #endif 2201 2202 return (ioat); 2203 } 2204 2205 static inline void 2206 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2207 { 2208 2209 _ioat_putn(ioat, n, kind, FALSE); 2210 } 2211 2212 static inline void 2213 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2214 { 2215 2216 _ioat_putn(ioat, n, kind, TRUE); 2217 } 2218 2219 static inline void 2220 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 2221 boolean_t locked) 2222 { 2223 uint32_t old; 2224 2225 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2226 2227 if (n == 0) 2228 return; 2229 2230 #ifdef INVARIANTS 2231 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 2232 KASSERT(old >= n, ("refcnt kind underflow")); 2233 #endif 2234 2235 /* Skip acquiring the lock if resulting refcnt > 0. */ 2236 for (;;) { 2237 old = ioat->refcnt; 2238 if (old <= n) 2239 break; 2240 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 2241 return; 2242 } 2243 2244 if (locked) 2245 mtx_assert(IOAT_REFLK, MA_OWNED); 2246 else 2247 mtx_lock(IOAT_REFLK); 2248 2249 old = atomic_fetchadd_32(&ioat->refcnt, -n); 2250 KASSERT(old >= n, ("refcnt error")); 2251 2252 if (old == n) 2253 wakeup(IOAT_REFLK); 2254 if (!locked) 2255 mtx_unlock(IOAT_REFLK); 2256 } 2257 2258 static inline void 2259 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2260 { 2261 2262 ioat_putn(ioat, 1, kind); 2263 } 2264 2265 static void 2266 ioat_drain_locked(struct ioat_softc *ioat) 2267 { 2268 2269 mtx_assert(IOAT_REFLK, MA_OWNED); 2270 while (ioat->refcnt > 0) 2271 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 2272 } 2273 2274 #ifdef DDB 2275 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 2276 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 2277 DB_SHOW_COMMAND(ioat, db_show_ioat) 2278 { 2279 struct ioat_softc *sc; 2280 unsigned idx; 2281 2282 if (!have_addr) 2283 goto usage; 2284 idx = (unsigned)addr; 2285 if (idx >= ioat_channel_index) 2286 goto usage; 2287 2288 sc = ioat_channel[idx]; 2289 db_printf("ioat softc at %p\n", sc); 2290 if (sc == NULL) 2291 return; 2292 2293 db_printf(" version: %d\n", sc->version); 2294 db_printf(" chan_idx: %u\n", sc->chan_idx); 2295 db_printf(" submit_lock: "); 2296 db_show_lock(&sc->submit_lock); 2297 2298 db_printf(" capabilities: %b\n", (int)sc->capabilities, 2299 IOAT_DMACAP_STR); 2300 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 2301 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 2302 2303 db_printf(" poll_timer:\n"); 2304 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 2305 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 2306 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 2307 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 2308 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 2309 2310 db_printf(" shrink_timer:\n"); 2311 db_printf(" c_time: %ju\n", (uintmax_t)sc->shrink_timer.c_time); 2312 db_printf(" c_arg: %p\n", sc->shrink_timer.c_arg); 2313 db_printf(" c_func: %p\n", sc->shrink_timer.c_func); 2314 db_printf(" c_lock: %p\n", sc->shrink_timer.c_lock); 2315 db_printf(" c_flags: 0x%x\n", (unsigned)sc->shrink_timer.c_flags); 2316 2317 db_printf(" quiescing: %d\n", (int)sc->quiescing); 2318 db_printf(" destroying: %d\n", (int)sc->destroying); 2319 db_printf(" is_resize_pending: %d\n", (int)sc->is_resize_pending); 2320 db_printf(" is_submitter_processing: %d\n", 2321 (int)sc->is_submitter_processing); 2322 db_printf(" is_completion_pending: %d\n", (int)sc->is_completion_pending); 2323 db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending); 2324 db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running); 2325 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 2326 db_printf(" resetting: %d\n", (int)sc->resetting); 2327 2328 db_printf(" head: %u\n", sc->head); 2329 db_printf(" tail: %u\n", sc->tail); 2330 db_printf(" hw_head: %u\n", sc->hw_head); 2331 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2332 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2333 db_printf(" ring: %p\n", sc->ring); 2334 2335 db_printf(" ring[%u] (tail):\n", sc->tail % 2336 (1 << sc->ring_size_order)); 2337 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 2338 db_printf(" addr: 0x%lx\n", 2339 ioat_get_ring_entry(sc, sc->tail)->hw_desc_bus_addr); 2340 db_printf(" next: 0x%lx\n", 2341 ioat_get_ring_entry(sc, sc->tail)->u.generic->next); 2342 2343 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 2344 (1 << sc->ring_size_order)); 2345 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 2346 db_printf(" addr: 0x%lx\n", 2347 ioat_get_ring_entry(sc, sc->head - 1)->hw_desc_bus_addr); 2348 db_printf(" next: 0x%lx\n", 2349 ioat_get_ring_entry(sc, sc->head - 1)->u.generic->next); 2350 2351 db_printf(" ring[%u] (head):\n", (sc->head) % 2352 (1 << sc->ring_size_order)); 2353 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2354 db_printf(" addr: 0x%lx\n", 2355 ioat_get_ring_entry(sc, sc->head)->hw_desc_bus_addr); 2356 db_printf(" next: 0x%lx\n", 2357 ioat_get_ring_entry(sc, sc->head)->u.generic->next); 2358 2359 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2360 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2361 == ioat_get_ring_entry(sc, idx)->hw_desc_bus_addr) 2362 db_printf(" ring[%u] == hardware tail\n", idx); 2363 2364 db_printf(" cleanup_lock: "); 2365 db_show_lock(&sc->cleanup_lock); 2366 2367 db_printf(" refcnt: %u\n", sc->refcnt); 2368 #ifdef INVARIANTS 2369 CTASSERT(IOAT_NUM_REF_KINDS == 2); 2370 db_printf(" refkinds: [ENG=%u, DESCR=%u]\n", sc->refkinds[0], 2371 sc->refkinds[1]); 2372 #endif 2373 db_printf(" stats:\n"); 2374 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2375 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2376 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2377 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2378 2379 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2380 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2381 2382 if (db_pager_quit) 2383 return; 2384 2385 db_printf(" hw status:\n"); 2386 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2387 db_printf(" chanctrl: 0x%x\n", 2388 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2389 db_printf(" chancmd: 0x%x\n", 2390 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2391 db_printf(" dmacount: 0x%x\n", 2392 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2393 db_printf(" chainaddr: 0x%lx\n", 2394 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2395 db_printf(" chancmp: 0x%lx\n", 2396 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2397 db_printf(" chanerr: %b\n", 2398 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2399 return; 2400 usage: 2401 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2402 return; 2403 } 2404 #endif /* DDB */ 2405