1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ddb.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/ioccom.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/sbuf.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #include <machine/stdarg.h> 52 53 #ifdef DDB 54 #include <ddb/ddb.h> 55 #endif 56 57 #include "ioat.h" 58 #include "ioat_hw.h" 59 #include "ioat_internal.h" 60 61 #ifndef BUS_SPACE_MAXADDR_40BIT 62 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 63 #endif 64 #define IOAT_REFLK (&ioat->submit_lock) 65 #define IOAT_SHRINK_PERIOD (10 * hz) 66 67 static int ioat_probe(device_t device); 68 static int ioat_attach(device_t device); 69 static int ioat_detach(device_t device); 70 static int ioat_setup_intr(struct ioat_softc *ioat); 71 static int ioat_teardown_intr(struct ioat_softc *ioat); 72 static int ioat3_attach(device_t device); 73 static int ioat_start_channel(struct ioat_softc *ioat); 74 static int ioat_map_pci_bar(struct ioat_softc *ioat); 75 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 76 int error); 77 static void ioat_interrupt_handler(void *arg); 78 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 79 static int chanerr_to_errno(uint32_t); 80 static void ioat_process_events(struct ioat_softc *ioat); 81 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 82 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 83 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 84 struct ioat_descriptor **); 85 static void ioat_free_ring_entry(struct ioat_softc *ioat, 86 struct ioat_descriptor *desc); 87 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 88 int mflags); 89 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 90 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 91 uint32_t index); 92 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 93 uint32_t size, boolean_t need_dscr, int mflags); 94 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 95 struct ioat_descriptor **); 96 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 97 struct ioat_descriptor **); 98 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 99 static void ioat_poll_timer_callback(void *arg); 100 static void ioat_shrink_timer_callback(void *arg); 101 static void dump_descriptor(void *hw_desc); 102 static void ioat_submit_single(struct ioat_softc *ioat); 103 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 104 int error); 105 static int ioat_reset_hw(struct ioat_softc *ioat); 106 static void ioat_reset_hw_task(void *, int); 107 static void ioat_setup_sysctl(device_t device); 108 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 109 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 110 enum ioat_ref_kind); 111 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 112 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 113 enum ioat_ref_kind, boolean_t); 114 static inline void ioat_putn(struct ioat_softc *, uint32_t, 115 enum ioat_ref_kind); 116 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 117 enum ioat_ref_kind); 118 static void ioat_drain_locked(struct ioat_softc *); 119 120 #define ioat_log_message(v, ...) do { \ 121 if ((v) <= g_ioat_debug_level) { \ 122 device_printf(ioat->device, __VA_ARGS__); \ 123 } \ 124 } while (0) 125 126 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 127 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 128 129 static int g_force_legacy_interrupts; 130 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 131 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 132 133 int g_ioat_debug_level = 0; 134 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 135 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 136 137 /* 138 * OS <-> Driver interface structures 139 */ 140 static device_method_t ioat_pci_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, ioat_probe), 143 DEVMETHOD(device_attach, ioat_attach), 144 DEVMETHOD(device_detach, ioat_detach), 145 DEVMETHOD_END 146 }; 147 148 static driver_t ioat_pci_driver = { 149 "ioat", 150 ioat_pci_methods, 151 sizeof(struct ioat_softc), 152 }; 153 154 static devclass_t ioat_devclass; 155 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 156 MODULE_VERSION(ioat, 1); 157 158 /* 159 * Private data structures 160 */ 161 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 162 static unsigned ioat_channel_index = 0; 163 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 164 "Number of IOAT channels attached"); 165 166 static struct _pcsid 167 { 168 u_int32_t type; 169 const char *desc; 170 } pci_ids[] = { 171 { 0x34308086, "TBG IOAT Ch0" }, 172 { 0x34318086, "TBG IOAT Ch1" }, 173 { 0x34328086, "TBG IOAT Ch2" }, 174 { 0x34338086, "TBG IOAT Ch3" }, 175 { 0x34298086, "TBG IOAT Ch4" }, 176 { 0x342a8086, "TBG IOAT Ch5" }, 177 { 0x342b8086, "TBG IOAT Ch6" }, 178 { 0x342c8086, "TBG IOAT Ch7" }, 179 180 { 0x37108086, "JSF IOAT Ch0" }, 181 { 0x37118086, "JSF IOAT Ch1" }, 182 { 0x37128086, "JSF IOAT Ch2" }, 183 { 0x37138086, "JSF IOAT Ch3" }, 184 { 0x37148086, "JSF IOAT Ch4" }, 185 { 0x37158086, "JSF IOAT Ch5" }, 186 { 0x37168086, "JSF IOAT Ch6" }, 187 { 0x37178086, "JSF IOAT Ch7" }, 188 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 189 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 190 191 { 0x3c208086, "SNB IOAT Ch0" }, 192 { 0x3c218086, "SNB IOAT Ch1" }, 193 { 0x3c228086, "SNB IOAT Ch2" }, 194 { 0x3c238086, "SNB IOAT Ch3" }, 195 { 0x3c248086, "SNB IOAT Ch4" }, 196 { 0x3c258086, "SNB IOAT Ch5" }, 197 { 0x3c268086, "SNB IOAT Ch6" }, 198 { 0x3c278086, "SNB IOAT Ch7" }, 199 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 200 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 201 202 { 0x0e208086, "IVB IOAT Ch0" }, 203 { 0x0e218086, "IVB IOAT Ch1" }, 204 { 0x0e228086, "IVB IOAT Ch2" }, 205 { 0x0e238086, "IVB IOAT Ch3" }, 206 { 0x0e248086, "IVB IOAT Ch4" }, 207 { 0x0e258086, "IVB IOAT Ch5" }, 208 { 0x0e268086, "IVB IOAT Ch6" }, 209 { 0x0e278086, "IVB IOAT Ch7" }, 210 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 211 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 212 213 { 0x2f208086, "HSW IOAT Ch0" }, 214 { 0x2f218086, "HSW IOAT Ch1" }, 215 { 0x2f228086, "HSW IOAT Ch2" }, 216 { 0x2f238086, "HSW IOAT Ch3" }, 217 { 0x2f248086, "HSW IOAT Ch4" }, 218 { 0x2f258086, "HSW IOAT Ch5" }, 219 { 0x2f268086, "HSW IOAT Ch6" }, 220 { 0x2f278086, "HSW IOAT Ch7" }, 221 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 222 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 223 224 { 0x0c508086, "BWD IOAT Ch0" }, 225 { 0x0c518086, "BWD IOAT Ch1" }, 226 { 0x0c528086, "BWD IOAT Ch2" }, 227 { 0x0c538086, "BWD IOAT Ch3" }, 228 229 { 0x6f508086, "BDXDE IOAT Ch0" }, 230 { 0x6f518086, "BDXDE IOAT Ch1" }, 231 { 0x6f528086, "BDXDE IOAT Ch2" }, 232 { 0x6f538086, "BDXDE IOAT Ch3" }, 233 234 { 0x6f208086, "BDX IOAT Ch0" }, 235 { 0x6f218086, "BDX IOAT Ch1" }, 236 { 0x6f228086, "BDX IOAT Ch2" }, 237 { 0x6f238086, "BDX IOAT Ch3" }, 238 { 0x6f248086, "BDX IOAT Ch4" }, 239 { 0x6f258086, "BDX IOAT Ch5" }, 240 { 0x6f268086, "BDX IOAT Ch6" }, 241 { 0x6f278086, "BDX IOAT Ch7" }, 242 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 243 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 244 245 { 0x00000000, NULL } 246 }; 247 248 /* 249 * OS <-> Driver linkage functions 250 */ 251 static int 252 ioat_probe(device_t device) 253 { 254 struct _pcsid *ep; 255 u_int32_t type; 256 257 type = pci_get_devid(device); 258 for (ep = pci_ids; ep->type; ep++) { 259 if (ep->type == type) { 260 device_set_desc(device, ep->desc); 261 return (0); 262 } 263 } 264 return (ENXIO); 265 } 266 267 static int 268 ioat_attach(device_t device) 269 { 270 struct ioat_softc *ioat; 271 int error; 272 273 ioat = DEVICE2SOFTC(device); 274 ioat->device = device; 275 276 error = ioat_map_pci_bar(ioat); 277 if (error != 0) 278 goto err; 279 280 ioat->version = ioat_read_cbver(ioat); 281 if (ioat->version < IOAT_VER_3_0) { 282 error = ENODEV; 283 goto err; 284 } 285 286 error = ioat3_attach(device); 287 if (error != 0) 288 goto err; 289 290 error = pci_enable_busmaster(device); 291 if (error != 0) 292 goto err; 293 294 error = ioat_setup_intr(ioat); 295 if (error != 0) 296 goto err; 297 298 error = ioat_reset_hw(ioat); 299 if (error != 0) 300 goto err; 301 302 ioat_process_events(ioat); 303 ioat_setup_sysctl(device); 304 305 ioat->chan_idx = ioat_channel_index; 306 ioat_channel[ioat_channel_index++] = ioat; 307 ioat_test_attach(); 308 309 err: 310 if (error != 0) 311 ioat_detach(device); 312 return (error); 313 } 314 315 static int 316 ioat_detach(device_t device) 317 { 318 struct ioat_softc *ioat; 319 320 ioat = DEVICE2SOFTC(device); 321 322 ioat_test_detach(); 323 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 324 325 mtx_lock(IOAT_REFLK); 326 ioat->quiescing = TRUE; 327 ioat->destroying = TRUE; 328 wakeup(&ioat->quiescing); 329 wakeup(&ioat->resetting); 330 331 ioat_channel[ioat->chan_idx] = NULL; 332 333 ioat_drain_locked(ioat); 334 mtx_unlock(IOAT_REFLK); 335 336 ioat_teardown_intr(ioat); 337 callout_drain(&ioat->poll_timer); 338 callout_drain(&ioat->shrink_timer); 339 340 pci_disable_busmaster(device); 341 342 if (ioat->pci_resource != NULL) 343 bus_release_resource(device, SYS_RES_MEMORY, 344 ioat->pci_resource_id, ioat->pci_resource); 345 346 if (ioat->ring != NULL) 347 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 348 349 if (ioat->comp_update != NULL) { 350 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 351 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 352 ioat->comp_update_map); 353 bus_dma_tag_destroy(ioat->comp_update_tag); 354 } 355 356 bus_dma_tag_destroy(ioat->hw_desc_tag); 357 358 return (0); 359 } 360 361 static int 362 ioat_teardown_intr(struct ioat_softc *ioat) 363 { 364 365 if (ioat->tag != NULL) 366 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 367 368 if (ioat->res != NULL) 369 bus_release_resource(ioat->device, SYS_RES_IRQ, 370 rman_get_rid(ioat->res), ioat->res); 371 372 pci_release_msi(ioat->device); 373 return (0); 374 } 375 376 static int 377 ioat_start_channel(struct ioat_softc *ioat) 378 { 379 struct ioat_dma_hw_descriptor *hw_desc; 380 struct ioat_descriptor *desc; 381 struct bus_dmadesc *dmadesc; 382 uint64_t status; 383 uint32_t chanerr; 384 int i; 385 386 ioat_acquire(&ioat->dmaengine); 387 388 /* Submit 'NULL' operation manually to avoid quiescing flag */ 389 desc = ioat_get_ring_entry(ioat, ioat->head); 390 dmadesc = &desc->bus_dmadesc; 391 hw_desc = desc->u.dma; 392 393 dmadesc->callback_fn = NULL; 394 dmadesc->callback_arg = NULL; 395 396 hw_desc->u.control_raw = 0; 397 hw_desc->u.control_generic.op = IOAT_OP_COPY; 398 hw_desc->u.control_generic.completion_update = 1; 399 hw_desc->size = 8; 400 hw_desc->src_addr = 0; 401 hw_desc->dest_addr = 0; 402 hw_desc->u.control.null = 1; 403 404 ioat_submit_single(ioat); 405 ioat_release(&ioat->dmaengine); 406 407 for (i = 0; i < 100; i++) { 408 DELAY(1); 409 status = ioat_get_chansts(ioat); 410 if (is_ioat_idle(status)) 411 return (0); 412 } 413 414 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 415 ioat_log_message(0, "could not start channel: " 416 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 417 IOAT_CHANERR_STR); 418 return (ENXIO); 419 } 420 421 /* 422 * Initialize Hardware 423 */ 424 static int 425 ioat3_attach(device_t device) 426 { 427 struct ioat_softc *ioat; 428 struct ioat_descriptor **ring; 429 struct ioat_descriptor *next; 430 struct ioat_dma_hw_descriptor *dma_hw_desc; 431 int i, num_descriptors; 432 int error; 433 uint8_t xfercap; 434 435 error = 0; 436 ioat = DEVICE2SOFTC(device); 437 ioat->capabilities = ioat_read_dmacapability(ioat); 438 439 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 440 IOAT_DMACAP_STR); 441 442 xfercap = ioat_read_xfercap(ioat); 443 ioat->max_xfer_size = 1 << xfercap; 444 445 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 446 IOAT_INTRDELAY_SUPPORTED) != 0; 447 if (ioat->intrdelay_supported) 448 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 449 450 /* TODO: need to check DCA here if we ever do XOR/PQ */ 451 452 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 453 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 454 callout_init(&ioat->poll_timer, 1); 455 callout_init(&ioat->shrink_timer, 1); 456 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 457 458 /* Establish lock order for Witness */ 459 mtx_lock(&ioat->submit_lock); 460 mtx_lock(&ioat->cleanup_lock); 461 mtx_unlock(&ioat->cleanup_lock); 462 mtx_unlock(&ioat->submit_lock); 463 464 ioat->is_resize_pending = FALSE; 465 ioat->is_submitter_processing = FALSE; 466 ioat->is_completion_pending = FALSE; 467 ioat->is_reset_pending = FALSE; 468 ioat->is_channel_running = FALSE; 469 470 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 471 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 472 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 473 &ioat->comp_update_tag); 474 475 error = bus_dmamem_alloc(ioat->comp_update_tag, 476 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 477 if (ioat->comp_update == NULL) 478 return (ENOMEM); 479 480 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 481 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 482 0); 483 if (error != 0) 484 return (error); 485 486 ioat->ring_size_order = IOAT_MIN_ORDER; 487 488 num_descriptors = 1 << ioat->ring_size_order; 489 490 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 491 BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL, 492 sizeof(struct ioat_dma_hw_descriptor), 1, 493 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 494 &ioat->hw_desc_tag); 495 496 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 497 M_ZERO | M_WAITOK); 498 499 ring = ioat->ring; 500 for (i = 0; i < num_descriptors; i++) { 501 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 502 if (ring[i] == NULL) 503 return (ENOMEM); 504 505 ring[i]->id = i; 506 } 507 508 for (i = 0; i < num_descriptors - 1; i++) { 509 next = ring[i + 1]; 510 dma_hw_desc = ring[i]->u.dma; 511 512 dma_hw_desc->next = next->hw_desc_bus_addr; 513 } 514 515 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 516 517 ioat->head = ioat->hw_head = 0; 518 ioat->tail = 0; 519 ioat->last_seen = 0; 520 *ioat->comp_update = 0; 521 return (0); 522 } 523 524 static int 525 ioat_map_pci_bar(struct ioat_softc *ioat) 526 { 527 528 ioat->pci_resource_id = PCIR_BAR(0); 529 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 530 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 531 532 if (ioat->pci_resource == NULL) { 533 ioat_log_message(0, "unable to allocate pci resource\n"); 534 return (ENODEV); 535 } 536 537 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 538 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 539 return (0); 540 } 541 542 static void 543 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 544 { 545 struct ioat_softc *ioat = arg; 546 547 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 548 ioat->comp_update_bus_addr = seg[0].ds_addr; 549 } 550 551 static void 552 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 553 { 554 bus_addr_t *baddr; 555 556 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 557 baddr = arg; 558 *baddr = segs->ds_addr; 559 } 560 561 /* 562 * Interrupt setup and handlers 563 */ 564 static int 565 ioat_setup_intr(struct ioat_softc *ioat) 566 { 567 uint32_t num_vectors; 568 int error; 569 boolean_t use_msix; 570 boolean_t force_legacy_interrupts; 571 572 use_msix = FALSE; 573 force_legacy_interrupts = FALSE; 574 575 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 576 num_vectors = 1; 577 pci_alloc_msix(ioat->device, &num_vectors); 578 if (num_vectors == 1) 579 use_msix = TRUE; 580 } 581 582 if (use_msix) { 583 ioat->rid = 1; 584 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 585 &ioat->rid, RF_ACTIVE); 586 } else { 587 ioat->rid = 0; 588 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 589 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 590 } 591 if (ioat->res == NULL) { 592 ioat_log_message(0, "bus_alloc_resource failed\n"); 593 return (ENOMEM); 594 } 595 596 ioat->tag = NULL; 597 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 598 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 599 if (error != 0) { 600 ioat_log_message(0, "bus_setup_intr failed\n"); 601 return (error); 602 } 603 604 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 605 return (0); 606 } 607 608 static boolean_t 609 ioat_model_resets_msix(struct ioat_softc *ioat) 610 { 611 u_int32_t pciid; 612 613 pciid = pci_get_devid(ioat->device); 614 switch (pciid) { 615 /* BWD: */ 616 case 0x0c508086: 617 case 0x0c518086: 618 case 0x0c528086: 619 case 0x0c538086: 620 /* BDXDE: */ 621 case 0x6f508086: 622 case 0x6f518086: 623 case 0x6f528086: 624 case 0x6f538086: 625 return (TRUE); 626 } 627 628 return (FALSE); 629 } 630 631 static void 632 ioat_interrupt_handler(void *arg) 633 { 634 struct ioat_softc *ioat = arg; 635 636 ioat->stats.interrupts++; 637 ioat_process_events(ioat); 638 } 639 640 static int 641 chanerr_to_errno(uint32_t chanerr) 642 { 643 644 if (chanerr == 0) 645 return (0); 646 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 647 return (EFAULT); 648 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 649 return (EIO); 650 /* This one is probably our fault: */ 651 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 652 return (EIO); 653 return (EIO); 654 } 655 656 static void 657 ioat_process_events(struct ioat_softc *ioat) 658 { 659 struct ioat_descriptor *desc; 660 struct bus_dmadesc *dmadesc; 661 uint64_t comp_update, status; 662 uint32_t completed, chanerr; 663 boolean_t pending; 664 int error; 665 666 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 667 668 mtx_lock(&ioat->cleanup_lock); 669 670 /* 671 * Don't run while the hardware is being reset. Reset is responsible 672 * for blocking new work and draining & completing existing work, so 673 * there is nothing to do until new work is queued after reset anyway. 674 */ 675 if (ioat->resetting_cleanup) { 676 mtx_unlock(&ioat->cleanup_lock); 677 return; 678 } 679 680 completed = 0; 681 comp_update = ioat_get_chansts(ioat); 682 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx", 683 __func__, ioat->chan_idx, comp_update, ioat->last_seen); 684 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 685 686 if (status == ioat->last_seen) { 687 /* 688 * If we landed in process_events and nothing has been 689 * completed, check for a timeout due to channel halt. 690 */ 691 goto out; 692 } 693 694 desc = ioat_get_ring_entry(ioat, ioat->tail - 1); 695 while (desc->hw_desc_bus_addr != status && ioat_get_active(ioat) > 0) { 696 desc = ioat_get_ring_entry(ioat, ioat->tail); 697 dmadesc = &desc->bus_dmadesc; 698 CTR4(KTR_IOAT, "channel=%u completing desc %u ok cb %p(%p)", 699 ioat->chan_idx, ioat->tail, dmadesc->callback_fn, 700 dmadesc->callback_arg); 701 702 if (dmadesc->callback_fn != NULL) 703 dmadesc->callback_fn(dmadesc->callback_arg, 0); 704 705 completed++; 706 ioat->tail++; 707 } 708 709 if (completed != 0) { 710 ioat->last_seen = desc->hw_desc_bus_addr; 711 ioat->stats.descriptors_processed += completed; 712 } 713 714 out: 715 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 716 717 /* Perform a racy check first; only take the locks if it passes. */ 718 pending = (ioat_get_active(ioat) != 0); 719 if (!pending && ioat->is_completion_pending) { 720 mtx_unlock(&ioat->cleanup_lock); 721 mtx_lock(&ioat->submit_lock); 722 mtx_lock(&ioat->cleanup_lock); 723 724 pending = (ioat_get_active(ioat) != 0); 725 if (!pending && ioat->is_completion_pending) { 726 ioat->is_completion_pending = FALSE; 727 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 728 ioat_shrink_timer_callback, ioat); 729 callout_stop(&ioat->poll_timer); 730 } 731 mtx_unlock(&ioat->submit_lock); 732 } 733 mtx_unlock(&ioat->cleanup_lock); 734 735 if (pending) 736 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 737 ioat); 738 739 if (completed != 0) { 740 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 741 wakeup(&ioat->tail); 742 } 743 744 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 745 return; 746 747 ioat->stats.channel_halts++; 748 749 /* 750 * Fatal programming error on this DMA channel. Flush any outstanding 751 * work with error status and restart the engine. 752 */ 753 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 754 mtx_lock(&ioat->submit_lock); 755 mtx_lock(&ioat->cleanup_lock); 756 ioat->quiescing = TRUE; 757 758 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 759 ioat_halted_debug(ioat, chanerr); 760 ioat->stats.last_halt_chanerr = chanerr; 761 762 while (ioat_get_active(ioat) > 0) { 763 desc = ioat_get_ring_entry(ioat, ioat->tail); 764 dmadesc = &desc->bus_dmadesc; 765 CTR4(KTR_IOAT, "channel=%u completing desc %u err cb %p(%p)", 766 ioat->chan_idx, ioat->tail, dmadesc->callback_fn, 767 dmadesc->callback_arg); 768 769 if (dmadesc->callback_fn != NULL) 770 dmadesc->callback_fn(dmadesc->callback_arg, 771 chanerr_to_errno(chanerr)); 772 773 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 774 ioat->tail++; 775 ioat->stats.descriptors_processed++; 776 ioat->stats.descriptors_error++; 777 } 778 779 if (ioat->is_completion_pending) { 780 ioat->is_completion_pending = FALSE; 781 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 782 ioat_shrink_timer_callback, ioat); 783 callout_stop(&ioat->poll_timer); 784 } 785 786 /* Clear error status */ 787 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 788 789 mtx_unlock(&ioat->cleanup_lock); 790 mtx_unlock(&ioat->submit_lock); 791 792 ioat_log_message(0, "Resetting channel to recover from error\n"); 793 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 794 KASSERT(error == 0, 795 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 796 } 797 798 static void 799 ioat_reset_hw_task(void *ctx, int pending __unused) 800 { 801 struct ioat_softc *ioat; 802 int error; 803 804 ioat = ctx; 805 ioat_log_message(1, "%s: Resetting channel\n", __func__); 806 807 error = ioat_reset_hw(ioat); 808 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 809 (void)error; 810 } 811 812 /* 813 * User API functions 814 */ 815 unsigned 816 ioat_get_nchannels(void) 817 { 818 819 return (ioat_channel_index); 820 } 821 822 bus_dmaengine_t 823 ioat_get_dmaengine(uint32_t index, int flags) 824 { 825 struct ioat_softc *ioat; 826 827 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 828 ("invalid flags: 0x%08x", flags)); 829 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 830 ("invalid wait | nowait")); 831 832 if (index >= ioat_channel_index) 833 return (NULL); 834 835 ioat = ioat_channel[index]; 836 if (ioat == NULL || ioat->destroying) 837 return (NULL); 838 839 if (ioat->quiescing) { 840 if ((flags & M_NOWAIT) != 0) 841 return (NULL); 842 843 mtx_lock(IOAT_REFLK); 844 while (ioat->quiescing && !ioat->destroying) 845 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 846 mtx_unlock(IOAT_REFLK); 847 848 if (ioat->destroying) 849 return (NULL); 850 } 851 852 /* 853 * There's a race here between the quiescing check and HW reset or 854 * module destroy. 855 */ 856 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 857 } 858 859 void 860 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 861 { 862 struct ioat_softc *ioat; 863 864 ioat = to_ioat_softc(dmaengine); 865 ioat_put(ioat, IOAT_DMAENGINE_REF); 866 } 867 868 int 869 ioat_get_hwversion(bus_dmaengine_t dmaengine) 870 { 871 struct ioat_softc *ioat; 872 873 ioat = to_ioat_softc(dmaengine); 874 return (ioat->version); 875 } 876 877 size_t 878 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 879 { 880 struct ioat_softc *ioat; 881 882 ioat = to_ioat_softc(dmaengine); 883 return (ioat->max_xfer_size); 884 } 885 886 uint32_t 887 ioat_get_capabilities(bus_dmaengine_t dmaengine) 888 { 889 struct ioat_softc *ioat; 890 891 ioat = to_ioat_softc(dmaengine); 892 return (ioat->capabilities); 893 } 894 895 int 896 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 897 { 898 struct ioat_softc *ioat; 899 900 ioat = to_ioat_softc(dmaengine); 901 if (!ioat->intrdelay_supported) 902 return (ENODEV); 903 if (delay > ioat->intrdelay_max) 904 return (ERANGE); 905 906 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 907 ioat->cached_intrdelay = 908 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 909 return (0); 910 } 911 912 uint16_t 913 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 914 { 915 struct ioat_softc *ioat; 916 917 ioat = to_ioat_softc(dmaengine); 918 return (ioat->intrdelay_max); 919 } 920 921 void 922 ioat_acquire(bus_dmaengine_t dmaengine) 923 { 924 struct ioat_softc *ioat; 925 926 ioat = to_ioat_softc(dmaengine); 927 mtx_lock(&ioat->submit_lock); 928 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 929 } 930 931 int 932 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 933 { 934 struct ioat_softc *ioat; 935 int error; 936 937 ioat = to_ioat_softc(dmaengine); 938 ioat_acquire(dmaengine); 939 940 error = ioat_reserve_space(ioat, n, mflags); 941 if (error != 0) 942 ioat_release(dmaengine); 943 return (error); 944 } 945 946 void 947 ioat_release(bus_dmaengine_t dmaengine) 948 { 949 struct ioat_softc *ioat; 950 951 ioat = to_ioat_softc(dmaengine); 952 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 953 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 954 mtx_unlock(&ioat->submit_lock); 955 } 956 957 static struct ioat_descriptor * 958 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 959 uint32_t size, uint64_t src, uint64_t dst, 960 bus_dmaengine_callback_t callback_fn, void *callback_arg, 961 uint32_t flags) 962 { 963 struct ioat_generic_hw_descriptor *hw_desc; 964 struct ioat_descriptor *desc; 965 int mflags; 966 967 mtx_assert(&ioat->submit_lock, MA_OWNED); 968 969 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 970 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 971 if ((flags & DMA_NO_WAIT) != 0) 972 mflags = M_NOWAIT; 973 else 974 mflags = M_WAITOK; 975 976 if (size > ioat->max_xfer_size) { 977 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 978 __func__, ioat->max_xfer_size, (unsigned)size); 979 return (NULL); 980 } 981 982 if (ioat_reserve_space(ioat, 1, mflags) != 0) 983 return (NULL); 984 985 desc = ioat_get_ring_entry(ioat, ioat->head); 986 hw_desc = desc->u.generic; 987 988 hw_desc->u.control_raw = 0; 989 hw_desc->u.control_generic.op = op; 990 hw_desc->u.control_generic.completion_update = 1; 991 992 if ((flags & DMA_INT_EN) != 0) 993 hw_desc->u.control_generic.int_enable = 1; 994 if ((flags & DMA_FENCE) != 0) 995 hw_desc->u.control_generic.fence = 1; 996 997 hw_desc->size = size; 998 hw_desc->src_addr = src; 999 hw_desc->dest_addr = dst; 1000 1001 desc->bus_dmadesc.callback_fn = callback_fn; 1002 desc->bus_dmadesc.callback_arg = callback_arg; 1003 return (desc); 1004 } 1005 1006 struct bus_dmadesc * 1007 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1008 void *callback_arg, uint32_t flags) 1009 { 1010 struct ioat_dma_hw_descriptor *hw_desc; 1011 struct ioat_descriptor *desc; 1012 struct ioat_softc *ioat; 1013 1014 ioat = to_ioat_softc(dmaengine); 1015 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1016 1017 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1018 callback_arg, flags); 1019 if (desc == NULL) 1020 return (NULL); 1021 1022 hw_desc = desc->u.dma; 1023 hw_desc->u.control.null = 1; 1024 ioat_submit_single(ioat); 1025 return (&desc->bus_dmadesc); 1026 } 1027 1028 struct bus_dmadesc * 1029 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1030 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1031 void *callback_arg, uint32_t flags) 1032 { 1033 struct ioat_dma_hw_descriptor *hw_desc; 1034 struct ioat_descriptor *desc; 1035 struct ioat_softc *ioat; 1036 1037 ioat = to_ioat_softc(dmaengine); 1038 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1039 1040 if (((src | dst) & (0xffffull << 48)) != 0) { 1041 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1042 __func__); 1043 return (NULL); 1044 } 1045 1046 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1047 callback_arg, flags); 1048 if (desc == NULL) 1049 return (NULL); 1050 1051 hw_desc = desc->u.dma; 1052 if (g_ioat_debug_level >= 3) 1053 dump_descriptor(hw_desc); 1054 1055 ioat_submit_single(ioat); 1056 return (&desc->bus_dmadesc); 1057 } 1058 1059 struct bus_dmadesc * 1060 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1061 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1062 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1063 { 1064 struct ioat_dma_hw_descriptor *hw_desc; 1065 struct ioat_descriptor *desc; 1066 struct ioat_softc *ioat; 1067 1068 ioat = to_ioat_softc(dmaengine); 1069 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1070 1071 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 1072 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1073 __func__); 1074 return (NULL); 1075 } 1076 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 1077 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 1078 __func__); 1079 return (NULL); 1080 } 1081 1082 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 1083 callback_fn, callback_arg, flags); 1084 if (desc == NULL) 1085 return (NULL); 1086 1087 hw_desc = desc->u.dma; 1088 if (src2 != src1 + PAGE_SIZE) { 1089 hw_desc->u.control.src_page_break = 1; 1090 hw_desc->next_src_addr = src2; 1091 } 1092 if (dst2 != dst1 + PAGE_SIZE) { 1093 hw_desc->u.control.dest_page_break = 1; 1094 hw_desc->next_dest_addr = dst2; 1095 } 1096 1097 if (g_ioat_debug_level >= 3) 1098 dump_descriptor(hw_desc); 1099 1100 ioat_submit_single(ioat); 1101 return (&desc->bus_dmadesc); 1102 } 1103 1104 struct bus_dmadesc * 1105 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1106 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1107 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1108 { 1109 struct ioat_crc32_hw_descriptor *hw_desc; 1110 struct ioat_descriptor *desc; 1111 struct ioat_softc *ioat; 1112 uint32_t teststore; 1113 uint8_t op; 1114 1115 ioat = to_ioat_softc(dmaengine); 1116 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1117 1118 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1119 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1120 __func__); 1121 return (NULL); 1122 } 1123 if (((src | dst) & (0xffffffull << 40)) != 0) { 1124 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1125 __func__); 1126 return (NULL); 1127 } 1128 teststore = (flags & _DMA_CRC_TESTSTORE); 1129 if (teststore == _DMA_CRC_TESTSTORE) { 1130 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1131 return (NULL); 1132 } 1133 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1134 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1135 __func__); 1136 return (NULL); 1137 } 1138 1139 switch (teststore) { 1140 case DMA_CRC_STORE: 1141 op = IOAT_OP_MOVECRC_STORE; 1142 break; 1143 case DMA_CRC_TEST: 1144 op = IOAT_OP_MOVECRC_TEST; 1145 break; 1146 default: 1147 KASSERT(teststore == 0, ("bogus")); 1148 op = IOAT_OP_MOVECRC; 1149 break; 1150 } 1151 1152 if ((flags & DMA_CRC_INLINE) == 0 && 1153 (crcptr & (0xffffffull << 40)) != 0) { 1154 ioat_log_message(0, 1155 "%s: High 24 bits of crcptr invalid\n", __func__); 1156 return (NULL); 1157 } 1158 1159 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1160 callback_arg, flags & ~_DMA_CRC_FLAGS); 1161 if (desc == NULL) 1162 return (NULL); 1163 1164 hw_desc = desc->u.crc32; 1165 1166 if ((flags & DMA_CRC_INLINE) == 0) 1167 hw_desc->crc_address = crcptr; 1168 else 1169 hw_desc->u.control.crc_location = 1; 1170 1171 if (initialseed != NULL) { 1172 hw_desc->u.control.use_seed = 1; 1173 hw_desc->seed = *initialseed; 1174 } 1175 1176 if (g_ioat_debug_level >= 3) 1177 dump_descriptor(hw_desc); 1178 1179 ioat_submit_single(ioat); 1180 return (&desc->bus_dmadesc); 1181 } 1182 1183 struct bus_dmadesc * 1184 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1185 uint32_t *initialseed, bus_addr_t crcptr, 1186 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1187 { 1188 struct ioat_crc32_hw_descriptor *hw_desc; 1189 struct ioat_descriptor *desc; 1190 struct ioat_softc *ioat; 1191 uint32_t teststore; 1192 uint8_t op; 1193 1194 ioat = to_ioat_softc(dmaengine); 1195 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1196 1197 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1198 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1199 __func__); 1200 return (NULL); 1201 } 1202 if ((src & (0xffffffull << 40)) != 0) { 1203 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1204 __func__); 1205 return (NULL); 1206 } 1207 teststore = (flags & _DMA_CRC_TESTSTORE); 1208 if (teststore == _DMA_CRC_TESTSTORE) { 1209 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1210 return (NULL); 1211 } 1212 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1213 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1214 __func__); 1215 return (NULL); 1216 } 1217 1218 switch (teststore) { 1219 case DMA_CRC_STORE: 1220 op = IOAT_OP_CRC_STORE; 1221 break; 1222 case DMA_CRC_TEST: 1223 op = IOAT_OP_CRC_TEST; 1224 break; 1225 default: 1226 KASSERT(teststore == 0, ("bogus")); 1227 op = IOAT_OP_CRC; 1228 break; 1229 } 1230 1231 if ((flags & DMA_CRC_INLINE) == 0 && 1232 (crcptr & (0xffffffull << 40)) != 0) { 1233 ioat_log_message(0, 1234 "%s: High 24 bits of crcptr invalid\n", __func__); 1235 return (NULL); 1236 } 1237 1238 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1239 callback_arg, flags & ~_DMA_CRC_FLAGS); 1240 if (desc == NULL) 1241 return (NULL); 1242 1243 hw_desc = desc->u.crc32; 1244 1245 if ((flags & DMA_CRC_INLINE) == 0) 1246 hw_desc->crc_address = crcptr; 1247 else 1248 hw_desc->u.control.crc_location = 1; 1249 1250 if (initialseed != NULL) { 1251 hw_desc->u.control.use_seed = 1; 1252 hw_desc->seed = *initialseed; 1253 } 1254 1255 if (g_ioat_debug_level >= 3) 1256 dump_descriptor(hw_desc); 1257 1258 ioat_submit_single(ioat); 1259 return (&desc->bus_dmadesc); 1260 } 1261 1262 struct bus_dmadesc * 1263 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1264 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1265 uint32_t flags) 1266 { 1267 struct ioat_fill_hw_descriptor *hw_desc; 1268 struct ioat_descriptor *desc; 1269 struct ioat_softc *ioat; 1270 1271 ioat = to_ioat_softc(dmaengine); 1272 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1273 1274 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1275 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1276 __func__); 1277 return (NULL); 1278 } 1279 1280 if ((dst & (0xffffull << 48)) != 0) { 1281 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1282 __func__); 1283 return (NULL); 1284 } 1285 1286 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1287 callback_fn, callback_arg, flags); 1288 if (desc == NULL) 1289 return (NULL); 1290 1291 hw_desc = desc->u.fill; 1292 if (g_ioat_debug_level >= 3) 1293 dump_descriptor(hw_desc); 1294 1295 ioat_submit_single(ioat); 1296 return (&desc->bus_dmadesc); 1297 } 1298 1299 /* 1300 * Ring Management 1301 */ 1302 static inline uint32_t 1303 ioat_get_active(struct ioat_softc *ioat) 1304 { 1305 1306 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1307 } 1308 1309 static inline uint32_t 1310 ioat_get_ring_space(struct ioat_softc *ioat) 1311 { 1312 1313 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1314 } 1315 1316 static struct ioat_descriptor * 1317 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 1318 { 1319 struct ioat_generic_hw_descriptor *hw_desc; 1320 struct ioat_descriptor *desc; 1321 int error, busdmaflag; 1322 1323 error = ENOMEM; 1324 hw_desc = NULL; 1325 1326 if ((mflags & M_WAITOK) != 0) 1327 busdmaflag = BUS_DMA_WAITOK; 1328 else 1329 busdmaflag = BUS_DMA_NOWAIT; 1330 1331 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1332 if (desc == NULL) 1333 goto out; 1334 1335 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1336 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1337 if (hw_desc == NULL) 1338 goto out; 1339 1340 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1341 desc->u.generic = hw_desc; 1342 1343 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1344 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1345 busdmaflag); 1346 if (error) 1347 goto out; 1348 1349 out: 1350 if (error) { 1351 ioat_free_ring_entry(ioat, desc); 1352 return (NULL); 1353 } 1354 return (desc); 1355 } 1356 1357 static void 1358 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1359 { 1360 1361 if (desc == NULL) 1362 return; 1363 1364 if (desc->u.generic) 1365 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1366 ioat->hw_desc_map); 1367 free(desc, M_IOAT); 1368 } 1369 1370 /* 1371 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1372 * for 'num_descs'. 1373 * 1374 * If mflags contains M_WAITOK, blocks until enough space is available. 1375 * 1376 * Returns zero on success, or an errno on error. If num_descs is beyond the 1377 * maximum ring size, returns EINVAl; if allocation would block and mflags 1378 * contains M_NOWAIT, returns EAGAIN. 1379 * 1380 * Must be called with the submit_lock held; returns with the lock held. The 1381 * lock may be dropped to allocate the ring. 1382 * 1383 * (The submit_lock is needed to add any entries to the ring, so callers are 1384 * assured enough room is available.) 1385 */ 1386 static int 1387 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1388 { 1389 struct ioat_descriptor **new_ring; 1390 uint32_t order; 1391 boolean_t dug; 1392 int error; 1393 1394 mtx_assert(&ioat->submit_lock, MA_OWNED); 1395 error = 0; 1396 dug = FALSE; 1397 1398 if (num_descs < 1 || num_descs >= (1 << IOAT_MAX_ORDER)) { 1399 error = EINVAL; 1400 goto out; 1401 } 1402 1403 for (;;) { 1404 if (ioat->quiescing) { 1405 error = ENXIO; 1406 goto out; 1407 } 1408 1409 if (ioat_get_ring_space(ioat) >= num_descs) 1410 goto out; 1411 1412 if (!dug && !ioat->is_submitter_processing && 1413 (1 << ioat->ring_size_order) > num_descs) { 1414 ioat->is_submitter_processing = TRUE; 1415 mtx_unlock(&ioat->submit_lock); 1416 1417 ioat_process_events(ioat); 1418 1419 mtx_lock(&ioat->submit_lock); 1420 dug = TRUE; 1421 KASSERT(ioat->is_submitter_processing == TRUE, 1422 ("is_submitter_processing")); 1423 ioat->is_submitter_processing = FALSE; 1424 wakeup(&ioat->tail); 1425 continue; 1426 } 1427 1428 order = ioat->ring_size_order; 1429 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1430 if ((mflags & M_WAITOK) != 0) { 1431 msleep(&ioat->tail, &ioat->submit_lock, 0, 1432 "ioat_rsz", 0); 1433 continue; 1434 } 1435 1436 error = EAGAIN; 1437 break; 1438 } 1439 1440 ioat->is_resize_pending = TRUE; 1441 for (;;) { 1442 mtx_unlock(&ioat->submit_lock); 1443 1444 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1445 TRUE, mflags); 1446 1447 mtx_lock(&ioat->submit_lock); 1448 KASSERT(ioat->ring_size_order == order, 1449 ("is_resize_pending should protect order")); 1450 1451 if (new_ring == NULL) { 1452 KASSERT((mflags & M_WAITOK) == 0, 1453 ("allocation failed")); 1454 error = EAGAIN; 1455 break; 1456 } 1457 1458 error = ring_grow(ioat, order, new_ring); 1459 if (error == 0) 1460 break; 1461 } 1462 ioat->is_resize_pending = FALSE; 1463 wakeup(&ioat->tail); 1464 if (error) 1465 break; 1466 } 1467 1468 out: 1469 mtx_assert(&ioat->submit_lock, MA_OWNED); 1470 KASSERT(!ioat->quiescing || error == ENXIO, 1471 ("reserved during quiesce")); 1472 return (error); 1473 } 1474 1475 static struct ioat_descriptor ** 1476 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1477 int mflags) 1478 { 1479 struct ioat_descriptor **ring; 1480 uint32_t i; 1481 int error; 1482 1483 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1484 1485 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1486 if (ring == NULL) 1487 return (NULL); 1488 1489 if (need_dscr) { 1490 error = ENOMEM; 1491 for (i = size / 2; i < size; i++) { 1492 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1493 if (ring[i] == NULL) 1494 goto out; 1495 ring[i]->id = i; 1496 } 1497 } 1498 error = 0; 1499 1500 out: 1501 if (error != 0 && ring != NULL) { 1502 ioat_free_ring(ioat, size, ring); 1503 ring = NULL; 1504 } 1505 return (ring); 1506 } 1507 1508 static void 1509 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1510 struct ioat_descriptor **ring) 1511 { 1512 uint32_t i; 1513 1514 for (i = 0; i < size; i++) { 1515 if (ring[i] != NULL) 1516 ioat_free_ring_entry(ioat, ring[i]); 1517 } 1518 free(ring, M_IOAT); 1519 } 1520 1521 static struct ioat_descriptor * 1522 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1523 { 1524 1525 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1526 } 1527 1528 static int 1529 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1530 struct ioat_descriptor **newring) 1531 { 1532 struct ioat_descriptor *tmp, *next; 1533 struct ioat_dma_hw_descriptor *hw; 1534 uint32_t oldsize, newsize, head, tail, i, end; 1535 int error; 1536 1537 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1538 1539 mtx_assert(&ioat->submit_lock, MA_OWNED); 1540 1541 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1542 error = EINVAL; 1543 goto out; 1544 } 1545 1546 oldsize = (1 << oldorder); 1547 newsize = (1 << (oldorder + 1)); 1548 1549 mtx_lock(&ioat->cleanup_lock); 1550 1551 head = ioat->head & (oldsize - 1); 1552 tail = ioat->tail & (oldsize - 1); 1553 1554 /* Copy old descriptors to new ring */ 1555 for (i = 0; i < oldsize; i++) 1556 newring[i] = ioat->ring[i]; 1557 1558 /* 1559 * If head has wrapped but tail hasn't, we must swap some descriptors 1560 * around so that tail can increment directly to head. 1561 */ 1562 if (head < tail) { 1563 for (i = 0; i <= head; i++) { 1564 tmp = newring[oldsize + i]; 1565 1566 newring[oldsize + i] = newring[i]; 1567 newring[oldsize + i]->id = oldsize + i; 1568 1569 newring[i] = tmp; 1570 newring[i]->id = i; 1571 } 1572 head += oldsize; 1573 } 1574 1575 KASSERT(head >= tail, ("invariants")); 1576 1577 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1578 if (head < oldsize) { 1579 i = oldsize - 1; 1580 end = newsize; 1581 } else { 1582 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1583 i = head; 1584 end = newsize + (head - oldsize) + 1; 1585 } 1586 1587 /* 1588 * Fix up hardware ring, being careful not to trample the active 1589 * section (tail -> head). 1590 */ 1591 for (; i < end; i++) { 1592 KASSERT((i & (newsize - 1)) < tail || 1593 (i & (newsize - 1)) >= head, ("trampling snake")); 1594 1595 next = newring[(i + 1) & (newsize - 1)]; 1596 hw = newring[i & (newsize - 1)]->u.dma; 1597 hw->next = next->hw_desc_bus_addr; 1598 } 1599 1600 #ifdef INVARIANTS 1601 for (i = 0; i < newsize; i++) { 1602 next = newring[(i + 1) & (newsize - 1)]; 1603 hw = newring[i & (newsize - 1)]->u.dma; 1604 1605 KASSERT(hw->next == next->hw_desc_bus_addr, 1606 ("mismatch at i:%u (oldsize:%u); next=%p nextaddr=0x%lx" 1607 " (tail:%u)", i, oldsize, next, next->hw_desc_bus_addr, 1608 tail)); 1609 } 1610 #endif 1611 1612 free(ioat->ring, M_IOAT); 1613 ioat->ring = newring; 1614 ioat->ring_size_order = oldorder + 1; 1615 ioat->tail = tail; 1616 ioat->head = head; 1617 error = 0; 1618 1619 mtx_unlock(&ioat->cleanup_lock); 1620 out: 1621 if (error) 1622 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1623 return (error); 1624 } 1625 1626 static int 1627 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1628 struct ioat_descriptor **newring) 1629 { 1630 struct ioat_dma_hw_descriptor *hw; 1631 struct ioat_descriptor *ent, *next; 1632 uint32_t oldsize, newsize, current_idx, new_idx, i; 1633 int error; 1634 1635 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1636 1637 mtx_assert(&ioat->submit_lock, MA_OWNED); 1638 1639 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1640 error = EINVAL; 1641 goto out_unlocked; 1642 } 1643 1644 oldsize = (1 << oldorder); 1645 newsize = (1 << (oldorder - 1)); 1646 1647 mtx_lock(&ioat->cleanup_lock); 1648 1649 /* Can't shrink below current active set! */ 1650 if (ioat_get_active(ioat) >= newsize) { 1651 error = ENOMEM; 1652 goto out; 1653 } 1654 1655 /* 1656 * Copy current descriptors to the new ring, dropping the removed 1657 * descriptors. 1658 */ 1659 for (i = 0; i < newsize; i++) { 1660 current_idx = (ioat->tail + i) & (oldsize - 1); 1661 new_idx = (ioat->tail + i) & (newsize - 1); 1662 1663 newring[new_idx] = ioat->ring[current_idx]; 1664 newring[new_idx]->id = new_idx; 1665 } 1666 1667 /* Free deleted descriptors */ 1668 for (i = newsize; i < oldsize; i++) { 1669 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1670 ioat_free_ring_entry(ioat, ent); 1671 } 1672 1673 /* Fix up hardware ring. */ 1674 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1675 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1676 hw->next = next->hw_desc_bus_addr; 1677 1678 #ifdef INVARIANTS 1679 for (i = 0; i < newsize; i++) { 1680 next = newring[(i + 1) & (newsize - 1)]; 1681 hw = newring[i & (newsize - 1)]->u.dma; 1682 1683 KASSERT(hw->next == next->hw_desc_bus_addr, 1684 ("mismatch at i:%u (newsize:%u); next=%p nextaddr=0x%lx " 1685 "(tail:%u)", i, newsize, next, next->hw_desc_bus_addr, 1686 ioat->tail)); 1687 } 1688 #endif 1689 1690 free(ioat->ring, M_IOAT); 1691 ioat->ring = newring; 1692 ioat->ring_size_order = oldorder - 1; 1693 error = 0; 1694 1695 out: 1696 mtx_unlock(&ioat->cleanup_lock); 1697 out_unlocked: 1698 if (error) 1699 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1700 return (error); 1701 } 1702 1703 static void 1704 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1705 { 1706 struct ioat_descriptor *desc; 1707 1708 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1709 IOAT_CHANERR_STR); 1710 if (chanerr == 0) 1711 return; 1712 1713 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1714 1715 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1716 dump_descriptor(desc->u.raw); 1717 1718 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1719 dump_descriptor(desc->u.raw); 1720 } 1721 1722 static void 1723 ioat_poll_timer_callback(void *arg) 1724 { 1725 struct ioat_softc *ioat; 1726 1727 ioat = arg; 1728 ioat_log_message(3, "%s\n", __func__); 1729 1730 ioat_process_events(ioat); 1731 } 1732 1733 static void 1734 ioat_shrink_timer_callback(void *arg) 1735 { 1736 struct ioat_descriptor **newring; 1737 struct ioat_softc *ioat; 1738 uint32_t order; 1739 1740 ioat = arg; 1741 ioat_log_message(1, "%s\n", __func__); 1742 1743 /* Slowly scale the ring down if idle. */ 1744 mtx_lock(&ioat->submit_lock); 1745 1746 /* Don't run while the hardware is being reset. */ 1747 if (ioat->resetting) { 1748 mtx_unlock(&ioat->submit_lock); 1749 return; 1750 } 1751 1752 order = ioat->ring_size_order; 1753 if (ioat->is_completion_pending || ioat->is_resize_pending || 1754 order == IOAT_MIN_ORDER) { 1755 mtx_unlock(&ioat->submit_lock); 1756 goto out; 1757 } 1758 ioat->is_resize_pending = TRUE; 1759 mtx_unlock(&ioat->submit_lock); 1760 1761 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1762 M_NOWAIT); 1763 1764 mtx_lock(&ioat->submit_lock); 1765 KASSERT(ioat->ring_size_order == order, 1766 ("resize_pending protects order")); 1767 1768 if (newring != NULL && !ioat->is_completion_pending) 1769 ring_shrink(ioat, order, newring); 1770 else if (newring != NULL) 1771 ioat_free_ring(ioat, (1 << (order - 1)), newring); 1772 1773 ioat->is_resize_pending = FALSE; 1774 mtx_unlock(&ioat->submit_lock); 1775 1776 out: 1777 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1778 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 1779 ioat_shrink_timer_callback, ioat); 1780 } 1781 1782 /* 1783 * Support Functions 1784 */ 1785 static void 1786 ioat_submit_single(struct ioat_softc *ioat) 1787 { 1788 1789 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1790 atomic_add_rel_int(&ioat->head, 1); 1791 atomic_add_rel_int(&ioat->hw_head, 1); 1792 1793 if (!ioat->is_completion_pending) { 1794 ioat->is_completion_pending = TRUE; 1795 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 1796 ioat); 1797 callout_stop(&ioat->shrink_timer); 1798 } 1799 1800 ioat->stats.descriptors_submitted++; 1801 } 1802 1803 static int 1804 ioat_reset_hw(struct ioat_softc *ioat) 1805 { 1806 uint64_t status; 1807 uint32_t chanerr; 1808 unsigned timeout; 1809 int error; 1810 1811 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1812 1813 mtx_lock(IOAT_REFLK); 1814 while (ioat->resetting && !ioat->destroying) 1815 msleep(&ioat->resetting, IOAT_REFLK, 0, "IRH_drain", 0); 1816 if (ioat->destroying) { 1817 mtx_unlock(IOAT_REFLK); 1818 return (ENXIO); 1819 } 1820 ioat->resetting = TRUE; 1821 1822 ioat->quiescing = TRUE; 1823 ioat_drain_locked(ioat); 1824 mtx_unlock(IOAT_REFLK); 1825 1826 /* 1827 * Suspend ioat_process_events while the hardware and softc are in an 1828 * indeterminate state. 1829 */ 1830 mtx_lock(&ioat->cleanup_lock); 1831 ioat->resetting_cleanup = TRUE; 1832 mtx_unlock(&ioat->cleanup_lock); 1833 1834 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__, 1835 ioat->chan_idx); 1836 1837 status = ioat_get_chansts(ioat); 1838 if (is_ioat_active(status) || is_ioat_idle(status)) 1839 ioat_suspend(ioat); 1840 1841 /* Wait at most 20 ms */ 1842 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1843 timeout < 20; timeout++) { 1844 DELAY(1000); 1845 status = ioat_get_chansts(ioat); 1846 } 1847 if (timeout == 20) { 1848 error = ETIMEDOUT; 1849 goto out; 1850 } 1851 1852 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1853 1854 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1855 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1856 1857 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__, 1858 ioat->chan_idx); 1859 1860 /* 1861 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1862 * that can cause stability issues for IOAT v3. 1863 */ 1864 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1865 4); 1866 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1867 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1868 1869 /* 1870 * BDXDE and BWD models reset MSI-X registers on device reset. 1871 * Save/restore their contents manually. 1872 */ 1873 if (ioat_model_resets_msix(ioat)) { 1874 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1875 pci_save_state(ioat->device); 1876 } 1877 1878 ioat_reset(ioat); 1879 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__, 1880 ioat->chan_idx); 1881 1882 /* Wait at most 20 ms */ 1883 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1884 DELAY(1000); 1885 if (timeout == 20) { 1886 error = ETIMEDOUT; 1887 goto out; 1888 } 1889 1890 if (ioat_model_resets_msix(ioat)) { 1891 ioat_log_message(1, "device resets registers; restored\n"); 1892 pci_restore_state(ioat->device); 1893 } 1894 1895 /* Reset attempts to return the hardware to "halted." */ 1896 status = ioat_get_chansts(ioat); 1897 if (is_ioat_active(status) || is_ioat_idle(status)) { 1898 /* So this really shouldn't happen... */ 1899 ioat_log_message(0, "Device is active after a reset?\n"); 1900 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1901 error = 0; 1902 goto out; 1903 } 1904 1905 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1906 if (chanerr != 0) { 1907 mtx_lock(&ioat->cleanup_lock); 1908 ioat_halted_debug(ioat, chanerr); 1909 mtx_unlock(&ioat->cleanup_lock); 1910 error = EIO; 1911 goto out; 1912 } 1913 1914 /* 1915 * Bring device back online after reset. Writing CHAINADDR brings the 1916 * device back to active. 1917 * 1918 * The internal ring counter resets to zero, so we have to start over 1919 * at zero as well. 1920 */ 1921 ioat->tail = ioat->head = ioat->hw_head = 0; 1922 ioat->last_seen = 0; 1923 *ioat->comp_update = 0; 1924 KASSERT(!ioat->is_completion_pending, ("bogus completion_pending")); 1925 1926 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1927 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1928 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1929 error = 0; 1930 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__, 1931 ioat->chan_idx); 1932 1933 out: 1934 /* Enqueues a null operation and ensures it completes. */ 1935 if (error == 0) { 1936 error = ioat_start_channel(ioat); 1937 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__, 1938 ioat->chan_idx); 1939 } 1940 1941 /* 1942 * Resume completions now that ring state is consistent. 1943 */ 1944 mtx_lock(&ioat->cleanup_lock); 1945 ioat->resetting_cleanup = FALSE; 1946 mtx_unlock(&ioat->cleanup_lock); 1947 1948 /* Unblock submission of new work */ 1949 mtx_lock(IOAT_REFLK); 1950 ioat->quiescing = FALSE; 1951 wakeup(&ioat->quiescing); 1952 1953 ioat->resetting = FALSE; 1954 wakeup(&ioat->resetting); 1955 1956 if (ioat->is_completion_pending) 1957 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 1958 ioat); 1959 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx); 1960 mtx_unlock(IOAT_REFLK); 1961 1962 return (error); 1963 } 1964 1965 static int 1966 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1967 { 1968 struct ioat_softc *ioat; 1969 struct sbuf sb; 1970 uint64_t status; 1971 int error; 1972 1973 ioat = arg1; 1974 1975 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1976 1977 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1978 switch (status) { 1979 case IOAT_CHANSTS_ACTIVE: 1980 sbuf_printf(&sb, "ACTIVE"); 1981 break; 1982 case IOAT_CHANSTS_IDLE: 1983 sbuf_printf(&sb, "IDLE"); 1984 break; 1985 case IOAT_CHANSTS_SUSPENDED: 1986 sbuf_printf(&sb, "SUSPENDED"); 1987 break; 1988 case IOAT_CHANSTS_HALTED: 1989 sbuf_printf(&sb, "HALTED"); 1990 break; 1991 case IOAT_CHANSTS_ARMED: 1992 sbuf_printf(&sb, "ARMED"); 1993 break; 1994 default: 1995 sbuf_printf(&sb, "UNKNOWN"); 1996 break; 1997 } 1998 error = sbuf_finish(&sb); 1999 sbuf_delete(&sb); 2000 2001 if (error != 0 || req->newptr == NULL) 2002 return (error); 2003 return (EINVAL); 2004 } 2005 2006 static int 2007 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 2008 { 2009 struct ioat_softc *ioat; 2010 struct sbuf sb; 2011 #define PRECISION "1" 2012 const uintmax_t factor = 10; 2013 uintmax_t rate; 2014 int error; 2015 2016 ioat = arg1; 2017 sbuf_new_for_sysctl(&sb, NULL, 16, req); 2018 2019 if (ioat->stats.interrupts == 0) { 2020 sbuf_printf(&sb, "NaN"); 2021 goto out; 2022 } 2023 rate = ioat->stats.descriptors_processed * factor / 2024 ioat->stats.interrupts; 2025 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 2026 rate % factor); 2027 #undef PRECISION 2028 out: 2029 error = sbuf_finish(&sb); 2030 sbuf_delete(&sb); 2031 if (error != 0 || req->newptr == NULL) 2032 return (error); 2033 return (EINVAL); 2034 } 2035 2036 static int 2037 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 2038 { 2039 struct ioat_softc *ioat; 2040 int error, arg; 2041 2042 ioat = arg1; 2043 2044 arg = 0; 2045 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 2046 if (error != 0 || req->newptr == NULL) 2047 return (error); 2048 2049 error = SYSCTL_IN(req, &arg, sizeof(arg)); 2050 if (error != 0) 2051 return (error); 2052 2053 if (arg != 0) 2054 error = ioat_reset_hw(ioat); 2055 2056 return (error); 2057 } 2058 2059 static void 2060 dump_descriptor(void *hw_desc) 2061 { 2062 int i, j; 2063 2064 for (i = 0; i < 2; i++) { 2065 for (j = 0; j < 8; j++) 2066 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 2067 printf("\n"); 2068 } 2069 } 2070 2071 static void 2072 ioat_setup_sysctl(device_t device) 2073 { 2074 struct sysctl_oid_list *par, *statpar, *state, *hammer; 2075 struct sysctl_ctx_list *ctx; 2076 struct sysctl_oid *tree, *tmp; 2077 struct ioat_softc *ioat; 2078 2079 ioat = DEVICE2SOFTC(device); 2080 ctx = device_get_sysctl_ctx(device); 2081 tree = device_get_sysctl_tree(device); 2082 par = SYSCTL_CHILDREN(tree); 2083 2084 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 2085 &ioat->version, 0, "HW version (0xMM form)"); 2086 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 2087 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 2088 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 2089 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 2090 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 2091 &ioat->intrdelay_max, 0, 2092 "Maximum configurable INTRDELAY on this channel (microseconds)"); 2093 2094 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 2095 "IOAT channel internal state"); 2096 state = SYSCTL_CHILDREN(tmp); 2097 2098 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 2099 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 2100 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 2101 0, "SW descriptor head pointer index"); 2102 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 2103 0, "SW descriptor tail pointer index"); 2104 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 2105 &ioat->hw_head, 0, "HW DMACOUNT"); 2106 2107 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 2108 ioat->comp_update, "HW addr of last completion"); 2109 2110 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 2111 &ioat->is_resize_pending, 0, "resize pending"); 2112 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 2113 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 2114 "submitter processing"); 2115 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 2116 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 2117 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 2118 &ioat->is_reset_pending, 0, "reset pending"); 2119 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 2120 &ioat->is_channel_running, 0, "channel running"); 2121 2122 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 2123 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 2124 "String of the channel status"); 2125 2126 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 2127 &ioat->cached_intrdelay, 0, 2128 "Current INTRDELAY on this channel (cached, microseconds)"); 2129 2130 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 2131 "Big hammers (mostly for testing)"); 2132 hammer = SYSCTL_CHILDREN(tmp); 2133 2134 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 2135 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 2136 "Set to non-zero to reset the hardware"); 2137 2138 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 2139 "IOAT channel statistics"); 2140 statpar = SYSCTL_CHILDREN(tmp); 2141 2142 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 2143 &ioat->stats.interrupts, 2144 "Number of interrupts processed on this channel"); 2145 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 2146 &ioat->stats.descriptors_processed, 2147 "Number of descriptors processed on this channel"); 2148 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 2149 &ioat->stats.descriptors_submitted, 2150 "Number of descriptors submitted to this channel"); 2151 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 2152 &ioat->stats.descriptors_error, 2153 "Number of descriptors failed by channel errors"); 2154 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 2155 &ioat->stats.channel_halts, 0, 2156 "Number of times the channel has halted"); 2157 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 2158 &ioat->stats.last_halt_chanerr, 0, 2159 "The raw CHANERR when the channel was last halted"); 2160 2161 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 2162 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 2163 "Descriptors per interrupt"); 2164 } 2165 2166 static inline struct ioat_softc * 2167 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2168 { 2169 uint32_t old; 2170 2171 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2172 2173 old = atomic_fetchadd_32(&ioat->refcnt, 1); 2174 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 2175 2176 #ifdef INVARIANTS 2177 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 2178 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 2179 #endif 2180 2181 return (ioat); 2182 } 2183 2184 static inline void 2185 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2186 { 2187 2188 _ioat_putn(ioat, n, kind, FALSE); 2189 } 2190 2191 static inline void 2192 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2193 { 2194 2195 _ioat_putn(ioat, n, kind, TRUE); 2196 } 2197 2198 static inline void 2199 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 2200 boolean_t locked) 2201 { 2202 uint32_t old; 2203 2204 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2205 2206 if (n == 0) 2207 return; 2208 2209 #ifdef INVARIANTS 2210 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 2211 KASSERT(old >= n, ("refcnt kind underflow")); 2212 #endif 2213 2214 /* Skip acquiring the lock if resulting refcnt > 0. */ 2215 for (;;) { 2216 old = ioat->refcnt; 2217 if (old <= n) 2218 break; 2219 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 2220 return; 2221 } 2222 2223 if (locked) 2224 mtx_assert(IOAT_REFLK, MA_OWNED); 2225 else 2226 mtx_lock(IOAT_REFLK); 2227 2228 old = atomic_fetchadd_32(&ioat->refcnt, -n); 2229 KASSERT(old >= n, ("refcnt error")); 2230 2231 if (old == n) 2232 wakeup(IOAT_REFLK); 2233 if (!locked) 2234 mtx_unlock(IOAT_REFLK); 2235 } 2236 2237 static inline void 2238 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2239 { 2240 2241 ioat_putn(ioat, 1, kind); 2242 } 2243 2244 static void 2245 ioat_drain_locked(struct ioat_softc *ioat) 2246 { 2247 2248 mtx_assert(IOAT_REFLK, MA_OWNED); 2249 while (ioat->refcnt > 0) 2250 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 2251 } 2252 2253 #ifdef DDB 2254 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 2255 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 2256 DB_SHOW_COMMAND(ioat, db_show_ioat) 2257 { 2258 struct ioat_softc *sc; 2259 unsigned idx; 2260 2261 if (!have_addr) 2262 goto usage; 2263 idx = (unsigned)addr; 2264 if (idx >= ioat_channel_index) 2265 goto usage; 2266 2267 sc = ioat_channel[idx]; 2268 db_printf("ioat softc at %p\n", sc); 2269 if (sc == NULL) 2270 return; 2271 2272 db_printf(" version: %d\n", sc->version); 2273 db_printf(" chan_idx: %u\n", sc->chan_idx); 2274 db_printf(" submit_lock: "); 2275 db_show_lock(&sc->submit_lock); 2276 2277 db_printf(" capabilities: %b\n", (int)sc->capabilities, 2278 IOAT_DMACAP_STR); 2279 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 2280 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 2281 2282 db_printf(" poll_timer:\n"); 2283 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 2284 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 2285 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 2286 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 2287 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 2288 2289 db_printf(" shrink_timer:\n"); 2290 db_printf(" c_time: %ju\n", (uintmax_t)sc->shrink_timer.c_time); 2291 db_printf(" c_arg: %p\n", sc->shrink_timer.c_arg); 2292 db_printf(" c_func: %p\n", sc->shrink_timer.c_func); 2293 db_printf(" c_lock: %p\n", sc->shrink_timer.c_lock); 2294 db_printf(" c_flags: 0x%x\n", (unsigned)sc->shrink_timer.c_flags); 2295 2296 db_printf(" quiescing: %d\n", (int)sc->quiescing); 2297 db_printf(" destroying: %d\n", (int)sc->destroying); 2298 db_printf(" is_resize_pending: %d\n", (int)sc->is_resize_pending); 2299 db_printf(" is_submitter_processing: %d\n", 2300 (int)sc->is_submitter_processing); 2301 db_printf(" is_completion_pending: %d\n", (int)sc->is_completion_pending); 2302 db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending); 2303 db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running); 2304 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 2305 db_printf(" resetting: %d\n", (int)sc->resetting); 2306 2307 db_printf(" head: %u\n", sc->head); 2308 db_printf(" tail: %u\n", sc->tail); 2309 db_printf(" hw_head: %u\n", sc->hw_head); 2310 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2311 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2312 db_printf(" ring: %p\n", sc->ring); 2313 2314 db_printf(" ring[%u] (tail):\n", sc->tail % 2315 (1 << sc->ring_size_order)); 2316 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 2317 db_printf(" addr: 0x%lx\n", 2318 ioat_get_ring_entry(sc, sc->tail)->hw_desc_bus_addr); 2319 db_printf(" next: 0x%lx\n", 2320 ioat_get_ring_entry(sc, sc->tail)->u.generic->next); 2321 2322 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 2323 (1 << sc->ring_size_order)); 2324 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 2325 db_printf(" addr: 0x%lx\n", 2326 ioat_get_ring_entry(sc, sc->head - 1)->hw_desc_bus_addr); 2327 db_printf(" next: 0x%lx\n", 2328 ioat_get_ring_entry(sc, sc->head - 1)->u.generic->next); 2329 2330 db_printf(" ring[%u] (head):\n", (sc->head) % 2331 (1 << sc->ring_size_order)); 2332 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2333 db_printf(" addr: 0x%lx\n", 2334 ioat_get_ring_entry(sc, sc->head)->hw_desc_bus_addr); 2335 db_printf(" next: 0x%lx\n", 2336 ioat_get_ring_entry(sc, sc->head)->u.generic->next); 2337 2338 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2339 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2340 == ioat_get_ring_entry(sc, idx)->hw_desc_bus_addr) 2341 db_printf(" ring[%u] == hardware tail\n", idx); 2342 2343 db_printf(" cleanup_lock: "); 2344 db_show_lock(&sc->cleanup_lock); 2345 2346 db_printf(" refcnt: %u\n", sc->refcnt); 2347 #ifdef INVARIANTS 2348 CTASSERT(IOAT_NUM_REF_KINDS == 2); 2349 db_printf(" refkinds: [ENG=%u, DESCR=%u]\n", sc->refkinds[0], 2350 sc->refkinds[1]); 2351 #endif 2352 db_printf(" stats:\n"); 2353 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2354 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2355 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2356 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2357 2358 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2359 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2360 2361 if (db_pager_quit) 2362 return; 2363 2364 db_printf(" hw status:\n"); 2365 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2366 db_printf(" chanctrl: 0x%x\n", 2367 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2368 db_printf(" chancmd: 0x%x\n", 2369 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2370 db_printf(" dmacount: 0x%x\n", 2371 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2372 db_printf(" chainaddr: 0x%lx\n", 2373 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2374 db_printf(" chancmp: 0x%lx\n", 2375 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2376 db_printf(" chanerr: %b\n", 2377 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2378 return; 2379 usage: 2380 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2381 return; 2382 } 2383 #endif /* DDB */ 2384