1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ddb.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/fail.h> 37 #include <sys/ioccom.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/sbuf.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 #include <sys/time.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <machine/stdarg.h> 53 54 #ifdef DDB 55 #include <ddb/ddb.h> 56 #endif 57 58 #include "ioat.h" 59 #include "ioat_hw.h" 60 #include "ioat_internal.h" 61 62 #ifndef BUS_SPACE_MAXADDR_40BIT 63 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 64 #endif 65 #define IOAT_REFLK (&ioat->submit_lock) 66 67 static int ioat_probe(device_t device); 68 static int ioat_attach(device_t device); 69 static int ioat_detach(device_t device); 70 static int ioat_setup_intr(struct ioat_softc *ioat); 71 static int ioat_teardown_intr(struct ioat_softc *ioat); 72 static int ioat3_attach(device_t device); 73 static int ioat_start_channel(struct ioat_softc *ioat); 74 static int ioat_map_pci_bar(struct ioat_softc *ioat); 75 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 76 int error); 77 static void ioat_interrupt_handler(void *arg); 78 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 79 static int chanerr_to_errno(uint32_t); 80 static void ioat_process_events(struct ioat_softc *ioat); 81 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 82 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 83 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 84 struct ioat_descriptor *); 85 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 86 static union ioat_hw_descriptor *ioat_get_descriptor(struct ioat_softc *, 87 uint32_t index); 88 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *, 89 uint32_t index); 90 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 91 static void ioat_poll_timer_callback(void *arg); 92 static void dump_descriptor(void *hw_desc); 93 static void ioat_submit_single(struct ioat_softc *ioat); 94 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 95 int error); 96 static int ioat_reset_hw(struct ioat_softc *ioat); 97 static void ioat_reset_hw_task(void *, int); 98 static void ioat_setup_sysctl(device_t device); 99 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 100 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 101 enum ioat_ref_kind); 102 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 103 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 104 enum ioat_ref_kind, boolean_t); 105 static inline void ioat_putn(struct ioat_softc *, uint32_t, 106 enum ioat_ref_kind); 107 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 108 enum ioat_ref_kind); 109 static void ioat_drain_locked(struct ioat_softc *); 110 111 #define ioat_log_message(v, ...) do { \ 112 if ((v) <= g_ioat_debug_level) { \ 113 device_printf(ioat->device, __VA_ARGS__); \ 114 } \ 115 } while (0) 116 117 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 118 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 119 120 static int g_force_legacy_interrupts; 121 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 122 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 123 124 int g_ioat_debug_level = 0; 125 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 126 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 127 128 unsigned g_ioat_ring_order = 13; 129 SYSCTL_UINT(_hw_ioat, OID_AUTO, ring_order, CTLFLAG_RDTUN, &g_ioat_ring_order, 130 0, "Set IOAT ring order. (1 << this) == ring size."); 131 132 /* 133 * OS <-> Driver interface structures 134 */ 135 static device_method_t ioat_pci_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, ioat_probe), 138 DEVMETHOD(device_attach, ioat_attach), 139 DEVMETHOD(device_detach, ioat_detach), 140 DEVMETHOD_END 141 }; 142 143 static driver_t ioat_pci_driver = { 144 "ioat", 145 ioat_pci_methods, 146 sizeof(struct ioat_softc), 147 }; 148 149 static devclass_t ioat_devclass; 150 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 151 MODULE_VERSION(ioat, 1); 152 153 /* 154 * Private data structures 155 */ 156 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 157 static unsigned ioat_channel_index = 0; 158 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 159 "Number of IOAT channels attached"); 160 161 static struct _pcsid 162 { 163 u_int32_t type; 164 const char *desc; 165 } pci_ids[] = { 166 { 0x34308086, "TBG IOAT Ch0" }, 167 { 0x34318086, "TBG IOAT Ch1" }, 168 { 0x34328086, "TBG IOAT Ch2" }, 169 { 0x34338086, "TBG IOAT Ch3" }, 170 { 0x34298086, "TBG IOAT Ch4" }, 171 { 0x342a8086, "TBG IOAT Ch5" }, 172 { 0x342b8086, "TBG IOAT Ch6" }, 173 { 0x342c8086, "TBG IOAT Ch7" }, 174 175 { 0x37108086, "JSF IOAT Ch0" }, 176 { 0x37118086, "JSF IOAT Ch1" }, 177 { 0x37128086, "JSF IOAT Ch2" }, 178 { 0x37138086, "JSF IOAT Ch3" }, 179 { 0x37148086, "JSF IOAT Ch4" }, 180 { 0x37158086, "JSF IOAT Ch5" }, 181 { 0x37168086, "JSF IOAT Ch6" }, 182 { 0x37178086, "JSF IOAT Ch7" }, 183 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 184 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 185 186 { 0x3c208086, "SNB IOAT Ch0" }, 187 { 0x3c218086, "SNB IOAT Ch1" }, 188 { 0x3c228086, "SNB IOAT Ch2" }, 189 { 0x3c238086, "SNB IOAT Ch3" }, 190 { 0x3c248086, "SNB IOAT Ch4" }, 191 { 0x3c258086, "SNB IOAT Ch5" }, 192 { 0x3c268086, "SNB IOAT Ch6" }, 193 { 0x3c278086, "SNB IOAT Ch7" }, 194 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 195 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 196 197 { 0x0e208086, "IVB IOAT Ch0" }, 198 { 0x0e218086, "IVB IOAT Ch1" }, 199 { 0x0e228086, "IVB IOAT Ch2" }, 200 { 0x0e238086, "IVB IOAT Ch3" }, 201 { 0x0e248086, "IVB IOAT Ch4" }, 202 { 0x0e258086, "IVB IOAT Ch5" }, 203 { 0x0e268086, "IVB IOAT Ch6" }, 204 { 0x0e278086, "IVB IOAT Ch7" }, 205 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 206 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 207 208 { 0x2f208086, "HSW IOAT Ch0" }, 209 { 0x2f218086, "HSW IOAT Ch1" }, 210 { 0x2f228086, "HSW IOAT Ch2" }, 211 { 0x2f238086, "HSW IOAT Ch3" }, 212 { 0x2f248086, "HSW IOAT Ch4" }, 213 { 0x2f258086, "HSW IOAT Ch5" }, 214 { 0x2f268086, "HSW IOAT Ch6" }, 215 { 0x2f278086, "HSW IOAT Ch7" }, 216 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 217 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 218 219 { 0x0c508086, "BWD IOAT Ch0" }, 220 { 0x0c518086, "BWD IOAT Ch1" }, 221 { 0x0c528086, "BWD IOAT Ch2" }, 222 { 0x0c538086, "BWD IOAT Ch3" }, 223 224 { 0x6f508086, "BDXDE IOAT Ch0" }, 225 { 0x6f518086, "BDXDE IOAT Ch1" }, 226 { 0x6f528086, "BDXDE IOAT Ch2" }, 227 { 0x6f538086, "BDXDE IOAT Ch3" }, 228 229 { 0x6f208086, "BDX IOAT Ch0" }, 230 { 0x6f218086, "BDX IOAT Ch1" }, 231 { 0x6f228086, "BDX IOAT Ch2" }, 232 { 0x6f238086, "BDX IOAT Ch3" }, 233 { 0x6f248086, "BDX IOAT Ch4" }, 234 { 0x6f258086, "BDX IOAT Ch5" }, 235 { 0x6f268086, "BDX IOAT Ch6" }, 236 { 0x6f278086, "BDX IOAT Ch7" }, 237 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 238 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 239 240 { 0x00000000, NULL } 241 }; 242 243 /* 244 * OS <-> Driver linkage functions 245 */ 246 static int 247 ioat_probe(device_t device) 248 { 249 struct _pcsid *ep; 250 u_int32_t type; 251 252 type = pci_get_devid(device); 253 for (ep = pci_ids; ep->type; ep++) { 254 if (ep->type == type) { 255 device_set_desc(device, ep->desc); 256 return (0); 257 } 258 } 259 return (ENXIO); 260 } 261 262 static int 263 ioat_attach(device_t device) 264 { 265 struct ioat_softc *ioat; 266 int error; 267 268 ioat = DEVICE2SOFTC(device); 269 ioat->device = device; 270 271 error = ioat_map_pci_bar(ioat); 272 if (error != 0) 273 goto err; 274 275 ioat->version = ioat_read_cbver(ioat); 276 if (ioat->version < IOAT_VER_3_0) { 277 error = ENODEV; 278 goto err; 279 } 280 281 error = ioat3_attach(device); 282 if (error != 0) 283 goto err; 284 285 error = pci_enable_busmaster(device); 286 if (error != 0) 287 goto err; 288 289 error = ioat_setup_intr(ioat); 290 if (error != 0) 291 goto err; 292 293 error = ioat_reset_hw(ioat); 294 if (error != 0) 295 goto err; 296 297 ioat_process_events(ioat); 298 ioat_setup_sysctl(device); 299 300 ioat->chan_idx = ioat_channel_index; 301 ioat_channel[ioat_channel_index++] = ioat; 302 ioat_test_attach(); 303 304 err: 305 if (error != 0) 306 ioat_detach(device); 307 return (error); 308 } 309 310 static int 311 ioat_detach(device_t device) 312 { 313 struct ioat_softc *ioat; 314 315 ioat = DEVICE2SOFTC(device); 316 317 ioat_test_detach(); 318 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 319 320 mtx_lock(IOAT_REFLK); 321 ioat->quiescing = TRUE; 322 ioat->destroying = TRUE; 323 wakeup(&ioat->quiescing); 324 wakeup(&ioat->resetting); 325 326 ioat_channel[ioat->chan_idx] = NULL; 327 328 ioat_drain_locked(ioat); 329 mtx_unlock(IOAT_REFLK); 330 331 ioat_teardown_intr(ioat); 332 callout_drain(&ioat->poll_timer); 333 334 pci_disable_busmaster(device); 335 336 if (ioat->pci_resource != NULL) 337 bus_release_resource(device, SYS_RES_MEMORY, 338 ioat->pci_resource_id, ioat->pci_resource); 339 340 if (ioat->ring != NULL) 341 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 342 343 if (ioat->comp_update != NULL) { 344 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 345 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 346 ioat->comp_update_map); 347 bus_dma_tag_destroy(ioat->comp_update_tag); 348 } 349 350 if (ioat->hw_desc_ring != NULL) { 351 bus_dmamap_unload(ioat->hw_desc_tag, ioat->hw_desc_map); 352 bus_dmamem_free(ioat->hw_desc_tag, ioat->hw_desc_ring, 353 ioat->hw_desc_map); 354 bus_dma_tag_destroy(ioat->hw_desc_tag); 355 } 356 357 return (0); 358 } 359 360 static int 361 ioat_teardown_intr(struct ioat_softc *ioat) 362 { 363 364 if (ioat->tag != NULL) 365 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 366 367 if (ioat->res != NULL) 368 bus_release_resource(ioat->device, SYS_RES_IRQ, 369 rman_get_rid(ioat->res), ioat->res); 370 371 pci_release_msi(ioat->device); 372 return (0); 373 } 374 375 static int 376 ioat_start_channel(struct ioat_softc *ioat) 377 { 378 struct ioat_dma_hw_descriptor *hw_desc; 379 struct ioat_descriptor *desc; 380 struct bus_dmadesc *dmadesc; 381 uint64_t status; 382 uint32_t chanerr; 383 int i; 384 385 ioat_acquire(&ioat->dmaengine); 386 387 /* Submit 'NULL' operation manually to avoid quiescing flag */ 388 desc = ioat_get_ring_entry(ioat, ioat->head); 389 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->dma; 390 dmadesc = &desc->bus_dmadesc; 391 392 dmadesc->callback_fn = NULL; 393 dmadesc->callback_arg = NULL; 394 395 hw_desc->u.control_raw = 0; 396 hw_desc->u.control_generic.op = IOAT_OP_COPY; 397 hw_desc->u.control_generic.completion_update = 1; 398 hw_desc->size = 8; 399 hw_desc->src_addr = 0; 400 hw_desc->dest_addr = 0; 401 hw_desc->u.control.null = 1; 402 403 ioat_submit_single(ioat); 404 ioat_release(&ioat->dmaengine); 405 406 for (i = 0; i < 100; i++) { 407 DELAY(1); 408 status = ioat_get_chansts(ioat); 409 if (is_ioat_idle(status)) 410 return (0); 411 } 412 413 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 414 ioat_log_message(0, "could not start channel: " 415 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 416 IOAT_CHANERR_STR); 417 return (ENXIO); 418 } 419 420 /* 421 * Initialize Hardware 422 */ 423 static int 424 ioat3_attach(device_t device) 425 { 426 struct ioat_softc *ioat; 427 struct ioat_descriptor *ring; 428 struct ioat_dma_hw_descriptor *dma_hw_desc; 429 void *hw_desc; 430 size_t ringsz; 431 int i, num_descriptors; 432 int error; 433 uint8_t xfercap; 434 435 error = 0; 436 ioat = DEVICE2SOFTC(device); 437 ioat->capabilities = ioat_read_dmacapability(ioat); 438 439 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 440 IOAT_DMACAP_STR); 441 442 xfercap = ioat_read_xfercap(ioat); 443 ioat->max_xfer_size = 1 << xfercap; 444 445 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 446 IOAT_INTRDELAY_SUPPORTED) != 0; 447 if (ioat->intrdelay_supported) 448 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 449 450 /* TODO: need to check DCA here if we ever do XOR/PQ */ 451 452 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 453 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 454 callout_init(&ioat->poll_timer, 1); 455 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 456 457 /* Establish lock order for Witness */ 458 mtx_lock(&ioat->submit_lock); 459 mtx_lock(&ioat->cleanup_lock); 460 mtx_unlock(&ioat->cleanup_lock); 461 mtx_unlock(&ioat->submit_lock); 462 463 ioat->is_submitter_processing = FALSE; 464 ioat->is_completion_pending = FALSE; 465 ioat->is_reset_pending = FALSE; 466 ioat->is_channel_running = FALSE; 467 468 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 469 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 470 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 471 &ioat->comp_update_tag); 472 473 error = bus_dmamem_alloc(ioat->comp_update_tag, 474 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 475 if (ioat->comp_update == NULL) 476 return (ENOMEM); 477 478 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 479 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 480 0); 481 if (error != 0) 482 return (error); 483 484 ioat->ring_size_order = g_ioat_ring_order; 485 num_descriptors = 1 << ioat->ring_size_order; 486 ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors; 487 488 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device), 489 2 * 1024 * 1024, 0x0, BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, 490 NULL, NULL, ringsz, 1, ringsz, 0, NULL, NULL, &ioat->hw_desc_tag); 491 if (error != 0) 492 return (error); 493 494 error = bus_dmamem_alloc(ioat->hw_desc_tag, &hw_desc, 495 BUS_DMA_ZERO | BUS_DMA_WAITOK, &ioat->hw_desc_map); 496 if (error != 0) 497 return (error); 498 499 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 500 ringsz, ioat_dmamap_cb, &ioat->hw_desc_bus_addr, BUS_DMA_WAITOK); 501 if (error) 502 return (error); 503 504 ioat->hw_desc_ring = hw_desc; 505 506 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 507 M_ZERO | M_WAITOK); 508 509 ring = ioat->ring; 510 for (i = 0; i < num_descriptors; i++) { 511 memset(&ring[i].bus_dmadesc, 0, sizeof(ring[i].bus_dmadesc)); 512 ring[i].id = i; 513 } 514 515 for (i = 0; i < num_descriptors; i++) { 516 dma_hw_desc = &ioat->hw_desc_ring[i].dma; 517 dma_hw_desc->next = RING_PHYS_ADDR(ioat, i + 1); 518 } 519 520 ioat->head = ioat->hw_head = 0; 521 ioat->tail = 0; 522 ioat->last_seen = 0; 523 *ioat->comp_update = 0; 524 return (0); 525 } 526 527 static int 528 ioat_map_pci_bar(struct ioat_softc *ioat) 529 { 530 531 ioat->pci_resource_id = PCIR_BAR(0); 532 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 533 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 534 535 if (ioat->pci_resource == NULL) { 536 ioat_log_message(0, "unable to allocate pci resource\n"); 537 return (ENODEV); 538 } 539 540 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 541 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 542 return (0); 543 } 544 545 static void 546 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 547 { 548 struct ioat_softc *ioat = arg; 549 550 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 551 ioat->comp_update_bus_addr = seg[0].ds_addr; 552 } 553 554 static void 555 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 556 { 557 bus_addr_t *baddr; 558 559 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 560 baddr = arg; 561 *baddr = segs->ds_addr; 562 } 563 564 /* 565 * Interrupt setup and handlers 566 */ 567 static int 568 ioat_setup_intr(struct ioat_softc *ioat) 569 { 570 uint32_t num_vectors; 571 int error; 572 boolean_t use_msix; 573 boolean_t force_legacy_interrupts; 574 575 use_msix = FALSE; 576 force_legacy_interrupts = FALSE; 577 578 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 579 num_vectors = 1; 580 pci_alloc_msix(ioat->device, &num_vectors); 581 if (num_vectors == 1) 582 use_msix = TRUE; 583 } 584 585 if (use_msix) { 586 ioat->rid = 1; 587 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 588 &ioat->rid, RF_ACTIVE); 589 } else { 590 ioat->rid = 0; 591 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 592 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 593 } 594 if (ioat->res == NULL) { 595 ioat_log_message(0, "bus_alloc_resource failed\n"); 596 return (ENOMEM); 597 } 598 599 ioat->tag = NULL; 600 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 601 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 602 if (error != 0) { 603 ioat_log_message(0, "bus_setup_intr failed\n"); 604 return (error); 605 } 606 607 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 608 return (0); 609 } 610 611 static boolean_t 612 ioat_model_resets_msix(struct ioat_softc *ioat) 613 { 614 u_int32_t pciid; 615 616 pciid = pci_get_devid(ioat->device); 617 switch (pciid) { 618 /* BWD: */ 619 case 0x0c508086: 620 case 0x0c518086: 621 case 0x0c528086: 622 case 0x0c538086: 623 /* BDXDE: */ 624 case 0x6f508086: 625 case 0x6f518086: 626 case 0x6f528086: 627 case 0x6f538086: 628 return (TRUE); 629 } 630 631 return (FALSE); 632 } 633 634 static void 635 ioat_interrupt_handler(void *arg) 636 { 637 struct ioat_softc *ioat = arg; 638 639 ioat->stats.interrupts++; 640 ioat_process_events(ioat); 641 } 642 643 static int 644 chanerr_to_errno(uint32_t chanerr) 645 { 646 647 if (chanerr == 0) 648 return (0); 649 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 650 return (EFAULT); 651 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 652 return (EIO); 653 /* This one is probably our fault: */ 654 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 655 return (EIO); 656 return (EIO); 657 } 658 659 static void 660 ioat_process_events(struct ioat_softc *ioat) 661 { 662 struct ioat_descriptor *desc; 663 struct bus_dmadesc *dmadesc; 664 uint64_t comp_update, status; 665 uint32_t completed, chanerr; 666 boolean_t pending; 667 int error; 668 669 mtx_lock(&ioat->cleanup_lock); 670 671 /* 672 * Don't run while the hardware is being reset. Reset is responsible 673 * for blocking new work and draining & completing existing work, so 674 * there is nothing to do until new work is queued after reset anyway. 675 */ 676 if (ioat->resetting_cleanup) { 677 mtx_unlock(&ioat->cleanup_lock); 678 return; 679 } 680 681 completed = 0; 682 comp_update = *ioat->comp_update; 683 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 684 685 if (status < ioat->hw_desc_bus_addr || 686 status >= ioat->hw_desc_bus_addr + (1 << ioat->ring_size_order) * 687 sizeof(struct ioat_generic_hw_descriptor)) 688 panic("Bogus completion address %jx (channel %u)", 689 (uintmax_t)status, ioat->chan_idx); 690 691 if (status == ioat->last_seen) { 692 /* 693 * If we landed in process_events and nothing has been 694 * completed, check for a timeout due to channel halt. 695 */ 696 goto out; 697 } 698 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx", 699 __func__, ioat->chan_idx, comp_update, ioat->last_seen); 700 701 while (RING_PHYS_ADDR(ioat, ioat->tail - 1) != status) { 702 desc = ioat_get_ring_entry(ioat, ioat->tail); 703 dmadesc = &desc->bus_dmadesc; 704 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) ok cb %p(%p)", 705 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 706 dmadesc->callback_arg); 707 708 if (dmadesc->callback_fn != NULL) 709 dmadesc->callback_fn(dmadesc->callback_arg, 0); 710 711 completed++; 712 ioat->tail++; 713 } 714 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 715 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 716 717 if (completed != 0) { 718 ioat->last_seen = RING_PHYS_ADDR(ioat, ioat->tail - 1); 719 ioat->stats.descriptors_processed += completed; 720 } 721 722 out: 723 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 724 725 /* Perform a racy check first; only take the locks if it passes. */ 726 pending = (ioat_get_active(ioat) != 0); 727 if (!pending && ioat->is_completion_pending) { 728 mtx_unlock(&ioat->cleanup_lock); 729 mtx_lock(&ioat->submit_lock); 730 mtx_lock(&ioat->cleanup_lock); 731 732 pending = (ioat_get_active(ioat) != 0); 733 if (!pending && ioat->is_completion_pending) { 734 ioat->is_completion_pending = FALSE; 735 callout_stop(&ioat->poll_timer); 736 } 737 mtx_unlock(&ioat->submit_lock); 738 } 739 mtx_unlock(&ioat->cleanup_lock); 740 741 if (pending) 742 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 743 ioat); 744 745 if (completed != 0) { 746 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 747 wakeup(&ioat->tail); 748 } 749 750 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 751 return; 752 753 ioat->stats.channel_halts++; 754 755 /* 756 * Fatal programming error on this DMA channel. Flush any outstanding 757 * work with error status and restart the engine. 758 */ 759 mtx_lock(&ioat->submit_lock); 760 mtx_lock(&ioat->cleanup_lock); 761 ioat->quiescing = TRUE; 762 763 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 764 if (1 <= g_ioat_debug_level) 765 ioat_halted_debug(ioat, chanerr); 766 ioat->stats.last_halt_chanerr = chanerr; 767 768 while (ioat_get_active(ioat) > 0) { 769 desc = ioat_get_ring_entry(ioat, ioat->tail); 770 dmadesc = &desc->bus_dmadesc; 771 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) err cb %p(%p)", 772 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn, 773 dmadesc->callback_arg); 774 775 if (dmadesc->callback_fn != NULL) 776 dmadesc->callback_fn(dmadesc->callback_arg, 777 chanerr_to_errno(chanerr)); 778 779 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 780 ioat->tail++; 781 ioat->stats.descriptors_processed++; 782 ioat->stats.descriptors_error++; 783 } 784 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__, 785 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat)); 786 787 if (ioat->is_completion_pending) { 788 ioat->is_completion_pending = FALSE; 789 callout_stop(&ioat->poll_timer); 790 } 791 792 /* Clear error status */ 793 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 794 795 mtx_unlock(&ioat->cleanup_lock); 796 mtx_unlock(&ioat->submit_lock); 797 798 ioat_log_message(0, "Resetting channel to recover from error\n"); 799 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 800 KASSERT(error == 0, 801 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 802 } 803 804 static void 805 ioat_reset_hw_task(void *ctx, int pending __unused) 806 { 807 struct ioat_softc *ioat; 808 int error; 809 810 ioat = ctx; 811 ioat_log_message(1, "%s: Resetting channel\n", __func__); 812 813 error = ioat_reset_hw(ioat); 814 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 815 (void)error; 816 } 817 818 /* 819 * User API functions 820 */ 821 unsigned 822 ioat_get_nchannels(void) 823 { 824 825 return (ioat_channel_index); 826 } 827 828 bus_dmaengine_t 829 ioat_get_dmaengine(uint32_t index, int flags) 830 { 831 struct ioat_softc *ioat; 832 833 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 834 ("invalid flags: 0x%08x", flags)); 835 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 836 ("invalid wait | nowait")); 837 838 if (index >= ioat_channel_index) 839 return (NULL); 840 841 ioat = ioat_channel[index]; 842 if (ioat == NULL || ioat->destroying) 843 return (NULL); 844 845 if (ioat->quiescing) { 846 if ((flags & M_NOWAIT) != 0) 847 return (NULL); 848 849 mtx_lock(IOAT_REFLK); 850 while (ioat->quiescing && !ioat->destroying) 851 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 852 mtx_unlock(IOAT_REFLK); 853 854 if (ioat->destroying) 855 return (NULL); 856 } 857 858 /* 859 * There's a race here between the quiescing check and HW reset or 860 * module destroy. 861 */ 862 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 863 } 864 865 void 866 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 867 { 868 struct ioat_softc *ioat; 869 870 ioat = to_ioat_softc(dmaengine); 871 ioat_put(ioat, IOAT_DMAENGINE_REF); 872 } 873 874 int 875 ioat_get_hwversion(bus_dmaengine_t dmaengine) 876 { 877 struct ioat_softc *ioat; 878 879 ioat = to_ioat_softc(dmaengine); 880 return (ioat->version); 881 } 882 883 size_t 884 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 885 { 886 struct ioat_softc *ioat; 887 888 ioat = to_ioat_softc(dmaengine); 889 return (ioat->max_xfer_size); 890 } 891 892 uint32_t 893 ioat_get_capabilities(bus_dmaengine_t dmaengine) 894 { 895 struct ioat_softc *ioat; 896 897 ioat = to_ioat_softc(dmaengine); 898 return (ioat->capabilities); 899 } 900 901 int 902 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 903 { 904 struct ioat_softc *ioat; 905 906 ioat = to_ioat_softc(dmaengine); 907 if (!ioat->intrdelay_supported) 908 return (ENODEV); 909 if (delay > ioat->intrdelay_max) 910 return (ERANGE); 911 912 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 913 ioat->cached_intrdelay = 914 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 915 return (0); 916 } 917 918 uint16_t 919 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 920 { 921 struct ioat_softc *ioat; 922 923 ioat = to_ioat_softc(dmaengine); 924 return (ioat->intrdelay_max); 925 } 926 927 void 928 ioat_acquire(bus_dmaengine_t dmaengine) 929 { 930 struct ioat_softc *ioat; 931 932 ioat = to_ioat_softc(dmaengine); 933 mtx_lock(&ioat->submit_lock); 934 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 935 } 936 937 int 938 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 939 { 940 struct ioat_softc *ioat; 941 int error; 942 943 ioat = to_ioat_softc(dmaengine); 944 ioat_acquire(dmaengine); 945 946 error = ioat_reserve_space(ioat, n, mflags); 947 if (error != 0) 948 ioat_release(dmaengine); 949 return (error); 950 } 951 952 void 953 ioat_release(bus_dmaengine_t dmaengine) 954 { 955 struct ioat_softc *ioat; 956 957 ioat = to_ioat_softc(dmaengine); 958 CTR4(KTR_IOAT, "%s channel=%u dispatch1 hw_head=%u head=%u", __func__, 959 ioat->chan_idx, ioat->hw_head & UINT16_MAX, ioat->head); 960 KFAIL_POINT_CODE(DEBUG_FP, ioat_release, /* do nothing */); 961 CTR4(KTR_IOAT, "%s channel=%u dispatch2 hw_head=%u head=%u", __func__, 962 ioat->chan_idx, ioat->hw_head & UINT16_MAX, ioat->head); 963 964 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 965 966 if (!ioat->is_completion_pending) { 967 ioat->is_completion_pending = TRUE; 968 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 969 ioat); 970 } 971 mtx_unlock(&ioat->submit_lock); 972 } 973 974 static struct ioat_descriptor * 975 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 976 uint32_t size, uint64_t src, uint64_t dst, 977 bus_dmaengine_callback_t callback_fn, void *callback_arg, 978 uint32_t flags) 979 { 980 struct ioat_generic_hw_descriptor *hw_desc; 981 struct ioat_descriptor *desc; 982 int mflags; 983 984 mtx_assert(&ioat->submit_lock, MA_OWNED); 985 986 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 987 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 988 if ((flags & DMA_NO_WAIT) != 0) 989 mflags = M_NOWAIT; 990 else 991 mflags = M_WAITOK; 992 993 if (size > ioat->max_xfer_size) { 994 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 995 __func__, ioat->max_xfer_size, (unsigned)size); 996 return (NULL); 997 } 998 999 if (ioat_reserve_space(ioat, 1, mflags) != 0) 1000 return (NULL); 1001 1002 desc = ioat_get_ring_entry(ioat, ioat->head); 1003 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->generic; 1004 1005 hw_desc->u.control_raw = 0; 1006 hw_desc->u.control_generic.op = op; 1007 hw_desc->u.control_generic.completion_update = 1; 1008 1009 if ((flags & DMA_INT_EN) != 0) 1010 hw_desc->u.control_generic.int_enable = 1; 1011 if ((flags & DMA_FENCE) != 0) 1012 hw_desc->u.control_generic.fence = 1; 1013 1014 hw_desc->size = size; 1015 hw_desc->src_addr = src; 1016 hw_desc->dest_addr = dst; 1017 1018 desc->bus_dmadesc.callback_fn = callback_fn; 1019 desc->bus_dmadesc.callback_arg = callback_arg; 1020 return (desc); 1021 } 1022 1023 struct bus_dmadesc * 1024 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1025 void *callback_arg, uint32_t flags) 1026 { 1027 struct ioat_dma_hw_descriptor *hw_desc; 1028 struct ioat_descriptor *desc; 1029 struct ioat_softc *ioat; 1030 1031 ioat = to_ioat_softc(dmaengine); 1032 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1033 1034 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1035 callback_arg, flags); 1036 if (desc == NULL) 1037 return (NULL); 1038 1039 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1040 hw_desc->u.control.null = 1; 1041 ioat_submit_single(ioat); 1042 return (&desc->bus_dmadesc); 1043 } 1044 1045 struct bus_dmadesc * 1046 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1047 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1048 void *callback_arg, uint32_t flags) 1049 { 1050 struct ioat_dma_hw_descriptor *hw_desc; 1051 struct ioat_descriptor *desc; 1052 struct ioat_softc *ioat; 1053 1054 ioat = to_ioat_softc(dmaengine); 1055 1056 if (((src | dst) & (0xffffull << 48)) != 0) { 1057 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1058 __func__); 1059 return (NULL); 1060 } 1061 1062 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1063 callback_arg, flags); 1064 if (desc == NULL) 1065 return (NULL); 1066 1067 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1068 if (g_ioat_debug_level >= 3) 1069 dump_descriptor(hw_desc); 1070 1071 ioat_submit_single(ioat); 1072 CTR6(KTR_IOAT, "%s channel=%u desc=%p dest=%lx src=%lx len=%lx", 1073 __func__, ioat->chan_idx, &desc->bus_dmadesc, dst, src, len); 1074 return (&desc->bus_dmadesc); 1075 } 1076 1077 struct bus_dmadesc * 1078 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1079 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1080 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1081 { 1082 struct ioat_dma_hw_descriptor *hw_desc; 1083 struct ioat_descriptor *desc; 1084 struct ioat_softc *ioat; 1085 1086 ioat = to_ioat_softc(dmaengine); 1087 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1088 1089 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 1090 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1091 __func__); 1092 return (NULL); 1093 } 1094 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 1095 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 1096 __func__); 1097 return (NULL); 1098 } 1099 1100 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 1101 callback_fn, callback_arg, flags); 1102 if (desc == NULL) 1103 return (NULL); 1104 1105 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma; 1106 if (src2 != src1 + PAGE_SIZE) { 1107 hw_desc->u.control.src_page_break = 1; 1108 hw_desc->next_src_addr = src2; 1109 } 1110 if (dst2 != dst1 + PAGE_SIZE) { 1111 hw_desc->u.control.dest_page_break = 1; 1112 hw_desc->next_dest_addr = dst2; 1113 } 1114 1115 if (g_ioat_debug_level >= 3) 1116 dump_descriptor(hw_desc); 1117 1118 ioat_submit_single(ioat); 1119 return (&desc->bus_dmadesc); 1120 } 1121 1122 struct bus_dmadesc * 1123 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1124 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1125 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1126 { 1127 struct ioat_crc32_hw_descriptor *hw_desc; 1128 struct ioat_descriptor *desc; 1129 struct ioat_softc *ioat; 1130 uint32_t teststore; 1131 uint8_t op; 1132 1133 ioat = to_ioat_softc(dmaengine); 1134 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1135 1136 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1137 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1138 __func__); 1139 return (NULL); 1140 } 1141 if (((src | dst) & (0xffffffull << 40)) != 0) { 1142 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1143 __func__); 1144 return (NULL); 1145 } 1146 teststore = (flags & _DMA_CRC_TESTSTORE); 1147 if (teststore == _DMA_CRC_TESTSTORE) { 1148 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1149 return (NULL); 1150 } 1151 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1152 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1153 __func__); 1154 return (NULL); 1155 } 1156 1157 switch (teststore) { 1158 case DMA_CRC_STORE: 1159 op = IOAT_OP_MOVECRC_STORE; 1160 break; 1161 case DMA_CRC_TEST: 1162 op = IOAT_OP_MOVECRC_TEST; 1163 break; 1164 default: 1165 KASSERT(teststore == 0, ("bogus")); 1166 op = IOAT_OP_MOVECRC; 1167 break; 1168 } 1169 1170 if ((flags & DMA_CRC_INLINE) == 0 && 1171 (crcptr & (0xffffffull << 40)) != 0) { 1172 ioat_log_message(0, 1173 "%s: High 24 bits of crcptr invalid\n", __func__); 1174 return (NULL); 1175 } 1176 1177 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1178 callback_arg, flags & ~_DMA_CRC_FLAGS); 1179 if (desc == NULL) 1180 return (NULL); 1181 1182 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1183 1184 if ((flags & DMA_CRC_INLINE) == 0) 1185 hw_desc->crc_address = crcptr; 1186 else 1187 hw_desc->u.control.crc_location = 1; 1188 1189 if (initialseed != NULL) { 1190 hw_desc->u.control.use_seed = 1; 1191 hw_desc->seed = *initialseed; 1192 } 1193 1194 if (g_ioat_debug_level >= 3) 1195 dump_descriptor(hw_desc); 1196 1197 ioat_submit_single(ioat); 1198 return (&desc->bus_dmadesc); 1199 } 1200 1201 struct bus_dmadesc * 1202 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1203 uint32_t *initialseed, bus_addr_t crcptr, 1204 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1205 { 1206 struct ioat_crc32_hw_descriptor *hw_desc; 1207 struct ioat_descriptor *desc; 1208 struct ioat_softc *ioat; 1209 uint32_t teststore; 1210 uint8_t op; 1211 1212 ioat = to_ioat_softc(dmaengine); 1213 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1214 1215 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1216 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1217 __func__); 1218 return (NULL); 1219 } 1220 if ((src & (0xffffffull << 40)) != 0) { 1221 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1222 __func__); 1223 return (NULL); 1224 } 1225 teststore = (flags & _DMA_CRC_TESTSTORE); 1226 if (teststore == _DMA_CRC_TESTSTORE) { 1227 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1228 return (NULL); 1229 } 1230 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1231 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1232 __func__); 1233 return (NULL); 1234 } 1235 1236 switch (teststore) { 1237 case DMA_CRC_STORE: 1238 op = IOAT_OP_CRC_STORE; 1239 break; 1240 case DMA_CRC_TEST: 1241 op = IOAT_OP_CRC_TEST; 1242 break; 1243 default: 1244 KASSERT(teststore == 0, ("bogus")); 1245 op = IOAT_OP_CRC; 1246 break; 1247 } 1248 1249 if ((flags & DMA_CRC_INLINE) == 0 && 1250 (crcptr & (0xffffffull << 40)) != 0) { 1251 ioat_log_message(0, 1252 "%s: High 24 bits of crcptr invalid\n", __func__); 1253 return (NULL); 1254 } 1255 1256 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1257 callback_arg, flags & ~_DMA_CRC_FLAGS); 1258 if (desc == NULL) 1259 return (NULL); 1260 1261 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32; 1262 1263 if ((flags & DMA_CRC_INLINE) == 0) 1264 hw_desc->crc_address = crcptr; 1265 else 1266 hw_desc->u.control.crc_location = 1; 1267 1268 if (initialseed != NULL) { 1269 hw_desc->u.control.use_seed = 1; 1270 hw_desc->seed = *initialseed; 1271 } 1272 1273 if (g_ioat_debug_level >= 3) 1274 dump_descriptor(hw_desc); 1275 1276 ioat_submit_single(ioat); 1277 return (&desc->bus_dmadesc); 1278 } 1279 1280 struct bus_dmadesc * 1281 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1282 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1283 uint32_t flags) 1284 { 1285 struct ioat_fill_hw_descriptor *hw_desc; 1286 struct ioat_descriptor *desc; 1287 struct ioat_softc *ioat; 1288 1289 ioat = to_ioat_softc(dmaengine); 1290 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1291 1292 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1293 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1294 __func__); 1295 return (NULL); 1296 } 1297 1298 if ((dst & (0xffffull << 48)) != 0) { 1299 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1300 __func__); 1301 return (NULL); 1302 } 1303 1304 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1305 callback_fn, callback_arg, flags); 1306 if (desc == NULL) 1307 return (NULL); 1308 1309 hw_desc = &ioat_get_descriptor(ioat, desc->id)->fill; 1310 if (g_ioat_debug_level >= 3) 1311 dump_descriptor(hw_desc); 1312 1313 ioat_submit_single(ioat); 1314 return (&desc->bus_dmadesc); 1315 } 1316 1317 /* 1318 * Ring Management 1319 */ 1320 static inline uint32_t 1321 ioat_get_active(struct ioat_softc *ioat) 1322 { 1323 1324 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1325 } 1326 1327 static inline uint32_t 1328 ioat_get_ring_space(struct ioat_softc *ioat) 1329 { 1330 1331 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1332 } 1333 1334 /* 1335 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1336 * for 'num_descs'. 1337 * 1338 * If mflags contains M_WAITOK, blocks until enough space is available. 1339 * 1340 * Returns zero on success, or an errno on error. If num_descs is beyond the 1341 * maximum ring size, returns EINVAl; if allocation would block and mflags 1342 * contains M_NOWAIT, returns EAGAIN. 1343 * 1344 * Must be called with the submit_lock held; returns with the lock held. The 1345 * lock may be dropped to allocate the ring. 1346 * 1347 * (The submit_lock is needed to add any entries to the ring, so callers are 1348 * assured enough room is available.) 1349 */ 1350 static int 1351 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1352 { 1353 boolean_t dug; 1354 int error; 1355 1356 mtx_assert(&ioat->submit_lock, MA_OWNED); 1357 error = 0; 1358 dug = FALSE; 1359 1360 if (num_descs < 1 || num_descs >= (1 << ioat->ring_size_order)) { 1361 error = EINVAL; 1362 goto out; 1363 } 1364 1365 for (;;) { 1366 if (ioat->quiescing) { 1367 error = ENXIO; 1368 goto out; 1369 } 1370 1371 if (ioat_get_ring_space(ioat) >= num_descs) 1372 goto out; 1373 1374 CTR3(KTR_IOAT, "%s channel=%u starved (%u)", __func__, 1375 ioat->chan_idx, num_descs); 1376 1377 if (!dug && !ioat->is_submitter_processing) { 1378 ioat->is_submitter_processing = TRUE; 1379 mtx_unlock(&ioat->submit_lock); 1380 1381 CTR2(KTR_IOAT, "%s channel=%u attempting to process events", 1382 __func__, ioat->chan_idx); 1383 ioat_process_events(ioat); 1384 1385 mtx_lock(&ioat->submit_lock); 1386 dug = TRUE; 1387 KASSERT(ioat->is_submitter_processing == TRUE, 1388 ("is_submitter_processing")); 1389 ioat->is_submitter_processing = FALSE; 1390 wakeup(&ioat->tail); 1391 continue; 1392 } 1393 1394 if ((mflags & M_WAITOK) == 0) { 1395 error = EAGAIN; 1396 break; 1397 } 1398 CTR2(KTR_IOAT, "%s channel=%u blocking on completions", 1399 __func__, ioat->chan_idx); 1400 msleep(&ioat->tail, &ioat->submit_lock, 0, 1401 "ioat_full", 0); 1402 continue; 1403 } 1404 1405 out: 1406 mtx_assert(&ioat->submit_lock, MA_OWNED); 1407 KASSERT(!ioat->quiescing || error == ENXIO, 1408 ("reserved during quiesce")); 1409 return (error); 1410 } 1411 1412 static void 1413 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1414 struct ioat_descriptor *ring) 1415 { 1416 1417 free(ring, M_IOAT); 1418 } 1419 1420 static struct ioat_descriptor * 1421 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1422 { 1423 1424 return (&ioat->ring[index % (1 << ioat->ring_size_order)]); 1425 } 1426 1427 static union ioat_hw_descriptor * 1428 ioat_get_descriptor(struct ioat_softc *ioat, uint32_t index) 1429 { 1430 1431 return (&ioat->hw_desc_ring[index % (1 << ioat->ring_size_order)]); 1432 } 1433 1434 static void 1435 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1436 { 1437 union ioat_hw_descriptor *desc; 1438 1439 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1440 IOAT_CHANERR_STR); 1441 if (chanerr == 0) 1442 return; 1443 1444 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1445 1446 desc = ioat_get_descriptor(ioat, ioat->tail + 0); 1447 dump_descriptor(desc); 1448 1449 desc = ioat_get_descriptor(ioat, ioat->tail + 1); 1450 dump_descriptor(desc); 1451 } 1452 1453 static void 1454 ioat_poll_timer_callback(void *arg) 1455 { 1456 struct ioat_softc *ioat; 1457 1458 ioat = arg; 1459 ioat_log_message(3, "%s\n", __func__); 1460 1461 ioat_process_events(ioat); 1462 } 1463 1464 /* 1465 * Support Functions 1466 */ 1467 static void 1468 ioat_submit_single(struct ioat_softc *ioat) 1469 { 1470 1471 mtx_assert(&ioat->submit_lock, MA_OWNED); 1472 1473 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1474 atomic_add_rel_int(&ioat->head, 1); 1475 atomic_add_rel_int(&ioat->hw_head, 1); 1476 CTR5(KTR_IOAT, "%s channel=%u head=%u hw_head=%u tail=%u", __func__, 1477 ioat->chan_idx, ioat->head, ioat->hw_head & UINT16_MAX, 1478 ioat->tail); 1479 1480 ioat->stats.descriptors_submitted++; 1481 } 1482 1483 static int 1484 ioat_reset_hw(struct ioat_softc *ioat) 1485 { 1486 uint64_t status; 1487 uint32_t chanerr; 1488 unsigned timeout; 1489 int error; 1490 1491 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1492 1493 mtx_lock(IOAT_REFLK); 1494 while (ioat->resetting && !ioat->destroying) 1495 msleep(&ioat->resetting, IOAT_REFLK, 0, "IRH_drain", 0); 1496 if (ioat->destroying) { 1497 mtx_unlock(IOAT_REFLK); 1498 return (ENXIO); 1499 } 1500 ioat->resetting = TRUE; 1501 1502 ioat->quiescing = TRUE; 1503 ioat_drain_locked(ioat); 1504 mtx_unlock(IOAT_REFLK); 1505 1506 /* 1507 * Suspend ioat_process_events while the hardware and softc are in an 1508 * indeterminate state. 1509 */ 1510 mtx_lock(&ioat->cleanup_lock); 1511 ioat->resetting_cleanup = TRUE; 1512 mtx_unlock(&ioat->cleanup_lock); 1513 1514 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__, 1515 ioat->chan_idx); 1516 1517 status = ioat_get_chansts(ioat); 1518 if (is_ioat_active(status) || is_ioat_idle(status)) 1519 ioat_suspend(ioat); 1520 1521 /* Wait at most 20 ms */ 1522 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1523 timeout < 20; timeout++) { 1524 DELAY(1000); 1525 status = ioat_get_chansts(ioat); 1526 } 1527 if (timeout == 20) { 1528 error = ETIMEDOUT; 1529 goto out; 1530 } 1531 1532 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1533 1534 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1535 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1536 1537 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__, 1538 ioat->chan_idx); 1539 1540 /* 1541 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1542 * that can cause stability issues for IOAT v3. 1543 */ 1544 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1545 4); 1546 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1547 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1548 1549 /* 1550 * BDXDE and BWD models reset MSI-X registers on device reset. 1551 * Save/restore their contents manually. 1552 */ 1553 if (ioat_model_resets_msix(ioat)) { 1554 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1555 pci_save_state(ioat->device); 1556 } 1557 1558 ioat_reset(ioat); 1559 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__, 1560 ioat->chan_idx); 1561 1562 /* Wait at most 20 ms */ 1563 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1564 DELAY(1000); 1565 if (timeout == 20) { 1566 error = ETIMEDOUT; 1567 goto out; 1568 } 1569 1570 if (ioat_model_resets_msix(ioat)) { 1571 ioat_log_message(1, "device resets registers; restored\n"); 1572 pci_restore_state(ioat->device); 1573 } 1574 1575 /* Reset attempts to return the hardware to "halted." */ 1576 status = ioat_get_chansts(ioat); 1577 if (is_ioat_active(status) || is_ioat_idle(status)) { 1578 /* So this really shouldn't happen... */ 1579 ioat_log_message(0, "Device is active after a reset?\n"); 1580 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1581 error = 0; 1582 goto out; 1583 } 1584 1585 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1586 if (chanerr != 0) { 1587 mtx_lock(&ioat->cleanup_lock); 1588 ioat_halted_debug(ioat, chanerr); 1589 mtx_unlock(&ioat->cleanup_lock); 1590 error = EIO; 1591 goto out; 1592 } 1593 1594 /* 1595 * Bring device back online after reset. Writing CHAINADDR brings the 1596 * device back to active. 1597 * 1598 * The internal ring counter resets to zero, so we have to start over 1599 * at zero as well. 1600 */ 1601 ioat->tail = ioat->head = ioat->hw_head = 0; 1602 ioat->last_seen = 0; 1603 *ioat->comp_update = 0; 1604 KASSERT(!ioat->is_completion_pending, ("bogus completion_pending")); 1605 1606 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1607 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1608 ioat_write_chainaddr(ioat, RING_PHYS_ADDR(ioat, 0)); 1609 error = 0; 1610 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__, 1611 ioat->chan_idx); 1612 1613 out: 1614 /* Enqueues a null operation and ensures it completes. */ 1615 if (error == 0) { 1616 error = ioat_start_channel(ioat); 1617 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__, 1618 ioat->chan_idx); 1619 } 1620 1621 /* 1622 * Resume completions now that ring state is consistent. 1623 */ 1624 mtx_lock(&ioat->cleanup_lock); 1625 ioat->resetting_cleanup = FALSE; 1626 mtx_unlock(&ioat->cleanup_lock); 1627 1628 /* Unblock submission of new work */ 1629 mtx_lock(IOAT_REFLK); 1630 ioat->quiescing = FALSE; 1631 wakeup(&ioat->quiescing); 1632 1633 ioat->resetting = FALSE; 1634 wakeup(&ioat->resetting); 1635 1636 if (ioat->is_completion_pending) 1637 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 1638 ioat); 1639 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx); 1640 mtx_unlock(IOAT_REFLK); 1641 1642 return (error); 1643 } 1644 1645 static int 1646 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1647 { 1648 struct ioat_softc *ioat; 1649 struct sbuf sb; 1650 uint64_t status; 1651 int error; 1652 1653 ioat = arg1; 1654 1655 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1656 1657 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1658 switch (status) { 1659 case IOAT_CHANSTS_ACTIVE: 1660 sbuf_printf(&sb, "ACTIVE"); 1661 break; 1662 case IOAT_CHANSTS_IDLE: 1663 sbuf_printf(&sb, "IDLE"); 1664 break; 1665 case IOAT_CHANSTS_SUSPENDED: 1666 sbuf_printf(&sb, "SUSPENDED"); 1667 break; 1668 case IOAT_CHANSTS_HALTED: 1669 sbuf_printf(&sb, "HALTED"); 1670 break; 1671 case IOAT_CHANSTS_ARMED: 1672 sbuf_printf(&sb, "ARMED"); 1673 break; 1674 default: 1675 sbuf_printf(&sb, "UNKNOWN"); 1676 break; 1677 } 1678 error = sbuf_finish(&sb); 1679 sbuf_delete(&sb); 1680 1681 if (error != 0 || req->newptr == NULL) 1682 return (error); 1683 return (EINVAL); 1684 } 1685 1686 static int 1687 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1688 { 1689 struct ioat_softc *ioat; 1690 struct sbuf sb; 1691 #define PRECISION "1" 1692 const uintmax_t factor = 10; 1693 uintmax_t rate; 1694 int error; 1695 1696 ioat = arg1; 1697 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1698 1699 if (ioat->stats.interrupts == 0) { 1700 sbuf_printf(&sb, "NaN"); 1701 goto out; 1702 } 1703 rate = ioat->stats.descriptors_processed * factor / 1704 ioat->stats.interrupts; 1705 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1706 rate % factor); 1707 #undef PRECISION 1708 out: 1709 error = sbuf_finish(&sb); 1710 sbuf_delete(&sb); 1711 if (error != 0 || req->newptr == NULL) 1712 return (error); 1713 return (EINVAL); 1714 } 1715 1716 static int 1717 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1718 { 1719 struct ioat_softc *ioat; 1720 int error, arg; 1721 1722 ioat = arg1; 1723 1724 arg = 0; 1725 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1726 if (error != 0 || req->newptr == NULL) 1727 return (error); 1728 1729 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1730 if (error != 0) 1731 return (error); 1732 1733 if (arg != 0) 1734 error = ioat_reset_hw(ioat); 1735 1736 return (error); 1737 } 1738 1739 static void 1740 dump_descriptor(void *hw_desc) 1741 { 1742 int i, j; 1743 1744 for (i = 0; i < 2; i++) { 1745 for (j = 0; j < 8; j++) 1746 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1747 printf("\n"); 1748 } 1749 } 1750 1751 static void 1752 ioat_setup_sysctl(device_t device) 1753 { 1754 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1755 struct sysctl_ctx_list *ctx; 1756 struct sysctl_oid *tree, *tmp; 1757 struct ioat_softc *ioat; 1758 1759 ioat = DEVICE2SOFTC(device); 1760 ctx = device_get_sysctl_ctx(device); 1761 tree = device_get_sysctl_tree(device); 1762 par = SYSCTL_CHILDREN(tree); 1763 1764 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1765 &ioat->version, 0, "HW version (0xMM form)"); 1766 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1767 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1768 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1769 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1770 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1771 &ioat->intrdelay_max, 0, 1772 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1773 1774 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 1775 "IOAT channel internal state"); 1776 state = SYSCTL_CHILDREN(tmp); 1777 1778 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1779 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1780 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1781 0, "SW descriptor head pointer index"); 1782 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1783 0, "SW descriptor tail pointer index"); 1784 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 1785 &ioat->hw_head, 0, "HW DMACOUNT"); 1786 1787 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1788 ioat->comp_update, "HW addr of last completion"); 1789 1790 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 1791 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 1792 "submitter processing"); 1793 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 1794 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 1795 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1796 &ioat->is_reset_pending, 0, "reset pending"); 1797 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1798 &ioat->is_channel_running, 0, "channel running"); 1799 1800 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1801 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1802 "String of the channel status"); 1803 1804 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1805 &ioat->cached_intrdelay, 0, 1806 "Current INTRDELAY on this channel (cached, microseconds)"); 1807 1808 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 1809 "Big hammers (mostly for testing)"); 1810 hammer = SYSCTL_CHILDREN(tmp); 1811 1812 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1813 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1814 "Set to non-zero to reset the hardware"); 1815 1816 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 1817 "IOAT channel statistics"); 1818 statpar = SYSCTL_CHILDREN(tmp); 1819 1820 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 1821 &ioat->stats.interrupts, 1822 "Number of interrupts processed on this channel"); 1823 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 1824 &ioat->stats.descriptors_processed, 1825 "Number of descriptors processed on this channel"); 1826 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 1827 &ioat->stats.descriptors_submitted, 1828 "Number of descriptors submitted to this channel"); 1829 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 1830 &ioat->stats.descriptors_error, 1831 "Number of descriptors failed by channel errors"); 1832 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 1833 &ioat->stats.channel_halts, 0, 1834 "Number of times the channel has halted"); 1835 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 1836 &ioat->stats.last_halt_chanerr, 0, 1837 "The raw CHANERR when the channel was last halted"); 1838 1839 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 1840 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 1841 "Descriptors per interrupt"); 1842 } 1843 1844 static inline struct ioat_softc * 1845 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1846 { 1847 uint32_t old; 1848 1849 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1850 1851 old = atomic_fetchadd_32(&ioat->refcnt, 1); 1852 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 1853 1854 #ifdef INVARIANTS 1855 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 1856 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 1857 #endif 1858 1859 return (ioat); 1860 } 1861 1862 static inline void 1863 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1864 { 1865 1866 _ioat_putn(ioat, n, kind, FALSE); 1867 } 1868 1869 static inline void 1870 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1871 { 1872 1873 _ioat_putn(ioat, n, kind, TRUE); 1874 } 1875 1876 static inline void 1877 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 1878 boolean_t locked) 1879 { 1880 uint32_t old; 1881 1882 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1883 1884 if (n == 0) 1885 return; 1886 1887 #ifdef INVARIANTS 1888 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 1889 KASSERT(old >= n, ("refcnt kind underflow")); 1890 #endif 1891 1892 /* Skip acquiring the lock if resulting refcnt > 0. */ 1893 for (;;) { 1894 old = ioat->refcnt; 1895 if (old <= n) 1896 break; 1897 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 1898 return; 1899 } 1900 1901 if (locked) 1902 mtx_assert(IOAT_REFLK, MA_OWNED); 1903 else 1904 mtx_lock(IOAT_REFLK); 1905 1906 old = atomic_fetchadd_32(&ioat->refcnt, -n); 1907 KASSERT(old >= n, ("refcnt error")); 1908 1909 if (old == n) 1910 wakeup(IOAT_REFLK); 1911 if (!locked) 1912 mtx_unlock(IOAT_REFLK); 1913 } 1914 1915 static inline void 1916 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1917 { 1918 1919 ioat_putn(ioat, 1, kind); 1920 } 1921 1922 static void 1923 ioat_drain_locked(struct ioat_softc *ioat) 1924 { 1925 1926 mtx_assert(IOAT_REFLK, MA_OWNED); 1927 while (ioat->refcnt > 0) 1928 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 1929 } 1930 1931 #ifdef DDB 1932 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 1933 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 1934 DB_SHOW_COMMAND(ioat, db_show_ioat) 1935 { 1936 struct ioat_softc *sc; 1937 unsigned idx; 1938 1939 if (!have_addr) 1940 goto usage; 1941 idx = (unsigned)addr; 1942 if (idx >= ioat_channel_index) 1943 goto usage; 1944 1945 sc = ioat_channel[idx]; 1946 db_printf("ioat softc at %p\n", sc); 1947 if (sc == NULL) 1948 return; 1949 1950 db_printf(" version: %d\n", sc->version); 1951 db_printf(" chan_idx: %u\n", sc->chan_idx); 1952 db_printf(" submit_lock: "); 1953 db_show_lock(&sc->submit_lock); 1954 1955 db_printf(" capabilities: %b\n", (int)sc->capabilities, 1956 IOAT_DMACAP_STR); 1957 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 1958 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 1959 1960 db_printf(" poll_timer:\n"); 1961 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 1962 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 1963 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 1964 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 1965 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 1966 1967 db_printf(" quiescing: %d\n", (int)sc->quiescing); 1968 db_printf(" destroying: %d\n", (int)sc->destroying); 1969 db_printf(" is_submitter_processing: %d\n", 1970 (int)sc->is_submitter_processing); 1971 db_printf(" is_completion_pending: %d\n", (int)sc->is_completion_pending); 1972 db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending); 1973 db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running); 1974 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 1975 db_printf(" resetting: %d\n", (int)sc->resetting); 1976 1977 db_printf(" head: %u\n", sc->head); 1978 db_printf(" tail: %u\n", sc->tail); 1979 db_printf(" hw_head: %u\n", sc->hw_head); 1980 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 1981 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 1982 db_printf(" ring: %p\n", sc->ring); 1983 db_printf(" descriptors: %p\n", sc->hw_desc_ring); 1984 db_printf(" descriptors (phys): 0x%jx\n", 1985 (uintmax_t)sc->hw_desc_bus_addr); 1986 1987 db_printf(" ring[%u] (tail):\n", sc->tail % 1988 (1 << sc->ring_size_order)); 1989 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 1990 db_printf(" addr: 0x%lx\n", 1991 RING_PHYS_ADDR(sc, sc->tail)); 1992 db_printf(" next: 0x%lx\n", 1993 ioat_get_descriptor(sc, sc->tail)->generic.next); 1994 1995 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 1996 (1 << sc->ring_size_order)); 1997 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 1998 db_printf(" addr: 0x%lx\n", 1999 RING_PHYS_ADDR(sc, sc->head - 1)); 2000 db_printf(" next: 0x%lx\n", 2001 ioat_get_descriptor(sc, sc->head - 1)->generic.next); 2002 2003 db_printf(" ring[%u] (head):\n", (sc->head) % 2004 (1 << sc->ring_size_order)); 2005 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2006 db_printf(" addr: 0x%lx\n", 2007 RING_PHYS_ADDR(sc, sc->head)); 2008 db_printf(" next: 0x%lx\n", 2009 ioat_get_descriptor(sc, sc->head)->generic.next); 2010 2011 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2012 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2013 == RING_PHYS_ADDR(sc, idx)) 2014 db_printf(" ring[%u] == hardware tail\n", idx); 2015 2016 db_printf(" cleanup_lock: "); 2017 db_show_lock(&sc->cleanup_lock); 2018 2019 db_printf(" refcnt: %u\n", sc->refcnt); 2020 #ifdef INVARIANTS 2021 CTASSERT(IOAT_NUM_REF_KINDS == 2); 2022 db_printf(" refkinds: [ENG=%u, DESCR=%u]\n", sc->refkinds[0], 2023 sc->refkinds[1]); 2024 #endif 2025 db_printf(" stats:\n"); 2026 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2027 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2028 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2029 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2030 2031 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2032 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2033 2034 if (db_pager_quit) 2035 return; 2036 2037 db_printf(" hw status:\n"); 2038 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2039 db_printf(" chanctrl: 0x%x\n", 2040 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2041 db_printf(" chancmd: 0x%x\n", 2042 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2043 db_printf(" dmacount: 0x%x\n", 2044 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2045 db_printf(" chainaddr: 0x%lx\n", 2046 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2047 db_printf(" chancmp: 0x%lx\n", 2048 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2049 db_printf(" chanerr: %b\n", 2050 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2051 return; 2052 usage: 2053 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2054 return; 2055 } 2056 #endif /* DDB */ 2057