1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ddb.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/ioccom.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/sbuf.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #include <machine/stdarg.h> 52 53 #ifdef DDB 54 #include <ddb/ddb.h> 55 #endif 56 57 #include "ioat.h" 58 #include "ioat_hw.h" 59 #include "ioat_internal.h" 60 61 #ifndef BUS_SPACE_MAXADDR_40BIT 62 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 63 #endif 64 #define IOAT_INTR_TIMO (hz / 10) 65 #define IOAT_REFLK (&ioat->submit_lock) 66 67 static int ioat_probe(device_t device); 68 static int ioat_attach(device_t device); 69 static int ioat_detach(device_t device); 70 static int ioat_setup_intr(struct ioat_softc *ioat); 71 static int ioat_teardown_intr(struct ioat_softc *ioat); 72 static int ioat3_attach(device_t device); 73 static int ioat_start_channel(struct ioat_softc *ioat); 74 static int ioat_map_pci_bar(struct ioat_softc *ioat); 75 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 76 int error); 77 static void ioat_interrupt_handler(void *arg); 78 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 79 static int chanerr_to_errno(uint32_t); 80 static void ioat_process_events(struct ioat_softc *ioat); 81 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 82 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 83 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 84 struct ioat_descriptor **); 85 static void ioat_free_ring_entry(struct ioat_softc *ioat, 86 struct ioat_descriptor *desc); 87 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 88 int mflags); 89 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 90 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 91 uint32_t index); 92 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 93 uint32_t size, boolean_t need_dscr, int mflags); 94 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 95 struct ioat_descriptor **); 96 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 97 struct ioat_descriptor **); 98 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 99 static void ioat_timer_callback(void *arg); 100 static void dump_descriptor(void *hw_desc); 101 static void ioat_submit_single(struct ioat_softc *ioat); 102 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 103 int error); 104 static int ioat_reset_hw(struct ioat_softc *ioat); 105 static void ioat_reset_hw_task(void *, int); 106 static void ioat_setup_sysctl(device_t device); 107 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 108 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 109 enum ioat_ref_kind); 110 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 111 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 112 enum ioat_ref_kind, boolean_t); 113 static inline void ioat_putn(struct ioat_softc *, uint32_t, 114 enum ioat_ref_kind); 115 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 116 enum ioat_ref_kind); 117 static void ioat_drain_locked(struct ioat_softc *); 118 119 #define ioat_log_message(v, ...) do { \ 120 if ((v) <= g_ioat_debug_level) { \ 121 device_printf(ioat->device, __VA_ARGS__); \ 122 } \ 123 } while (0) 124 125 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 126 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 127 128 static int g_force_legacy_interrupts; 129 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 130 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 131 132 int g_ioat_debug_level = 0; 133 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 134 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 135 136 /* 137 * OS <-> Driver interface structures 138 */ 139 static device_method_t ioat_pci_methods[] = { 140 /* Device interface */ 141 DEVMETHOD(device_probe, ioat_probe), 142 DEVMETHOD(device_attach, ioat_attach), 143 DEVMETHOD(device_detach, ioat_detach), 144 DEVMETHOD_END 145 }; 146 147 static driver_t ioat_pci_driver = { 148 "ioat", 149 ioat_pci_methods, 150 sizeof(struct ioat_softc), 151 }; 152 153 static devclass_t ioat_devclass; 154 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 155 MODULE_VERSION(ioat, 1); 156 157 /* 158 * Private data structures 159 */ 160 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 161 static unsigned ioat_channel_index = 0; 162 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 163 "Number of IOAT channels attached"); 164 165 static struct _pcsid 166 { 167 u_int32_t type; 168 const char *desc; 169 } pci_ids[] = { 170 { 0x34308086, "TBG IOAT Ch0" }, 171 { 0x34318086, "TBG IOAT Ch1" }, 172 { 0x34328086, "TBG IOAT Ch2" }, 173 { 0x34338086, "TBG IOAT Ch3" }, 174 { 0x34298086, "TBG IOAT Ch4" }, 175 { 0x342a8086, "TBG IOAT Ch5" }, 176 { 0x342b8086, "TBG IOAT Ch6" }, 177 { 0x342c8086, "TBG IOAT Ch7" }, 178 179 { 0x37108086, "JSF IOAT Ch0" }, 180 { 0x37118086, "JSF IOAT Ch1" }, 181 { 0x37128086, "JSF IOAT Ch2" }, 182 { 0x37138086, "JSF IOAT Ch3" }, 183 { 0x37148086, "JSF IOAT Ch4" }, 184 { 0x37158086, "JSF IOAT Ch5" }, 185 { 0x37168086, "JSF IOAT Ch6" }, 186 { 0x37178086, "JSF IOAT Ch7" }, 187 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 188 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 189 190 { 0x3c208086, "SNB IOAT Ch0" }, 191 { 0x3c218086, "SNB IOAT Ch1" }, 192 { 0x3c228086, "SNB IOAT Ch2" }, 193 { 0x3c238086, "SNB IOAT Ch3" }, 194 { 0x3c248086, "SNB IOAT Ch4" }, 195 { 0x3c258086, "SNB IOAT Ch5" }, 196 { 0x3c268086, "SNB IOAT Ch6" }, 197 { 0x3c278086, "SNB IOAT Ch7" }, 198 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 199 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 200 201 { 0x0e208086, "IVB IOAT Ch0" }, 202 { 0x0e218086, "IVB IOAT Ch1" }, 203 { 0x0e228086, "IVB IOAT Ch2" }, 204 { 0x0e238086, "IVB IOAT Ch3" }, 205 { 0x0e248086, "IVB IOAT Ch4" }, 206 { 0x0e258086, "IVB IOAT Ch5" }, 207 { 0x0e268086, "IVB IOAT Ch6" }, 208 { 0x0e278086, "IVB IOAT Ch7" }, 209 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 210 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 211 212 { 0x2f208086, "HSW IOAT Ch0" }, 213 { 0x2f218086, "HSW IOAT Ch1" }, 214 { 0x2f228086, "HSW IOAT Ch2" }, 215 { 0x2f238086, "HSW IOAT Ch3" }, 216 { 0x2f248086, "HSW IOAT Ch4" }, 217 { 0x2f258086, "HSW IOAT Ch5" }, 218 { 0x2f268086, "HSW IOAT Ch6" }, 219 { 0x2f278086, "HSW IOAT Ch7" }, 220 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 221 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 222 223 { 0x0c508086, "BWD IOAT Ch0" }, 224 { 0x0c518086, "BWD IOAT Ch1" }, 225 { 0x0c528086, "BWD IOAT Ch2" }, 226 { 0x0c538086, "BWD IOAT Ch3" }, 227 228 { 0x6f508086, "BDXDE IOAT Ch0" }, 229 { 0x6f518086, "BDXDE IOAT Ch1" }, 230 { 0x6f528086, "BDXDE IOAT Ch2" }, 231 { 0x6f538086, "BDXDE IOAT Ch3" }, 232 233 { 0x6f208086, "BDX IOAT Ch0" }, 234 { 0x6f218086, "BDX IOAT Ch1" }, 235 { 0x6f228086, "BDX IOAT Ch2" }, 236 { 0x6f238086, "BDX IOAT Ch3" }, 237 { 0x6f248086, "BDX IOAT Ch4" }, 238 { 0x6f258086, "BDX IOAT Ch5" }, 239 { 0x6f268086, "BDX IOAT Ch6" }, 240 { 0x6f278086, "BDX IOAT Ch7" }, 241 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 242 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 243 244 { 0x00000000, NULL } 245 }; 246 247 /* 248 * OS <-> Driver linkage functions 249 */ 250 static int 251 ioat_probe(device_t device) 252 { 253 struct _pcsid *ep; 254 u_int32_t type; 255 256 type = pci_get_devid(device); 257 for (ep = pci_ids; ep->type; ep++) { 258 if (ep->type == type) { 259 device_set_desc(device, ep->desc); 260 return (0); 261 } 262 } 263 return (ENXIO); 264 } 265 266 static int 267 ioat_attach(device_t device) 268 { 269 struct ioat_softc *ioat; 270 int error; 271 272 ioat = DEVICE2SOFTC(device); 273 ioat->device = device; 274 275 error = ioat_map_pci_bar(ioat); 276 if (error != 0) 277 goto err; 278 279 ioat->version = ioat_read_cbver(ioat); 280 if (ioat->version < IOAT_VER_3_0) { 281 error = ENODEV; 282 goto err; 283 } 284 285 error = ioat3_attach(device); 286 if (error != 0) 287 goto err; 288 289 error = pci_enable_busmaster(device); 290 if (error != 0) 291 goto err; 292 293 error = ioat_setup_intr(ioat); 294 if (error != 0) 295 goto err; 296 297 error = ioat_reset_hw(ioat); 298 if (error != 0) 299 goto err; 300 301 ioat_process_events(ioat); 302 ioat_setup_sysctl(device); 303 304 ioat->chan_idx = ioat_channel_index; 305 ioat_channel[ioat_channel_index++] = ioat; 306 ioat_test_attach(); 307 308 err: 309 if (error != 0) 310 ioat_detach(device); 311 return (error); 312 } 313 314 static int 315 ioat_detach(device_t device) 316 { 317 struct ioat_softc *ioat; 318 319 ioat = DEVICE2SOFTC(device); 320 321 ioat_test_detach(); 322 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 323 324 mtx_lock(IOAT_REFLK); 325 ioat->quiescing = TRUE; 326 ioat->destroying = TRUE; 327 wakeup(&ioat->quiescing); 328 329 ioat_channel[ioat->chan_idx] = NULL; 330 331 ioat_drain_locked(ioat); 332 mtx_unlock(IOAT_REFLK); 333 334 ioat_teardown_intr(ioat); 335 callout_drain(&ioat->timer); 336 337 pci_disable_busmaster(device); 338 339 if (ioat->pci_resource != NULL) 340 bus_release_resource(device, SYS_RES_MEMORY, 341 ioat->pci_resource_id, ioat->pci_resource); 342 343 if (ioat->ring != NULL) 344 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 345 346 if (ioat->comp_update != NULL) { 347 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 348 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 349 ioat->comp_update_map); 350 bus_dma_tag_destroy(ioat->comp_update_tag); 351 } 352 353 bus_dma_tag_destroy(ioat->hw_desc_tag); 354 355 return (0); 356 } 357 358 static int 359 ioat_teardown_intr(struct ioat_softc *ioat) 360 { 361 362 if (ioat->tag != NULL) 363 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 364 365 if (ioat->res != NULL) 366 bus_release_resource(ioat->device, SYS_RES_IRQ, 367 rman_get_rid(ioat->res), ioat->res); 368 369 pci_release_msi(ioat->device); 370 return (0); 371 } 372 373 static int 374 ioat_start_channel(struct ioat_softc *ioat) 375 { 376 uint64_t status; 377 uint32_t chanerr; 378 int i; 379 380 ioat_acquire(&ioat->dmaengine); 381 ioat_null(&ioat->dmaengine, NULL, NULL, 0); 382 ioat_release(&ioat->dmaengine); 383 384 for (i = 0; i < 100; i++) { 385 DELAY(1); 386 status = ioat_get_chansts(ioat); 387 if (is_ioat_idle(status)) 388 return (0); 389 } 390 391 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 392 ioat_log_message(0, "could not start channel: " 393 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 394 IOAT_CHANERR_STR); 395 return (ENXIO); 396 } 397 398 /* 399 * Initialize Hardware 400 */ 401 static int 402 ioat3_attach(device_t device) 403 { 404 struct ioat_softc *ioat; 405 struct ioat_descriptor **ring; 406 struct ioat_descriptor *next; 407 struct ioat_dma_hw_descriptor *dma_hw_desc; 408 int i, num_descriptors; 409 int error; 410 uint8_t xfercap; 411 412 error = 0; 413 ioat = DEVICE2SOFTC(device); 414 ioat->capabilities = ioat_read_dmacapability(ioat); 415 416 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 417 IOAT_DMACAP_STR); 418 419 xfercap = ioat_read_xfercap(ioat); 420 ioat->max_xfer_size = 1 << xfercap; 421 422 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 423 IOAT_INTRDELAY_SUPPORTED) != 0; 424 if (ioat->intrdelay_supported) 425 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 426 427 /* TODO: need to check DCA here if we ever do XOR/PQ */ 428 429 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 430 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 431 callout_init(&ioat->timer, 1); 432 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 433 434 /* Establish lock order for Witness */ 435 mtx_lock(&ioat->submit_lock); 436 mtx_lock(&ioat->cleanup_lock); 437 mtx_unlock(&ioat->cleanup_lock); 438 mtx_unlock(&ioat->submit_lock); 439 440 ioat->is_resize_pending = FALSE; 441 ioat->is_completion_pending = FALSE; 442 ioat->is_reset_pending = FALSE; 443 ioat->is_channel_running = FALSE; 444 445 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 446 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 447 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 448 &ioat->comp_update_tag); 449 450 error = bus_dmamem_alloc(ioat->comp_update_tag, 451 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 452 if (ioat->comp_update == NULL) 453 return (ENOMEM); 454 455 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 456 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 457 0); 458 if (error != 0) 459 return (error); 460 461 ioat->ring_size_order = IOAT_MIN_ORDER; 462 463 num_descriptors = 1 << ioat->ring_size_order; 464 465 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 466 BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL, 467 sizeof(struct ioat_dma_hw_descriptor), 1, 468 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 469 &ioat->hw_desc_tag); 470 471 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 472 M_ZERO | M_WAITOK); 473 474 ring = ioat->ring; 475 for (i = 0; i < num_descriptors; i++) { 476 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 477 if (ring[i] == NULL) 478 return (ENOMEM); 479 480 ring[i]->id = i; 481 } 482 483 for (i = 0; i < num_descriptors - 1; i++) { 484 next = ring[i + 1]; 485 dma_hw_desc = ring[i]->u.dma; 486 487 dma_hw_desc->next = next->hw_desc_bus_addr; 488 } 489 490 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 491 492 ioat->head = ioat->hw_head = 0; 493 ioat->tail = 0; 494 ioat->last_seen = 0; 495 return (0); 496 } 497 498 static int 499 ioat_map_pci_bar(struct ioat_softc *ioat) 500 { 501 502 ioat->pci_resource_id = PCIR_BAR(0); 503 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 504 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 505 506 if (ioat->pci_resource == NULL) { 507 ioat_log_message(0, "unable to allocate pci resource\n"); 508 return (ENODEV); 509 } 510 511 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 512 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 513 return (0); 514 } 515 516 static void 517 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 518 { 519 struct ioat_softc *ioat = arg; 520 521 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 522 ioat->comp_update_bus_addr = seg[0].ds_addr; 523 } 524 525 static void 526 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 527 { 528 bus_addr_t *baddr; 529 530 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 531 baddr = arg; 532 *baddr = segs->ds_addr; 533 } 534 535 /* 536 * Interrupt setup and handlers 537 */ 538 static int 539 ioat_setup_intr(struct ioat_softc *ioat) 540 { 541 uint32_t num_vectors; 542 int error; 543 boolean_t use_msix; 544 boolean_t force_legacy_interrupts; 545 546 use_msix = FALSE; 547 force_legacy_interrupts = FALSE; 548 549 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 550 num_vectors = 1; 551 pci_alloc_msix(ioat->device, &num_vectors); 552 if (num_vectors == 1) 553 use_msix = TRUE; 554 } 555 556 if (use_msix) { 557 ioat->rid = 1; 558 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 559 &ioat->rid, RF_ACTIVE); 560 } else { 561 ioat->rid = 0; 562 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 563 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 564 } 565 if (ioat->res == NULL) { 566 ioat_log_message(0, "bus_alloc_resource failed\n"); 567 return (ENOMEM); 568 } 569 570 ioat->tag = NULL; 571 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 572 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 573 if (error != 0) { 574 ioat_log_message(0, "bus_setup_intr failed\n"); 575 return (error); 576 } 577 578 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 579 return (0); 580 } 581 582 static boolean_t 583 ioat_model_resets_msix(struct ioat_softc *ioat) 584 { 585 u_int32_t pciid; 586 587 pciid = pci_get_devid(ioat->device); 588 switch (pciid) { 589 /* BWD: */ 590 case 0x0c508086: 591 case 0x0c518086: 592 case 0x0c528086: 593 case 0x0c538086: 594 /* BDXDE: */ 595 case 0x6f508086: 596 case 0x6f518086: 597 case 0x6f528086: 598 case 0x6f538086: 599 return (TRUE); 600 } 601 602 return (FALSE); 603 } 604 605 static void 606 ioat_interrupt_handler(void *arg) 607 { 608 struct ioat_softc *ioat = arg; 609 610 ioat->stats.interrupts++; 611 ioat_process_events(ioat); 612 } 613 614 static int 615 chanerr_to_errno(uint32_t chanerr) 616 { 617 618 if (chanerr == 0) 619 return (0); 620 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 621 return (EFAULT); 622 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 623 return (EIO); 624 /* This one is probably our fault: */ 625 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 626 return (EIO); 627 return (EIO); 628 } 629 630 static void 631 ioat_process_events(struct ioat_softc *ioat) 632 { 633 struct ioat_descriptor *desc; 634 struct bus_dmadesc *dmadesc; 635 uint64_t comp_update, status; 636 uint32_t completed, chanerr; 637 int error; 638 639 mtx_lock(&ioat->cleanup_lock); 640 641 completed = 0; 642 comp_update = *ioat->comp_update; 643 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 644 645 CTR0(KTR_IOAT, __func__); 646 647 if (status == ioat->last_seen) { 648 /* 649 * If we landed in process_events and nothing has been 650 * completed, check for a timeout due to channel halt. 651 */ 652 comp_update = ioat_get_chansts(ioat); 653 goto out; 654 } 655 656 while (1) { 657 desc = ioat_get_ring_entry(ioat, ioat->tail); 658 dmadesc = &desc->bus_dmadesc; 659 CTR1(KTR_IOAT, "completing desc %d", ioat->tail); 660 661 if (dmadesc->callback_fn != NULL) 662 dmadesc->callback_fn(dmadesc->callback_arg, 0); 663 664 completed++; 665 ioat->tail++; 666 if (desc->hw_desc_bus_addr == status) 667 break; 668 } 669 670 ioat->last_seen = desc->hw_desc_bus_addr; 671 672 if (ioat->head == ioat->tail) { 673 ioat->is_completion_pending = FALSE; 674 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 675 ioat_timer_callback, ioat); 676 } 677 678 ioat->stats.descriptors_processed += completed; 679 680 out: 681 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 682 mtx_unlock(&ioat->cleanup_lock); 683 684 if (completed != 0) { 685 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 686 wakeup(&ioat->tail); 687 } 688 689 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 690 return; 691 692 ioat->stats.channel_halts++; 693 694 /* 695 * Fatal programming error on this DMA channel. Flush any outstanding 696 * work with error status and restart the engine. 697 */ 698 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 699 mtx_lock(&ioat->submit_lock); 700 mtx_lock(&ioat->cleanup_lock); 701 ioat->quiescing = TRUE; 702 703 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 704 ioat_halted_debug(ioat, chanerr); 705 ioat->stats.last_halt_chanerr = chanerr; 706 707 while (ioat_get_active(ioat) > 0) { 708 desc = ioat_get_ring_entry(ioat, ioat->tail); 709 dmadesc = &desc->bus_dmadesc; 710 CTR1(KTR_IOAT, "completing err desc %d", ioat->tail); 711 712 if (dmadesc->callback_fn != NULL) 713 dmadesc->callback_fn(dmadesc->callback_arg, 714 chanerr_to_errno(chanerr)); 715 716 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 717 ioat->tail++; 718 ioat->stats.descriptors_processed++; 719 ioat->stats.descriptors_error++; 720 } 721 722 /* Clear error status */ 723 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 724 725 mtx_unlock(&ioat->cleanup_lock); 726 mtx_unlock(&ioat->submit_lock); 727 728 ioat_log_message(0, "Resetting channel to recover from error\n"); 729 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 730 KASSERT(error == 0, 731 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 732 } 733 734 static void 735 ioat_reset_hw_task(void *ctx, int pending __unused) 736 { 737 struct ioat_softc *ioat; 738 int error; 739 740 ioat = ctx; 741 ioat_log_message(1, "%s: Resetting channel\n", __func__); 742 743 error = ioat_reset_hw(ioat); 744 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 745 (void)error; 746 } 747 748 /* 749 * User API functions 750 */ 751 unsigned 752 ioat_get_nchannels(void) 753 { 754 755 return (ioat_channel_index); 756 } 757 758 bus_dmaengine_t 759 ioat_get_dmaengine(uint32_t index, int flags) 760 { 761 struct ioat_softc *ioat; 762 763 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 764 ("invalid flags: 0x%08x", flags)); 765 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 766 ("invalid wait | nowait")); 767 768 if (index >= ioat_channel_index) 769 return (NULL); 770 771 ioat = ioat_channel[index]; 772 if (ioat == NULL || ioat->destroying) 773 return (NULL); 774 775 if (ioat->quiescing) { 776 if ((flags & M_NOWAIT) != 0) 777 return (NULL); 778 779 mtx_lock(IOAT_REFLK); 780 while (ioat->quiescing && !ioat->destroying) 781 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 782 mtx_unlock(IOAT_REFLK); 783 784 if (ioat->destroying) 785 return (NULL); 786 } 787 788 /* 789 * There's a race here between the quiescing check and HW reset or 790 * module destroy. 791 */ 792 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 793 } 794 795 void 796 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 797 { 798 struct ioat_softc *ioat; 799 800 ioat = to_ioat_softc(dmaengine); 801 ioat_put(ioat, IOAT_DMAENGINE_REF); 802 } 803 804 int 805 ioat_get_hwversion(bus_dmaengine_t dmaengine) 806 { 807 struct ioat_softc *ioat; 808 809 ioat = to_ioat_softc(dmaengine); 810 return (ioat->version); 811 } 812 813 size_t 814 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 815 { 816 struct ioat_softc *ioat; 817 818 ioat = to_ioat_softc(dmaengine); 819 return (ioat->max_xfer_size); 820 } 821 822 int 823 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 824 { 825 struct ioat_softc *ioat; 826 827 ioat = to_ioat_softc(dmaengine); 828 if (!ioat->intrdelay_supported) 829 return (ENODEV); 830 if (delay > ioat->intrdelay_max) 831 return (ERANGE); 832 833 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 834 ioat->cached_intrdelay = 835 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 836 return (0); 837 } 838 839 uint16_t 840 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 841 { 842 struct ioat_softc *ioat; 843 844 ioat = to_ioat_softc(dmaengine); 845 return (ioat->intrdelay_max); 846 } 847 848 void 849 ioat_acquire(bus_dmaengine_t dmaengine) 850 { 851 struct ioat_softc *ioat; 852 853 ioat = to_ioat_softc(dmaengine); 854 mtx_lock(&ioat->submit_lock); 855 CTR0(KTR_IOAT, __func__); 856 } 857 858 int 859 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 860 { 861 struct ioat_softc *ioat; 862 int error; 863 864 ioat = to_ioat_softc(dmaengine); 865 ioat_acquire(dmaengine); 866 867 error = ioat_reserve_space(ioat, n, mflags); 868 if (error != 0) 869 ioat_release(dmaengine); 870 return (error); 871 } 872 873 void 874 ioat_release(bus_dmaengine_t dmaengine) 875 { 876 struct ioat_softc *ioat; 877 878 ioat = to_ioat_softc(dmaengine); 879 CTR0(KTR_IOAT, __func__); 880 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 881 mtx_unlock(&ioat->submit_lock); 882 } 883 884 static struct ioat_descriptor * 885 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 886 uint32_t size, uint64_t src, uint64_t dst, 887 bus_dmaengine_callback_t callback_fn, void *callback_arg, 888 uint32_t flags) 889 { 890 struct ioat_generic_hw_descriptor *hw_desc; 891 struct ioat_descriptor *desc; 892 int mflags; 893 894 mtx_assert(&ioat->submit_lock, MA_OWNED); 895 896 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 897 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 898 if ((flags & DMA_NO_WAIT) != 0) 899 mflags = M_NOWAIT; 900 else 901 mflags = M_WAITOK; 902 903 if (size > ioat->max_xfer_size) { 904 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 905 __func__, ioat->max_xfer_size, (unsigned)size); 906 return (NULL); 907 } 908 909 if (ioat_reserve_space(ioat, 1, mflags) != 0) 910 return (NULL); 911 912 desc = ioat_get_ring_entry(ioat, ioat->head); 913 hw_desc = desc->u.generic; 914 915 hw_desc->u.control_raw = 0; 916 hw_desc->u.control_generic.op = op; 917 hw_desc->u.control_generic.completion_update = 1; 918 919 if ((flags & DMA_INT_EN) != 0) 920 hw_desc->u.control_generic.int_enable = 1; 921 if ((flags & DMA_FENCE) != 0) 922 hw_desc->u.control_generic.fence = 1; 923 924 hw_desc->size = size; 925 hw_desc->src_addr = src; 926 hw_desc->dest_addr = dst; 927 928 desc->bus_dmadesc.callback_fn = callback_fn; 929 desc->bus_dmadesc.callback_arg = callback_arg; 930 return (desc); 931 } 932 933 struct bus_dmadesc * 934 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 935 void *callback_arg, uint32_t flags) 936 { 937 struct ioat_dma_hw_descriptor *hw_desc; 938 struct ioat_descriptor *desc; 939 struct ioat_softc *ioat; 940 941 CTR0(KTR_IOAT, __func__); 942 ioat = to_ioat_softc(dmaengine); 943 944 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 945 callback_arg, flags); 946 if (desc == NULL) 947 return (NULL); 948 949 hw_desc = desc->u.dma; 950 hw_desc->u.control.null = 1; 951 ioat_submit_single(ioat); 952 return (&desc->bus_dmadesc); 953 } 954 955 struct bus_dmadesc * 956 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 957 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 958 void *callback_arg, uint32_t flags) 959 { 960 struct ioat_dma_hw_descriptor *hw_desc; 961 struct ioat_descriptor *desc; 962 struct ioat_softc *ioat; 963 964 CTR0(KTR_IOAT, __func__); 965 ioat = to_ioat_softc(dmaengine); 966 967 if (((src | dst) & (0xffffull << 48)) != 0) { 968 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 969 __func__); 970 return (NULL); 971 } 972 973 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 974 callback_arg, flags); 975 if (desc == NULL) 976 return (NULL); 977 978 hw_desc = desc->u.dma; 979 if (g_ioat_debug_level >= 3) 980 dump_descriptor(hw_desc); 981 982 ioat_submit_single(ioat); 983 return (&desc->bus_dmadesc); 984 } 985 986 struct bus_dmadesc * 987 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 988 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 989 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 990 { 991 struct ioat_dma_hw_descriptor *hw_desc; 992 struct ioat_descriptor *desc; 993 struct ioat_softc *ioat; 994 995 CTR0(KTR_IOAT, __func__); 996 ioat = to_ioat_softc(dmaengine); 997 998 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 999 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1000 __func__); 1001 return (NULL); 1002 } 1003 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 1004 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 1005 __func__); 1006 return (NULL); 1007 } 1008 1009 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 1010 callback_fn, callback_arg, flags); 1011 if (desc == NULL) 1012 return (NULL); 1013 1014 hw_desc = desc->u.dma; 1015 if (src2 != src1 + PAGE_SIZE) { 1016 hw_desc->u.control.src_page_break = 1; 1017 hw_desc->next_src_addr = src2; 1018 } 1019 if (dst2 != dst1 + PAGE_SIZE) { 1020 hw_desc->u.control.dest_page_break = 1; 1021 hw_desc->next_dest_addr = dst2; 1022 } 1023 1024 if (g_ioat_debug_level >= 3) 1025 dump_descriptor(hw_desc); 1026 1027 ioat_submit_single(ioat); 1028 return (&desc->bus_dmadesc); 1029 } 1030 1031 struct bus_dmadesc * 1032 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1033 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1034 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1035 { 1036 struct ioat_crc32_hw_descriptor *hw_desc; 1037 struct ioat_descriptor *desc; 1038 struct ioat_softc *ioat; 1039 uint32_t teststore; 1040 uint8_t op; 1041 1042 CTR0(KTR_IOAT, __func__); 1043 ioat = to_ioat_softc(dmaengine); 1044 1045 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1046 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1047 __func__); 1048 return (NULL); 1049 } 1050 if (((src | dst) & (0xffffffull << 40)) != 0) { 1051 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1052 __func__); 1053 return (NULL); 1054 } 1055 teststore = (flags & _DMA_CRC_TESTSTORE); 1056 if (teststore == _DMA_CRC_TESTSTORE) { 1057 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1058 return (NULL); 1059 } 1060 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1061 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1062 __func__); 1063 return (NULL); 1064 } 1065 1066 switch (teststore) { 1067 case DMA_CRC_STORE: 1068 op = IOAT_OP_MOVECRC_STORE; 1069 break; 1070 case DMA_CRC_TEST: 1071 op = IOAT_OP_MOVECRC_TEST; 1072 break; 1073 default: 1074 KASSERT(teststore == 0, ("bogus")); 1075 op = IOAT_OP_MOVECRC; 1076 break; 1077 } 1078 1079 if ((flags & DMA_CRC_INLINE) == 0 && 1080 (crcptr & (0xffffffull << 40)) != 0) { 1081 ioat_log_message(0, 1082 "%s: High 24 bits of crcptr invalid\n", __func__); 1083 return (NULL); 1084 } 1085 1086 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1087 callback_arg, flags & ~_DMA_CRC_FLAGS); 1088 if (desc == NULL) 1089 return (NULL); 1090 1091 hw_desc = desc->u.crc32; 1092 1093 if ((flags & DMA_CRC_INLINE) == 0) 1094 hw_desc->crc_address = crcptr; 1095 else 1096 hw_desc->u.control.crc_location = 1; 1097 1098 if (initialseed != NULL) { 1099 hw_desc->u.control.use_seed = 1; 1100 hw_desc->seed = *initialseed; 1101 } 1102 1103 if (g_ioat_debug_level >= 3) 1104 dump_descriptor(hw_desc); 1105 1106 ioat_submit_single(ioat); 1107 return (&desc->bus_dmadesc); 1108 } 1109 1110 struct bus_dmadesc * 1111 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1112 uint32_t *initialseed, bus_addr_t crcptr, 1113 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1114 { 1115 struct ioat_crc32_hw_descriptor *hw_desc; 1116 struct ioat_descriptor *desc; 1117 struct ioat_softc *ioat; 1118 uint32_t teststore; 1119 uint8_t op; 1120 1121 CTR0(KTR_IOAT, __func__); 1122 ioat = to_ioat_softc(dmaengine); 1123 1124 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1125 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1126 __func__); 1127 return (NULL); 1128 } 1129 if ((src & (0xffffffull << 40)) != 0) { 1130 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1131 __func__); 1132 return (NULL); 1133 } 1134 teststore = (flags & _DMA_CRC_TESTSTORE); 1135 if (teststore == _DMA_CRC_TESTSTORE) { 1136 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1137 return (NULL); 1138 } 1139 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1140 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1141 __func__); 1142 return (NULL); 1143 } 1144 1145 switch (teststore) { 1146 case DMA_CRC_STORE: 1147 op = IOAT_OP_CRC_STORE; 1148 break; 1149 case DMA_CRC_TEST: 1150 op = IOAT_OP_CRC_TEST; 1151 break; 1152 default: 1153 KASSERT(teststore == 0, ("bogus")); 1154 op = IOAT_OP_CRC; 1155 break; 1156 } 1157 1158 if ((flags & DMA_CRC_INLINE) == 0 && 1159 (crcptr & (0xffffffull << 40)) != 0) { 1160 ioat_log_message(0, 1161 "%s: High 24 bits of crcptr invalid\n", __func__); 1162 return (NULL); 1163 } 1164 1165 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1166 callback_arg, flags & ~_DMA_CRC_FLAGS); 1167 if (desc == NULL) 1168 return (NULL); 1169 1170 hw_desc = desc->u.crc32; 1171 1172 if ((flags & DMA_CRC_INLINE) == 0) 1173 hw_desc->crc_address = crcptr; 1174 else 1175 hw_desc->u.control.crc_location = 1; 1176 1177 if (initialseed != NULL) { 1178 hw_desc->u.control.use_seed = 1; 1179 hw_desc->seed = *initialseed; 1180 } 1181 1182 if (g_ioat_debug_level >= 3) 1183 dump_descriptor(hw_desc); 1184 1185 ioat_submit_single(ioat); 1186 return (&desc->bus_dmadesc); 1187 } 1188 1189 struct bus_dmadesc * 1190 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1191 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1192 uint32_t flags) 1193 { 1194 struct ioat_fill_hw_descriptor *hw_desc; 1195 struct ioat_descriptor *desc; 1196 struct ioat_softc *ioat; 1197 1198 CTR0(KTR_IOAT, __func__); 1199 ioat = to_ioat_softc(dmaengine); 1200 1201 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1202 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1203 __func__); 1204 return (NULL); 1205 } 1206 1207 if ((dst & (0xffffull << 48)) != 0) { 1208 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1209 __func__); 1210 return (NULL); 1211 } 1212 1213 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1214 callback_fn, callback_arg, flags); 1215 if (desc == NULL) 1216 return (NULL); 1217 1218 hw_desc = desc->u.fill; 1219 if (g_ioat_debug_level >= 3) 1220 dump_descriptor(hw_desc); 1221 1222 ioat_submit_single(ioat); 1223 return (&desc->bus_dmadesc); 1224 } 1225 1226 /* 1227 * Ring Management 1228 */ 1229 static inline uint32_t 1230 ioat_get_active(struct ioat_softc *ioat) 1231 { 1232 1233 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1234 } 1235 1236 static inline uint32_t 1237 ioat_get_ring_space(struct ioat_softc *ioat) 1238 { 1239 1240 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1241 } 1242 1243 static struct ioat_descriptor * 1244 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 1245 { 1246 struct ioat_generic_hw_descriptor *hw_desc; 1247 struct ioat_descriptor *desc; 1248 int error, busdmaflag; 1249 1250 error = ENOMEM; 1251 hw_desc = NULL; 1252 1253 if ((mflags & M_WAITOK) != 0) 1254 busdmaflag = BUS_DMA_WAITOK; 1255 else 1256 busdmaflag = BUS_DMA_NOWAIT; 1257 1258 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1259 if (desc == NULL) 1260 goto out; 1261 1262 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1263 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1264 if (hw_desc == NULL) 1265 goto out; 1266 1267 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1268 desc->u.generic = hw_desc; 1269 1270 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1271 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1272 busdmaflag); 1273 if (error) 1274 goto out; 1275 1276 out: 1277 if (error) { 1278 ioat_free_ring_entry(ioat, desc); 1279 return (NULL); 1280 } 1281 return (desc); 1282 } 1283 1284 static void 1285 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1286 { 1287 1288 if (desc == NULL) 1289 return; 1290 1291 if (desc->u.generic) 1292 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1293 ioat->hw_desc_map); 1294 free(desc, M_IOAT); 1295 } 1296 1297 /* 1298 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1299 * for 'num_descs'. 1300 * 1301 * If mflags contains M_WAITOK, blocks until enough space is available. 1302 * 1303 * Returns zero on success, or an errno on error. If num_descs is beyond the 1304 * maximum ring size, returns EINVAl; if allocation would block and mflags 1305 * contains M_NOWAIT, returns EAGAIN. 1306 * 1307 * Must be called with the submit_lock held; returns with the lock held. The 1308 * lock may be dropped to allocate the ring. 1309 * 1310 * (The submit_lock is needed to add any entries to the ring, so callers are 1311 * assured enough room is available.) 1312 */ 1313 static int 1314 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1315 { 1316 struct ioat_descriptor **new_ring; 1317 uint32_t order; 1318 int error; 1319 1320 mtx_assert(&ioat->submit_lock, MA_OWNED); 1321 error = 0; 1322 1323 if (num_descs < 1 || num_descs > (1 << IOAT_MAX_ORDER)) { 1324 error = EINVAL; 1325 goto out; 1326 } 1327 if (ioat->quiescing) { 1328 error = ENXIO; 1329 goto out; 1330 } 1331 1332 for (;;) { 1333 if (ioat_get_ring_space(ioat) >= num_descs) 1334 goto out; 1335 1336 order = ioat->ring_size_order; 1337 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1338 if ((mflags & M_WAITOK) != 0) { 1339 msleep(&ioat->tail, &ioat->submit_lock, 0, 1340 "ioat_rsz", 0); 1341 continue; 1342 } 1343 1344 error = EAGAIN; 1345 break; 1346 } 1347 1348 ioat->is_resize_pending = TRUE; 1349 for (;;) { 1350 mtx_unlock(&ioat->submit_lock); 1351 1352 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1353 TRUE, mflags); 1354 1355 mtx_lock(&ioat->submit_lock); 1356 KASSERT(ioat->ring_size_order == order, 1357 ("is_resize_pending should protect order")); 1358 1359 if (new_ring == NULL) { 1360 KASSERT((mflags & M_WAITOK) == 0, 1361 ("allocation failed")); 1362 error = EAGAIN; 1363 break; 1364 } 1365 1366 error = ring_grow(ioat, order, new_ring); 1367 if (error == 0) 1368 break; 1369 } 1370 ioat->is_resize_pending = FALSE; 1371 wakeup(&ioat->tail); 1372 if (error) 1373 break; 1374 } 1375 1376 out: 1377 mtx_assert(&ioat->submit_lock, MA_OWNED); 1378 return (error); 1379 } 1380 1381 static struct ioat_descriptor ** 1382 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1383 int mflags) 1384 { 1385 struct ioat_descriptor **ring; 1386 uint32_t i; 1387 int error; 1388 1389 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1390 1391 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1392 if (ring == NULL) 1393 return (NULL); 1394 1395 if (need_dscr) { 1396 error = ENOMEM; 1397 for (i = size / 2; i < size; i++) { 1398 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1399 if (ring[i] == NULL) 1400 goto out; 1401 ring[i]->id = i; 1402 } 1403 } 1404 error = 0; 1405 1406 out: 1407 if (error != 0 && ring != NULL) { 1408 ioat_free_ring(ioat, size, ring); 1409 ring = NULL; 1410 } 1411 return (ring); 1412 } 1413 1414 static void 1415 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1416 struct ioat_descriptor **ring) 1417 { 1418 uint32_t i; 1419 1420 for (i = 0; i < size; i++) { 1421 if (ring[i] != NULL) 1422 ioat_free_ring_entry(ioat, ring[i]); 1423 } 1424 free(ring, M_IOAT); 1425 } 1426 1427 static struct ioat_descriptor * 1428 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1429 { 1430 1431 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1432 } 1433 1434 static int 1435 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1436 struct ioat_descriptor **newring) 1437 { 1438 struct ioat_descriptor *tmp, *next; 1439 struct ioat_dma_hw_descriptor *hw; 1440 uint32_t oldsize, newsize, head, tail, i, end; 1441 int error; 1442 1443 CTR0(KTR_IOAT, __func__); 1444 1445 mtx_assert(&ioat->submit_lock, MA_OWNED); 1446 1447 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1448 error = EINVAL; 1449 goto out; 1450 } 1451 1452 oldsize = (1 << oldorder); 1453 newsize = (1 << (oldorder + 1)); 1454 1455 mtx_lock(&ioat->cleanup_lock); 1456 1457 head = ioat->head & (oldsize - 1); 1458 tail = ioat->tail & (oldsize - 1); 1459 1460 /* Copy old descriptors to new ring */ 1461 for (i = 0; i < oldsize; i++) 1462 newring[i] = ioat->ring[i]; 1463 1464 /* 1465 * If head has wrapped but tail hasn't, we must swap some descriptors 1466 * around so that tail can increment directly to head. 1467 */ 1468 if (head < tail) { 1469 for (i = 0; i <= head; i++) { 1470 tmp = newring[oldsize + i]; 1471 1472 newring[oldsize + i] = newring[i]; 1473 newring[oldsize + i]->id = oldsize + i; 1474 1475 newring[i] = tmp; 1476 newring[i]->id = i; 1477 } 1478 head += oldsize; 1479 } 1480 1481 KASSERT(head >= tail, ("invariants")); 1482 1483 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1484 if (head < oldsize) { 1485 i = oldsize - 1; 1486 end = newsize; 1487 } else { 1488 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1489 i = head; 1490 end = newsize + (head - oldsize) + 1; 1491 } 1492 1493 /* 1494 * Fix up hardware ring, being careful not to trample the active 1495 * section (tail -> head). 1496 */ 1497 for (; i < end; i++) { 1498 KASSERT((i & (newsize - 1)) < tail || 1499 (i & (newsize - 1)) >= head, ("trampling snake")); 1500 1501 next = newring[(i + 1) & (newsize - 1)]; 1502 hw = newring[i & (newsize - 1)]->u.dma; 1503 hw->next = next->hw_desc_bus_addr; 1504 } 1505 1506 free(ioat->ring, M_IOAT); 1507 ioat->ring = newring; 1508 ioat->ring_size_order = oldorder + 1; 1509 ioat->tail = tail; 1510 ioat->head = head; 1511 error = 0; 1512 1513 mtx_unlock(&ioat->cleanup_lock); 1514 out: 1515 if (error) 1516 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1517 return (error); 1518 } 1519 1520 static int 1521 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1522 struct ioat_descriptor **newring) 1523 { 1524 struct ioat_dma_hw_descriptor *hw; 1525 struct ioat_descriptor *ent, *next; 1526 uint32_t oldsize, newsize, current_idx, new_idx, i; 1527 int error; 1528 1529 CTR0(KTR_IOAT, __func__); 1530 1531 mtx_assert(&ioat->submit_lock, MA_OWNED); 1532 1533 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1534 error = EINVAL; 1535 goto out_unlocked; 1536 } 1537 1538 oldsize = (1 << oldorder); 1539 newsize = (1 << (oldorder - 1)); 1540 1541 mtx_lock(&ioat->cleanup_lock); 1542 1543 /* Can't shrink below current active set! */ 1544 if (ioat_get_active(ioat) >= newsize) { 1545 error = ENOMEM; 1546 goto out; 1547 } 1548 1549 /* 1550 * Copy current descriptors to the new ring, dropping the removed 1551 * descriptors. 1552 */ 1553 for (i = 0; i < newsize; i++) { 1554 current_idx = (ioat->tail + i) & (oldsize - 1); 1555 new_idx = (ioat->tail + i) & (newsize - 1); 1556 1557 newring[new_idx] = ioat->ring[current_idx]; 1558 newring[new_idx]->id = new_idx; 1559 } 1560 1561 /* Free deleted descriptors */ 1562 for (i = newsize; i < oldsize; i++) { 1563 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1564 ioat_free_ring_entry(ioat, ent); 1565 } 1566 1567 /* Fix up hardware ring. */ 1568 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1569 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1570 hw->next = next->hw_desc_bus_addr; 1571 1572 free(ioat->ring, M_IOAT); 1573 ioat->ring = newring; 1574 ioat->ring_size_order = oldorder - 1; 1575 error = 0; 1576 1577 out: 1578 mtx_unlock(&ioat->cleanup_lock); 1579 out_unlocked: 1580 if (error) 1581 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1582 return (error); 1583 } 1584 1585 static void 1586 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1587 { 1588 struct ioat_descriptor *desc; 1589 1590 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1591 IOAT_CHANERR_STR); 1592 if (chanerr == 0) 1593 return; 1594 1595 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1596 1597 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1598 dump_descriptor(desc->u.raw); 1599 1600 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1601 dump_descriptor(desc->u.raw); 1602 } 1603 1604 static void 1605 ioat_timer_callback(void *arg) 1606 { 1607 struct ioat_descriptor **newring; 1608 struct ioat_softc *ioat; 1609 uint32_t order; 1610 1611 ioat = arg; 1612 ioat_log_message(1, "%s\n", __func__); 1613 1614 if (ioat->is_completion_pending) { 1615 ioat_process_events(ioat); 1616 return; 1617 } 1618 1619 /* Slowly scale the ring down if idle. */ 1620 mtx_lock(&ioat->submit_lock); 1621 order = ioat->ring_size_order; 1622 if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) { 1623 mtx_unlock(&ioat->submit_lock); 1624 goto out; 1625 } 1626 ioat->is_resize_pending = TRUE; 1627 mtx_unlock(&ioat->submit_lock); 1628 1629 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1630 M_NOWAIT); 1631 1632 mtx_lock(&ioat->submit_lock); 1633 KASSERT(ioat->ring_size_order == order, 1634 ("resize_pending protects order")); 1635 1636 if (newring != NULL) 1637 ring_shrink(ioat, order, newring); 1638 1639 ioat->is_resize_pending = FALSE; 1640 mtx_unlock(&ioat->submit_lock); 1641 1642 out: 1643 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1644 callout_reset(&ioat->timer, 10 * hz, 1645 ioat_timer_callback, ioat); 1646 } 1647 1648 /* 1649 * Support Functions 1650 */ 1651 static void 1652 ioat_submit_single(struct ioat_softc *ioat) 1653 { 1654 1655 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1656 atomic_add_rel_int(&ioat->head, 1); 1657 atomic_add_rel_int(&ioat->hw_head, 1); 1658 1659 if (!ioat->is_completion_pending) { 1660 ioat->is_completion_pending = TRUE; 1661 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 1662 ioat_timer_callback, ioat); 1663 } 1664 1665 ioat->stats.descriptors_submitted++; 1666 } 1667 1668 static int 1669 ioat_reset_hw(struct ioat_softc *ioat) 1670 { 1671 uint64_t status; 1672 uint32_t chanerr; 1673 unsigned timeout; 1674 int error; 1675 1676 mtx_lock(IOAT_REFLK); 1677 ioat->quiescing = TRUE; 1678 ioat_drain_locked(ioat); 1679 mtx_unlock(IOAT_REFLK); 1680 1681 status = ioat_get_chansts(ioat); 1682 if (is_ioat_active(status) || is_ioat_idle(status)) 1683 ioat_suspend(ioat); 1684 1685 /* Wait at most 20 ms */ 1686 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1687 timeout < 20; timeout++) { 1688 DELAY(1000); 1689 status = ioat_get_chansts(ioat); 1690 } 1691 if (timeout == 20) { 1692 error = ETIMEDOUT; 1693 goto out; 1694 } 1695 1696 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1697 1698 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1699 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1700 1701 /* 1702 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1703 * that can cause stability issues for IOAT v3. 1704 */ 1705 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1706 4); 1707 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1708 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1709 1710 /* 1711 * BDXDE and BWD models reset MSI-X registers on device reset. 1712 * Save/restore their contents manually. 1713 */ 1714 if (ioat_model_resets_msix(ioat)) { 1715 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1716 pci_save_state(ioat->device); 1717 } 1718 1719 ioat_reset(ioat); 1720 1721 /* Wait at most 20 ms */ 1722 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1723 DELAY(1000); 1724 if (timeout == 20) { 1725 error = ETIMEDOUT; 1726 goto out; 1727 } 1728 1729 if (ioat_model_resets_msix(ioat)) { 1730 ioat_log_message(1, "device resets registers; restored\n"); 1731 pci_restore_state(ioat->device); 1732 } 1733 1734 /* Reset attempts to return the hardware to "halted." */ 1735 status = ioat_get_chansts(ioat); 1736 if (is_ioat_active(status) || is_ioat_idle(status)) { 1737 /* So this really shouldn't happen... */ 1738 ioat_log_message(0, "Device is active after a reset?\n"); 1739 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1740 error = 0; 1741 goto out; 1742 } 1743 1744 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1745 if (chanerr != 0) { 1746 mtx_lock(&ioat->cleanup_lock); 1747 ioat_halted_debug(ioat, chanerr); 1748 mtx_unlock(&ioat->cleanup_lock); 1749 error = EIO; 1750 goto out; 1751 } 1752 1753 /* 1754 * Bring device back online after reset. Writing CHAINADDR brings the 1755 * device back to active. 1756 * 1757 * The internal ring counter resets to zero, so we have to start over 1758 * at zero as well. 1759 */ 1760 ioat->tail = ioat->head = ioat->hw_head = 0; 1761 ioat->last_seen = 0; 1762 1763 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1764 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1765 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1766 error = 0; 1767 1768 out: 1769 mtx_lock(IOAT_REFLK); 1770 ioat->quiescing = FALSE; 1771 wakeup(&ioat->quiescing); 1772 mtx_unlock(IOAT_REFLK); 1773 1774 if (error == 0) 1775 error = ioat_start_channel(ioat); 1776 1777 return (error); 1778 } 1779 1780 static int 1781 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1782 { 1783 struct ioat_softc *ioat; 1784 struct sbuf sb; 1785 uint64_t status; 1786 int error; 1787 1788 ioat = arg1; 1789 1790 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1791 1792 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1793 switch (status) { 1794 case IOAT_CHANSTS_ACTIVE: 1795 sbuf_printf(&sb, "ACTIVE"); 1796 break; 1797 case IOAT_CHANSTS_IDLE: 1798 sbuf_printf(&sb, "IDLE"); 1799 break; 1800 case IOAT_CHANSTS_SUSPENDED: 1801 sbuf_printf(&sb, "SUSPENDED"); 1802 break; 1803 case IOAT_CHANSTS_HALTED: 1804 sbuf_printf(&sb, "HALTED"); 1805 break; 1806 case IOAT_CHANSTS_ARMED: 1807 sbuf_printf(&sb, "ARMED"); 1808 break; 1809 default: 1810 sbuf_printf(&sb, "UNKNOWN"); 1811 break; 1812 } 1813 error = sbuf_finish(&sb); 1814 sbuf_delete(&sb); 1815 1816 if (error != 0 || req->newptr == NULL) 1817 return (error); 1818 return (EINVAL); 1819 } 1820 1821 static int 1822 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1823 { 1824 struct ioat_softc *ioat; 1825 struct sbuf sb; 1826 #define PRECISION "1" 1827 const uintmax_t factor = 10; 1828 uintmax_t rate; 1829 int error; 1830 1831 ioat = arg1; 1832 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1833 1834 if (ioat->stats.interrupts == 0) { 1835 sbuf_printf(&sb, "NaN"); 1836 goto out; 1837 } 1838 rate = ioat->stats.descriptors_processed * factor / 1839 ioat->stats.interrupts; 1840 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1841 rate % factor); 1842 #undef PRECISION 1843 out: 1844 error = sbuf_finish(&sb); 1845 sbuf_delete(&sb); 1846 if (error != 0 || req->newptr == NULL) 1847 return (error); 1848 return (EINVAL); 1849 } 1850 1851 static int 1852 sysctl_handle_error(SYSCTL_HANDLER_ARGS) 1853 { 1854 struct ioat_descriptor *desc; 1855 struct ioat_softc *ioat; 1856 int error, arg; 1857 1858 ioat = arg1; 1859 1860 arg = 0; 1861 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1862 if (error != 0 || req->newptr == NULL) 1863 return (error); 1864 1865 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1866 if (error != 0) 1867 return (error); 1868 1869 if (arg != 0) { 1870 ioat_acquire(&ioat->dmaengine); 1871 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 1, 1872 0xffff000000000000ull, 0xffff000000000000ull, NULL, NULL, 1873 0); 1874 if (desc == NULL) 1875 error = ENOMEM; 1876 else 1877 ioat_submit_single(ioat); 1878 ioat_release(&ioat->dmaengine); 1879 } 1880 return (error); 1881 } 1882 1883 static int 1884 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1885 { 1886 struct ioat_softc *ioat; 1887 int error, arg; 1888 1889 ioat = arg1; 1890 1891 arg = 0; 1892 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1893 if (error != 0 || req->newptr == NULL) 1894 return (error); 1895 1896 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1897 if (error != 0) 1898 return (error); 1899 1900 if (arg != 0) 1901 error = ioat_reset_hw(ioat); 1902 1903 return (error); 1904 } 1905 1906 static void 1907 dump_descriptor(void *hw_desc) 1908 { 1909 int i, j; 1910 1911 for (i = 0; i < 2; i++) { 1912 for (j = 0; j < 8; j++) 1913 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1914 printf("\n"); 1915 } 1916 } 1917 1918 static void 1919 ioat_setup_sysctl(device_t device) 1920 { 1921 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1922 struct sysctl_ctx_list *ctx; 1923 struct sysctl_oid *tree, *tmp; 1924 struct ioat_softc *ioat; 1925 1926 ioat = DEVICE2SOFTC(device); 1927 ctx = device_get_sysctl_ctx(device); 1928 tree = device_get_sysctl_tree(device); 1929 par = SYSCTL_CHILDREN(tree); 1930 1931 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1932 &ioat->version, 0, "HW version (0xMM form)"); 1933 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1934 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1935 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1936 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1937 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1938 &ioat->intrdelay_max, 0, 1939 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1940 1941 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 1942 "IOAT channel internal state"); 1943 state = SYSCTL_CHILDREN(tmp); 1944 1945 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1946 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1947 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1948 0, "SW descriptor head pointer index"); 1949 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1950 0, "SW descriptor tail pointer index"); 1951 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 1952 &ioat->hw_head, 0, "HW DMACOUNT"); 1953 1954 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1955 ioat->comp_update, "HW addr of last completion"); 1956 1957 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 1958 &ioat->is_resize_pending, 0, "resize pending"); 1959 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 1960 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 1961 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1962 &ioat->is_reset_pending, 0, "reset pending"); 1963 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1964 &ioat->is_channel_running, 0, "channel running"); 1965 1966 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1967 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1968 "String of the channel status"); 1969 1970 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1971 &ioat->cached_intrdelay, 0, 1972 "Current INTRDELAY on this channel (cached, microseconds)"); 1973 1974 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 1975 "Big hammers (mostly for testing)"); 1976 hammer = SYSCTL_CHILDREN(tmp); 1977 1978 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1979 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1980 "Set to non-zero to reset the hardware"); 1981 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_error", 1982 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_error, "I", 1983 "Set to non-zero to inject a recoverable hardware error"); 1984 1985 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 1986 "IOAT channel statistics"); 1987 statpar = SYSCTL_CHILDREN(tmp); 1988 1989 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 1990 &ioat->stats.interrupts, 1991 "Number of interrupts processed on this channel"); 1992 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 1993 &ioat->stats.descriptors_processed, 1994 "Number of descriptors processed on this channel"); 1995 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 1996 &ioat->stats.descriptors_submitted, 1997 "Number of descriptors submitted to this channel"); 1998 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 1999 &ioat->stats.descriptors_error, 2000 "Number of descriptors failed by channel errors"); 2001 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 2002 &ioat->stats.channel_halts, 0, 2003 "Number of times the channel has halted"); 2004 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 2005 &ioat->stats.last_halt_chanerr, 0, 2006 "The raw CHANERR when the channel was last halted"); 2007 2008 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 2009 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 2010 "Descriptors per interrupt"); 2011 } 2012 2013 static inline struct ioat_softc * 2014 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2015 { 2016 uint32_t old; 2017 2018 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2019 2020 old = atomic_fetchadd_32(&ioat->refcnt, 1); 2021 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 2022 2023 #ifdef INVARIANTS 2024 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 2025 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 2026 #endif 2027 2028 return (ioat); 2029 } 2030 2031 static inline void 2032 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2033 { 2034 2035 _ioat_putn(ioat, n, kind, FALSE); 2036 } 2037 2038 static inline void 2039 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2040 { 2041 2042 _ioat_putn(ioat, n, kind, TRUE); 2043 } 2044 2045 static inline void 2046 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 2047 boolean_t locked) 2048 { 2049 uint32_t old; 2050 2051 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2052 2053 if (n == 0) 2054 return; 2055 2056 #ifdef INVARIANTS 2057 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 2058 KASSERT(old >= n, ("refcnt kind underflow")); 2059 #endif 2060 2061 /* Skip acquiring the lock if resulting refcnt > 0. */ 2062 for (;;) { 2063 old = ioat->refcnt; 2064 if (old <= n) 2065 break; 2066 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 2067 return; 2068 } 2069 2070 if (locked) 2071 mtx_assert(IOAT_REFLK, MA_OWNED); 2072 else 2073 mtx_lock(IOAT_REFLK); 2074 2075 old = atomic_fetchadd_32(&ioat->refcnt, -n); 2076 KASSERT(old >= n, ("refcnt error")); 2077 2078 if (old == n) 2079 wakeup(IOAT_REFLK); 2080 if (!locked) 2081 mtx_unlock(IOAT_REFLK); 2082 } 2083 2084 static inline void 2085 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2086 { 2087 2088 ioat_putn(ioat, 1, kind); 2089 } 2090 2091 static void 2092 ioat_drain_locked(struct ioat_softc *ioat) 2093 { 2094 2095 mtx_assert(IOAT_REFLK, MA_OWNED); 2096 while (ioat->refcnt > 0) 2097 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 2098 } 2099 2100 #ifdef DDB 2101 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 2102 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 2103 DB_SHOW_COMMAND(ioat, db_show_ioat) 2104 { 2105 struct ioat_softc *sc; 2106 unsigned idx; 2107 2108 if (!have_addr) 2109 goto usage; 2110 idx = (unsigned)addr; 2111 if (addr >= ioat_channel_index) 2112 goto usage; 2113 2114 sc = ioat_channel[idx]; 2115 db_printf("ioat softc at %p\n", sc); 2116 if (sc == NULL) 2117 return; 2118 2119 db_printf(" version: %d\n", sc->version); 2120 db_printf(" chan_idx: %u\n", sc->chan_idx); 2121 db_printf(" submit_lock: "); 2122 db_show_lock(&sc->submit_lock); 2123 2124 db_printf(" capabilities: %b\n", (int)sc->capabilities, 2125 IOAT_DMACAP_STR); 2126 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 2127 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 2128 2129 db_printf(" timer:\n"); 2130 db_printf(" c_time: %ju\n", (uintmax_t)sc->timer.c_time); 2131 db_printf(" c_arg: %p\n", sc->timer.c_arg); 2132 db_printf(" c_func: %p\n", sc->timer.c_func); 2133 db_printf(" c_lock: %p\n", sc->timer.c_lock); 2134 db_printf(" c_flags: 0x%x\n", (unsigned)sc->timer.c_flags); 2135 2136 db_printf(" quiescing: %d\n", (int)sc->quiescing); 2137 db_printf(" destroying: %d\n", (int)sc->destroying); 2138 db_printf(" is_resize_pending: %d\n", (int)sc->is_resize_pending); 2139 db_printf(" is_completion_pending: %d\n", (int)sc->is_completion_pending); 2140 db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending); 2141 db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running); 2142 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 2143 2144 db_printf(" head: %u\n", sc->head); 2145 db_printf(" tail: %u\n", sc->tail); 2146 db_printf(" hw_head: %u\n", sc->hw_head); 2147 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2148 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2149 db_printf(" ring: %p\n", sc->ring); 2150 2151 db_printf(" cleanup_lock: "); 2152 db_show_lock(&sc->cleanup_lock); 2153 2154 db_printf(" refcnt: %u\n", sc->refcnt); 2155 #ifdef INVARIANTS 2156 CTASSERT(IOAT_NUM_REF_KINDS == 2); 2157 db_printf(" refkinds: [ENG=%u, DESCR=%u]\n", sc->refkinds[0], 2158 sc->refkinds[1]); 2159 #endif 2160 db_printf(" stats:\n"); 2161 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2162 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2163 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2164 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2165 2166 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2167 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2168 2169 if (db_pager_quit) 2170 return; 2171 2172 db_printf(" hw status:\n"); 2173 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2174 db_printf(" chanctrl: 0x%x\n", 2175 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2176 db_printf(" chancmd: 0x%x\n", 2177 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2178 db_printf(" dmacount: 0x%x\n", 2179 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2180 db_printf(" chainaddr: 0x%lx\n", 2181 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2182 db_printf(" chancmp: 0x%lx\n", 2183 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2184 db_printf(" chanerr: %b\n", 2185 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2186 return; 2187 usage: 2188 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2189 return; 2190 } 2191 #endif /* DDB */ 2192