1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/ioccom.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/sbuf.h> 42 #include <sys/sysctl.h> 43 #include <sys/time.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <machine/stdarg.h> 49 50 #include "ioat.h" 51 #include "ioat_hw.h" 52 #include "ioat_internal.h" 53 54 #define IOAT_INTR_TIMO (hz / 10) 55 #define IOAT_REFLK (&ioat->submit_lock) 56 57 static int ioat_probe(device_t device); 58 static int ioat_attach(device_t device); 59 static int ioat_detach(device_t device); 60 static int ioat_setup_intr(struct ioat_softc *ioat); 61 static int ioat_teardown_intr(struct ioat_softc *ioat); 62 static int ioat3_attach(device_t device); 63 static int ioat_start_channel(struct ioat_softc *ioat); 64 static int ioat_map_pci_bar(struct ioat_softc *ioat); 65 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 66 int error); 67 static void ioat_interrupt_handler(void *arg); 68 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 69 static int chanerr_to_errno(uint32_t); 70 static void ioat_process_events(struct ioat_softc *ioat); 71 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 72 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 73 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 74 struct ioat_descriptor **); 75 static void ioat_free_ring_entry(struct ioat_softc *ioat, 76 struct ioat_descriptor *desc); 77 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 78 int mflags); 79 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 80 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 81 uint32_t index); 82 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 83 uint32_t size, boolean_t need_dscr, int mflags); 84 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 85 struct ioat_descriptor **); 86 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 87 struct ioat_descriptor **); 88 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 89 static void ioat_timer_callback(void *arg); 90 static void dump_descriptor(void *hw_desc); 91 static void ioat_submit_single(struct ioat_softc *ioat); 92 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 93 int error); 94 static int ioat_reset_hw(struct ioat_softc *ioat); 95 static void ioat_setup_sysctl(device_t device); 96 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 97 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 98 enum ioat_ref_kind); 99 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 100 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 101 enum ioat_ref_kind, boolean_t); 102 static inline void ioat_putn(struct ioat_softc *, uint32_t, 103 enum ioat_ref_kind); 104 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 105 enum ioat_ref_kind); 106 static void ioat_drain_locked(struct ioat_softc *); 107 108 #define ioat_log_message(v, ...) do { \ 109 if ((v) <= g_ioat_debug_level) { \ 110 device_printf(ioat->device, __VA_ARGS__); \ 111 } \ 112 } while (0) 113 114 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 115 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 116 117 static int g_force_legacy_interrupts; 118 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 119 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 120 121 int g_ioat_debug_level = 0; 122 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 123 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 124 125 /* 126 * OS <-> Driver interface structures 127 */ 128 static device_method_t ioat_pci_methods[] = { 129 /* Device interface */ 130 DEVMETHOD(device_probe, ioat_probe), 131 DEVMETHOD(device_attach, ioat_attach), 132 DEVMETHOD(device_detach, ioat_detach), 133 { 0, 0 } 134 }; 135 136 static driver_t ioat_pci_driver = { 137 "ioat", 138 ioat_pci_methods, 139 sizeof(struct ioat_softc), 140 }; 141 142 static devclass_t ioat_devclass; 143 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 144 MODULE_VERSION(ioat, 1); 145 146 /* 147 * Private data structures 148 */ 149 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 150 static int ioat_channel_index = 0; 151 SYSCTL_INT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 152 "Number of IOAT channels attached"); 153 154 static struct _pcsid 155 { 156 u_int32_t type; 157 const char *desc; 158 } pci_ids[] = { 159 { 0x34308086, "TBG IOAT Ch0" }, 160 { 0x34318086, "TBG IOAT Ch1" }, 161 { 0x34328086, "TBG IOAT Ch2" }, 162 { 0x34338086, "TBG IOAT Ch3" }, 163 { 0x34298086, "TBG IOAT Ch4" }, 164 { 0x342a8086, "TBG IOAT Ch5" }, 165 { 0x342b8086, "TBG IOAT Ch6" }, 166 { 0x342c8086, "TBG IOAT Ch7" }, 167 168 { 0x37108086, "JSF IOAT Ch0" }, 169 { 0x37118086, "JSF IOAT Ch1" }, 170 { 0x37128086, "JSF IOAT Ch2" }, 171 { 0x37138086, "JSF IOAT Ch3" }, 172 { 0x37148086, "JSF IOAT Ch4" }, 173 { 0x37158086, "JSF IOAT Ch5" }, 174 { 0x37168086, "JSF IOAT Ch6" }, 175 { 0x37178086, "JSF IOAT Ch7" }, 176 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 177 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 178 179 { 0x3c208086, "SNB IOAT Ch0" }, 180 { 0x3c218086, "SNB IOAT Ch1" }, 181 { 0x3c228086, "SNB IOAT Ch2" }, 182 { 0x3c238086, "SNB IOAT Ch3" }, 183 { 0x3c248086, "SNB IOAT Ch4" }, 184 { 0x3c258086, "SNB IOAT Ch5" }, 185 { 0x3c268086, "SNB IOAT Ch6" }, 186 { 0x3c278086, "SNB IOAT Ch7" }, 187 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 188 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 189 190 { 0x0e208086, "IVB IOAT Ch0" }, 191 { 0x0e218086, "IVB IOAT Ch1" }, 192 { 0x0e228086, "IVB IOAT Ch2" }, 193 { 0x0e238086, "IVB IOAT Ch3" }, 194 { 0x0e248086, "IVB IOAT Ch4" }, 195 { 0x0e258086, "IVB IOAT Ch5" }, 196 { 0x0e268086, "IVB IOAT Ch6" }, 197 { 0x0e278086, "IVB IOAT Ch7" }, 198 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 199 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 200 201 { 0x2f208086, "HSW IOAT Ch0" }, 202 { 0x2f218086, "HSW IOAT Ch1" }, 203 { 0x2f228086, "HSW IOAT Ch2" }, 204 { 0x2f238086, "HSW IOAT Ch3" }, 205 { 0x2f248086, "HSW IOAT Ch4" }, 206 { 0x2f258086, "HSW IOAT Ch5" }, 207 { 0x2f268086, "HSW IOAT Ch6" }, 208 { 0x2f278086, "HSW IOAT Ch7" }, 209 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 210 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 211 212 { 0x0c508086, "BWD IOAT Ch0" }, 213 { 0x0c518086, "BWD IOAT Ch1" }, 214 { 0x0c528086, "BWD IOAT Ch2" }, 215 { 0x0c538086, "BWD IOAT Ch3" }, 216 217 { 0x6f508086, "BDXDE IOAT Ch0" }, 218 { 0x6f518086, "BDXDE IOAT Ch1" }, 219 { 0x6f528086, "BDXDE IOAT Ch2" }, 220 { 0x6f538086, "BDXDE IOAT Ch3" }, 221 222 { 0x6f208086, "BDX IOAT Ch0" }, 223 { 0x6f218086, "BDX IOAT Ch1" }, 224 { 0x6f228086, "BDX IOAT Ch2" }, 225 { 0x6f238086, "BDX IOAT Ch3" }, 226 { 0x6f248086, "BDX IOAT Ch4" }, 227 { 0x6f258086, "BDX IOAT Ch5" }, 228 { 0x6f268086, "BDX IOAT Ch6" }, 229 { 0x6f278086, "BDX IOAT Ch7" }, 230 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 231 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 232 233 { 0x00000000, NULL } 234 }; 235 236 /* 237 * OS <-> Driver linkage functions 238 */ 239 static int 240 ioat_probe(device_t device) 241 { 242 struct _pcsid *ep; 243 u_int32_t type; 244 245 type = pci_get_devid(device); 246 for (ep = pci_ids; ep->type; ep++) { 247 if (ep->type == type) { 248 device_set_desc(device, ep->desc); 249 return (0); 250 } 251 } 252 return (ENXIO); 253 } 254 255 static int 256 ioat_attach(device_t device) 257 { 258 struct ioat_softc *ioat; 259 int error; 260 261 ioat = DEVICE2SOFTC(device); 262 ioat->device = device; 263 264 error = ioat_map_pci_bar(ioat); 265 if (error != 0) 266 goto err; 267 268 ioat->version = ioat_read_cbver(ioat); 269 if (ioat->version < IOAT_VER_3_0) { 270 error = ENODEV; 271 goto err; 272 } 273 274 error = ioat3_attach(device); 275 if (error != 0) 276 goto err; 277 278 error = pci_enable_busmaster(device); 279 if (error != 0) 280 goto err; 281 282 error = ioat_setup_intr(ioat); 283 if (error != 0) 284 goto err; 285 286 error = ioat_reset_hw(ioat); 287 if (error != 0) 288 goto err; 289 290 ioat_process_events(ioat); 291 ioat_setup_sysctl(device); 292 293 ioat->chan_idx = ioat_channel_index; 294 ioat_channel[ioat_channel_index++] = ioat; 295 ioat_test_attach(); 296 297 err: 298 if (error != 0) 299 ioat_detach(device); 300 return (error); 301 } 302 303 static int 304 ioat_detach(device_t device) 305 { 306 struct ioat_softc *ioat; 307 308 ioat = DEVICE2SOFTC(device); 309 310 ioat_test_detach(); 311 312 mtx_lock(IOAT_REFLK); 313 ioat->quiescing = TRUE; 314 ioat_channel[ioat->chan_idx] = NULL; 315 316 ioat_drain_locked(ioat); 317 mtx_unlock(IOAT_REFLK); 318 319 ioat_teardown_intr(ioat); 320 callout_drain(&ioat->timer); 321 322 pci_disable_busmaster(device); 323 324 if (ioat->pci_resource != NULL) 325 bus_release_resource(device, SYS_RES_MEMORY, 326 ioat->pci_resource_id, ioat->pci_resource); 327 328 if (ioat->ring != NULL) 329 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 330 331 if (ioat->comp_update != NULL) { 332 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 333 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 334 ioat->comp_update_map); 335 bus_dma_tag_destroy(ioat->comp_update_tag); 336 } 337 338 bus_dma_tag_destroy(ioat->hw_desc_tag); 339 340 return (0); 341 } 342 343 static int 344 ioat_teardown_intr(struct ioat_softc *ioat) 345 { 346 347 if (ioat->tag != NULL) 348 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 349 350 if (ioat->res != NULL) 351 bus_release_resource(ioat->device, SYS_RES_IRQ, 352 rman_get_rid(ioat->res), ioat->res); 353 354 pci_release_msi(ioat->device); 355 return (0); 356 } 357 358 static int 359 ioat_start_channel(struct ioat_softc *ioat) 360 { 361 uint64_t status; 362 uint32_t chanerr; 363 int i; 364 365 ioat_acquire(&ioat->dmaengine); 366 ioat_null(&ioat->dmaengine, NULL, NULL, 0); 367 ioat_release(&ioat->dmaengine); 368 369 for (i = 0; i < 100; i++) { 370 DELAY(1); 371 status = ioat_get_chansts(ioat); 372 if (is_ioat_idle(status)) 373 return (0); 374 } 375 376 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 377 ioat_log_message(0, "could not start channel: " 378 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 379 IOAT_CHANERR_STR); 380 return (ENXIO); 381 } 382 383 /* 384 * Initialize Hardware 385 */ 386 static int 387 ioat3_attach(device_t device) 388 { 389 struct ioat_softc *ioat; 390 struct ioat_descriptor **ring; 391 struct ioat_descriptor *next; 392 struct ioat_dma_hw_descriptor *dma_hw_desc; 393 int i, num_descriptors; 394 int error; 395 uint8_t xfercap; 396 397 error = 0; 398 ioat = DEVICE2SOFTC(device); 399 ioat->capabilities = ioat_read_dmacapability(ioat); 400 401 ioat_log_message(1, "Capabilities: %b\n", (int)ioat->capabilities, 402 IOAT_DMACAP_STR); 403 404 xfercap = ioat_read_xfercap(ioat); 405 ioat->max_xfer_size = 1 << xfercap; 406 407 /* TODO: need to check DCA here if we ever do XOR/PQ */ 408 409 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 410 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 411 callout_init(&ioat->timer, 1); 412 413 /* Establish lock order for Witness */ 414 mtx_lock(&ioat->submit_lock); 415 mtx_lock(&ioat->cleanup_lock); 416 mtx_unlock(&ioat->cleanup_lock); 417 mtx_unlock(&ioat->submit_lock); 418 419 ioat->is_resize_pending = FALSE; 420 ioat->is_completion_pending = FALSE; 421 ioat->is_reset_pending = FALSE; 422 ioat->is_channel_running = FALSE; 423 424 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 425 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 426 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 427 &ioat->comp_update_tag); 428 429 error = bus_dmamem_alloc(ioat->comp_update_tag, 430 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 431 if (ioat->comp_update == NULL) 432 return (ENOMEM); 433 434 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 435 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 436 0); 437 if (error != 0) 438 return (error); 439 440 ioat->ring_size_order = IOAT_MIN_ORDER; 441 442 num_descriptors = 1 << ioat->ring_size_order; 443 444 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 445 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 446 sizeof(struct ioat_dma_hw_descriptor), 1, 447 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 448 &ioat->hw_desc_tag); 449 450 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 451 M_ZERO | M_WAITOK); 452 if (ioat->ring == NULL) 453 return (ENOMEM); 454 455 ring = ioat->ring; 456 for (i = 0; i < num_descriptors; i++) { 457 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 458 if (ring[i] == NULL) 459 return (ENOMEM); 460 461 ring[i]->id = i; 462 } 463 464 for (i = 0; i < num_descriptors - 1; i++) { 465 next = ring[i + 1]; 466 dma_hw_desc = ring[i]->u.dma; 467 468 dma_hw_desc->next = next->hw_desc_bus_addr; 469 } 470 471 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 472 473 ioat->head = ioat->hw_head = 0; 474 ioat->tail = 0; 475 ioat->last_seen = 0; 476 return (0); 477 } 478 479 static int 480 ioat_map_pci_bar(struct ioat_softc *ioat) 481 { 482 483 ioat->pci_resource_id = PCIR_BAR(0); 484 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 485 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 486 487 if (ioat->pci_resource == NULL) { 488 ioat_log_message(0, "unable to allocate pci resource\n"); 489 return (ENODEV); 490 } 491 492 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 493 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 494 return (0); 495 } 496 497 static void 498 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 499 { 500 struct ioat_softc *ioat = arg; 501 502 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 503 ioat->comp_update_bus_addr = seg[0].ds_addr; 504 } 505 506 static void 507 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 508 { 509 bus_addr_t *baddr; 510 511 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 512 baddr = arg; 513 *baddr = segs->ds_addr; 514 } 515 516 /* 517 * Interrupt setup and handlers 518 */ 519 static int 520 ioat_setup_intr(struct ioat_softc *ioat) 521 { 522 uint32_t num_vectors; 523 int error; 524 boolean_t use_msix; 525 boolean_t force_legacy_interrupts; 526 527 use_msix = FALSE; 528 force_legacy_interrupts = FALSE; 529 530 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 531 num_vectors = 1; 532 pci_alloc_msix(ioat->device, &num_vectors); 533 if (num_vectors == 1) 534 use_msix = TRUE; 535 } 536 537 if (use_msix) { 538 ioat->rid = 1; 539 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 540 &ioat->rid, RF_ACTIVE); 541 } else { 542 ioat->rid = 0; 543 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 544 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 545 } 546 if (ioat->res == NULL) { 547 ioat_log_message(0, "bus_alloc_resource failed\n"); 548 return (ENOMEM); 549 } 550 551 ioat->tag = NULL; 552 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 553 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 554 if (error != 0) { 555 ioat_log_message(0, "bus_setup_intr failed\n"); 556 return (error); 557 } 558 559 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 560 return (0); 561 } 562 563 static boolean_t 564 ioat_model_resets_msix(struct ioat_softc *ioat) 565 { 566 u_int32_t pciid; 567 568 pciid = pci_get_devid(ioat->device); 569 switch (pciid) { 570 /* BWD: */ 571 case 0x0c508086: 572 case 0x0c518086: 573 case 0x0c528086: 574 case 0x0c538086: 575 /* BDXDE: */ 576 case 0x6f508086: 577 case 0x6f518086: 578 case 0x6f528086: 579 case 0x6f538086: 580 return (TRUE); 581 } 582 583 return (FALSE); 584 } 585 586 static void 587 ioat_interrupt_handler(void *arg) 588 { 589 struct ioat_softc *ioat = arg; 590 591 ioat_process_events(ioat); 592 } 593 594 static int 595 chanerr_to_errno(uint32_t chanerr) 596 { 597 598 if (chanerr == 0) 599 return (0); 600 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 601 return (EFAULT); 602 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 603 return (EIO); 604 /* This one is probably our fault: */ 605 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 606 return (EIO); 607 return (EIO); 608 } 609 610 static void 611 ioat_process_events(struct ioat_softc *ioat) 612 { 613 struct ioat_descriptor *desc; 614 struct bus_dmadesc *dmadesc; 615 uint64_t comp_update, status; 616 uint32_t completed, chanerr; 617 int error; 618 619 mtx_lock(&ioat->cleanup_lock); 620 621 completed = 0; 622 comp_update = *ioat->comp_update; 623 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 624 625 CTR0(KTR_IOAT, __func__); 626 627 if (status == ioat->last_seen) 628 goto out; 629 630 while (1) { 631 desc = ioat_get_ring_entry(ioat, ioat->tail); 632 dmadesc = &desc->bus_dmadesc; 633 CTR1(KTR_IOAT, "completing desc %d", ioat->tail); 634 635 if (dmadesc->callback_fn != NULL) 636 dmadesc->callback_fn(dmadesc->callback_arg, 0); 637 638 completed++; 639 ioat->tail++; 640 if (desc->hw_desc_bus_addr == status) 641 break; 642 } 643 644 ioat->last_seen = desc->hw_desc_bus_addr; 645 646 if (ioat->head == ioat->tail) { 647 ioat->is_completion_pending = FALSE; 648 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 649 ioat_timer_callback, ioat); 650 } 651 652 out: 653 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 654 mtx_unlock(&ioat->cleanup_lock); 655 656 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 657 wakeup(&ioat->tail); 658 659 if (!is_ioat_halted(comp_update)) 660 return; 661 662 /* 663 * Fatal programming error on this DMA channel. Flush any outstanding 664 * work with error status and restart the engine. 665 */ 666 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 667 mtx_lock(&ioat->submit_lock); 668 mtx_lock(&ioat->cleanup_lock); 669 ioat->quiescing = TRUE; 670 671 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 672 ioat_halted_debug(ioat, chanerr); 673 674 while (ioat_get_active(ioat) > 0) { 675 desc = ioat_get_ring_entry(ioat, ioat->tail); 676 dmadesc = &desc->bus_dmadesc; 677 CTR1(KTR_IOAT, "completing err desc %d", ioat->tail); 678 679 if (dmadesc->callback_fn != NULL) 680 dmadesc->callback_fn(dmadesc->callback_arg, 681 chanerr_to_errno(chanerr)); 682 683 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 684 ioat->tail++; 685 } 686 687 /* Clear error status */ 688 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 689 690 mtx_unlock(&ioat->cleanup_lock); 691 mtx_unlock(&ioat->submit_lock); 692 693 ioat_log_message(0, "Resetting channel to recover from error\n"); 694 error = ioat_reset_hw(ioat); 695 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 696 } 697 698 /* 699 * User API functions 700 */ 701 bus_dmaengine_t 702 ioat_get_dmaengine(uint32_t index) 703 { 704 struct ioat_softc *sc; 705 706 if (index >= ioat_channel_index) 707 return (NULL); 708 709 sc = ioat_channel[index]; 710 if (sc == NULL || sc->quiescing) 711 return (NULL); 712 713 return (&ioat_get(sc, IOAT_DMAENGINE_REF)->dmaengine); 714 } 715 716 void 717 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 718 { 719 struct ioat_softc *ioat; 720 721 ioat = to_ioat_softc(dmaengine); 722 ioat_put(ioat, IOAT_DMAENGINE_REF); 723 } 724 725 void 726 ioat_acquire(bus_dmaengine_t dmaengine) 727 { 728 struct ioat_softc *ioat; 729 730 ioat = to_ioat_softc(dmaengine); 731 mtx_lock(&ioat->submit_lock); 732 CTR0(KTR_IOAT, __func__); 733 } 734 735 void 736 ioat_release(bus_dmaengine_t dmaengine) 737 { 738 struct ioat_softc *ioat; 739 740 ioat = to_ioat_softc(dmaengine); 741 CTR0(KTR_IOAT, __func__); 742 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 743 mtx_unlock(&ioat->submit_lock); 744 } 745 746 static struct ioat_descriptor * 747 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 748 uint32_t size, uint64_t src, uint64_t dst, 749 bus_dmaengine_callback_t callback_fn, void *callback_arg, 750 uint32_t flags) 751 { 752 struct ioat_generic_hw_descriptor *hw_desc; 753 struct ioat_descriptor *desc; 754 int mflags; 755 756 mtx_assert(&ioat->submit_lock, MA_OWNED); 757 758 KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x", 759 flags & ~DMA_ALL_FLAGS)); 760 if ((flags & DMA_NO_WAIT) != 0) 761 mflags = M_NOWAIT; 762 else 763 mflags = M_WAITOK; 764 765 if (size > ioat->max_xfer_size) { 766 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 767 __func__, ioat->max_xfer_size, (unsigned)size); 768 return (NULL); 769 } 770 771 if (ioat_reserve_space(ioat, 1, mflags) != 0) 772 return (NULL); 773 774 desc = ioat_get_ring_entry(ioat, ioat->head); 775 hw_desc = desc->u.generic; 776 777 hw_desc->u.control_raw = 0; 778 hw_desc->u.control_generic.op = op; 779 hw_desc->u.control_generic.completion_update = 1; 780 781 if ((flags & DMA_INT_EN) != 0) 782 hw_desc->u.control_generic.int_enable = 1; 783 784 hw_desc->size = size; 785 hw_desc->src_addr = src; 786 hw_desc->dest_addr = dst; 787 788 desc->bus_dmadesc.callback_fn = callback_fn; 789 desc->bus_dmadesc.callback_arg = callback_arg; 790 return (desc); 791 } 792 793 struct bus_dmadesc * 794 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 795 void *callback_arg, uint32_t flags) 796 { 797 struct ioat_dma_hw_descriptor *hw_desc; 798 struct ioat_descriptor *desc; 799 struct ioat_softc *ioat; 800 801 CTR0(KTR_IOAT, __func__); 802 ioat = to_ioat_softc(dmaengine); 803 804 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 805 callback_arg, flags); 806 if (desc == NULL) 807 return (NULL); 808 809 hw_desc = desc->u.dma; 810 hw_desc->u.control.null = 1; 811 ioat_submit_single(ioat); 812 return (&desc->bus_dmadesc); 813 } 814 815 struct bus_dmadesc * 816 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 817 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 818 void *callback_arg, uint32_t flags) 819 { 820 struct ioat_dma_hw_descriptor *hw_desc; 821 struct ioat_descriptor *desc; 822 struct ioat_softc *ioat; 823 824 CTR0(KTR_IOAT, __func__); 825 ioat = to_ioat_softc(dmaengine); 826 827 if (((src | dst) & (0xffffull << 48)) != 0) { 828 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 829 __func__); 830 return (NULL); 831 } 832 833 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 834 callback_arg, flags); 835 if (desc == NULL) 836 return (NULL); 837 838 hw_desc = desc->u.dma; 839 if (g_ioat_debug_level >= 3) 840 dump_descriptor(hw_desc); 841 842 ioat_submit_single(ioat); 843 return (&desc->bus_dmadesc); 844 } 845 846 struct bus_dmadesc * 847 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 848 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 849 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 850 { 851 struct ioat_dma_hw_descriptor *hw_desc; 852 struct ioat_descriptor *desc; 853 struct ioat_softc *ioat; 854 855 CTR0(KTR_IOAT, __func__); 856 ioat = to_ioat_softc(dmaengine); 857 858 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 859 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 860 __func__); 861 return (NULL); 862 } 863 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 864 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 865 __func__); 866 return (NULL); 867 } 868 869 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 870 callback_fn, callback_arg, flags); 871 if (desc == NULL) 872 return (NULL); 873 874 hw_desc = desc->u.dma; 875 if (src2 != src1 + PAGE_SIZE) { 876 hw_desc->u.control.src_page_break = 1; 877 hw_desc->next_src_addr = src2; 878 } 879 if (dst2 != dst1 + PAGE_SIZE) { 880 hw_desc->u.control.dest_page_break = 1; 881 hw_desc->next_dest_addr = dst2; 882 } 883 884 if (g_ioat_debug_level >= 3) 885 dump_descriptor(hw_desc); 886 887 ioat_submit_single(ioat); 888 return (&desc->bus_dmadesc); 889 } 890 891 struct bus_dmadesc * 892 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 893 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 894 uint32_t flags) 895 { 896 struct ioat_fill_hw_descriptor *hw_desc; 897 struct ioat_descriptor *desc; 898 struct ioat_softc *ioat; 899 900 CTR0(KTR_IOAT, __func__); 901 ioat = to_ioat_softc(dmaengine); 902 903 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 904 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 905 __func__); 906 return (NULL); 907 } 908 909 if ((dst & (0xffffull << 48)) != 0) { 910 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 911 __func__); 912 return (NULL); 913 } 914 915 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 916 callback_fn, callback_arg, flags); 917 if (desc == NULL) 918 return (NULL); 919 920 hw_desc = desc->u.fill; 921 if (g_ioat_debug_level >= 3) 922 dump_descriptor(hw_desc); 923 924 ioat_submit_single(ioat); 925 return (&desc->bus_dmadesc); 926 } 927 928 /* 929 * Ring Management 930 */ 931 static inline uint32_t 932 ioat_get_active(struct ioat_softc *ioat) 933 { 934 935 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 936 } 937 938 static inline uint32_t 939 ioat_get_ring_space(struct ioat_softc *ioat) 940 { 941 942 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 943 } 944 945 static struct ioat_descriptor * 946 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 947 { 948 struct ioat_generic_hw_descriptor *hw_desc; 949 struct ioat_descriptor *desc; 950 int error, busdmaflag; 951 952 error = ENOMEM; 953 hw_desc = NULL; 954 955 if ((mflags & M_WAITOK) != 0) 956 busdmaflag = BUS_DMA_WAITOK; 957 else 958 busdmaflag = BUS_DMA_NOWAIT; 959 960 desc = malloc(sizeof(*desc), M_IOAT, mflags); 961 if (desc == NULL) 962 goto out; 963 964 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 965 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 966 if (hw_desc == NULL) 967 goto out; 968 969 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 970 desc->u.generic = hw_desc; 971 972 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 973 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 974 busdmaflag); 975 if (error) 976 goto out; 977 978 out: 979 if (error) { 980 ioat_free_ring_entry(ioat, desc); 981 return (NULL); 982 } 983 return (desc); 984 } 985 986 static void 987 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 988 { 989 990 if (desc == NULL) 991 return; 992 993 if (desc->u.generic) 994 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 995 ioat->hw_desc_map); 996 free(desc, M_IOAT); 997 } 998 999 /* 1000 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1001 * for 'num_descs'. 1002 * 1003 * If mflags contains M_WAITOK, blocks until enough space is available. 1004 * 1005 * Returns zero on success, or an errno on error. If num_descs is beyond the 1006 * maximum ring size, returns EINVAl; if allocation would block and mflags 1007 * contains M_NOWAIT, returns EAGAIN. 1008 * 1009 * Must be called with the submit_lock held; returns with the lock held. The 1010 * lock may be dropped to allocate the ring. 1011 * 1012 * (The submit_lock is needed to add any entries to the ring, so callers are 1013 * assured enough room is available.) 1014 */ 1015 static int 1016 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1017 { 1018 struct ioat_descriptor **new_ring; 1019 uint32_t order; 1020 int error; 1021 1022 mtx_assert(&ioat->submit_lock, MA_OWNED); 1023 error = 0; 1024 1025 if (num_descs < 1 || num_descs > (1 << IOAT_MAX_ORDER)) { 1026 error = EINVAL; 1027 goto out; 1028 } 1029 if (ioat->quiescing) { 1030 error = ENXIO; 1031 goto out; 1032 } 1033 1034 for (;;) { 1035 if (ioat_get_ring_space(ioat) >= num_descs) 1036 goto out; 1037 1038 order = ioat->ring_size_order; 1039 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1040 if ((mflags & M_WAITOK) != 0) { 1041 msleep(&ioat->tail, &ioat->submit_lock, 0, 1042 "ioat_rsz", 0); 1043 continue; 1044 } 1045 1046 error = EAGAIN; 1047 break; 1048 } 1049 1050 ioat->is_resize_pending = TRUE; 1051 for (;;) { 1052 mtx_unlock(&ioat->submit_lock); 1053 1054 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1055 TRUE, mflags); 1056 1057 mtx_lock(&ioat->submit_lock); 1058 KASSERT(ioat->ring_size_order == order, 1059 ("is_resize_pending should protect order")); 1060 1061 if (new_ring == NULL) { 1062 KASSERT((mflags & M_WAITOK) == 0, 1063 ("allocation failed")); 1064 error = EAGAIN; 1065 break; 1066 } 1067 1068 error = ring_grow(ioat, order, new_ring); 1069 if (error == 0) 1070 break; 1071 } 1072 ioat->is_resize_pending = FALSE; 1073 wakeup(&ioat->tail); 1074 if (error) 1075 break; 1076 } 1077 1078 out: 1079 mtx_assert(&ioat->submit_lock, MA_OWNED); 1080 return (error); 1081 } 1082 1083 static struct ioat_descriptor ** 1084 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1085 int mflags) 1086 { 1087 struct ioat_descriptor **ring; 1088 uint32_t i; 1089 int error; 1090 1091 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1092 1093 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1094 if (ring == NULL) 1095 return (NULL); 1096 1097 if (need_dscr) { 1098 error = ENOMEM; 1099 for (i = size / 2; i < size; i++) { 1100 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1101 if (ring[i] == NULL) 1102 goto out; 1103 ring[i]->id = i; 1104 } 1105 } 1106 error = 0; 1107 1108 out: 1109 if (error != 0 && ring != NULL) { 1110 ioat_free_ring(ioat, size, ring); 1111 ring = NULL; 1112 } 1113 return (ring); 1114 } 1115 1116 static void 1117 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1118 struct ioat_descriptor **ring) 1119 { 1120 uint32_t i; 1121 1122 for (i = 0; i < size; i++) { 1123 if (ring[i] != NULL) 1124 ioat_free_ring_entry(ioat, ring[i]); 1125 } 1126 free(ring, M_IOAT); 1127 } 1128 1129 static struct ioat_descriptor * 1130 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1131 { 1132 1133 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1134 } 1135 1136 static int 1137 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1138 struct ioat_descriptor **newring) 1139 { 1140 struct ioat_descriptor *tmp, *next; 1141 struct ioat_dma_hw_descriptor *hw; 1142 uint32_t oldsize, newsize, head, tail, i, end; 1143 int error; 1144 1145 CTR0(KTR_IOAT, __func__); 1146 1147 mtx_assert(&ioat->submit_lock, MA_OWNED); 1148 1149 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1150 error = EINVAL; 1151 goto out; 1152 } 1153 1154 oldsize = (1 << oldorder); 1155 newsize = (1 << (oldorder + 1)); 1156 1157 mtx_lock(&ioat->cleanup_lock); 1158 1159 head = ioat->head & (oldsize - 1); 1160 tail = ioat->tail & (oldsize - 1); 1161 1162 /* Copy old descriptors to new ring */ 1163 for (i = 0; i < oldsize; i++) 1164 newring[i] = ioat->ring[i]; 1165 1166 /* 1167 * If head has wrapped but tail hasn't, we must swap some descriptors 1168 * around so that tail can increment directly to head. 1169 */ 1170 if (head < tail) { 1171 for (i = 0; i <= head; i++) { 1172 tmp = newring[oldsize + i]; 1173 1174 newring[oldsize + i] = newring[i]; 1175 newring[oldsize + i]->id = oldsize + i; 1176 1177 newring[i] = tmp; 1178 newring[i]->id = i; 1179 } 1180 head += oldsize; 1181 } 1182 1183 KASSERT(head >= tail, ("invariants")); 1184 1185 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1186 if (head < oldsize) { 1187 i = oldsize - 1; 1188 end = newsize; 1189 } else { 1190 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1191 i = head; 1192 end = newsize + (head - oldsize) + 1; 1193 } 1194 1195 /* 1196 * Fix up hardware ring, being careful not to trample the active 1197 * section (tail -> head). 1198 */ 1199 for (; i < end; i++) { 1200 KASSERT((i & (newsize - 1)) < tail || 1201 (i & (newsize - 1)) >= head, ("trampling snake")); 1202 1203 next = newring[(i + 1) & (newsize - 1)]; 1204 hw = newring[i & (newsize - 1)]->u.dma; 1205 hw->next = next->hw_desc_bus_addr; 1206 } 1207 1208 free(ioat->ring, M_IOAT); 1209 ioat->ring = newring; 1210 ioat->ring_size_order = oldorder + 1; 1211 ioat->tail = tail; 1212 ioat->head = head; 1213 error = 0; 1214 1215 mtx_unlock(&ioat->cleanup_lock); 1216 out: 1217 if (error) 1218 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1219 return (error); 1220 } 1221 1222 static int 1223 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1224 struct ioat_descriptor **newring) 1225 { 1226 struct ioat_dma_hw_descriptor *hw; 1227 struct ioat_descriptor *ent, *next; 1228 uint32_t oldsize, newsize, current_idx, new_idx, i; 1229 int error; 1230 1231 CTR0(KTR_IOAT, __func__); 1232 1233 mtx_assert(&ioat->submit_lock, MA_OWNED); 1234 1235 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1236 error = EINVAL; 1237 goto out_unlocked; 1238 } 1239 1240 oldsize = (1 << oldorder); 1241 newsize = (1 << (oldorder - 1)); 1242 1243 mtx_lock(&ioat->cleanup_lock); 1244 1245 /* Can't shrink below current active set! */ 1246 if (ioat_get_active(ioat) >= newsize) { 1247 error = ENOMEM; 1248 goto out; 1249 } 1250 1251 /* 1252 * Copy current descriptors to the new ring, dropping the removed 1253 * descriptors. 1254 */ 1255 for (i = 0; i < newsize; i++) { 1256 current_idx = (ioat->tail + i) & (oldsize - 1); 1257 new_idx = (ioat->tail + i) & (newsize - 1); 1258 1259 newring[new_idx] = ioat->ring[current_idx]; 1260 newring[new_idx]->id = new_idx; 1261 } 1262 1263 /* Free deleted descriptors */ 1264 for (i = newsize; i < oldsize; i++) { 1265 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1266 ioat_free_ring_entry(ioat, ent); 1267 } 1268 1269 /* Fix up hardware ring. */ 1270 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1271 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1272 hw->next = next->hw_desc_bus_addr; 1273 1274 free(ioat->ring, M_IOAT); 1275 ioat->ring = newring; 1276 ioat->ring_size_order = oldorder - 1; 1277 error = 0; 1278 1279 out: 1280 mtx_unlock(&ioat->cleanup_lock); 1281 out_unlocked: 1282 if (error) 1283 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1284 return (error); 1285 } 1286 1287 static void 1288 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1289 { 1290 struct ioat_descriptor *desc; 1291 1292 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1293 IOAT_CHANERR_STR); 1294 if (chanerr == 0) 1295 return; 1296 1297 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1298 1299 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1300 dump_descriptor(desc->u.raw); 1301 1302 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1303 dump_descriptor(desc->u.raw); 1304 } 1305 1306 static void 1307 ioat_timer_callback(void *arg) 1308 { 1309 struct ioat_descriptor **newring; 1310 struct ioat_softc *ioat; 1311 uint32_t order; 1312 1313 ioat = arg; 1314 ioat_log_message(1, "%s\n", __func__); 1315 1316 if (ioat->is_completion_pending) { 1317 ioat_process_events(ioat); 1318 return; 1319 } 1320 1321 /* Slowly scale the ring down if idle. */ 1322 mtx_lock(&ioat->submit_lock); 1323 order = ioat->ring_size_order; 1324 if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) { 1325 mtx_unlock(&ioat->submit_lock); 1326 goto out; 1327 } 1328 ioat->is_resize_pending = TRUE; 1329 mtx_unlock(&ioat->submit_lock); 1330 1331 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1332 M_NOWAIT); 1333 1334 mtx_lock(&ioat->submit_lock); 1335 KASSERT(ioat->ring_size_order == order, 1336 ("resize_pending protects order")); 1337 1338 if (newring != NULL) 1339 ring_shrink(ioat, order, newring); 1340 1341 ioat->is_resize_pending = FALSE; 1342 mtx_unlock(&ioat->submit_lock); 1343 1344 out: 1345 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1346 callout_reset(&ioat->timer, 10 * hz, 1347 ioat_timer_callback, ioat); 1348 } 1349 1350 /* 1351 * Support Functions 1352 */ 1353 static void 1354 ioat_submit_single(struct ioat_softc *ioat) 1355 { 1356 1357 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1358 atomic_add_rel_int(&ioat->head, 1); 1359 atomic_add_rel_int(&ioat->hw_head, 1); 1360 1361 if (!ioat->is_completion_pending) { 1362 ioat->is_completion_pending = TRUE; 1363 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 1364 ioat_timer_callback, ioat); 1365 } 1366 } 1367 1368 static int 1369 ioat_reset_hw(struct ioat_softc *ioat) 1370 { 1371 uint64_t status; 1372 uint32_t chanerr; 1373 unsigned timeout; 1374 int error; 1375 1376 mtx_lock(IOAT_REFLK); 1377 ioat->quiescing = TRUE; 1378 ioat_drain_locked(ioat); 1379 mtx_unlock(IOAT_REFLK); 1380 1381 status = ioat_get_chansts(ioat); 1382 if (is_ioat_active(status) || is_ioat_idle(status)) 1383 ioat_suspend(ioat); 1384 1385 /* Wait at most 20 ms */ 1386 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1387 timeout < 20; timeout++) { 1388 DELAY(1000); 1389 status = ioat_get_chansts(ioat); 1390 } 1391 if (timeout == 20) { 1392 error = ETIMEDOUT; 1393 goto out; 1394 } 1395 1396 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1397 1398 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1399 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1400 1401 /* 1402 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1403 * that can cause stability issues for IOAT v3. 1404 */ 1405 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1406 4); 1407 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1408 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1409 1410 /* 1411 * BDXDE and BWD models reset MSI-X registers on device reset. 1412 * Save/restore their contents manually. 1413 */ 1414 if (ioat_model_resets_msix(ioat)) { 1415 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1416 pci_save_state(ioat->device); 1417 } 1418 1419 ioat_reset(ioat); 1420 1421 /* Wait at most 20 ms */ 1422 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1423 DELAY(1000); 1424 if (timeout == 20) { 1425 error = ETIMEDOUT; 1426 goto out; 1427 } 1428 1429 if (ioat_model_resets_msix(ioat)) { 1430 ioat_log_message(1, "device resets registers; restored\n"); 1431 pci_restore_state(ioat->device); 1432 } 1433 1434 /* Reset attempts to return the hardware to "halted." */ 1435 status = ioat_get_chansts(ioat); 1436 if (is_ioat_active(status) || is_ioat_idle(status)) { 1437 /* So this really shouldn't happen... */ 1438 ioat_log_message(0, "Device is active after a reset?\n"); 1439 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1440 error = 0; 1441 goto out; 1442 } 1443 1444 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1445 if (chanerr != 0) { 1446 mtx_lock(&ioat->cleanup_lock); 1447 ioat_halted_debug(ioat, chanerr); 1448 mtx_unlock(&ioat->cleanup_lock); 1449 error = EIO; 1450 goto out; 1451 } 1452 1453 /* 1454 * Bring device back online after reset. Writing CHAINADDR brings the 1455 * device back to active. 1456 * 1457 * The internal ring counter resets to zero, so we have to start over 1458 * at zero as well. 1459 */ 1460 ioat->tail = ioat->head = ioat->hw_head = 0; 1461 ioat->last_seen = 0; 1462 1463 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1464 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1465 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1466 error = 0; 1467 1468 out: 1469 mtx_lock(IOAT_REFLK); 1470 ioat->quiescing = FALSE; 1471 mtx_unlock(IOAT_REFLK); 1472 1473 if (error == 0) 1474 error = ioat_start_channel(ioat); 1475 1476 return (error); 1477 } 1478 1479 static int 1480 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1481 { 1482 struct ioat_softc *ioat; 1483 struct sbuf sb; 1484 uint64_t status; 1485 int error; 1486 1487 ioat = arg1; 1488 1489 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1490 1491 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1492 switch (status) { 1493 case IOAT_CHANSTS_ACTIVE: 1494 sbuf_printf(&sb, "ACTIVE"); 1495 break; 1496 case IOAT_CHANSTS_IDLE: 1497 sbuf_printf(&sb, "IDLE"); 1498 break; 1499 case IOAT_CHANSTS_SUSPENDED: 1500 sbuf_printf(&sb, "SUSPENDED"); 1501 break; 1502 case IOAT_CHANSTS_HALTED: 1503 sbuf_printf(&sb, "HALTED"); 1504 break; 1505 case IOAT_CHANSTS_ARMED: 1506 sbuf_printf(&sb, "ARMED"); 1507 break; 1508 default: 1509 sbuf_printf(&sb, "UNKNOWN"); 1510 break; 1511 } 1512 error = sbuf_finish(&sb); 1513 sbuf_delete(&sb); 1514 1515 if (error != 0 || req->newptr == NULL) 1516 return (error); 1517 return (EINVAL); 1518 } 1519 1520 static int 1521 sysctl_handle_error(SYSCTL_HANDLER_ARGS) 1522 { 1523 struct ioat_descriptor *desc; 1524 struct ioat_softc *ioat; 1525 int error, arg; 1526 1527 ioat = arg1; 1528 1529 arg = 0; 1530 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1531 if (error != 0 || req->newptr == NULL) 1532 return (error); 1533 1534 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1535 if (error != 0) 1536 return (error); 1537 1538 if (arg != 0) { 1539 ioat_acquire(&ioat->dmaengine); 1540 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 1, 1541 0xffff000000000000ull, 0xffff000000000000ull, NULL, NULL, 1542 0); 1543 if (desc == NULL) 1544 error = ENOMEM; 1545 else 1546 ioat_submit_single(ioat); 1547 ioat_release(&ioat->dmaengine); 1548 } 1549 return (error); 1550 } 1551 1552 static int 1553 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1554 { 1555 struct ioat_softc *ioat; 1556 int error, arg; 1557 1558 ioat = arg1; 1559 1560 arg = 0; 1561 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1562 if (error != 0 || req->newptr == NULL) 1563 return (error); 1564 1565 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1566 if (error != 0) 1567 return (error); 1568 1569 if (arg != 0) 1570 error = ioat_reset_hw(ioat); 1571 1572 return (error); 1573 } 1574 1575 static void 1576 dump_descriptor(void *hw_desc) 1577 { 1578 int i, j; 1579 1580 for (i = 0; i < 2; i++) { 1581 for (j = 0; j < 8; j++) 1582 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1583 printf("\n"); 1584 } 1585 } 1586 1587 static void 1588 ioat_setup_sysctl(device_t device) 1589 { 1590 struct sysctl_oid_list *par; 1591 struct sysctl_ctx_list *ctx; 1592 struct sysctl_oid *tree; 1593 struct ioat_softc *ioat; 1594 1595 ioat = DEVICE2SOFTC(device); 1596 ctx = device_get_sysctl_ctx(device); 1597 tree = device_get_sysctl_tree(device); 1598 par = SYSCTL_CHILDREN(tree); 1599 1600 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1601 &ioat->version, 0, "HW version (0xMM form)"); 1602 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1603 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1604 1605 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1606 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1607 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 0, 1608 "SW descriptor head pointer index"); 1609 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 0, 1610 "SW descriptor tail pointer index"); 1611 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "hw_head", CTLFLAG_RD, 1612 &ioat->hw_head, 0, "HW DMACOUNT"); 1613 1614 SYSCTL_ADD_UQUAD(ctx, par, OID_AUTO, "last_completion", CTLFLAG_RD, 1615 ioat->comp_update, "HW addr of last completion"); 1616 1617 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 1618 &ioat->is_resize_pending, 0, "resize pending"); 1619 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_completion_pending", CTLFLAG_RD, 1620 &ioat->is_completion_pending, 0, "completion pending"); 1621 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1622 &ioat->is_reset_pending, 0, "reset pending"); 1623 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1624 &ioat->is_channel_running, 0, "channel running"); 1625 1626 SYSCTL_ADD_PROC(ctx, par, OID_AUTO, "force_hw_reset", 1627 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1628 "Set to non-zero to reset the hardware"); 1629 SYSCTL_ADD_PROC(ctx, par, OID_AUTO, "force_hw_error", 1630 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_error, "I", 1631 "Set to non-zero to inject a recoverable hardware error"); 1632 SYSCTL_ADD_PROC(ctx, par, OID_AUTO, "chansts", 1633 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1634 "String of the channel status"); 1635 } 1636 1637 static inline struct ioat_softc * 1638 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1639 { 1640 uint32_t old; 1641 1642 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1643 1644 old = atomic_fetchadd_32(&ioat->refcnt, 1); 1645 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 1646 1647 #ifdef INVARIANTS 1648 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 1649 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 1650 #endif 1651 1652 return (ioat); 1653 } 1654 1655 static inline void 1656 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1657 { 1658 1659 _ioat_putn(ioat, n, kind, FALSE); 1660 } 1661 1662 static inline void 1663 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1664 { 1665 1666 _ioat_putn(ioat, n, kind, TRUE); 1667 } 1668 1669 static inline void 1670 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 1671 boolean_t locked) 1672 { 1673 uint32_t old; 1674 1675 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1676 1677 if (n == 0) 1678 return; 1679 1680 #ifdef INVARIANTS 1681 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 1682 KASSERT(old >= n, ("refcnt kind underflow")); 1683 #endif 1684 1685 /* Skip acquiring the lock if resulting refcnt > 0. */ 1686 for (;;) { 1687 old = ioat->refcnt; 1688 if (old <= n) 1689 break; 1690 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 1691 return; 1692 } 1693 1694 if (locked) 1695 mtx_assert(IOAT_REFLK, MA_OWNED); 1696 else 1697 mtx_lock(IOAT_REFLK); 1698 1699 old = atomic_fetchadd_32(&ioat->refcnt, -n); 1700 KASSERT(old >= n, ("refcnt error")); 1701 1702 if (old == n) 1703 wakeup(IOAT_REFLK); 1704 if (!locked) 1705 mtx_unlock(IOAT_REFLK); 1706 } 1707 1708 static inline void 1709 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1710 { 1711 1712 ioat_putn(ioat, 1, kind); 1713 } 1714 1715 static void 1716 ioat_drain_locked(struct ioat_softc *ioat) 1717 { 1718 1719 mtx_assert(IOAT_REFLK, MA_OWNED); 1720 while (ioat->refcnt > 0) 1721 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 1722 } 1723