1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/ioccom.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 #include <sys/sbuf.h> 42 #include <sys/sysctl.h> 43 #include <sys/time.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <machine/stdarg.h> 49 50 #include "ioat.h" 51 #include "ioat_hw.h" 52 #include "ioat_internal.h" 53 54 #define IOAT_INTR_TIMO (hz / 10) 55 #define IOAT_REFLK (&ioat->submit_lock) 56 57 static int ioat_probe(device_t device); 58 static int ioat_attach(device_t device); 59 static int ioat_detach(device_t device); 60 static int ioat_setup_intr(struct ioat_softc *ioat); 61 static int ioat_teardown_intr(struct ioat_softc *ioat); 62 static int ioat3_attach(device_t device); 63 static int ioat_start_channel(struct ioat_softc *ioat); 64 static int ioat_map_pci_bar(struct ioat_softc *ioat); 65 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 66 int error); 67 static void ioat_interrupt_handler(void *arg); 68 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 69 static int chanerr_to_errno(uint32_t); 70 static void ioat_process_events(struct ioat_softc *ioat); 71 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 72 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 73 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 74 struct ioat_descriptor **); 75 static void ioat_free_ring_entry(struct ioat_softc *ioat, 76 struct ioat_descriptor *desc); 77 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 78 int mflags); 79 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 80 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 81 uint32_t index); 82 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 83 uint32_t size, boolean_t need_dscr, int mflags); 84 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 85 struct ioat_descriptor **); 86 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 87 struct ioat_descriptor **); 88 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 89 static void ioat_timer_callback(void *arg); 90 static void dump_descriptor(void *hw_desc); 91 static void ioat_submit_single(struct ioat_softc *ioat); 92 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 93 int error); 94 static int ioat_reset_hw(struct ioat_softc *ioat); 95 static void ioat_setup_sysctl(device_t device); 96 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 97 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 98 enum ioat_ref_kind); 99 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 100 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 101 enum ioat_ref_kind, boolean_t); 102 static inline void ioat_putn(struct ioat_softc *, uint32_t, 103 enum ioat_ref_kind); 104 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 105 enum ioat_ref_kind); 106 static void ioat_drain_locked(struct ioat_softc *); 107 108 #define ioat_log_message(v, ...) do { \ 109 if ((v) <= g_ioat_debug_level) { \ 110 device_printf(ioat->device, __VA_ARGS__); \ 111 } \ 112 } while (0) 113 114 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 115 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 116 117 static int g_force_legacy_interrupts; 118 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 119 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 120 121 int g_ioat_debug_level = 0; 122 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 123 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 124 125 /* 126 * OS <-> Driver interface structures 127 */ 128 static device_method_t ioat_pci_methods[] = { 129 /* Device interface */ 130 DEVMETHOD(device_probe, ioat_probe), 131 DEVMETHOD(device_attach, ioat_attach), 132 DEVMETHOD(device_detach, ioat_detach), 133 { 0, 0 } 134 }; 135 136 static driver_t ioat_pci_driver = { 137 "ioat", 138 ioat_pci_methods, 139 sizeof(struct ioat_softc), 140 }; 141 142 static devclass_t ioat_devclass; 143 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 144 MODULE_VERSION(ioat, 1); 145 146 /* 147 * Private data structures 148 */ 149 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 150 static int ioat_channel_index = 0; 151 SYSCTL_INT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 152 "Number of IOAT channels attached"); 153 154 static struct _pcsid 155 { 156 u_int32_t type; 157 const char *desc; 158 } pci_ids[] = { 159 { 0x34308086, "TBG IOAT Ch0" }, 160 { 0x34318086, "TBG IOAT Ch1" }, 161 { 0x34328086, "TBG IOAT Ch2" }, 162 { 0x34338086, "TBG IOAT Ch3" }, 163 { 0x34298086, "TBG IOAT Ch4" }, 164 { 0x342a8086, "TBG IOAT Ch5" }, 165 { 0x342b8086, "TBG IOAT Ch6" }, 166 { 0x342c8086, "TBG IOAT Ch7" }, 167 168 { 0x37108086, "JSF IOAT Ch0" }, 169 { 0x37118086, "JSF IOAT Ch1" }, 170 { 0x37128086, "JSF IOAT Ch2" }, 171 { 0x37138086, "JSF IOAT Ch3" }, 172 { 0x37148086, "JSF IOAT Ch4" }, 173 { 0x37158086, "JSF IOAT Ch5" }, 174 { 0x37168086, "JSF IOAT Ch6" }, 175 { 0x37178086, "JSF IOAT Ch7" }, 176 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 177 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 178 179 { 0x3c208086, "SNB IOAT Ch0" }, 180 { 0x3c218086, "SNB IOAT Ch1" }, 181 { 0x3c228086, "SNB IOAT Ch2" }, 182 { 0x3c238086, "SNB IOAT Ch3" }, 183 { 0x3c248086, "SNB IOAT Ch4" }, 184 { 0x3c258086, "SNB IOAT Ch5" }, 185 { 0x3c268086, "SNB IOAT Ch6" }, 186 { 0x3c278086, "SNB IOAT Ch7" }, 187 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 188 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 189 190 { 0x0e208086, "IVB IOAT Ch0" }, 191 { 0x0e218086, "IVB IOAT Ch1" }, 192 { 0x0e228086, "IVB IOAT Ch2" }, 193 { 0x0e238086, "IVB IOAT Ch3" }, 194 { 0x0e248086, "IVB IOAT Ch4" }, 195 { 0x0e258086, "IVB IOAT Ch5" }, 196 { 0x0e268086, "IVB IOAT Ch6" }, 197 { 0x0e278086, "IVB IOAT Ch7" }, 198 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 199 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 200 201 { 0x2f208086, "HSW IOAT Ch0" }, 202 { 0x2f218086, "HSW IOAT Ch1" }, 203 { 0x2f228086, "HSW IOAT Ch2" }, 204 { 0x2f238086, "HSW IOAT Ch3" }, 205 { 0x2f248086, "HSW IOAT Ch4" }, 206 { 0x2f258086, "HSW IOAT Ch5" }, 207 { 0x2f268086, "HSW IOAT Ch6" }, 208 { 0x2f278086, "HSW IOAT Ch7" }, 209 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 210 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 211 212 { 0x0c508086, "BWD IOAT Ch0" }, 213 { 0x0c518086, "BWD IOAT Ch1" }, 214 { 0x0c528086, "BWD IOAT Ch2" }, 215 { 0x0c538086, "BWD IOAT Ch3" }, 216 217 { 0x6f508086, "BDXDE IOAT Ch0" }, 218 { 0x6f518086, "BDXDE IOAT Ch1" }, 219 { 0x6f528086, "BDXDE IOAT Ch2" }, 220 { 0x6f538086, "BDXDE IOAT Ch3" }, 221 222 { 0x6f208086, "BDX IOAT Ch0" }, 223 { 0x6f218086, "BDX IOAT Ch1" }, 224 { 0x6f228086, "BDX IOAT Ch2" }, 225 { 0x6f238086, "BDX IOAT Ch3" }, 226 { 0x6f248086, "BDX IOAT Ch4" }, 227 { 0x6f258086, "BDX IOAT Ch5" }, 228 { 0x6f268086, "BDX IOAT Ch6" }, 229 { 0x6f278086, "BDX IOAT Ch7" }, 230 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 231 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 232 233 { 0x00000000, NULL } 234 }; 235 236 /* 237 * OS <-> Driver linkage functions 238 */ 239 static int 240 ioat_probe(device_t device) 241 { 242 struct _pcsid *ep; 243 u_int32_t type; 244 245 type = pci_get_devid(device); 246 for (ep = pci_ids; ep->type; ep++) { 247 if (ep->type == type) { 248 device_set_desc(device, ep->desc); 249 return (0); 250 } 251 } 252 return (ENXIO); 253 } 254 255 static int 256 ioat_attach(device_t device) 257 { 258 struct ioat_softc *ioat; 259 int error; 260 261 ioat = DEVICE2SOFTC(device); 262 ioat->device = device; 263 264 error = ioat_map_pci_bar(ioat); 265 if (error != 0) 266 goto err; 267 268 ioat->version = ioat_read_cbver(ioat); 269 if (ioat->version < IOAT_VER_3_0) { 270 error = ENODEV; 271 goto err; 272 } 273 274 error = ioat3_attach(device); 275 if (error != 0) 276 goto err; 277 278 error = pci_enable_busmaster(device); 279 if (error != 0) 280 goto err; 281 282 error = ioat_setup_intr(ioat); 283 if (error != 0) 284 goto err; 285 286 error = ioat_reset_hw(ioat); 287 if (error != 0) 288 goto err; 289 290 ioat_process_events(ioat); 291 ioat_setup_sysctl(device); 292 293 ioat->chan_idx = ioat_channel_index; 294 ioat_channel[ioat_channel_index++] = ioat; 295 ioat_test_attach(); 296 297 err: 298 if (error != 0) 299 ioat_detach(device); 300 return (error); 301 } 302 303 static int 304 ioat_detach(device_t device) 305 { 306 struct ioat_softc *ioat; 307 308 ioat = DEVICE2SOFTC(device); 309 310 ioat_test_detach(); 311 312 mtx_lock(IOAT_REFLK); 313 ioat->quiescing = TRUE; 314 ioat_channel[ioat->chan_idx] = NULL; 315 316 ioat_drain_locked(ioat); 317 mtx_unlock(IOAT_REFLK); 318 319 ioat_teardown_intr(ioat); 320 callout_drain(&ioat->timer); 321 322 pci_disable_busmaster(device); 323 324 if (ioat->pci_resource != NULL) 325 bus_release_resource(device, SYS_RES_MEMORY, 326 ioat->pci_resource_id, ioat->pci_resource); 327 328 if (ioat->ring != NULL) 329 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 330 331 if (ioat->comp_update != NULL) { 332 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 333 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 334 ioat->comp_update_map); 335 bus_dma_tag_destroy(ioat->comp_update_tag); 336 } 337 338 bus_dma_tag_destroy(ioat->hw_desc_tag); 339 340 return (0); 341 } 342 343 static int 344 ioat_teardown_intr(struct ioat_softc *ioat) 345 { 346 347 if (ioat->tag != NULL) 348 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 349 350 if (ioat->res != NULL) 351 bus_release_resource(ioat->device, SYS_RES_IRQ, 352 rman_get_rid(ioat->res), ioat->res); 353 354 pci_release_msi(ioat->device); 355 return (0); 356 } 357 358 static int 359 ioat_start_channel(struct ioat_softc *ioat) 360 { 361 uint64_t status; 362 uint32_t chanerr; 363 int i; 364 365 ioat_acquire(&ioat->dmaengine); 366 ioat_null(&ioat->dmaengine, NULL, NULL, 0); 367 ioat_release(&ioat->dmaengine); 368 369 for (i = 0; i < 100; i++) { 370 DELAY(1); 371 status = ioat_get_chansts(ioat); 372 if (is_ioat_idle(status)) 373 return (0); 374 } 375 376 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 377 ioat_log_message(0, "could not start channel: " 378 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 379 IOAT_CHANERR_STR); 380 return (ENXIO); 381 } 382 383 /* 384 * Initialize Hardware 385 */ 386 static int 387 ioat3_attach(device_t device) 388 { 389 struct ioat_softc *ioat; 390 struct ioat_descriptor **ring; 391 struct ioat_descriptor *next; 392 struct ioat_dma_hw_descriptor *dma_hw_desc; 393 int i, num_descriptors; 394 int error; 395 uint8_t xfercap; 396 397 error = 0; 398 ioat = DEVICE2SOFTC(device); 399 ioat->capabilities = ioat_read_dmacapability(ioat); 400 401 ioat_log_message(1, "Capabilities: %b\n", (int)ioat->capabilities, 402 IOAT_DMACAP_STR); 403 404 xfercap = ioat_read_xfercap(ioat); 405 ioat->max_xfer_size = 1 << xfercap; 406 407 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 408 IOAT_INTRDELAY_SUPPORTED) != 0; 409 if (ioat->intrdelay_supported) 410 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 411 412 /* TODO: need to check DCA here if we ever do XOR/PQ */ 413 414 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 415 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 416 callout_init(&ioat->timer, 1); 417 418 /* Establish lock order for Witness */ 419 mtx_lock(&ioat->submit_lock); 420 mtx_lock(&ioat->cleanup_lock); 421 mtx_unlock(&ioat->cleanup_lock); 422 mtx_unlock(&ioat->submit_lock); 423 424 ioat->is_resize_pending = FALSE; 425 ioat->is_completion_pending = FALSE; 426 ioat->is_reset_pending = FALSE; 427 ioat->is_channel_running = FALSE; 428 429 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 430 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 431 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 432 &ioat->comp_update_tag); 433 434 error = bus_dmamem_alloc(ioat->comp_update_tag, 435 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 436 if (ioat->comp_update == NULL) 437 return (ENOMEM); 438 439 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 440 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 441 0); 442 if (error != 0) 443 return (error); 444 445 ioat->ring_size_order = IOAT_MIN_ORDER; 446 447 num_descriptors = 1 << ioat->ring_size_order; 448 449 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 450 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 451 sizeof(struct ioat_dma_hw_descriptor), 1, 452 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 453 &ioat->hw_desc_tag); 454 455 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 456 M_ZERO | M_WAITOK); 457 if (ioat->ring == NULL) 458 return (ENOMEM); 459 460 ring = ioat->ring; 461 for (i = 0; i < num_descriptors; i++) { 462 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 463 if (ring[i] == NULL) 464 return (ENOMEM); 465 466 ring[i]->id = i; 467 } 468 469 for (i = 0; i < num_descriptors - 1; i++) { 470 next = ring[i + 1]; 471 dma_hw_desc = ring[i]->u.dma; 472 473 dma_hw_desc->next = next->hw_desc_bus_addr; 474 } 475 476 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 477 478 ioat->head = ioat->hw_head = 0; 479 ioat->tail = 0; 480 ioat->last_seen = 0; 481 return (0); 482 } 483 484 static int 485 ioat_map_pci_bar(struct ioat_softc *ioat) 486 { 487 488 ioat->pci_resource_id = PCIR_BAR(0); 489 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 490 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 491 492 if (ioat->pci_resource == NULL) { 493 ioat_log_message(0, "unable to allocate pci resource\n"); 494 return (ENODEV); 495 } 496 497 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 498 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 499 return (0); 500 } 501 502 static void 503 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 504 { 505 struct ioat_softc *ioat = arg; 506 507 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 508 ioat->comp_update_bus_addr = seg[0].ds_addr; 509 } 510 511 static void 512 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 513 { 514 bus_addr_t *baddr; 515 516 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 517 baddr = arg; 518 *baddr = segs->ds_addr; 519 } 520 521 /* 522 * Interrupt setup and handlers 523 */ 524 static int 525 ioat_setup_intr(struct ioat_softc *ioat) 526 { 527 uint32_t num_vectors; 528 int error; 529 boolean_t use_msix; 530 boolean_t force_legacy_interrupts; 531 532 use_msix = FALSE; 533 force_legacy_interrupts = FALSE; 534 535 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 536 num_vectors = 1; 537 pci_alloc_msix(ioat->device, &num_vectors); 538 if (num_vectors == 1) 539 use_msix = TRUE; 540 } 541 542 if (use_msix) { 543 ioat->rid = 1; 544 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 545 &ioat->rid, RF_ACTIVE); 546 } else { 547 ioat->rid = 0; 548 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 549 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 550 } 551 if (ioat->res == NULL) { 552 ioat_log_message(0, "bus_alloc_resource failed\n"); 553 return (ENOMEM); 554 } 555 556 ioat->tag = NULL; 557 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 558 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 559 if (error != 0) { 560 ioat_log_message(0, "bus_setup_intr failed\n"); 561 return (error); 562 } 563 564 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 565 return (0); 566 } 567 568 static boolean_t 569 ioat_model_resets_msix(struct ioat_softc *ioat) 570 { 571 u_int32_t pciid; 572 573 pciid = pci_get_devid(ioat->device); 574 switch (pciid) { 575 /* BWD: */ 576 case 0x0c508086: 577 case 0x0c518086: 578 case 0x0c528086: 579 case 0x0c538086: 580 /* BDXDE: */ 581 case 0x6f508086: 582 case 0x6f518086: 583 case 0x6f528086: 584 case 0x6f538086: 585 return (TRUE); 586 } 587 588 return (FALSE); 589 } 590 591 static void 592 ioat_interrupt_handler(void *arg) 593 { 594 struct ioat_softc *ioat = arg; 595 596 ioat->stats.interrupts++; 597 ioat_process_events(ioat); 598 } 599 600 static int 601 chanerr_to_errno(uint32_t chanerr) 602 { 603 604 if (chanerr == 0) 605 return (0); 606 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 607 return (EFAULT); 608 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 609 return (EIO); 610 /* This one is probably our fault: */ 611 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 612 return (EIO); 613 return (EIO); 614 } 615 616 static void 617 ioat_process_events(struct ioat_softc *ioat) 618 { 619 struct ioat_descriptor *desc; 620 struct bus_dmadesc *dmadesc; 621 uint64_t comp_update, status; 622 uint32_t completed, chanerr; 623 int error; 624 625 mtx_lock(&ioat->cleanup_lock); 626 627 completed = 0; 628 comp_update = *ioat->comp_update; 629 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 630 631 CTR0(KTR_IOAT, __func__); 632 633 if (status == ioat->last_seen) 634 goto out; 635 636 while (1) { 637 desc = ioat_get_ring_entry(ioat, ioat->tail); 638 dmadesc = &desc->bus_dmadesc; 639 CTR1(KTR_IOAT, "completing desc %d", ioat->tail); 640 641 if (dmadesc->callback_fn != NULL) 642 dmadesc->callback_fn(dmadesc->callback_arg, 0); 643 644 completed++; 645 ioat->tail++; 646 if (desc->hw_desc_bus_addr == status) 647 break; 648 } 649 650 ioat->last_seen = desc->hw_desc_bus_addr; 651 652 if (ioat->head == ioat->tail) { 653 ioat->is_completion_pending = FALSE; 654 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 655 ioat_timer_callback, ioat); 656 } 657 658 ioat->stats.descriptors_processed += completed; 659 660 out: 661 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 662 mtx_unlock(&ioat->cleanup_lock); 663 664 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 665 wakeup(&ioat->tail); 666 667 if (!is_ioat_halted(comp_update)) 668 return; 669 670 ioat->stats.channel_halts++; 671 672 /* 673 * Fatal programming error on this DMA channel. Flush any outstanding 674 * work with error status and restart the engine. 675 */ 676 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 677 mtx_lock(&ioat->submit_lock); 678 mtx_lock(&ioat->cleanup_lock); 679 ioat->quiescing = TRUE; 680 681 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 682 ioat_halted_debug(ioat, chanerr); 683 ioat->stats.last_halt_chanerr = chanerr; 684 685 while (ioat_get_active(ioat) > 0) { 686 desc = ioat_get_ring_entry(ioat, ioat->tail); 687 dmadesc = &desc->bus_dmadesc; 688 CTR1(KTR_IOAT, "completing err desc %d", ioat->tail); 689 690 if (dmadesc->callback_fn != NULL) 691 dmadesc->callback_fn(dmadesc->callback_arg, 692 chanerr_to_errno(chanerr)); 693 694 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 695 ioat->tail++; 696 ioat->stats.descriptors_processed++; 697 ioat->stats.descriptors_error++; 698 } 699 700 /* Clear error status */ 701 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 702 703 mtx_unlock(&ioat->cleanup_lock); 704 mtx_unlock(&ioat->submit_lock); 705 706 ioat_log_message(0, "Resetting channel to recover from error\n"); 707 error = ioat_reset_hw(ioat); 708 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 709 } 710 711 /* 712 * User API functions 713 */ 714 bus_dmaengine_t 715 ioat_get_dmaengine(uint32_t index) 716 { 717 struct ioat_softc *sc; 718 719 if (index >= ioat_channel_index) 720 return (NULL); 721 722 sc = ioat_channel[index]; 723 if (sc == NULL || sc->quiescing) 724 return (NULL); 725 726 return (&ioat_get(sc, IOAT_DMAENGINE_REF)->dmaengine); 727 } 728 729 void 730 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 731 { 732 struct ioat_softc *ioat; 733 734 ioat = to_ioat_softc(dmaengine); 735 ioat_put(ioat, IOAT_DMAENGINE_REF); 736 } 737 738 int 739 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 740 { 741 struct ioat_softc *ioat; 742 743 ioat = to_ioat_softc(dmaengine); 744 if (!ioat->intrdelay_supported) 745 return (ENODEV); 746 if (delay > ioat->intrdelay_max) 747 return (ERANGE); 748 749 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 750 ioat->cached_intrdelay = 751 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 752 return (0); 753 } 754 755 uint16_t 756 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 757 { 758 struct ioat_softc *ioat; 759 760 ioat = to_ioat_softc(dmaengine); 761 return (ioat->intrdelay_max); 762 } 763 764 void 765 ioat_acquire(bus_dmaengine_t dmaengine) 766 { 767 struct ioat_softc *ioat; 768 769 ioat = to_ioat_softc(dmaengine); 770 mtx_lock(&ioat->submit_lock); 771 CTR0(KTR_IOAT, __func__); 772 } 773 774 void 775 ioat_release(bus_dmaengine_t dmaengine) 776 { 777 struct ioat_softc *ioat; 778 779 ioat = to_ioat_softc(dmaengine); 780 CTR0(KTR_IOAT, __func__); 781 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 782 mtx_unlock(&ioat->submit_lock); 783 } 784 785 static struct ioat_descriptor * 786 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 787 uint32_t size, uint64_t src, uint64_t dst, 788 bus_dmaengine_callback_t callback_fn, void *callback_arg, 789 uint32_t flags) 790 { 791 struct ioat_generic_hw_descriptor *hw_desc; 792 struct ioat_descriptor *desc; 793 int mflags; 794 795 mtx_assert(&ioat->submit_lock, MA_OWNED); 796 797 KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x", 798 flags & ~DMA_ALL_FLAGS)); 799 if ((flags & DMA_NO_WAIT) != 0) 800 mflags = M_NOWAIT; 801 else 802 mflags = M_WAITOK; 803 804 if (size > ioat->max_xfer_size) { 805 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 806 __func__, ioat->max_xfer_size, (unsigned)size); 807 return (NULL); 808 } 809 810 if (ioat_reserve_space(ioat, 1, mflags) != 0) 811 return (NULL); 812 813 desc = ioat_get_ring_entry(ioat, ioat->head); 814 hw_desc = desc->u.generic; 815 816 hw_desc->u.control_raw = 0; 817 hw_desc->u.control_generic.op = op; 818 hw_desc->u.control_generic.completion_update = 1; 819 820 if ((flags & DMA_INT_EN) != 0) 821 hw_desc->u.control_generic.int_enable = 1; 822 823 hw_desc->size = size; 824 hw_desc->src_addr = src; 825 hw_desc->dest_addr = dst; 826 827 desc->bus_dmadesc.callback_fn = callback_fn; 828 desc->bus_dmadesc.callback_arg = callback_arg; 829 return (desc); 830 } 831 832 struct bus_dmadesc * 833 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 834 void *callback_arg, uint32_t flags) 835 { 836 struct ioat_dma_hw_descriptor *hw_desc; 837 struct ioat_descriptor *desc; 838 struct ioat_softc *ioat; 839 840 CTR0(KTR_IOAT, __func__); 841 ioat = to_ioat_softc(dmaengine); 842 843 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 844 callback_arg, flags); 845 if (desc == NULL) 846 return (NULL); 847 848 hw_desc = desc->u.dma; 849 hw_desc->u.control.null = 1; 850 ioat_submit_single(ioat); 851 return (&desc->bus_dmadesc); 852 } 853 854 struct bus_dmadesc * 855 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 856 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 857 void *callback_arg, uint32_t flags) 858 { 859 struct ioat_dma_hw_descriptor *hw_desc; 860 struct ioat_descriptor *desc; 861 struct ioat_softc *ioat; 862 863 CTR0(KTR_IOAT, __func__); 864 ioat = to_ioat_softc(dmaengine); 865 866 if (((src | dst) & (0xffffull << 48)) != 0) { 867 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 868 __func__); 869 return (NULL); 870 } 871 872 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 873 callback_arg, flags); 874 if (desc == NULL) 875 return (NULL); 876 877 hw_desc = desc->u.dma; 878 if (g_ioat_debug_level >= 3) 879 dump_descriptor(hw_desc); 880 881 ioat_submit_single(ioat); 882 return (&desc->bus_dmadesc); 883 } 884 885 struct bus_dmadesc * 886 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 887 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 888 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 889 { 890 struct ioat_dma_hw_descriptor *hw_desc; 891 struct ioat_descriptor *desc; 892 struct ioat_softc *ioat; 893 894 CTR0(KTR_IOAT, __func__); 895 ioat = to_ioat_softc(dmaengine); 896 897 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 898 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 899 __func__); 900 return (NULL); 901 } 902 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 903 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 904 __func__); 905 return (NULL); 906 } 907 908 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 909 callback_fn, callback_arg, flags); 910 if (desc == NULL) 911 return (NULL); 912 913 hw_desc = desc->u.dma; 914 if (src2 != src1 + PAGE_SIZE) { 915 hw_desc->u.control.src_page_break = 1; 916 hw_desc->next_src_addr = src2; 917 } 918 if (dst2 != dst1 + PAGE_SIZE) { 919 hw_desc->u.control.dest_page_break = 1; 920 hw_desc->next_dest_addr = dst2; 921 } 922 923 if (g_ioat_debug_level >= 3) 924 dump_descriptor(hw_desc); 925 926 ioat_submit_single(ioat); 927 return (&desc->bus_dmadesc); 928 } 929 930 struct bus_dmadesc * 931 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 932 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 933 uint32_t flags) 934 { 935 struct ioat_fill_hw_descriptor *hw_desc; 936 struct ioat_descriptor *desc; 937 struct ioat_softc *ioat; 938 939 CTR0(KTR_IOAT, __func__); 940 ioat = to_ioat_softc(dmaengine); 941 942 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 943 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 944 __func__); 945 return (NULL); 946 } 947 948 if ((dst & (0xffffull << 48)) != 0) { 949 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 950 __func__); 951 return (NULL); 952 } 953 954 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 955 callback_fn, callback_arg, flags); 956 if (desc == NULL) 957 return (NULL); 958 959 hw_desc = desc->u.fill; 960 if (g_ioat_debug_level >= 3) 961 dump_descriptor(hw_desc); 962 963 ioat_submit_single(ioat); 964 return (&desc->bus_dmadesc); 965 } 966 967 /* 968 * Ring Management 969 */ 970 static inline uint32_t 971 ioat_get_active(struct ioat_softc *ioat) 972 { 973 974 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 975 } 976 977 static inline uint32_t 978 ioat_get_ring_space(struct ioat_softc *ioat) 979 { 980 981 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 982 } 983 984 static struct ioat_descriptor * 985 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 986 { 987 struct ioat_generic_hw_descriptor *hw_desc; 988 struct ioat_descriptor *desc; 989 int error, busdmaflag; 990 991 error = ENOMEM; 992 hw_desc = NULL; 993 994 if ((mflags & M_WAITOK) != 0) 995 busdmaflag = BUS_DMA_WAITOK; 996 else 997 busdmaflag = BUS_DMA_NOWAIT; 998 999 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1000 if (desc == NULL) 1001 goto out; 1002 1003 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1004 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1005 if (hw_desc == NULL) 1006 goto out; 1007 1008 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1009 desc->u.generic = hw_desc; 1010 1011 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1012 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1013 busdmaflag); 1014 if (error) 1015 goto out; 1016 1017 out: 1018 if (error) { 1019 ioat_free_ring_entry(ioat, desc); 1020 return (NULL); 1021 } 1022 return (desc); 1023 } 1024 1025 static void 1026 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1027 { 1028 1029 if (desc == NULL) 1030 return; 1031 1032 if (desc->u.generic) 1033 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1034 ioat->hw_desc_map); 1035 free(desc, M_IOAT); 1036 } 1037 1038 /* 1039 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1040 * for 'num_descs'. 1041 * 1042 * If mflags contains M_WAITOK, blocks until enough space is available. 1043 * 1044 * Returns zero on success, or an errno on error. If num_descs is beyond the 1045 * maximum ring size, returns EINVAl; if allocation would block and mflags 1046 * contains M_NOWAIT, returns EAGAIN. 1047 * 1048 * Must be called with the submit_lock held; returns with the lock held. The 1049 * lock may be dropped to allocate the ring. 1050 * 1051 * (The submit_lock is needed to add any entries to the ring, so callers are 1052 * assured enough room is available.) 1053 */ 1054 static int 1055 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1056 { 1057 struct ioat_descriptor **new_ring; 1058 uint32_t order; 1059 int error; 1060 1061 mtx_assert(&ioat->submit_lock, MA_OWNED); 1062 error = 0; 1063 1064 if (num_descs < 1 || num_descs > (1 << IOAT_MAX_ORDER)) { 1065 error = EINVAL; 1066 goto out; 1067 } 1068 if (ioat->quiescing) { 1069 error = ENXIO; 1070 goto out; 1071 } 1072 1073 for (;;) { 1074 if (ioat_get_ring_space(ioat) >= num_descs) 1075 goto out; 1076 1077 order = ioat->ring_size_order; 1078 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1079 if ((mflags & M_WAITOK) != 0) { 1080 msleep(&ioat->tail, &ioat->submit_lock, 0, 1081 "ioat_rsz", 0); 1082 continue; 1083 } 1084 1085 error = EAGAIN; 1086 break; 1087 } 1088 1089 ioat->is_resize_pending = TRUE; 1090 for (;;) { 1091 mtx_unlock(&ioat->submit_lock); 1092 1093 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1094 TRUE, mflags); 1095 1096 mtx_lock(&ioat->submit_lock); 1097 KASSERT(ioat->ring_size_order == order, 1098 ("is_resize_pending should protect order")); 1099 1100 if (new_ring == NULL) { 1101 KASSERT((mflags & M_WAITOK) == 0, 1102 ("allocation failed")); 1103 error = EAGAIN; 1104 break; 1105 } 1106 1107 error = ring_grow(ioat, order, new_ring); 1108 if (error == 0) 1109 break; 1110 } 1111 ioat->is_resize_pending = FALSE; 1112 wakeup(&ioat->tail); 1113 if (error) 1114 break; 1115 } 1116 1117 out: 1118 mtx_assert(&ioat->submit_lock, MA_OWNED); 1119 return (error); 1120 } 1121 1122 static struct ioat_descriptor ** 1123 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1124 int mflags) 1125 { 1126 struct ioat_descriptor **ring; 1127 uint32_t i; 1128 int error; 1129 1130 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1131 1132 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1133 if (ring == NULL) 1134 return (NULL); 1135 1136 if (need_dscr) { 1137 error = ENOMEM; 1138 for (i = size / 2; i < size; i++) { 1139 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1140 if (ring[i] == NULL) 1141 goto out; 1142 ring[i]->id = i; 1143 } 1144 } 1145 error = 0; 1146 1147 out: 1148 if (error != 0 && ring != NULL) { 1149 ioat_free_ring(ioat, size, ring); 1150 ring = NULL; 1151 } 1152 return (ring); 1153 } 1154 1155 static void 1156 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1157 struct ioat_descriptor **ring) 1158 { 1159 uint32_t i; 1160 1161 for (i = 0; i < size; i++) { 1162 if (ring[i] != NULL) 1163 ioat_free_ring_entry(ioat, ring[i]); 1164 } 1165 free(ring, M_IOAT); 1166 } 1167 1168 static struct ioat_descriptor * 1169 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1170 { 1171 1172 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1173 } 1174 1175 static int 1176 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1177 struct ioat_descriptor **newring) 1178 { 1179 struct ioat_descriptor *tmp, *next; 1180 struct ioat_dma_hw_descriptor *hw; 1181 uint32_t oldsize, newsize, head, tail, i, end; 1182 int error; 1183 1184 CTR0(KTR_IOAT, __func__); 1185 1186 mtx_assert(&ioat->submit_lock, MA_OWNED); 1187 1188 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1189 error = EINVAL; 1190 goto out; 1191 } 1192 1193 oldsize = (1 << oldorder); 1194 newsize = (1 << (oldorder + 1)); 1195 1196 mtx_lock(&ioat->cleanup_lock); 1197 1198 head = ioat->head & (oldsize - 1); 1199 tail = ioat->tail & (oldsize - 1); 1200 1201 /* Copy old descriptors to new ring */ 1202 for (i = 0; i < oldsize; i++) 1203 newring[i] = ioat->ring[i]; 1204 1205 /* 1206 * If head has wrapped but tail hasn't, we must swap some descriptors 1207 * around so that tail can increment directly to head. 1208 */ 1209 if (head < tail) { 1210 for (i = 0; i <= head; i++) { 1211 tmp = newring[oldsize + i]; 1212 1213 newring[oldsize + i] = newring[i]; 1214 newring[oldsize + i]->id = oldsize + i; 1215 1216 newring[i] = tmp; 1217 newring[i]->id = i; 1218 } 1219 head += oldsize; 1220 } 1221 1222 KASSERT(head >= tail, ("invariants")); 1223 1224 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1225 if (head < oldsize) { 1226 i = oldsize - 1; 1227 end = newsize; 1228 } else { 1229 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1230 i = head; 1231 end = newsize + (head - oldsize) + 1; 1232 } 1233 1234 /* 1235 * Fix up hardware ring, being careful not to trample the active 1236 * section (tail -> head). 1237 */ 1238 for (; i < end; i++) { 1239 KASSERT((i & (newsize - 1)) < tail || 1240 (i & (newsize - 1)) >= head, ("trampling snake")); 1241 1242 next = newring[(i + 1) & (newsize - 1)]; 1243 hw = newring[i & (newsize - 1)]->u.dma; 1244 hw->next = next->hw_desc_bus_addr; 1245 } 1246 1247 free(ioat->ring, M_IOAT); 1248 ioat->ring = newring; 1249 ioat->ring_size_order = oldorder + 1; 1250 ioat->tail = tail; 1251 ioat->head = head; 1252 error = 0; 1253 1254 mtx_unlock(&ioat->cleanup_lock); 1255 out: 1256 if (error) 1257 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1258 return (error); 1259 } 1260 1261 static int 1262 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1263 struct ioat_descriptor **newring) 1264 { 1265 struct ioat_dma_hw_descriptor *hw; 1266 struct ioat_descriptor *ent, *next; 1267 uint32_t oldsize, newsize, current_idx, new_idx, i; 1268 int error; 1269 1270 CTR0(KTR_IOAT, __func__); 1271 1272 mtx_assert(&ioat->submit_lock, MA_OWNED); 1273 1274 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1275 error = EINVAL; 1276 goto out_unlocked; 1277 } 1278 1279 oldsize = (1 << oldorder); 1280 newsize = (1 << (oldorder - 1)); 1281 1282 mtx_lock(&ioat->cleanup_lock); 1283 1284 /* Can't shrink below current active set! */ 1285 if (ioat_get_active(ioat) >= newsize) { 1286 error = ENOMEM; 1287 goto out; 1288 } 1289 1290 /* 1291 * Copy current descriptors to the new ring, dropping the removed 1292 * descriptors. 1293 */ 1294 for (i = 0; i < newsize; i++) { 1295 current_idx = (ioat->tail + i) & (oldsize - 1); 1296 new_idx = (ioat->tail + i) & (newsize - 1); 1297 1298 newring[new_idx] = ioat->ring[current_idx]; 1299 newring[new_idx]->id = new_idx; 1300 } 1301 1302 /* Free deleted descriptors */ 1303 for (i = newsize; i < oldsize; i++) { 1304 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1305 ioat_free_ring_entry(ioat, ent); 1306 } 1307 1308 /* Fix up hardware ring. */ 1309 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1310 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1311 hw->next = next->hw_desc_bus_addr; 1312 1313 free(ioat->ring, M_IOAT); 1314 ioat->ring = newring; 1315 ioat->ring_size_order = oldorder - 1; 1316 error = 0; 1317 1318 out: 1319 mtx_unlock(&ioat->cleanup_lock); 1320 out_unlocked: 1321 if (error) 1322 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1323 return (error); 1324 } 1325 1326 static void 1327 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1328 { 1329 struct ioat_descriptor *desc; 1330 1331 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1332 IOAT_CHANERR_STR); 1333 if (chanerr == 0) 1334 return; 1335 1336 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1337 1338 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1339 dump_descriptor(desc->u.raw); 1340 1341 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1342 dump_descriptor(desc->u.raw); 1343 } 1344 1345 static void 1346 ioat_timer_callback(void *arg) 1347 { 1348 struct ioat_descriptor **newring; 1349 struct ioat_softc *ioat; 1350 uint32_t order; 1351 1352 ioat = arg; 1353 ioat_log_message(1, "%s\n", __func__); 1354 1355 if (ioat->is_completion_pending) { 1356 ioat_process_events(ioat); 1357 return; 1358 } 1359 1360 /* Slowly scale the ring down if idle. */ 1361 mtx_lock(&ioat->submit_lock); 1362 order = ioat->ring_size_order; 1363 if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) { 1364 mtx_unlock(&ioat->submit_lock); 1365 goto out; 1366 } 1367 ioat->is_resize_pending = TRUE; 1368 mtx_unlock(&ioat->submit_lock); 1369 1370 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1371 M_NOWAIT); 1372 1373 mtx_lock(&ioat->submit_lock); 1374 KASSERT(ioat->ring_size_order == order, 1375 ("resize_pending protects order")); 1376 1377 if (newring != NULL) 1378 ring_shrink(ioat, order, newring); 1379 1380 ioat->is_resize_pending = FALSE; 1381 mtx_unlock(&ioat->submit_lock); 1382 1383 out: 1384 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1385 callout_reset(&ioat->timer, 10 * hz, 1386 ioat_timer_callback, ioat); 1387 } 1388 1389 /* 1390 * Support Functions 1391 */ 1392 static void 1393 ioat_submit_single(struct ioat_softc *ioat) 1394 { 1395 1396 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1397 atomic_add_rel_int(&ioat->head, 1); 1398 atomic_add_rel_int(&ioat->hw_head, 1); 1399 1400 if (!ioat->is_completion_pending) { 1401 ioat->is_completion_pending = TRUE; 1402 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 1403 ioat_timer_callback, ioat); 1404 } 1405 1406 ioat->stats.descriptors_submitted++; 1407 } 1408 1409 static int 1410 ioat_reset_hw(struct ioat_softc *ioat) 1411 { 1412 uint64_t status; 1413 uint32_t chanerr; 1414 unsigned timeout; 1415 int error; 1416 1417 mtx_lock(IOAT_REFLK); 1418 ioat->quiescing = TRUE; 1419 ioat_drain_locked(ioat); 1420 mtx_unlock(IOAT_REFLK); 1421 1422 status = ioat_get_chansts(ioat); 1423 if (is_ioat_active(status) || is_ioat_idle(status)) 1424 ioat_suspend(ioat); 1425 1426 /* Wait at most 20 ms */ 1427 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1428 timeout < 20; timeout++) { 1429 DELAY(1000); 1430 status = ioat_get_chansts(ioat); 1431 } 1432 if (timeout == 20) { 1433 error = ETIMEDOUT; 1434 goto out; 1435 } 1436 1437 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1438 1439 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1440 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1441 1442 /* 1443 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1444 * that can cause stability issues for IOAT v3. 1445 */ 1446 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1447 4); 1448 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1449 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1450 1451 /* 1452 * BDXDE and BWD models reset MSI-X registers on device reset. 1453 * Save/restore their contents manually. 1454 */ 1455 if (ioat_model_resets_msix(ioat)) { 1456 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1457 pci_save_state(ioat->device); 1458 } 1459 1460 ioat_reset(ioat); 1461 1462 /* Wait at most 20 ms */ 1463 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1464 DELAY(1000); 1465 if (timeout == 20) { 1466 error = ETIMEDOUT; 1467 goto out; 1468 } 1469 1470 if (ioat_model_resets_msix(ioat)) { 1471 ioat_log_message(1, "device resets registers; restored\n"); 1472 pci_restore_state(ioat->device); 1473 } 1474 1475 /* Reset attempts to return the hardware to "halted." */ 1476 status = ioat_get_chansts(ioat); 1477 if (is_ioat_active(status) || is_ioat_idle(status)) { 1478 /* So this really shouldn't happen... */ 1479 ioat_log_message(0, "Device is active after a reset?\n"); 1480 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1481 error = 0; 1482 goto out; 1483 } 1484 1485 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1486 if (chanerr != 0) { 1487 mtx_lock(&ioat->cleanup_lock); 1488 ioat_halted_debug(ioat, chanerr); 1489 mtx_unlock(&ioat->cleanup_lock); 1490 error = EIO; 1491 goto out; 1492 } 1493 1494 /* 1495 * Bring device back online after reset. Writing CHAINADDR brings the 1496 * device back to active. 1497 * 1498 * The internal ring counter resets to zero, so we have to start over 1499 * at zero as well. 1500 */ 1501 ioat->tail = ioat->head = ioat->hw_head = 0; 1502 ioat->last_seen = 0; 1503 1504 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1505 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1506 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1507 error = 0; 1508 1509 out: 1510 mtx_lock(IOAT_REFLK); 1511 ioat->quiescing = FALSE; 1512 mtx_unlock(IOAT_REFLK); 1513 1514 if (error == 0) 1515 error = ioat_start_channel(ioat); 1516 1517 return (error); 1518 } 1519 1520 static int 1521 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1522 { 1523 struct ioat_softc *ioat; 1524 struct sbuf sb; 1525 uint64_t status; 1526 int error; 1527 1528 ioat = arg1; 1529 1530 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1531 1532 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1533 switch (status) { 1534 case IOAT_CHANSTS_ACTIVE: 1535 sbuf_printf(&sb, "ACTIVE"); 1536 break; 1537 case IOAT_CHANSTS_IDLE: 1538 sbuf_printf(&sb, "IDLE"); 1539 break; 1540 case IOAT_CHANSTS_SUSPENDED: 1541 sbuf_printf(&sb, "SUSPENDED"); 1542 break; 1543 case IOAT_CHANSTS_HALTED: 1544 sbuf_printf(&sb, "HALTED"); 1545 break; 1546 case IOAT_CHANSTS_ARMED: 1547 sbuf_printf(&sb, "ARMED"); 1548 break; 1549 default: 1550 sbuf_printf(&sb, "UNKNOWN"); 1551 break; 1552 } 1553 error = sbuf_finish(&sb); 1554 sbuf_delete(&sb); 1555 1556 if (error != 0 || req->newptr == NULL) 1557 return (error); 1558 return (EINVAL); 1559 } 1560 1561 static int 1562 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1563 { 1564 struct ioat_softc *ioat; 1565 struct sbuf sb; 1566 #define PRECISION "1" 1567 const uintmax_t factor = 10; 1568 uintmax_t rate; 1569 int error; 1570 1571 ioat = arg1; 1572 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1573 1574 if (ioat->stats.interrupts == 0) { 1575 sbuf_printf(&sb, "NaN"); 1576 goto out; 1577 } 1578 rate = ioat->stats.descriptors_processed * factor / 1579 ioat->stats.interrupts; 1580 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1581 rate % factor); 1582 #undef PRECISION 1583 out: 1584 error = sbuf_finish(&sb); 1585 sbuf_delete(&sb); 1586 if (error != 0 || req->newptr == NULL) 1587 return (error); 1588 return (EINVAL); 1589 } 1590 1591 static int 1592 sysctl_handle_error(SYSCTL_HANDLER_ARGS) 1593 { 1594 struct ioat_descriptor *desc; 1595 struct ioat_softc *ioat; 1596 int error, arg; 1597 1598 ioat = arg1; 1599 1600 arg = 0; 1601 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1602 if (error != 0 || req->newptr == NULL) 1603 return (error); 1604 1605 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1606 if (error != 0) 1607 return (error); 1608 1609 if (arg != 0) { 1610 ioat_acquire(&ioat->dmaengine); 1611 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 1, 1612 0xffff000000000000ull, 0xffff000000000000ull, NULL, NULL, 1613 0); 1614 if (desc == NULL) 1615 error = ENOMEM; 1616 else 1617 ioat_submit_single(ioat); 1618 ioat_release(&ioat->dmaengine); 1619 } 1620 return (error); 1621 } 1622 1623 static int 1624 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1625 { 1626 struct ioat_softc *ioat; 1627 int error, arg; 1628 1629 ioat = arg1; 1630 1631 arg = 0; 1632 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1633 if (error != 0 || req->newptr == NULL) 1634 return (error); 1635 1636 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1637 if (error != 0) 1638 return (error); 1639 1640 if (arg != 0) 1641 error = ioat_reset_hw(ioat); 1642 1643 return (error); 1644 } 1645 1646 static void 1647 dump_descriptor(void *hw_desc) 1648 { 1649 int i, j; 1650 1651 for (i = 0; i < 2; i++) { 1652 for (j = 0; j < 8; j++) 1653 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1654 printf("\n"); 1655 } 1656 } 1657 1658 static void 1659 ioat_setup_sysctl(device_t device) 1660 { 1661 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1662 struct sysctl_ctx_list *ctx; 1663 struct sysctl_oid *tree, *tmp; 1664 struct ioat_softc *ioat; 1665 1666 ioat = DEVICE2SOFTC(device); 1667 ctx = device_get_sysctl_ctx(device); 1668 tree = device_get_sysctl_tree(device); 1669 par = SYSCTL_CHILDREN(tree); 1670 1671 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1672 &ioat->version, 0, "HW version (0xMM form)"); 1673 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1674 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1675 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1676 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1677 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1678 &ioat->intrdelay_max, 0, 1679 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1680 1681 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 1682 "IOAT channel internal state"); 1683 state = SYSCTL_CHILDREN(tmp); 1684 1685 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1686 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1687 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1688 0, "SW descriptor head pointer index"); 1689 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1690 0, "SW descriptor tail pointer index"); 1691 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 1692 &ioat->hw_head, 0, "HW DMACOUNT"); 1693 1694 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1695 ioat->comp_update, "HW addr of last completion"); 1696 1697 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 1698 &ioat->is_resize_pending, 0, "resize pending"); 1699 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 1700 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 1701 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1702 &ioat->is_reset_pending, 0, "reset pending"); 1703 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1704 &ioat->is_channel_running, 0, "channel running"); 1705 1706 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1707 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1708 "String of the channel status"); 1709 1710 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1711 &ioat->cached_intrdelay, 0, 1712 "Current INTRDELAY on this channel (cached, microseconds)"); 1713 1714 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 1715 "Big hammers (mostly for testing)"); 1716 hammer = SYSCTL_CHILDREN(tmp); 1717 1718 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1719 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1720 "Set to non-zero to reset the hardware"); 1721 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_error", 1722 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_error, "I", 1723 "Set to non-zero to inject a recoverable hardware error"); 1724 1725 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 1726 "IOAT channel statistics"); 1727 statpar = SYSCTL_CHILDREN(tmp); 1728 1729 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 1730 &ioat->stats.interrupts, 1731 "Number of interrupts processed on this channel"); 1732 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 1733 &ioat->stats.descriptors_processed, 1734 "Number of descriptors processed on this channel"); 1735 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 1736 &ioat->stats.descriptors_submitted, 1737 "Number of descriptors submitted to this channel"); 1738 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 1739 &ioat->stats.descriptors_error, 1740 "Number of descriptors failed by channel errors"); 1741 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 1742 &ioat->stats.channel_halts, 0, 1743 "Number of times the channel has halted"); 1744 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 1745 &ioat->stats.last_halt_chanerr, 0, 1746 "The raw CHANERR when the channel was last halted"); 1747 1748 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 1749 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 1750 "Descriptors per interrupt"); 1751 } 1752 1753 static inline struct ioat_softc * 1754 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1755 { 1756 uint32_t old; 1757 1758 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1759 1760 old = atomic_fetchadd_32(&ioat->refcnt, 1); 1761 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 1762 1763 #ifdef INVARIANTS 1764 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 1765 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 1766 #endif 1767 1768 return (ioat); 1769 } 1770 1771 static inline void 1772 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1773 { 1774 1775 _ioat_putn(ioat, n, kind, FALSE); 1776 } 1777 1778 static inline void 1779 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 1780 { 1781 1782 _ioat_putn(ioat, n, kind, TRUE); 1783 } 1784 1785 static inline void 1786 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 1787 boolean_t locked) 1788 { 1789 uint32_t old; 1790 1791 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 1792 1793 if (n == 0) 1794 return; 1795 1796 #ifdef INVARIANTS 1797 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 1798 KASSERT(old >= n, ("refcnt kind underflow")); 1799 #endif 1800 1801 /* Skip acquiring the lock if resulting refcnt > 0. */ 1802 for (;;) { 1803 old = ioat->refcnt; 1804 if (old <= n) 1805 break; 1806 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 1807 return; 1808 } 1809 1810 if (locked) 1811 mtx_assert(IOAT_REFLK, MA_OWNED); 1812 else 1813 mtx_lock(IOAT_REFLK); 1814 1815 old = atomic_fetchadd_32(&ioat->refcnt, -n); 1816 KASSERT(old >= n, ("refcnt error")); 1817 1818 if (old == n) 1819 wakeup(IOAT_REFLK); 1820 if (!locked) 1821 mtx_unlock(IOAT_REFLK); 1822 } 1823 1824 static inline void 1825 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 1826 { 1827 1828 ioat_putn(ioat, 1, kind); 1829 } 1830 1831 static void 1832 ioat_drain_locked(struct ioat_softc *ioat) 1833 { 1834 1835 mtx_assert(IOAT_REFLK, MA_OWNED); 1836 while (ioat->refcnt > 0) 1837 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 1838 } 1839