1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_ddb.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/ioccom.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/sbuf.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 #include <sys/time.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #include <machine/stdarg.h> 52 53 #ifdef DDB 54 #include <ddb/ddb.h> 55 #endif 56 57 #include "ioat.h" 58 #include "ioat_hw.h" 59 #include "ioat_internal.h" 60 61 #ifndef BUS_SPACE_MAXADDR_40BIT 62 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 63 #endif 64 #define IOAT_REFLK (&ioat->submit_lock) 65 #define IOAT_SHRINK_PERIOD (10 * hz) 66 67 static int ioat_probe(device_t device); 68 static int ioat_attach(device_t device); 69 static int ioat_detach(device_t device); 70 static int ioat_setup_intr(struct ioat_softc *ioat); 71 static int ioat_teardown_intr(struct ioat_softc *ioat); 72 static int ioat3_attach(device_t device); 73 static int ioat_start_channel(struct ioat_softc *ioat); 74 static int ioat_map_pci_bar(struct ioat_softc *ioat); 75 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 76 int error); 77 static void ioat_interrupt_handler(void *arg); 78 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 79 static int chanerr_to_errno(uint32_t); 80 static void ioat_process_events(struct ioat_softc *ioat); 81 static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 82 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 83 static void ioat_free_ring(struct ioat_softc *, uint32_t size, 84 struct ioat_descriptor **); 85 static void ioat_free_ring_entry(struct ioat_softc *ioat, 86 struct ioat_descriptor *desc); 87 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 88 int mflags); 89 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 90 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 91 uint32_t index); 92 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 93 uint32_t size, boolean_t need_dscr, int mflags); 94 static int ring_grow(struct ioat_softc *, uint32_t oldorder, 95 struct ioat_descriptor **); 96 static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 97 struct ioat_descriptor **); 98 static void ioat_halted_debug(struct ioat_softc *, uint32_t); 99 static void ioat_poll_timer_callback(void *arg); 100 static void ioat_shrink_timer_callback(void *arg); 101 static void dump_descriptor(void *hw_desc); 102 static void ioat_submit_single(struct ioat_softc *ioat); 103 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 104 int error); 105 static int ioat_reset_hw(struct ioat_softc *ioat); 106 static void ioat_reset_hw_task(void *, int); 107 static void ioat_setup_sysctl(device_t device); 108 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 109 static inline struct ioat_softc *ioat_get(struct ioat_softc *, 110 enum ioat_ref_kind); 111 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 112 static inline void _ioat_putn(struct ioat_softc *, uint32_t, 113 enum ioat_ref_kind, boolean_t); 114 static inline void ioat_putn(struct ioat_softc *, uint32_t, 115 enum ioat_ref_kind); 116 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 117 enum ioat_ref_kind); 118 static void ioat_drain_locked(struct ioat_softc *); 119 120 #define ioat_log_message(v, ...) do { \ 121 if ((v) <= g_ioat_debug_level) { \ 122 device_printf(ioat->device, __VA_ARGS__); \ 123 } \ 124 } while (0) 125 126 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 127 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 128 129 static int g_force_legacy_interrupts; 130 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 131 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 132 133 int g_ioat_debug_level = 0; 134 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 135 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 136 137 /* 138 * OS <-> Driver interface structures 139 */ 140 static device_method_t ioat_pci_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, ioat_probe), 143 DEVMETHOD(device_attach, ioat_attach), 144 DEVMETHOD(device_detach, ioat_detach), 145 DEVMETHOD_END 146 }; 147 148 static driver_t ioat_pci_driver = { 149 "ioat", 150 ioat_pci_methods, 151 sizeof(struct ioat_softc), 152 }; 153 154 static devclass_t ioat_devclass; 155 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 156 MODULE_VERSION(ioat, 1); 157 158 /* 159 * Private data structures 160 */ 161 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 162 static unsigned ioat_channel_index = 0; 163 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 164 "Number of IOAT channels attached"); 165 166 static struct _pcsid 167 { 168 u_int32_t type; 169 const char *desc; 170 } pci_ids[] = { 171 { 0x34308086, "TBG IOAT Ch0" }, 172 { 0x34318086, "TBG IOAT Ch1" }, 173 { 0x34328086, "TBG IOAT Ch2" }, 174 { 0x34338086, "TBG IOAT Ch3" }, 175 { 0x34298086, "TBG IOAT Ch4" }, 176 { 0x342a8086, "TBG IOAT Ch5" }, 177 { 0x342b8086, "TBG IOAT Ch6" }, 178 { 0x342c8086, "TBG IOAT Ch7" }, 179 180 { 0x37108086, "JSF IOAT Ch0" }, 181 { 0x37118086, "JSF IOAT Ch1" }, 182 { 0x37128086, "JSF IOAT Ch2" }, 183 { 0x37138086, "JSF IOAT Ch3" }, 184 { 0x37148086, "JSF IOAT Ch4" }, 185 { 0x37158086, "JSF IOAT Ch5" }, 186 { 0x37168086, "JSF IOAT Ch6" }, 187 { 0x37178086, "JSF IOAT Ch7" }, 188 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 189 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 190 191 { 0x3c208086, "SNB IOAT Ch0" }, 192 { 0x3c218086, "SNB IOAT Ch1" }, 193 { 0x3c228086, "SNB IOAT Ch2" }, 194 { 0x3c238086, "SNB IOAT Ch3" }, 195 { 0x3c248086, "SNB IOAT Ch4" }, 196 { 0x3c258086, "SNB IOAT Ch5" }, 197 { 0x3c268086, "SNB IOAT Ch6" }, 198 { 0x3c278086, "SNB IOAT Ch7" }, 199 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 200 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 201 202 { 0x0e208086, "IVB IOAT Ch0" }, 203 { 0x0e218086, "IVB IOAT Ch1" }, 204 { 0x0e228086, "IVB IOAT Ch2" }, 205 { 0x0e238086, "IVB IOAT Ch3" }, 206 { 0x0e248086, "IVB IOAT Ch4" }, 207 { 0x0e258086, "IVB IOAT Ch5" }, 208 { 0x0e268086, "IVB IOAT Ch6" }, 209 { 0x0e278086, "IVB IOAT Ch7" }, 210 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 211 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 212 213 { 0x2f208086, "HSW IOAT Ch0" }, 214 { 0x2f218086, "HSW IOAT Ch1" }, 215 { 0x2f228086, "HSW IOAT Ch2" }, 216 { 0x2f238086, "HSW IOAT Ch3" }, 217 { 0x2f248086, "HSW IOAT Ch4" }, 218 { 0x2f258086, "HSW IOAT Ch5" }, 219 { 0x2f268086, "HSW IOAT Ch6" }, 220 { 0x2f278086, "HSW IOAT Ch7" }, 221 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 222 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 223 224 { 0x0c508086, "BWD IOAT Ch0" }, 225 { 0x0c518086, "BWD IOAT Ch1" }, 226 { 0x0c528086, "BWD IOAT Ch2" }, 227 { 0x0c538086, "BWD IOAT Ch3" }, 228 229 { 0x6f508086, "BDXDE IOAT Ch0" }, 230 { 0x6f518086, "BDXDE IOAT Ch1" }, 231 { 0x6f528086, "BDXDE IOAT Ch2" }, 232 { 0x6f538086, "BDXDE IOAT Ch3" }, 233 234 { 0x6f208086, "BDX IOAT Ch0" }, 235 { 0x6f218086, "BDX IOAT Ch1" }, 236 { 0x6f228086, "BDX IOAT Ch2" }, 237 { 0x6f238086, "BDX IOAT Ch3" }, 238 { 0x6f248086, "BDX IOAT Ch4" }, 239 { 0x6f258086, "BDX IOAT Ch5" }, 240 { 0x6f268086, "BDX IOAT Ch6" }, 241 { 0x6f278086, "BDX IOAT Ch7" }, 242 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 243 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 244 245 { 0x00000000, NULL } 246 }; 247 248 /* 249 * OS <-> Driver linkage functions 250 */ 251 static int 252 ioat_probe(device_t device) 253 { 254 struct _pcsid *ep; 255 u_int32_t type; 256 257 type = pci_get_devid(device); 258 for (ep = pci_ids; ep->type; ep++) { 259 if (ep->type == type) { 260 device_set_desc(device, ep->desc); 261 return (0); 262 } 263 } 264 return (ENXIO); 265 } 266 267 static int 268 ioat_attach(device_t device) 269 { 270 struct ioat_softc *ioat; 271 int error; 272 273 ioat = DEVICE2SOFTC(device); 274 ioat->device = device; 275 276 error = ioat_map_pci_bar(ioat); 277 if (error != 0) 278 goto err; 279 280 ioat->version = ioat_read_cbver(ioat); 281 if (ioat->version < IOAT_VER_3_0) { 282 error = ENODEV; 283 goto err; 284 } 285 286 error = ioat3_attach(device); 287 if (error != 0) 288 goto err; 289 290 error = pci_enable_busmaster(device); 291 if (error != 0) 292 goto err; 293 294 error = ioat_setup_intr(ioat); 295 if (error != 0) 296 goto err; 297 298 error = ioat_reset_hw(ioat); 299 if (error != 0) 300 goto err; 301 302 ioat_process_events(ioat); 303 ioat_setup_sysctl(device); 304 305 ioat->chan_idx = ioat_channel_index; 306 ioat_channel[ioat_channel_index++] = ioat; 307 ioat_test_attach(); 308 309 err: 310 if (error != 0) 311 ioat_detach(device); 312 return (error); 313 } 314 315 static int 316 ioat_detach(device_t device) 317 { 318 struct ioat_softc *ioat; 319 320 ioat = DEVICE2SOFTC(device); 321 322 ioat_test_detach(); 323 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 324 325 mtx_lock(IOAT_REFLK); 326 ioat->quiescing = TRUE; 327 ioat->destroying = TRUE; 328 wakeup(&ioat->quiescing); 329 wakeup(&ioat->resetting); 330 331 ioat_channel[ioat->chan_idx] = NULL; 332 333 ioat_drain_locked(ioat); 334 mtx_unlock(IOAT_REFLK); 335 336 ioat_teardown_intr(ioat); 337 callout_drain(&ioat->poll_timer); 338 callout_drain(&ioat->shrink_timer); 339 340 pci_disable_busmaster(device); 341 342 if (ioat->pci_resource != NULL) 343 bus_release_resource(device, SYS_RES_MEMORY, 344 ioat->pci_resource_id, ioat->pci_resource); 345 346 if (ioat->ring != NULL) 347 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 348 349 if (ioat->comp_update != NULL) { 350 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 351 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 352 ioat->comp_update_map); 353 bus_dma_tag_destroy(ioat->comp_update_tag); 354 } 355 356 bus_dma_tag_destroy(ioat->hw_desc_tag); 357 358 return (0); 359 } 360 361 static int 362 ioat_teardown_intr(struct ioat_softc *ioat) 363 { 364 365 if (ioat->tag != NULL) 366 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 367 368 if (ioat->res != NULL) 369 bus_release_resource(ioat->device, SYS_RES_IRQ, 370 rman_get_rid(ioat->res), ioat->res); 371 372 pci_release_msi(ioat->device); 373 return (0); 374 } 375 376 static int 377 ioat_start_channel(struct ioat_softc *ioat) 378 { 379 struct ioat_dma_hw_descriptor *hw_desc; 380 struct ioat_descriptor *desc; 381 struct bus_dmadesc *dmadesc; 382 uint64_t status; 383 uint32_t chanerr; 384 int i; 385 386 ioat_acquire(&ioat->dmaengine); 387 388 /* Submit 'NULL' operation manually to avoid quiescing flag */ 389 desc = ioat_get_ring_entry(ioat, ioat->head); 390 dmadesc = &desc->bus_dmadesc; 391 hw_desc = desc->u.dma; 392 393 dmadesc->callback_fn = NULL; 394 dmadesc->callback_arg = NULL; 395 396 hw_desc->u.control_raw = 0; 397 hw_desc->u.control_generic.op = IOAT_OP_COPY; 398 hw_desc->u.control_generic.completion_update = 1; 399 hw_desc->size = 8; 400 hw_desc->src_addr = 0; 401 hw_desc->dest_addr = 0; 402 hw_desc->u.control.null = 1; 403 404 ioat_submit_single(ioat); 405 ioat_release(&ioat->dmaengine); 406 407 for (i = 0; i < 100; i++) { 408 DELAY(1); 409 status = ioat_get_chansts(ioat); 410 if (is_ioat_idle(status)) 411 return (0); 412 } 413 414 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 415 ioat_log_message(0, "could not start channel: " 416 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 417 IOAT_CHANERR_STR); 418 return (ENXIO); 419 } 420 421 /* 422 * Initialize Hardware 423 */ 424 static int 425 ioat3_attach(device_t device) 426 { 427 struct ioat_softc *ioat; 428 struct ioat_descriptor **ring; 429 struct ioat_descriptor *next; 430 struct ioat_dma_hw_descriptor *dma_hw_desc; 431 int i, num_descriptors; 432 int error; 433 uint8_t xfercap; 434 435 error = 0; 436 ioat = DEVICE2SOFTC(device); 437 ioat->capabilities = ioat_read_dmacapability(ioat); 438 439 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities, 440 IOAT_DMACAP_STR); 441 442 xfercap = ioat_read_xfercap(ioat); 443 ioat->max_xfer_size = 1 << xfercap; 444 445 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 446 IOAT_INTRDELAY_SUPPORTED) != 0; 447 if (ioat->intrdelay_supported) 448 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 449 450 /* TODO: need to check DCA here if we ever do XOR/PQ */ 451 452 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 453 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 454 callout_init(&ioat->poll_timer, 1); 455 callout_init(&ioat->shrink_timer, 1); 456 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 457 458 /* Establish lock order for Witness */ 459 mtx_lock(&ioat->submit_lock); 460 mtx_lock(&ioat->cleanup_lock); 461 mtx_unlock(&ioat->cleanup_lock); 462 mtx_unlock(&ioat->submit_lock); 463 464 ioat->is_resize_pending = FALSE; 465 ioat->is_submitter_processing = FALSE; 466 ioat->is_completion_pending = FALSE; 467 ioat->is_reset_pending = FALSE; 468 ioat->is_channel_running = FALSE; 469 470 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 471 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 472 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 473 &ioat->comp_update_tag); 474 475 error = bus_dmamem_alloc(ioat->comp_update_tag, 476 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 477 if (ioat->comp_update == NULL) 478 return (ENOMEM); 479 480 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 481 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 482 0); 483 if (error != 0) 484 return (error); 485 486 ioat->ring_size_order = IOAT_MIN_ORDER; 487 488 num_descriptors = 1 << ioat->ring_size_order; 489 490 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 491 BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL, 492 sizeof(struct ioat_dma_hw_descriptor), 1, 493 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 494 &ioat->hw_desc_tag); 495 496 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 497 M_ZERO | M_WAITOK); 498 499 ring = ioat->ring; 500 for (i = 0; i < num_descriptors; i++) { 501 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 502 if (ring[i] == NULL) 503 return (ENOMEM); 504 505 ring[i]->id = i; 506 } 507 508 for (i = 0; i < num_descriptors - 1; i++) { 509 next = ring[i + 1]; 510 dma_hw_desc = ring[i]->u.dma; 511 512 dma_hw_desc->next = next->hw_desc_bus_addr; 513 } 514 515 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 516 517 ioat->head = ioat->hw_head = 0; 518 ioat->tail = 0; 519 ioat->last_seen = 0; 520 *ioat->comp_update = 0; 521 return (0); 522 } 523 524 static int 525 ioat_map_pci_bar(struct ioat_softc *ioat) 526 { 527 528 ioat->pci_resource_id = PCIR_BAR(0); 529 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 530 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 531 532 if (ioat->pci_resource == NULL) { 533 ioat_log_message(0, "unable to allocate pci resource\n"); 534 return (ENODEV); 535 } 536 537 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 538 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 539 return (0); 540 } 541 542 static void 543 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 544 { 545 struct ioat_softc *ioat = arg; 546 547 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 548 ioat->comp_update_bus_addr = seg[0].ds_addr; 549 } 550 551 static void 552 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 553 { 554 bus_addr_t *baddr; 555 556 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 557 baddr = arg; 558 *baddr = segs->ds_addr; 559 } 560 561 /* 562 * Interrupt setup and handlers 563 */ 564 static int 565 ioat_setup_intr(struct ioat_softc *ioat) 566 { 567 uint32_t num_vectors; 568 int error; 569 boolean_t use_msix; 570 boolean_t force_legacy_interrupts; 571 572 use_msix = FALSE; 573 force_legacy_interrupts = FALSE; 574 575 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 576 num_vectors = 1; 577 pci_alloc_msix(ioat->device, &num_vectors); 578 if (num_vectors == 1) 579 use_msix = TRUE; 580 } 581 582 if (use_msix) { 583 ioat->rid = 1; 584 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 585 &ioat->rid, RF_ACTIVE); 586 } else { 587 ioat->rid = 0; 588 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 589 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 590 } 591 if (ioat->res == NULL) { 592 ioat_log_message(0, "bus_alloc_resource failed\n"); 593 return (ENOMEM); 594 } 595 596 ioat->tag = NULL; 597 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 598 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 599 if (error != 0) { 600 ioat_log_message(0, "bus_setup_intr failed\n"); 601 return (error); 602 } 603 604 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 605 return (0); 606 } 607 608 static boolean_t 609 ioat_model_resets_msix(struct ioat_softc *ioat) 610 { 611 u_int32_t pciid; 612 613 pciid = pci_get_devid(ioat->device); 614 switch (pciid) { 615 /* BWD: */ 616 case 0x0c508086: 617 case 0x0c518086: 618 case 0x0c528086: 619 case 0x0c538086: 620 /* BDXDE: */ 621 case 0x6f508086: 622 case 0x6f518086: 623 case 0x6f528086: 624 case 0x6f538086: 625 return (TRUE); 626 } 627 628 return (FALSE); 629 } 630 631 static void 632 ioat_interrupt_handler(void *arg) 633 { 634 struct ioat_softc *ioat = arg; 635 636 ioat->stats.interrupts++; 637 ioat_process_events(ioat); 638 } 639 640 static int 641 chanerr_to_errno(uint32_t chanerr) 642 { 643 644 if (chanerr == 0) 645 return (0); 646 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 647 return (EFAULT); 648 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 649 return (EIO); 650 /* This one is probably our fault: */ 651 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 652 return (EIO); 653 return (EIO); 654 } 655 656 static void 657 ioat_process_events(struct ioat_softc *ioat) 658 { 659 struct ioat_descriptor *desc; 660 struct bus_dmadesc *dmadesc; 661 uint64_t comp_update, status; 662 uint32_t completed, chanerr; 663 boolean_t pending; 664 int error; 665 666 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 667 668 mtx_lock(&ioat->cleanup_lock); 669 670 /* 671 * Don't run while the hardware is being reset. Reset is responsible 672 * for blocking new work and draining & completing existing work, so 673 * there is nothing to do until new work is queued after reset anyway. 674 */ 675 if (ioat->resetting_cleanup) { 676 mtx_unlock(&ioat->cleanup_lock); 677 return; 678 } 679 680 completed = 0; 681 comp_update = *ioat->comp_update; 682 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 683 684 if (status == ioat->last_seen) { 685 /* 686 * If we landed in process_events and nothing has been 687 * completed, check for a timeout due to channel halt. 688 */ 689 comp_update = ioat_get_chansts(ioat); 690 goto out; 691 } 692 693 while (1) { 694 desc = ioat_get_ring_entry(ioat, ioat->tail); 695 dmadesc = &desc->bus_dmadesc; 696 CTR4(KTR_IOAT, "channel=%u completing desc %u ok cb %p(%p)", 697 ioat->chan_idx, ioat->tail, dmadesc->callback_fn, 698 dmadesc->callback_arg); 699 700 if (dmadesc->callback_fn != NULL) 701 dmadesc->callback_fn(dmadesc->callback_arg, 0); 702 703 completed++; 704 ioat->tail++; 705 if (desc->hw_desc_bus_addr == status) 706 break; 707 708 KASSERT(ioat_get_active(ioat) > 0, ("overrunning ring t:%u " 709 "h:%u st:0x%016lx last_seen:%016lx completed:%u\n", 710 ioat->tail, ioat->head, comp_update, ioat->last_seen, 711 completed)); 712 } 713 714 ioat->last_seen = desc->hw_desc_bus_addr; 715 ioat->stats.descriptors_processed += completed; 716 717 out: 718 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 719 720 /* Perform a racy check first; only take the locks if it passes. */ 721 pending = (ioat_get_active(ioat) != 0); 722 if (!pending && ioat->is_completion_pending) { 723 mtx_unlock(&ioat->cleanup_lock); 724 mtx_lock(&ioat->submit_lock); 725 mtx_lock(&ioat->cleanup_lock); 726 727 pending = (ioat_get_active(ioat) != 0); 728 if (!pending && ioat->is_completion_pending) { 729 ioat->is_completion_pending = FALSE; 730 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 731 ioat_shrink_timer_callback, ioat); 732 callout_stop(&ioat->poll_timer); 733 } 734 mtx_unlock(&ioat->submit_lock); 735 } 736 mtx_unlock(&ioat->cleanup_lock); 737 738 if (pending) 739 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 740 ioat); 741 742 if (completed != 0) { 743 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 744 wakeup(&ioat->tail); 745 } 746 747 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 748 return; 749 750 ioat->stats.channel_halts++; 751 752 /* 753 * Fatal programming error on this DMA channel. Flush any outstanding 754 * work with error status and restart the engine. 755 */ 756 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 757 mtx_lock(&ioat->submit_lock); 758 mtx_lock(&ioat->cleanup_lock); 759 ioat->quiescing = TRUE; 760 761 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 762 ioat_halted_debug(ioat, chanerr); 763 ioat->stats.last_halt_chanerr = chanerr; 764 765 while (ioat_get_active(ioat) > 0) { 766 desc = ioat_get_ring_entry(ioat, ioat->tail); 767 dmadesc = &desc->bus_dmadesc; 768 CTR4(KTR_IOAT, "channel=%u completing desc %u err cb %p(%p)", 769 ioat->chan_idx, ioat->tail, dmadesc->callback_fn, 770 dmadesc->callback_arg); 771 772 if (dmadesc->callback_fn != NULL) 773 dmadesc->callback_fn(dmadesc->callback_arg, 774 chanerr_to_errno(chanerr)); 775 776 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 777 ioat->tail++; 778 ioat->stats.descriptors_processed++; 779 ioat->stats.descriptors_error++; 780 } 781 782 /* Clear error status */ 783 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 784 785 mtx_unlock(&ioat->cleanup_lock); 786 mtx_unlock(&ioat->submit_lock); 787 788 ioat_log_message(0, "Resetting channel to recover from error\n"); 789 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 790 KASSERT(error == 0, 791 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 792 } 793 794 static void 795 ioat_reset_hw_task(void *ctx, int pending __unused) 796 { 797 struct ioat_softc *ioat; 798 int error; 799 800 ioat = ctx; 801 ioat_log_message(1, "%s: Resetting channel\n", __func__); 802 803 error = ioat_reset_hw(ioat); 804 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 805 (void)error; 806 } 807 808 /* 809 * User API functions 810 */ 811 unsigned 812 ioat_get_nchannels(void) 813 { 814 815 return (ioat_channel_index); 816 } 817 818 bus_dmaengine_t 819 ioat_get_dmaengine(uint32_t index, int flags) 820 { 821 struct ioat_softc *ioat; 822 823 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 824 ("invalid flags: 0x%08x", flags)); 825 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 826 ("invalid wait | nowait")); 827 828 if (index >= ioat_channel_index) 829 return (NULL); 830 831 ioat = ioat_channel[index]; 832 if (ioat == NULL || ioat->destroying) 833 return (NULL); 834 835 if (ioat->quiescing) { 836 if ((flags & M_NOWAIT) != 0) 837 return (NULL); 838 839 mtx_lock(IOAT_REFLK); 840 while (ioat->quiescing && !ioat->destroying) 841 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 842 mtx_unlock(IOAT_REFLK); 843 844 if (ioat->destroying) 845 return (NULL); 846 } 847 848 /* 849 * There's a race here between the quiescing check and HW reset or 850 * module destroy. 851 */ 852 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 853 } 854 855 void 856 ioat_put_dmaengine(bus_dmaengine_t dmaengine) 857 { 858 struct ioat_softc *ioat; 859 860 ioat = to_ioat_softc(dmaengine); 861 ioat_put(ioat, IOAT_DMAENGINE_REF); 862 } 863 864 int 865 ioat_get_hwversion(bus_dmaengine_t dmaengine) 866 { 867 struct ioat_softc *ioat; 868 869 ioat = to_ioat_softc(dmaengine); 870 return (ioat->version); 871 } 872 873 size_t 874 ioat_get_max_io_size(bus_dmaengine_t dmaengine) 875 { 876 struct ioat_softc *ioat; 877 878 ioat = to_ioat_softc(dmaengine); 879 return (ioat->max_xfer_size); 880 } 881 882 uint32_t 883 ioat_get_capabilities(bus_dmaengine_t dmaengine) 884 { 885 struct ioat_softc *ioat; 886 887 ioat = to_ioat_softc(dmaengine); 888 return (ioat->capabilities); 889 } 890 891 int 892 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 893 { 894 struct ioat_softc *ioat; 895 896 ioat = to_ioat_softc(dmaengine); 897 if (!ioat->intrdelay_supported) 898 return (ENODEV); 899 if (delay > ioat->intrdelay_max) 900 return (ERANGE); 901 902 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 903 ioat->cached_intrdelay = 904 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 905 return (0); 906 } 907 908 uint16_t 909 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 910 { 911 struct ioat_softc *ioat; 912 913 ioat = to_ioat_softc(dmaengine); 914 return (ioat->intrdelay_max); 915 } 916 917 void 918 ioat_acquire(bus_dmaengine_t dmaengine) 919 { 920 struct ioat_softc *ioat; 921 922 ioat = to_ioat_softc(dmaengine); 923 mtx_lock(&ioat->submit_lock); 924 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 925 } 926 927 int 928 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 929 { 930 struct ioat_softc *ioat; 931 int error; 932 933 ioat = to_ioat_softc(dmaengine); 934 ioat_acquire(dmaengine); 935 936 error = ioat_reserve_space(ioat, n, mflags); 937 if (error != 0) 938 ioat_release(dmaengine); 939 return (error); 940 } 941 942 void 943 ioat_release(bus_dmaengine_t dmaengine) 944 { 945 struct ioat_softc *ioat; 946 947 ioat = to_ioat_softc(dmaengine); 948 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 949 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 950 mtx_unlock(&ioat->submit_lock); 951 } 952 953 static struct ioat_descriptor * 954 ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 955 uint32_t size, uint64_t src, uint64_t dst, 956 bus_dmaengine_callback_t callback_fn, void *callback_arg, 957 uint32_t flags) 958 { 959 struct ioat_generic_hw_descriptor *hw_desc; 960 struct ioat_descriptor *desc; 961 int mflags; 962 963 mtx_assert(&ioat->submit_lock, MA_OWNED); 964 965 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 966 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 967 if ((flags & DMA_NO_WAIT) != 0) 968 mflags = M_NOWAIT; 969 else 970 mflags = M_WAITOK; 971 972 if (size > ioat->max_xfer_size) { 973 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 974 __func__, ioat->max_xfer_size, (unsigned)size); 975 return (NULL); 976 } 977 978 if (ioat_reserve_space(ioat, 1, mflags) != 0) 979 return (NULL); 980 981 desc = ioat_get_ring_entry(ioat, ioat->head); 982 hw_desc = desc->u.generic; 983 984 hw_desc->u.control_raw = 0; 985 hw_desc->u.control_generic.op = op; 986 hw_desc->u.control_generic.completion_update = 1; 987 988 if ((flags & DMA_INT_EN) != 0) 989 hw_desc->u.control_generic.int_enable = 1; 990 if ((flags & DMA_FENCE) != 0) 991 hw_desc->u.control_generic.fence = 1; 992 993 hw_desc->size = size; 994 hw_desc->src_addr = src; 995 hw_desc->dest_addr = dst; 996 997 desc->bus_dmadesc.callback_fn = callback_fn; 998 desc->bus_dmadesc.callback_arg = callback_arg; 999 return (desc); 1000 } 1001 1002 struct bus_dmadesc * 1003 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 1004 void *callback_arg, uint32_t flags) 1005 { 1006 struct ioat_dma_hw_descriptor *hw_desc; 1007 struct ioat_descriptor *desc; 1008 struct ioat_softc *ioat; 1009 1010 ioat = to_ioat_softc(dmaengine); 1011 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1012 1013 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 1014 callback_arg, flags); 1015 if (desc == NULL) 1016 return (NULL); 1017 1018 hw_desc = desc->u.dma; 1019 hw_desc->u.control.null = 1; 1020 ioat_submit_single(ioat); 1021 return (&desc->bus_dmadesc); 1022 } 1023 1024 struct bus_dmadesc * 1025 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 1026 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 1027 void *callback_arg, uint32_t flags) 1028 { 1029 struct ioat_dma_hw_descriptor *hw_desc; 1030 struct ioat_descriptor *desc; 1031 struct ioat_softc *ioat; 1032 1033 ioat = to_ioat_softc(dmaengine); 1034 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1035 1036 if (((src | dst) & (0xffffull << 48)) != 0) { 1037 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1038 __func__); 1039 return (NULL); 1040 } 1041 1042 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 1043 callback_arg, flags); 1044 if (desc == NULL) 1045 return (NULL); 1046 1047 hw_desc = desc->u.dma; 1048 if (g_ioat_debug_level >= 3) 1049 dump_descriptor(hw_desc); 1050 1051 ioat_submit_single(ioat); 1052 return (&desc->bus_dmadesc); 1053 } 1054 1055 struct bus_dmadesc * 1056 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 1057 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 1058 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1059 { 1060 struct ioat_dma_hw_descriptor *hw_desc; 1061 struct ioat_descriptor *desc; 1062 struct ioat_softc *ioat; 1063 1064 ioat = to_ioat_softc(dmaengine); 1065 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1066 1067 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 1068 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 1069 __func__); 1070 return (NULL); 1071 } 1072 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 1073 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 1074 __func__); 1075 return (NULL); 1076 } 1077 1078 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 1079 callback_fn, callback_arg, flags); 1080 if (desc == NULL) 1081 return (NULL); 1082 1083 hw_desc = desc->u.dma; 1084 if (src2 != src1 + PAGE_SIZE) { 1085 hw_desc->u.control.src_page_break = 1; 1086 hw_desc->next_src_addr = src2; 1087 } 1088 if (dst2 != dst1 + PAGE_SIZE) { 1089 hw_desc->u.control.dest_page_break = 1; 1090 hw_desc->next_dest_addr = dst2; 1091 } 1092 1093 if (g_ioat_debug_level >= 3) 1094 dump_descriptor(hw_desc); 1095 1096 ioat_submit_single(ioat); 1097 return (&desc->bus_dmadesc); 1098 } 1099 1100 struct bus_dmadesc * 1101 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1102 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1103 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1104 { 1105 struct ioat_crc32_hw_descriptor *hw_desc; 1106 struct ioat_descriptor *desc; 1107 struct ioat_softc *ioat; 1108 uint32_t teststore; 1109 uint8_t op; 1110 1111 ioat = to_ioat_softc(dmaengine); 1112 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1113 1114 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1115 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1116 __func__); 1117 return (NULL); 1118 } 1119 if (((src | dst) & (0xffffffull << 40)) != 0) { 1120 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1121 __func__); 1122 return (NULL); 1123 } 1124 teststore = (flags & _DMA_CRC_TESTSTORE); 1125 if (teststore == _DMA_CRC_TESTSTORE) { 1126 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1127 return (NULL); 1128 } 1129 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1130 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1131 __func__); 1132 return (NULL); 1133 } 1134 1135 switch (teststore) { 1136 case DMA_CRC_STORE: 1137 op = IOAT_OP_MOVECRC_STORE; 1138 break; 1139 case DMA_CRC_TEST: 1140 op = IOAT_OP_MOVECRC_TEST; 1141 break; 1142 default: 1143 KASSERT(teststore == 0, ("bogus")); 1144 op = IOAT_OP_MOVECRC; 1145 break; 1146 } 1147 1148 if ((flags & DMA_CRC_INLINE) == 0 && 1149 (crcptr & (0xffffffull << 40)) != 0) { 1150 ioat_log_message(0, 1151 "%s: High 24 bits of crcptr invalid\n", __func__); 1152 return (NULL); 1153 } 1154 1155 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1156 callback_arg, flags & ~_DMA_CRC_FLAGS); 1157 if (desc == NULL) 1158 return (NULL); 1159 1160 hw_desc = desc->u.crc32; 1161 1162 if ((flags & DMA_CRC_INLINE) == 0) 1163 hw_desc->crc_address = crcptr; 1164 else 1165 hw_desc->u.control.crc_location = 1; 1166 1167 if (initialseed != NULL) { 1168 hw_desc->u.control.use_seed = 1; 1169 hw_desc->seed = *initialseed; 1170 } 1171 1172 if (g_ioat_debug_level >= 3) 1173 dump_descriptor(hw_desc); 1174 1175 ioat_submit_single(ioat); 1176 return (&desc->bus_dmadesc); 1177 } 1178 1179 struct bus_dmadesc * 1180 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1181 uint32_t *initialseed, bus_addr_t crcptr, 1182 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1183 { 1184 struct ioat_crc32_hw_descriptor *hw_desc; 1185 struct ioat_descriptor *desc; 1186 struct ioat_softc *ioat; 1187 uint32_t teststore; 1188 uint8_t op; 1189 1190 ioat = to_ioat_softc(dmaengine); 1191 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1192 1193 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1194 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1195 __func__); 1196 return (NULL); 1197 } 1198 if ((src & (0xffffffull << 40)) != 0) { 1199 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1200 __func__); 1201 return (NULL); 1202 } 1203 teststore = (flags & _DMA_CRC_TESTSTORE); 1204 if (teststore == _DMA_CRC_TESTSTORE) { 1205 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1206 return (NULL); 1207 } 1208 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1209 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1210 __func__); 1211 return (NULL); 1212 } 1213 1214 switch (teststore) { 1215 case DMA_CRC_STORE: 1216 op = IOAT_OP_CRC_STORE; 1217 break; 1218 case DMA_CRC_TEST: 1219 op = IOAT_OP_CRC_TEST; 1220 break; 1221 default: 1222 KASSERT(teststore == 0, ("bogus")); 1223 op = IOAT_OP_CRC; 1224 break; 1225 } 1226 1227 if ((flags & DMA_CRC_INLINE) == 0 && 1228 (crcptr & (0xffffffull << 40)) != 0) { 1229 ioat_log_message(0, 1230 "%s: High 24 bits of crcptr invalid\n", __func__); 1231 return (NULL); 1232 } 1233 1234 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1235 callback_arg, flags & ~_DMA_CRC_FLAGS); 1236 if (desc == NULL) 1237 return (NULL); 1238 1239 hw_desc = desc->u.crc32; 1240 1241 if ((flags & DMA_CRC_INLINE) == 0) 1242 hw_desc->crc_address = crcptr; 1243 else 1244 hw_desc->u.control.crc_location = 1; 1245 1246 if (initialseed != NULL) { 1247 hw_desc->u.control.use_seed = 1; 1248 hw_desc->seed = *initialseed; 1249 } 1250 1251 if (g_ioat_debug_level >= 3) 1252 dump_descriptor(hw_desc); 1253 1254 ioat_submit_single(ioat); 1255 return (&desc->bus_dmadesc); 1256 } 1257 1258 struct bus_dmadesc * 1259 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1260 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1261 uint32_t flags) 1262 { 1263 struct ioat_fill_hw_descriptor *hw_desc; 1264 struct ioat_descriptor *desc; 1265 struct ioat_softc *ioat; 1266 1267 ioat = to_ioat_softc(dmaengine); 1268 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1269 1270 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1271 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1272 __func__); 1273 return (NULL); 1274 } 1275 1276 if ((dst & (0xffffull << 48)) != 0) { 1277 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1278 __func__); 1279 return (NULL); 1280 } 1281 1282 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1283 callback_fn, callback_arg, flags); 1284 if (desc == NULL) 1285 return (NULL); 1286 1287 hw_desc = desc->u.fill; 1288 if (g_ioat_debug_level >= 3) 1289 dump_descriptor(hw_desc); 1290 1291 ioat_submit_single(ioat); 1292 return (&desc->bus_dmadesc); 1293 } 1294 1295 /* 1296 * Ring Management 1297 */ 1298 static inline uint32_t 1299 ioat_get_active(struct ioat_softc *ioat) 1300 { 1301 1302 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1303 } 1304 1305 static inline uint32_t 1306 ioat_get_ring_space(struct ioat_softc *ioat) 1307 { 1308 1309 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1310 } 1311 1312 static struct ioat_descriptor * 1313 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 1314 { 1315 struct ioat_generic_hw_descriptor *hw_desc; 1316 struct ioat_descriptor *desc; 1317 int error, busdmaflag; 1318 1319 error = ENOMEM; 1320 hw_desc = NULL; 1321 1322 if ((mflags & M_WAITOK) != 0) 1323 busdmaflag = BUS_DMA_WAITOK; 1324 else 1325 busdmaflag = BUS_DMA_NOWAIT; 1326 1327 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1328 if (desc == NULL) 1329 goto out; 1330 1331 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1332 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1333 if (hw_desc == NULL) 1334 goto out; 1335 1336 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1337 desc->u.generic = hw_desc; 1338 1339 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1340 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1341 busdmaflag); 1342 if (error) 1343 goto out; 1344 1345 out: 1346 if (error) { 1347 ioat_free_ring_entry(ioat, desc); 1348 return (NULL); 1349 } 1350 return (desc); 1351 } 1352 1353 static void 1354 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1355 { 1356 1357 if (desc == NULL) 1358 return; 1359 1360 if (desc->u.generic) 1361 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1362 ioat->hw_desc_map); 1363 free(desc, M_IOAT); 1364 } 1365 1366 /* 1367 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1368 * for 'num_descs'. 1369 * 1370 * If mflags contains M_WAITOK, blocks until enough space is available. 1371 * 1372 * Returns zero on success, or an errno on error. If num_descs is beyond the 1373 * maximum ring size, returns EINVAl; if allocation would block and mflags 1374 * contains M_NOWAIT, returns EAGAIN. 1375 * 1376 * Must be called with the submit_lock held; returns with the lock held. The 1377 * lock may be dropped to allocate the ring. 1378 * 1379 * (The submit_lock is needed to add any entries to the ring, so callers are 1380 * assured enough room is available.) 1381 */ 1382 static int 1383 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1384 { 1385 struct ioat_descriptor **new_ring; 1386 uint32_t order; 1387 boolean_t dug; 1388 int error; 1389 1390 mtx_assert(&ioat->submit_lock, MA_OWNED); 1391 error = 0; 1392 dug = FALSE; 1393 1394 if (num_descs < 1 || num_descs >= (1 << IOAT_MAX_ORDER)) { 1395 error = EINVAL; 1396 goto out; 1397 } 1398 1399 for (;;) { 1400 if (ioat->quiescing) { 1401 error = ENXIO; 1402 goto out; 1403 } 1404 1405 if (ioat_get_ring_space(ioat) >= num_descs) 1406 goto out; 1407 1408 if (!dug && !ioat->is_submitter_processing && 1409 (1 << ioat->ring_size_order) > num_descs) { 1410 ioat->is_submitter_processing = TRUE; 1411 mtx_unlock(&ioat->submit_lock); 1412 1413 ioat_process_events(ioat); 1414 1415 mtx_lock(&ioat->submit_lock); 1416 dug = TRUE; 1417 KASSERT(ioat->is_submitter_processing == TRUE, 1418 ("is_submitter_processing")); 1419 ioat->is_submitter_processing = FALSE; 1420 wakeup(&ioat->tail); 1421 continue; 1422 } 1423 1424 order = ioat->ring_size_order; 1425 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1426 if ((mflags & M_WAITOK) != 0) { 1427 msleep(&ioat->tail, &ioat->submit_lock, 0, 1428 "ioat_rsz", 0); 1429 continue; 1430 } 1431 1432 error = EAGAIN; 1433 break; 1434 } 1435 1436 ioat->is_resize_pending = TRUE; 1437 for (;;) { 1438 mtx_unlock(&ioat->submit_lock); 1439 1440 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1441 TRUE, mflags); 1442 1443 mtx_lock(&ioat->submit_lock); 1444 KASSERT(ioat->ring_size_order == order, 1445 ("is_resize_pending should protect order")); 1446 1447 if (new_ring == NULL) { 1448 KASSERT((mflags & M_WAITOK) == 0, 1449 ("allocation failed")); 1450 error = EAGAIN; 1451 break; 1452 } 1453 1454 error = ring_grow(ioat, order, new_ring); 1455 if (error == 0) 1456 break; 1457 } 1458 ioat->is_resize_pending = FALSE; 1459 wakeup(&ioat->tail); 1460 if (error) 1461 break; 1462 } 1463 1464 out: 1465 mtx_assert(&ioat->submit_lock, MA_OWNED); 1466 KASSERT(!ioat->quiescing || error == ENXIO, 1467 ("reserved during quiesce")); 1468 return (error); 1469 } 1470 1471 static struct ioat_descriptor ** 1472 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1473 int mflags) 1474 { 1475 struct ioat_descriptor **ring; 1476 uint32_t i; 1477 int error; 1478 1479 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1480 1481 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1482 if (ring == NULL) 1483 return (NULL); 1484 1485 if (need_dscr) { 1486 error = ENOMEM; 1487 for (i = size / 2; i < size; i++) { 1488 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1489 if (ring[i] == NULL) 1490 goto out; 1491 ring[i]->id = i; 1492 } 1493 } 1494 error = 0; 1495 1496 out: 1497 if (error != 0 && ring != NULL) { 1498 ioat_free_ring(ioat, size, ring); 1499 ring = NULL; 1500 } 1501 return (ring); 1502 } 1503 1504 static void 1505 ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1506 struct ioat_descriptor **ring) 1507 { 1508 uint32_t i; 1509 1510 for (i = 0; i < size; i++) { 1511 if (ring[i] != NULL) 1512 ioat_free_ring_entry(ioat, ring[i]); 1513 } 1514 free(ring, M_IOAT); 1515 } 1516 1517 static struct ioat_descriptor * 1518 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1519 { 1520 1521 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1522 } 1523 1524 static int 1525 ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1526 struct ioat_descriptor **newring) 1527 { 1528 struct ioat_descriptor *tmp, *next; 1529 struct ioat_dma_hw_descriptor *hw; 1530 uint32_t oldsize, newsize, head, tail, i, end; 1531 int error; 1532 1533 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1534 1535 mtx_assert(&ioat->submit_lock, MA_OWNED); 1536 1537 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1538 error = EINVAL; 1539 goto out; 1540 } 1541 1542 oldsize = (1 << oldorder); 1543 newsize = (1 << (oldorder + 1)); 1544 1545 mtx_lock(&ioat->cleanup_lock); 1546 1547 head = ioat->head & (oldsize - 1); 1548 tail = ioat->tail & (oldsize - 1); 1549 1550 /* Copy old descriptors to new ring */ 1551 for (i = 0; i < oldsize; i++) 1552 newring[i] = ioat->ring[i]; 1553 1554 /* 1555 * If head has wrapped but tail hasn't, we must swap some descriptors 1556 * around so that tail can increment directly to head. 1557 */ 1558 if (head < tail) { 1559 for (i = 0; i <= head; i++) { 1560 tmp = newring[oldsize + i]; 1561 1562 newring[oldsize + i] = newring[i]; 1563 newring[oldsize + i]->id = oldsize + i; 1564 1565 newring[i] = tmp; 1566 newring[i]->id = i; 1567 } 1568 head += oldsize; 1569 } 1570 1571 KASSERT(head >= tail, ("invariants")); 1572 1573 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1574 if (head < oldsize) { 1575 i = oldsize - 1; 1576 end = newsize; 1577 } else { 1578 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1579 i = head; 1580 end = newsize + (head - oldsize) + 1; 1581 } 1582 1583 /* 1584 * Fix up hardware ring, being careful not to trample the active 1585 * section (tail -> head). 1586 */ 1587 for (; i < end; i++) { 1588 KASSERT((i & (newsize - 1)) < tail || 1589 (i & (newsize - 1)) >= head, ("trampling snake")); 1590 1591 next = newring[(i + 1) & (newsize - 1)]; 1592 hw = newring[i & (newsize - 1)]->u.dma; 1593 hw->next = next->hw_desc_bus_addr; 1594 } 1595 1596 #ifdef INVARIANTS 1597 for (i = 0; i < newsize; i++) { 1598 next = newring[(i + 1) & (newsize - 1)]; 1599 hw = newring[i & (newsize - 1)]->u.dma; 1600 1601 KASSERT(hw->next == next->hw_desc_bus_addr, 1602 ("mismatch at i:%u (oldsize:%u); next=%p nextaddr=0x%lx" 1603 " (tail:%u)", i, oldsize, next, next->hw_desc_bus_addr, 1604 tail)); 1605 } 1606 #endif 1607 1608 free(ioat->ring, M_IOAT); 1609 ioat->ring = newring; 1610 ioat->ring_size_order = oldorder + 1; 1611 ioat->tail = tail; 1612 ioat->head = head; 1613 error = 0; 1614 1615 mtx_unlock(&ioat->cleanup_lock); 1616 out: 1617 if (error) 1618 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1619 return (error); 1620 } 1621 1622 static int 1623 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1624 struct ioat_descriptor **newring) 1625 { 1626 struct ioat_dma_hw_descriptor *hw; 1627 struct ioat_descriptor *ent, *next; 1628 uint32_t oldsize, newsize, current_idx, new_idx, i; 1629 int error; 1630 1631 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1632 1633 mtx_assert(&ioat->submit_lock, MA_OWNED); 1634 1635 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1636 error = EINVAL; 1637 goto out_unlocked; 1638 } 1639 1640 oldsize = (1 << oldorder); 1641 newsize = (1 << (oldorder - 1)); 1642 1643 mtx_lock(&ioat->cleanup_lock); 1644 1645 /* Can't shrink below current active set! */ 1646 if (ioat_get_active(ioat) >= newsize) { 1647 error = ENOMEM; 1648 goto out; 1649 } 1650 1651 /* 1652 * Copy current descriptors to the new ring, dropping the removed 1653 * descriptors. 1654 */ 1655 for (i = 0; i < newsize; i++) { 1656 current_idx = (ioat->tail + i) & (oldsize - 1); 1657 new_idx = (ioat->tail + i) & (newsize - 1); 1658 1659 newring[new_idx] = ioat->ring[current_idx]; 1660 newring[new_idx]->id = new_idx; 1661 } 1662 1663 /* Free deleted descriptors */ 1664 for (i = newsize; i < oldsize; i++) { 1665 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1666 ioat_free_ring_entry(ioat, ent); 1667 } 1668 1669 /* Fix up hardware ring. */ 1670 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1671 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1672 hw->next = next->hw_desc_bus_addr; 1673 1674 #ifdef INVARIANTS 1675 for (i = 0; i < newsize; i++) { 1676 next = newring[(i + 1) & (newsize - 1)]; 1677 hw = newring[i & (newsize - 1)]->u.dma; 1678 1679 KASSERT(hw->next == next->hw_desc_bus_addr, 1680 ("mismatch at i:%u (newsize:%u); next=%p nextaddr=0x%lx " 1681 "(tail:%u)", i, newsize, next, next->hw_desc_bus_addr, 1682 ioat->tail)); 1683 } 1684 #endif 1685 1686 free(ioat->ring, M_IOAT); 1687 ioat->ring = newring; 1688 ioat->ring_size_order = oldorder - 1; 1689 error = 0; 1690 1691 out: 1692 mtx_unlock(&ioat->cleanup_lock); 1693 out_unlocked: 1694 if (error) 1695 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1696 return (error); 1697 } 1698 1699 static void 1700 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1701 { 1702 struct ioat_descriptor *desc; 1703 1704 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1705 IOAT_CHANERR_STR); 1706 if (chanerr == 0) 1707 return; 1708 1709 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1710 1711 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1712 dump_descriptor(desc->u.raw); 1713 1714 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1715 dump_descriptor(desc->u.raw); 1716 } 1717 1718 static void 1719 ioat_poll_timer_callback(void *arg) 1720 { 1721 struct ioat_softc *ioat; 1722 1723 ioat = arg; 1724 ioat_log_message(3, "%s\n", __func__); 1725 1726 ioat_process_events(ioat); 1727 } 1728 1729 static void 1730 ioat_shrink_timer_callback(void *arg) 1731 { 1732 struct ioat_descriptor **newring; 1733 struct ioat_softc *ioat; 1734 uint32_t order; 1735 1736 ioat = arg; 1737 ioat_log_message(1, "%s\n", __func__); 1738 1739 /* Slowly scale the ring down if idle. */ 1740 mtx_lock(&ioat->submit_lock); 1741 1742 /* Don't run while the hardware is being reset. */ 1743 if (ioat->resetting) { 1744 mtx_unlock(&ioat->submit_lock); 1745 return; 1746 } 1747 1748 order = ioat->ring_size_order; 1749 if (ioat->is_completion_pending || ioat->is_resize_pending || 1750 order == IOAT_MIN_ORDER) { 1751 mtx_unlock(&ioat->submit_lock); 1752 goto out; 1753 } 1754 ioat->is_resize_pending = TRUE; 1755 mtx_unlock(&ioat->submit_lock); 1756 1757 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1758 M_NOWAIT); 1759 1760 mtx_lock(&ioat->submit_lock); 1761 KASSERT(ioat->ring_size_order == order, 1762 ("resize_pending protects order")); 1763 1764 if (newring != NULL && !ioat->is_completion_pending) 1765 ring_shrink(ioat, order, newring); 1766 else if (newring != NULL) 1767 ioat_free_ring(ioat, (1 << (order - 1)), newring); 1768 1769 ioat->is_resize_pending = FALSE; 1770 mtx_unlock(&ioat->submit_lock); 1771 1772 out: 1773 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1774 callout_reset(&ioat->shrink_timer, IOAT_SHRINK_PERIOD, 1775 ioat_shrink_timer_callback, ioat); 1776 } 1777 1778 /* 1779 * Support Functions 1780 */ 1781 static void 1782 ioat_submit_single(struct ioat_softc *ioat) 1783 { 1784 1785 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1786 atomic_add_rel_int(&ioat->head, 1); 1787 atomic_add_rel_int(&ioat->hw_head, 1); 1788 1789 if (!ioat->is_completion_pending) { 1790 ioat->is_completion_pending = TRUE; 1791 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback, 1792 ioat); 1793 callout_stop(&ioat->shrink_timer); 1794 } 1795 1796 ioat->stats.descriptors_submitted++; 1797 } 1798 1799 static int 1800 ioat_reset_hw(struct ioat_softc *ioat) 1801 { 1802 uint64_t status; 1803 uint32_t chanerr; 1804 unsigned timeout; 1805 int error; 1806 1807 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx); 1808 1809 mtx_lock(IOAT_REFLK); 1810 while (ioat->resetting && !ioat->destroying) 1811 msleep(&ioat->resetting, IOAT_REFLK, 0, "IRH_drain", 0); 1812 if (ioat->destroying) { 1813 mtx_unlock(IOAT_REFLK); 1814 return (ENXIO); 1815 } 1816 ioat->resetting = TRUE; 1817 1818 ioat->quiescing = TRUE; 1819 ioat_drain_locked(ioat); 1820 mtx_unlock(IOAT_REFLK); 1821 1822 /* 1823 * Suspend ioat_process_events while the hardware and softc are in an 1824 * indeterminate state. 1825 */ 1826 mtx_lock(&ioat->cleanup_lock); 1827 ioat->resetting_cleanup = TRUE; 1828 mtx_unlock(&ioat->cleanup_lock); 1829 1830 status = ioat_get_chansts(ioat); 1831 if (is_ioat_active(status) || is_ioat_idle(status)) 1832 ioat_suspend(ioat); 1833 1834 /* Wait at most 20 ms */ 1835 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1836 timeout < 20; timeout++) { 1837 DELAY(1000); 1838 status = ioat_get_chansts(ioat); 1839 } 1840 if (timeout == 20) { 1841 error = ETIMEDOUT; 1842 goto out; 1843 } 1844 1845 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1846 1847 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1848 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1849 1850 /* 1851 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1852 * that can cause stability issues for IOAT v3. 1853 */ 1854 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1855 4); 1856 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1857 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1858 1859 /* 1860 * BDXDE and BWD models reset MSI-X registers on device reset. 1861 * Save/restore their contents manually. 1862 */ 1863 if (ioat_model_resets_msix(ioat)) { 1864 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1865 pci_save_state(ioat->device); 1866 } 1867 1868 ioat_reset(ioat); 1869 1870 /* Wait at most 20 ms */ 1871 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1872 DELAY(1000); 1873 if (timeout == 20) { 1874 error = ETIMEDOUT; 1875 goto out; 1876 } 1877 1878 if (ioat_model_resets_msix(ioat)) { 1879 ioat_log_message(1, "device resets registers; restored\n"); 1880 pci_restore_state(ioat->device); 1881 } 1882 1883 /* Reset attempts to return the hardware to "halted." */ 1884 status = ioat_get_chansts(ioat); 1885 if (is_ioat_active(status) || is_ioat_idle(status)) { 1886 /* So this really shouldn't happen... */ 1887 ioat_log_message(0, "Device is active after a reset?\n"); 1888 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1889 error = 0; 1890 goto out; 1891 } 1892 1893 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1894 if (chanerr != 0) { 1895 mtx_lock(&ioat->cleanup_lock); 1896 ioat_halted_debug(ioat, chanerr); 1897 mtx_unlock(&ioat->cleanup_lock); 1898 error = EIO; 1899 goto out; 1900 } 1901 1902 /* 1903 * Bring device back online after reset. Writing CHAINADDR brings the 1904 * device back to active. 1905 * 1906 * The internal ring counter resets to zero, so we have to start over 1907 * at zero as well. 1908 */ 1909 ioat->tail = ioat->head = ioat->hw_head = 0; 1910 ioat->last_seen = 0; 1911 *ioat->comp_update = 0; 1912 1913 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1914 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1915 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1916 error = 0; 1917 1918 out: 1919 /* 1920 * Resume completions now that ring state is consistent. 1921 * ioat_start_channel will add a pending completion and if we are still 1922 * blocking completions, we may livelock. 1923 */ 1924 mtx_lock(&ioat->cleanup_lock); 1925 ioat->resetting_cleanup = FALSE; 1926 mtx_unlock(&ioat->cleanup_lock); 1927 1928 /* Enqueues a null operation and ensures it completes. */ 1929 if (error == 0) 1930 error = ioat_start_channel(ioat); 1931 1932 /* Unblock submission of new work */ 1933 mtx_lock(IOAT_REFLK); 1934 ioat->quiescing = FALSE; 1935 wakeup(&ioat->quiescing); 1936 1937 ioat->resetting = FALSE; 1938 wakeup(&ioat->resetting); 1939 mtx_unlock(IOAT_REFLK); 1940 1941 return (error); 1942 } 1943 1944 static int 1945 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1946 { 1947 struct ioat_softc *ioat; 1948 struct sbuf sb; 1949 uint64_t status; 1950 int error; 1951 1952 ioat = arg1; 1953 1954 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1955 1956 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1957 switch (status) { 1958 case IOAT_CHANSTS_ACTIVE: 1959 sbuf_printf(&sb, "ACTIVE"); 1960 break; 1961 case IOAT_CHANSTS_IDLE: 1962 sbuf_printf(&sb, "IDLE"); 1963 break; 1964 case IOAT_CHANSTS_SUSPENDED: 1965 sbuf_printf(&sb, "SUSPENDED"); 1966 break; 1967 case IOAT_CHANSTS_HALTED: 1968 sbuf_printf(&sb, "HALTED"); 1969 break; 1970 case IOAT_CHANSTS_ARMED: 1971 sbuf_printf(&sb, "ARMED"); 1972 break; 1973 default: 1974 sbuf_printf(&sb, "UNKNOWN"); 1975 break; 1976 } 1977 error = sbuf_finish(&sb); 1978 sbuf_delete(&sb); 1979 1980 if (error != 0 || req->newptr == NULL) 1981 return (error); 1982 return (EINVAL); 1983 } 1984 1985 static int 1986 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1987 { 1988 struct ioat_softc *ioat; 1989 struct sbuf sb; 1990 #define PRECISION "1" 1991 const uintmax_t factor = 10; 1992 uintmax_t rate; 1993 int error; 1994 1995 ioat = arg1; 1996 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1997 1998 if (ioat->stats.interrupts == 0) { 1999 sbuf_printf(&sb, "NaN"); 2000 goto out; 2001 } 2002 rate = ioat->stats.descriptors_processed * factor / 2003 ioat->stats.interrupts; 2004 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 2005 rate % factor); 2006 #undef PRECISION 2007 out: 2008 error = sbuf_finish(&sb); 2009 sbuf_delete(&sb); 2010 if (error != 0 || req->newptr == NULL) 2011 return (error); 2012 return (EINVAL); 2013 } 2014 2015 static int 2016 sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 2017 { 2018 struct ioat_softc *ioat; 2019 int error, arg; 2020 2021 ioat = arg1; 2022 2023 arg = 0; 2024 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 2025 if (error != 0 || req->newptr == NULL) 2026 return (error); 2027 2028 error = SYSCTL_IN(req, &arg, sizeof(arg)); 2029 if (error != 0) 2030 return (error); 2031 2032 if (arg != 0) 2033 error = ioat_reset_hw(ioat); 2034 2035 return (error); 2036 } 2037 2038 static void 2039 dump_descriptor(void *hw_desc) 2040 { 2041 int i, j; 2042 2043 for (i = 0; i < 2; i++) { 2044 for (j = 0; j < 8; j++) 2045 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 2046 printf("\n"); 2047 } 2048 } 2049 2050 static void 2051 ioat_setup_sysctl(device_t device) 2052 { 2053 struct sysctl_oid_list *par, *statpar, *state, *hammer; 2054 struct sysctl_ctx_list *ctx; 2055 struct sysctl_oid *tree, *tmp; 2056 struct ioat_softc *ioat; 2057 2058 ioat = DEVICE2SOFTC(device); 2059 ctx = device_get_sysctl_ctx(device); 2060 tree = device_get_sysctl_tree(device); 2061 par = SYSCTL_CHILDREN(tree); 2062 2063 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 2064 &ioat->version, 0, "HW version (0xMM form)"); 2065 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 2066 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 2067 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 2068 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 2069 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 2070 &ioat->intrdelay_max, 0, 2071 "Maximum configurable INTRDELAY on this channel (microseconds)"); 2072 2073 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 2074 "IOAT channel internal state"); 2075 state = SYSCTL_CHILDREN(tmp); 2076 2077 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 2078 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 2079 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 2080 0, "SW descriptor head pointer index"); 2081 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 2082 0, "SW descriptor tail pointer index"); 2083 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 2084 &ioat->hw_head, 0, "HW DMACOUNT"); 2085 2086 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 2087 ioat->comp_update, "HW addr of last completion"); 2088 2089 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 2090 &ioat->is_resize_pending, 0, "resize pending"); 2091 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing", 2092 CTLFLAG_RD, &ioat->is_submitter_processing, 0, 2093 "submitter processing"); 2094 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 2095 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 2096 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 2097 &ioat->is_reset_pending, 0, "reset pending"); 2098 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 2099 &ioat->is_channel_running, 0, "channel running"); 2100 2101 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 2102 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 2103 "String of the channel status"); 2104 2105 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 2106 &ioat->cached_intrdelay, 0, 2107 "Current INTRDELAY on this channel (cached, microseconds)"); 2108 2109 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 2110 "Big hammers (mostly for testing)"); 2111 hammer = SYSCTL_CHILDREN(tmp); 2112 2113 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 2114 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 2115 "Set to non-zero to reset the hardware"); 2116 2117 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 2118 "IOAT channel statistics"); 2119 statpar = SYSCTL_CHILDREN(tmp); 2120 2121 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 2122 &ioat->stats.interrupts, 2123 "Number of interrupts processed on this channel"); 2124 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 2125 &ioat->stats.descriptors_processed, 2126 "Number of descriptors processed on this channel"); 2127 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 2128 &ioat->stats.descriptors_submitted, 2129 "Number of descriptors submitted to this channel"); 2130 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 2131 &ioat->stats.descriptors_error, 2132 "Number of descriptors failed by channel errors"); 2133 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 2134 &ioat->stats.channel_halts, 0, 2135 "Number of times the channel has halted"); 2136 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 2137 &ioat->stats.last_halt_chanerr, 0, 2138 "The raw CHANERR when the channel was last halted"); 2139 2140 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 2141 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 2142 "Descriptors per interrupt"); 2143 } 2144 2145 static inline struct ioat_softc * 2146 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2147 { 2148 uint32_t old; 2149 2150 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2151 2152 old = atomic_fetchadd_32(&ioat->refcnt, 1); 2153 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 2154 2155 #ifdef INVARIANTS 2156 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 2157 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 2158 #endif 2159 2160 return (ioat); 2161 } 2162 2163 static inline void 2164 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2165 { 2166 2167 _ioat_putn(ioat, n, kind, FALSE); 2168 } 2169 2170 static inline void 2171 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2172 { 2173 2174 _ioat_putn(ioat, n, kind, TRUE); 2175 } 2176 2177 static inline void 2178 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 2179 boolean_t locked) 2180 { 2181 uint32_t old; 2182 2183 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2184 2185 if (n == 0) 2186 return; 2187 2188 #ifdef INVARIANTS 2189 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 2190 KASSERT(old >= n, ("refcnt kind underflow")); 2191 #endif 2192 2193 /* Skip acquiring the lock if resulting refcnt > 0. */ 2194 for (;;) { 2195 old = ioat->refcnt; 2196 if (old <= n) 2197 break; 2198 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 2199 return; 2200 } 2201 2202 if (locked) 2203 mtx_assert(IOAT_REFLK, MA_OWNED); 2204 else 2205 mtx_lock(IOAT_REFLK); 2206 2207 old = atomic_fetchadd_32(&ioat->refcnt, -n); 2208 KASSERT(old >= n, ("refcnt error")); 2209 2210 if (old == n) 2211 wakeup(IOAT_REFLK); 2212 if (!locked) 2213 mtx_unlock(IOAT_REFLK); 2214 } 2215 2216 static inline void 2217 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2218 { 2219 2220 ioat_putn(ioat, 1, kind); 2221 } 2222 2223 static void 2224 ioat_drain_locked(struct ioat_softc *ioat) 2225 { 2226 2227 mtx_assert(IOAT_REFLK, MA_OWNED); 2228 while (ioat->refcnt > 0) 2229 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 2230 } 2231 2232 #ifdef DDB 2233 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo) 2234 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object) 2235 DB_SHOW_COMMAND(ioat, db_show_ioat) 2236 { 2237 struct ioat_softc *sc; 2238 unsigned idx; 2239 2240 if (!have_addr) 2241 goto usage; 2242 idx = (unsigned)addr; 2243 if (idx >= ioat_channel_index) 2244 goto usage; 2245 2246 sc = ioat_channel[idx]; 2247 db_printf("ioat softc at %p\n", sc); 2248 if (sc == NULL) 2249 return; 2250 2251 db_printf(" version: %d\n", sc->version); 2252 db_printf(" chan_idx: %u\n", sc->chan_idx); 2253 db_printf(" submit_lock: "); 2254 db_show_lock(&sc->submit_lock); 2255 2256 db_printf(" capabilities: %b\n", (int)sc->capabilities, 2257 IOAT_DMACAP_STR); 2258 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay); 2259 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update); 2260 2261 db_printf(" poll_timer:\n"); 2262 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time); 2263 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg); 2264 db_printf(" c_func: %p\n", sc->poll_timer.c_func); 2265 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock); 2266 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags); 2267 2268 db_printf(" shrink_timer:\n"); 2269 db_printf(" c_time: %ju\n", (uintmax_t)sc->shrink_timer.c_time); 2270 db_printf(" c_arg: %p\n", sc->shrink_timer.c_arg); 2271 db_printf(" c_func: %p\n", sc->shrink_timer.c_func); 2272 db_printf(" c_lock: %p\n", sc->shrink_timer.c_lock); 2273 db_printf(" c_flags: 0x%x\n", (unsigned)sc->shrink_timer.c_flags); 2274 2275 db_printf(" quiescing: %d\n", (int)sc->quiescing); 2276 db_printf(" destroying: %d\n", (int)sc->destroying); 2277 db_printf(" is_resize_pending: %d\n", (int)sc->is_resize_pending); 2278 db_printf(" is_submitter_processing: %d\n", 2279 (int)sc->is_submitter_processing); 2280 db_printf(" is_completion_pending: %d\n", (int)sc->is_completion_pending); 2281 db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending); 2282 db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running); 2283 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported); 2284 db_printf(" resetting: %d\n", (int)sc->resetting); 2285 2286 db_printf(" head: %u\n", sc->head); 2287 db_printf(" tail: %u\n", sc->tail); 2288 db_printf(" hw_head: %u\n", sc->hw_head); 2289 db_printf(" ring_size_order: %u\n", sc->ring_size_order); 2290 db_printf(" last_seen: 0x%lx\n", sc->last_seen); 2291 db_printf(" ring: %p\n", sc->ring); 2292 2293 db_printf(" ring[%u] (tail):\n", sc->tail % 2294 (1 << sc->ring_size_order)); 2295 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id); 2296 db_printf(" addr: 0x%lx\n", 2297 ioat_get_ring_entry(sc, sc->tail)->hw_desc_bus_addr); 2298 db_printf(" next: 0x%lx\n", 2299 ioat_get_ring_entry(sc, sc->tail)->u.generic->next); 2300 2301 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) % 2302 (1 << sc->ring_size_order)); 2303 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id); 2304 db_printf(" addr: 0x%lx\n", 2305 ioat_get_ring_entry(sc, sc->head - 1)->hw_desc_bus_addr); 2306 db_printf(" next: 0x%lx\n", 2307 ioat_get_ring_entry(sc, sc->head - 1)->u.generic->next); 2308 2309 db_printf(" ring[%u] (head):\n", (sc->head) % 2310 (1 << sc->ring_size_order)); 2311 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id); 2312 db_printf(" addr: 0x%lx\n", 2313 ioat_get_ring_entry(sc, sc->head)->hw_desc_bus_addr); 2314 db_printf(" next: 0x%lx\n", 2315 ioat_get_ring_entry(sc, sc->head)->u.generic->next); 2316 2317 for (idx = 0; idx < (1 << sc->ring_size_order); idx++) 2318 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK) 2319 == ioat_get_ring_entry(sc, idx)->hw_desc_bus_addr) 2320 db_printf(" ring[%u] == hardware tail\n", idx); 2321 2322 db_printf(" cleanup_lock: "); 2323 db_show_lock(&sc->cleanup_lock); 2324 2325 db_printf(" refcnt: %u\n", sc->refcnt); 2326 #ifdef INVARIANTS 2327 CTASSERT(IOAT_NUM_REF_KINDS == 2); 2328 db_printf(" refkinds: [ENG=%u, DESCR=%u]\n", sc->refkinds[0], 2329 sc->refkinds[1]); 2330 #endif 2331 db_printf(" stats:\n"); 2332 db_printf(" interrupts: %lu\n", sc->stats.interrupts); 2333 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed); 2334 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error); 2335 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted); 2336 2337 db_printf(" channel_halts: %u\n", sc->stats.channel_halts); 2338 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr); 2339 2340 if (db_pager_quit) 2341 return; 2342 2343 db_printf(" hw status:\n"); 2344 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc)); 2345 db_printf(" chanctrl: 0x%x\n", 2346 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET)); 2347 db_printf(" chancmd: 0x%x\n", 2348 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET)); 2349 db_printf(" dmacount: 0x%x\n", 2350 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET)); 2351 db_printf(" chainaddr: 0x%lx\n", 2352 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW)); 2353 db_printf(" chancmp: 0x%lx\n", 2354 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW)); 2355 db_printf(" chanerr: %b\n", 2356 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR); 2357 return; 2358 usage: 2359 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index); 2360 return; 2361 } 2362 #endif /* DDB */ 2363