1 /*- 2 * Copyright (c) 1998, 1999 Takanori Watanabe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/bus.h> 30 #include <sys/kernel.h> 31 #include <sys/lock.h> 32 #include <sys/module.h> 33 #include <sys/mutex.h> 34 #include <sys/rman.h> 35 #include <machine/bus.h> 36 #include <dev/smbus/smbconf.h> 37 38 #include "smbus_if.h" 39 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 #include <dev/intpm/intpmreg.h> 43 #include <dev/amdsbwd/amd_chipset.h> 44 45 #include "opt_intpm.h" 46 47 struct intsmb_softc { 48 device_t dev; 49 struct resource *io_res; 50 struct resource *irq_res; 51 void *irq_hand; 52 device_t smbus; 53 int io_rid; 54 int isbusy; 55 int cfg_irq9; 56 int sb8xx; 57 int poll; 58 struct mtx lock; 59 }; 60 61 #define INTSMB_LOCK(sc) mtx_lock(&(sc)->lock) 62 #define INTSMB_UNLOCK(sc) mtx_unlock(&(sc)->lock) 63 #define INTSMB_LOCK_ASSERT(sc) mtx_assert(&(sc)->lock, MA_OWNED) 64 65 static int intsmb_probe(device_t); 66 static int intsmb_attach(device_t); 67 static int intsmb_detach(device_t); 68 static int intsmb_intr(struct intsmb_softc *sc); 69 static int intsmb_slvintr(struct intsmb_softc *sc); 70 static void intsmb_alrintr(struct intsmb_softc *sc); 71 static int intsmb_callback(device_t dev, int index, void *data); 72 static int intsmb_quick(device_t dev, u_char slave, int how); 73 static int intsmb_sendb(device_t dev, u_char slave, char byte); 74 static int intsmb_recvb(device_t dev, u_char slave, char *byte); 75 static int intsmb_writeb(device_t dev, u_char slave, char cmd, char byte); 76 static int intsmb_writew(device_t dev, u_char slave, char cmd, short word); 77 static int intsmb_readb(device_t dev, u_char slave, char cmd, char *byte); 78 static int intsmb_readw(device_t dev, u_char slave, char cmd, short *word); 79 static int intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata); 80 static int intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf); 81 static int intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf); 82 static void intsmb_start(struct intsmb_softc *sc, u_char cmd, int nointr); 83 static int intsmb_stop(struct intsmb_softc *sc); 84 static int intsmb_stop_poll(struct intsmb_softc *sc); 85 static int intsmb_free(struct intsmb_softc *sc); 86 static void intsmb_rawintr(void *arg); 87 88 const struct intsmb_device { 89 uint32_t devid; 90 const char *description; 91 } intsmb_products[] = { 92 { 0x71138086, "Intel PIIX4 SMBUS Interface" }, 93 { 0x719b8086, "Intel PIIX4 SMBUS Interface" }, 94 #if 0 95 /* Not a good idea yet, this stops isab0 functioning */ 96 { 0x02001166, "ServerWorks OSB4" }, 97 #endif 98 { 0x43721002, "ATI IXP400 SMBus Controller" }, 99 { AMDSB_SMBUS_DEVID, "AMD SB600/7xx/8xx/9xx SMBus Controller" }, 100 { AMDFCH_SMBUS_DEVID, "AMD FCH SMBus Controller" }, 101 { AMDCZ_SMBUS_DEVID, "AMD FCH SMBus Controller" }, 102 { HYGONCZ_SMBUS_DEVID, "Hygon FCH SMBus Controller" }, 103 }; 104 105 static int 106 intsmb_probe(device_t dev) 107 { 108 const struct intsmb_device *isd; 109 uint32_t devid; 110 size_t i; 111 112 devid = pci_get_devid(dev); 113 for (i = 0; i < nitems(intsmb_products); i++) { 114 isd = &intsmb_products[i]; 115 if (isd->devid == devid) { 116 device_set_desc(dev, isd->description); 117 return (BUS_PROBE_DEFAULT); 118 } 119 } 120 return (ENXIO); 121 } 122 123 static uint8_t 124 amd_pmio_read(struct resource *res, uint8_t reg) 125 { 126 bus_write_1(res, 0, reg); /* Index */ 127 return (bus_read_1(res, 1)); /* Data */ 128 } 129 130 static int 131 sb8xx_attach(device_t dev) 132 { 133 static const int AMDSB_SMBIO_WIDTH = 0x10; 134 struct intsmb_softc *sc; 135 struct resource *res; 136 uint32_t devid; 137 uint8_t revid; 138 uint16_t addr; 139 int rid; 140 int rc; 141 bool enabled; 142 143 sc = device_get_softc(dev); 144 rid = 0; 145 rc = bus_set_resource(dev, SYS_RES_IOPORT, rid, AMDSB_PMIO_INDEX, 146 AMDSB_PMIO_WIDTH); 147 if (rc != 0) { 148 device_printf(dev, "bus_set_resource for PM IO failed\n"); 149 return (ENXIO); 150 } 151 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 152 RF_ACTIVE); 153 if (res == NULL) { 154 device_printf(dev, "bus_alloc_resource for PM IO failed\n"); 155 return (ENXIO); 156 } 157 158 devid = pci_get_devid(dev); 159 revid = pci_get_revid(dev); 160 if (devid == AMDSB_SMBUS_DEVID || 161 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) || 162 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) { 163 addr = amd_pmio_read(res, AMDSB8_PM_SMBUS_EN + 1); 164 addr <<= 8; 165 addr |= amd_pmio_read(res, AMDSB8_PM_SMBUS_EN); 166 enabled = (addr & AMDSB8_SMBUS_EN) != 0; 167 addr &= AMDSB8_SMBUS_ADDR_MASK; 168 } else { 169 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN0); 170 enabled = (addr & AMDFCH41_SMBUS_EN) != 0; 171 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN1); 172 addr <<= 8; 173 } 174 175 bus_release_resource(dev, SYS_RES_IOPORT, rid, res); 176 bus_delete_resource(dev, SYS_RES_IOPORT, rid); 177 178 if (!enabled) { 179 device_printf(dev, "SB8xx/SB9xx/FCH SMBus not enabled\n"); 180 return (ENXIO); 181 } 182 183 sc->io_rid = 0; 184 rc = bus_set_resource(dev, SYS_RES_IOPORT, sc->io_rid, addr, 185 AMDSB_SMBIO_WIDTH); 186 if (rc != 0) { 187 device_printf(dev, "bus_set_resource for SMBus IO failed\n"); 188 return (ENXIO); 189 } 190 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid, 191 RF_ACTIVE); 192 if (sc->io_res == NULL) { 193 device_printf(dev, "Could not allocate I/O space\n"); 194 return (ENXIO); 195 } 196 sc->poll = 1; 197 return (0); 198 } 199 200 static void 201 intsmb_release_resources(device_t dev) 202 { 203 struct intsmb_softc *sc = device_get_softc(dev); 204 205 if (sc->smbus) 206 device_delete_child(dev, sc->smbus); 207 if (sc->irq_hand) 208 bus_teardown_intr(dev, sc->irq_res, sc->irq_hand); 209 if (sc->irq_res) 210 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 211 if (sc->io_res) 212 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid, 213 sc->io_res); 214 mtx_destroy(&sc->lock); 215 } 216 217 static int 218 intsmb_attach(device_t dev) 219 { 220 struct intsmb_softc *sc = device_get_softc(dev); 221 int error, rid, value; 222 int intr; 223 char *str; 224 225 sc->dev = dev; 226 227 mtx_init(&sc->lock, device_get_nameunit(dev), "intsmb", MTX_DEF); 228 229 sc->cfg_irq9 = 0; 230 switch (pci_get_devid(dev)) { 231 #ifndef NO_CHANGE_PCICONF 232 case 0x71138086: /* Intel 82371AB */ 233 case 0x719b8086: /* Intel 82443MX */ 234 /* Changing configuration is allowed. */ 235 sc->cfg_irq9 = 1; 236 break; 237 #endif 238 case AMDSB_SMBUS_DEVID: 239 if (pci_get_revid(dev) >= AMDSB8_SMBUS_REVID) 240 sc->sb8xx = 1; 241 break; 242 case AMDFCH_SMBUS_DEVID: 243 case AMDCZ_SMBUS_DEVID: 244 case HYGONCZ_SMBUS_DEVID: 245 sc->sb8xx = 1; 246 break; 247 } 248 249 if (sc->sb8xx) { 250 error = sb8xx_attach(dev); 251 if (error != 0) 252 goto fail; 253 else 254 goto no_intr; 255 } 256 257 sc->io_rid = PCI_BASE_ADDR_SMB; 258 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid, 259 RF_ACTIVE); 260 if (sc->io_res == NULL) { 261 device_printf(dev, "Could not allocate I/O space\n"); 262 error = ENXIO; 263 goto fail; 264 } 265 266 if (sc->cfg_irq9) { 267 pci_write_config(dev, PCIR_INTLINE, 0x9, 1); 268 pci_write_config(dev, PCI_HST_CFG_SMB, 269 PCI_INTR_SMB_IRQ9 | PCI_INTR_SMB_ENABLE, 1); 270 } 271 value = pci_read_config(dev, PCI_HST_CFG_SMB, 1); 272 sc->poll = (value & PCI_INTR_SMB_ENABLE) == 0; 273 intr = value & PCI_INTR_SMB_MASK; 274 switch (intr) { 275 case PCI_INTR_SMB_SMI: 276 str = "SMI"; 277 break; 278 case PCI_INTR_SMB_IRQ9: 279 str = "IRQ 9"; 280 break; 281 case PCI_INTR_SMB_IRQ_PCI: 282 str = "PCI IRQ"; 283 break; 284 default: 285 str = "BOGUS"; 286 } 287 288 device_printf(dev, "intr %s %s ", str, 289 sc->poll == 0 ? "enabled" : "disabled"); 290 printf("revision %d\n", pci_read_config(dev, PCI_REVID_SMB, 1)); 291 292 if (!sc->poll && intr == PCI_INTR_SMB_SMI) { 293 device_printf(dev, 294 "using polling mode when configured interrupt is SMI\n"); 295 sc->poll = 1; 296 } 297 298 if (sc->poll) 299 goto no_intr; 300 301 if (intr != PCI_INTR_SMB_IRQ9 && intr != PCI_INTR_SMB_IRQ_PCI) { 302 device_printf(dev, "Unsupported interrupt mode\n"); 303 error = ENXIO; 304 goto fail; 305 } 306 307 /* Force IRQ 9. */ 308 rid = 0; 309 if (sc->cfg_irq9) 310 bus_set_resource(dev, SYS_RES_IRQ, rid, 9, 1); 311 312 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 313 RF_SHAREABLE | RF_ACTIVE); 314 if (sc->irq_res == NULL) { 315 device_printf(dev, "Could not allocate irq\n"); 316 error = ENXIO; 317 goto fail; 318 } 319 320 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 321 NULL, intsmb_rawintr, sc, &sc->irq_hand); 322 if (error) { 323 device_printf(dev, "Failed to map intr\n"); 324 goto fail; 325 } 326 327 no_intr: 328 sc->isbusy = 0; 329 sc->smbus = device_add_child(dev, "smbus", -1); 330 if (sc->smbus == NULL) { 331 device_printf(dev, "failed to add smbus child\n"); 332 error = ENXIO; 333 goto fail; 334 } 335 error = device_probe_and_attach(sc->smbus); 336 if (error) { 337 device_printf(dev, "failed to probe+attach smbus child\n"); 338 goto fail; 339 } 340 341 #ifdef ENABLE_ALART 342 /* Enable Arart */ 343 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN); 344 #endif 345 return (0); 346 347 fail: 348 intsmb_release_resources(dev); 349 return (error); 350 } 351 352 static int 353 intsmb_detach(device_t dev) 354 { 355 int error; 356 357 error = bus_generic_detach(dev); 358 if (error) { 359 device_printf(dev, "bus detach failed\n"); 360 return (error); 361 } 362 363 intsmb_release_resources(dev); 364 return (0); 365 } 366 367 static void 368 intsmb_rawintr(void *arg) 369 { 370 struct intsmb_softc *sc = arg; 371 372 INTSMB_LOCK(sc); 373 intsmb_intr(sc); 374 intsmb_slvintr(sc); 375 INTSMB_UNLOCK(sc); 376 } 377 378 static int 379 intsmb_callback(device_t dev, int index, void *data) 380 { 381 int error = 0; 382 383 switch (index) { 384 case SMB_REQUEST_BUS: 385 break; 386 case SMB_RELEASE_BUS: 387 break; 388 default: 389 error = SMB_EINVAL; 390 } 391 392 return (error); 393 } 394 395 /* Counterpart of smbtx_smb_free(). */ 396 static int 397 intsmb_free(struct intsmb_softc *sc) 398 { 399 400 INTSMB_LOCK_ASSERT(sc); 401 if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) || 402 #ifdef ENABLE_ALART 403 (bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) || 404 #endif 405 sc->isbusy) 406 return (SMB_EBUSY); 407 408 sc->isbusy = 1; 409 /* Disable Interrupt in slave part. */ 410 #ifndef ENABLE_ALART 411 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0); 412 #endif 413 /* Reset INTR Flag to prepare INTR. */ 414 bus_write_1(sc->io_res, PIIX4_SMBHSTSTS, 415 PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR | 416 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL); 417 return (0); 418 } 419 420 static int 421 intsmb_intr(struct intsmb_softc *sc) 422 { 423 int status, tmp; 424 425 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS); 426 if (status & PIIX4_SMBHSTSTAT_BUSY) 427 return (1); 428 429 if (status & (PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR | 430 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL)) { 431 432 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); 433 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, 434 tmp & ~PIIX4_SMBHSTCNT_INTREN); 435 if (sc->isbusy) { 436 sc->isbusy = 0; 437 wakeup(sc); 438 } 439 return (0); 440 } 441 return (1); /* Not Completed */ 442 } 443 444 static int 445 intsmb_slvintr(struct intsmb_softc *sc) 446 { 447 int status; 448 449 status = bus_read_1(sc->io_res, PIIX4_SMBSLVSTS); 450 if (status & PIIX4_SMBSLVSTS_BUSY) 451 return (1); 452 if (status & PIIX4_SMBSLVSTS_ALART) 453 intsmb_alrintr(sc); 454 else if (status & ~(PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 455 | PIIX4_SMBSLVSTS_SDW1)) { 456 } 457 458 /* Reset Status Register */ 459 bus_write_1(sc->io_res, PIIX4_SMBSLVSTS, 460 PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 | 461 PIIX4_SMBSLVSTS_SDW1 | PIIX4_SMBSLVSTS_SLV); 462 return (0); 463 } 464 465 static void 466 intsmb_alrintr(struct intsmb_softc *sc) 467 { 468 int slvcnt __unused; 469 #ifdef ENABLE_ALART 470 int error; 471 uint8_t addr; 472 #endif 473 474 /* Stop generating INTR from ALART. */ 475 slvcnt = bus_read_1(sc->io_res, PIIX4_SMBSLVCNT); 476 #ifdef ENABLE_ALART 477 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 478 slvcnt & ~PIIX4_SMBSLVCNT_ALTEN); 479 #endif 480 DELAY(5); 481 482 /* Ask bus who asserted it and then ask it what's the matter. */ 483 #ifdef ENABLE_ALART 484 error = intsmb_free(sc); 485 if (error) 486 return; 487 488 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB); 489 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 1); 490 error = intsmb_stop_poll(sc); 491 if (error) 492 device_printf(sc->dev, "ALART: ERROR\n"); 493 else { 494 addr = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); 495 device_printf(sc->dev, "ALART_RESPONSE: 0x%x\n", addr); 496 } 497 498 /* Re-enable INTR from ALART. */ 499 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 500 slvcnt | PIIX4_SMBSLVCNT_ALTEN); 501 DELAY(5); 502 #endif 503 } 504 505 static void 506 intsmb_start(struct intsmb_softc *sc, unsigned char cmd, int nointr) 507 { 508 unsigned char tmp; 509 510 INTSMB_LOCK_ASSERT(sc); 511 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); 512 tmp &= 0xe0; 513 tmp |= cmd; 514 tmp |= PIIX4_SMBHSTCNT_START; 515 516 /* While not in autoconfiguration enable interrupts. */ 517 if (!sc->poll && !cold && !nointr) 518 tmp |= PIIX4_SMBHSTCNT_INTREN; 519 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp); 520 } 521 522 static int 523 intsmb_error(device_t dev, int status) 524 { 525 int error = 0; 526 527 /* 528 * PIIX4_SMBHSTSTAT_ERR can mean either of 529 * - SMB_ENOACK ("Unclaimed cycle"), 530 * - SMB_ETIMEOUT ("Host device time-out"), 531 * - SMB_EINVAL ("Illegal command field"). 532 * SMB_ENOACK seems to be most typical. 533 */ 534 if (status & PIIX4_SMBHSTSTAT_ERR) 535 error |= SMB_ENOACK; 536 if (status & PIIX4_SMBHSTSTAT_BUSC) 537 error |= SMB_ECOLLI; 538 if (status & PIIX4_SMBHSTSTAT_FAIL) 539 error |= SMB_EABORT; 540 541 if (error != 0 && bootverbose) 542 device_printf(dev, "error = %d, status = %#x\n", error, status); 543 544 return (error); 545 } 546 547 /* 548 * Polling Code. 549 * 550 * Polling is not encouraged because it requires waiting for the 551 * device if it is busy. 552 * (29063505.pdf from Intel) But during boot, interrupt cannot be used, so use 553 * polling code then. 554 */ 555 static int 556 intsmb_stop_poll(struct intsmb_softc *sc) 557 { 558 int error, i, status, tmp; 559 560 INTSMB_LOCK_ASSERT(sc); 561 562 /* First, wait for busy to be set. */ 563 for (i = 0; i < 0x7fff; i++) 564 if (bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & 565 PIIX4_SMBHSTSTAT_BUSY) 566 break; 567 568 /* Wait for busy to clear. */ 569 for (i = 0; i < 0x7fff; i++) { 570 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS); 571 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) { 572 sc->isbusy = 0; 573 error = intsmb_error(sc->dev, status); 574 return (error); 575 } 576 } 577 578 /* Timed out waiting for busy to clear. */ 579 sc->isbusy = 0; 580 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); 581 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN); 582 return (SMB_ETIMEOUT); 583 } 584 585 /* 586 * Wait for completion and return result. 587 */ 588 static int 589 intsmb_stop(struct intsmb_softc *sc) 590 { 591 int error, status; 592 593 INTSMB_LOCK_ASSERT(sc); 594 595 if (sc->poll || cold) 596 /* So that it can use device during device probe on SMBus. */ 597 return (intsmb_stop_poll(sc)); 598 599 error = msleep(sc, &sc->lock, PWAIT | PCATCH, "SMBWAI", hz / 8); 600 if (error == 0) { 601 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS); 602 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) { 603 error = intsmb_error(sc->dev, status); 604 if (error == 0 && !(status & PIIX4_SMBHSTSTAT_INTR)) 605 device_printf(sc->dev, "unknown cause why?\n"); 606 #ifdef ENABLE_ALART 607 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 608 PIIX4_SMBSLVCNT_ALTEN); 609 #endif 610 return (error); 611 } 612 } 613 614 /* Timeout Procedure. */ 615 sc->isbusy = 0; 616 617 /* Re-enable suppressed interrupt from slave part. */ 618 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN); 619 if (error == EWOULDBLOCK) 620 return (SMB_ETIMEOUT); 621 else 622 return (SMB_EABORT); 623 } 624 625 static int 626 intsmb_quick(device_t dev, u_char slave, int how) 627 { 628 struct intsmb_softc *sc = device_get_softc(dev); 629 int error; 630 u_char data; 631 632 data = slave; 633 634 /* Quick command is part of Address, I think. */ 635 switch(how) { 636 case SMB_QWRITE: 637 data &= ~LSB; 638 break; 639 case SMB_QREAD: 640 data |= LSB; 641 break; 642 default: 643 return (SMB_EINVAL); 644 } 645 646 INTSMB_LOCK(sc); 647 error = intsmb_free(sc); 648 if (error) { 649 INTSMB_UNLOCK(sc); 650 return (error); 651 } 652 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, data); 653 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_QUICK, 0); 654 error = intsmb_stop(sc); 655 INTSMB_UNLOCK(sc); 656 return (error); 657 } 658 659 static int 660 intsmb_sendb(device_t dev, u_char slave, char byte) 661 { 662 struct intsmb_softc *sc = device_get_softc(dev); 663 int error; 664 665 INTSMB_LOCK(sc); 666 error = intsmb_free(sc); 667 if (error) { 668 INTSMB_UNLOCK(sc); 669 return (error); 670 } 671 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); 672 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, byte); 673 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0); 674 error = intsmb_stop(sc); 675 INTSMB_UNLOCK(sc); 676 return (error); 677 } 678 679 static int 680 intsmb_recvb(device_t dev, u_char slave, char *byte) 681 { 682 struct intsmb_softc *sc = device_get_softc(dev); 683 int error; 684 685 INTSMB_LOCK(sc); 686 error = intsmb_free(sc); 687 if (error) { 688 INTSMB_UNLOCK(sc); 689 return (error); 690 } 691 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB); 692 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0); 693 error = intsmb_stop(sc); 694 if (error == 0) { 695 #ifdef RECV_IS_IN_CMD 696 /* 697 * Linux SMBus stuff also troubles 698 * Because Intel's datasheet does not make clear. 699 */ 700 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTCMD); 701 #else 702 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); 703 #endif 704 } 705 INTSMB_UNLOCK(sc); 706 return (error); 707 } 708 709 static int 710 intsmb_writeb(device_t dev, u_char slave, char cmd, char byte) 711 { 712 struct intsmb_softc *sc = device_get_softc(dev); 713 int error; 714 715 INTSMB_LOCK(sc); 716 error = intsmb_free(sc); 717 if (error) { 718 INTSMB_UNLOCK(sc); 719 return (error); 720 } 721 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); 722 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); 723 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, byte); 724 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0); 725 error = intsmb_stop(sc); 726 INTSMB_UNLOCK(sc); 727 return (error); 728 } 729 730 static int 731 intsmb_writew(device_t dev, u_char slave, char cmd, short word) 732 { 733 struct intsmb_softc *sc = device_get_softc(dev); 734 int error; 735 736 INTSMB_LOCK(sc); 737 error = intsmb_free(sc); 738 if (error) { 739 INTSMB_UNLOCK(sc); 740 return (error); 741 } 742 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); 743 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); 744 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, word & 0xff); 745 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (word >> 8) & 0xff); 746 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0); 747 error = intsmb_stop(sc); 748 INTSMB_UNLOCK(sc); 749 return (error); 750 } 751 752 static int 753 intsmb_readb(device_t dev, u_char slave, char cmd, char *byte) 754 { 755 struct intsmb_softc *sc = device_get_softc(dev); 756 int error; 757 758 INTSMB_LOCK(sc); 759 error = intsmb_free(sc); 760 if (error) { 761 INTSMB_UNLOCK(sc); 762 return (error); 763 } 764 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB); 765 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); 766 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0); 767 error = intsmb_stop(sc); 768 if (error == 0) 769 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); 770 INTSMB_UNLOCK(sc); 771 return (error); 772 } 773 774 static int 775 intsmb_readw(device_t dev, u_char slave, char cmd, short *word) 776 { 777 struct intsmb_softc *sc = device_get_softc(dev); 778 int error; 779 780 INTSMB_LOCK(sc); 781 error = intsmb_free(sc); 782 if (error) { 783 INTSMB_UNLOCK(sc); 784 return (error); 785 } 786 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB); 787 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); 788 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0); 789 error = intsmb_stop(sc); 790 if (error == 0) { 791 *word = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); 792 *word |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8; 793 } 794 INTSMB_UNLOCK(sc); 795 return (error); 796 } 797 798 static int 799 intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata) 800 { 801 802 return (SMB_ENOTSUPP); 803 } 804 805 static int 806 intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf) 807 { 808 struct intsmb_softc *sc = device_get_softc(dev); 809 int error, i; 810 811 if (count > SMBBLOCKTRANS_MAX || count == 0) 812 return (SMB_EINVAL); 813 814 INTSMB_LOCK(sc); 815 error = intsmb_free(sc); 816 if (error) { 817 INTSMB_UNLOCK(sc); 818 return (error); 819 } 820 821 /* Reset internal array index. */ 822 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); 823 824 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB); 825 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); 826 for (i = 0; i < count; i++) 827 bus_write_1(sc->io_res, PIIX4_SMBBLKDAT, buf[i]); 828 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, count); 829 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0); 830 error = intsmb_stop(sc); 831 INTSMB_UNLOCK(sc); 832 return (error); 833 } 834 835 static int 836 intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf) 837 { 838 struct intsmb_softc *sc = device_get_softc(dev); 839 int error, i; 840 u_char nread; 841 842 INTSMB_LOCK(sc); 843 error = intsmb_free(sc); 844 if (error) { 845 INTSMB_UNLOCK(sc); 846 return (error); 847 } 848 849 /* Reset internal array index. */ 850 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT); 851 852 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB); 853 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd); 854 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0); 855 error = intsmb_stop(sc); 856 if (error == 0) { 857 nread = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0); 858 if (nread != 0 && nread <= SMBBLOCKTRANS_MAX) { 859 *count = nread; 860 for (i = 0; i < nread; i++) 861 bus_read_1(sc->io_res, PIIX4_SMBBLKDAT); 862 } else 863 error = SMB_EBUSERR; 864 } 865 INTSMB_UNLOCK(sc); 866 return (error); 867 } 868 869 static device_method_t intsmb_methods[] = { 870 /* Device interface */ 871 DEVMETHOD(device_probe, intsmb_probe), 872 DEVMETHOD(device_attach, intsmb_attach), 873 DEVMETHOD(device_detach, intsmb_detach), 874 875 /* SMBus interface */ 876 DEVMETHOD(smbus_callback, intsmb_callback), 877 DEVMETHOD(smbus_quick, intsmb_quick), 878 DEVMETHOD(smbus_sendb, intsmb_sendb), 879 DEVMETHOD(smbus_recvb, intsmb_recvb), 880 DEVMETHOD(smbus_writeb, intsmb_writeb), 881 DEVMETHOD(smbus_writew, intsmb_writew), 882 DEVMETHOD(smbus_readb, intsmb_readb), 883 DEVMETHOD(smbus_readw, intsmb_readw), 884 DEVMETHOD(smbus_pcall, intsmb_pcall), 885 DEVMETHOD(smbus_bwrite, intsmb_bwrite), 886 DEVMETHOD(smbus_bread, intsmb_bread), 887 888 DEVMETHOD_END 889 }; 890 891 static driver_t intsmb_driver = { 892 "intsmb", 893 intsmb_methods, 894 sizeof(struct intsmb_softc), 895 }; 896 897 DRIVER_MODULE_ORDERED(intsmb, pci, intsmb_driver, 0, 0, SI_ORDER_ANY); 898 DRIVER_MODULE(smbus, intsmb, smbus_driver, 0, 0); 899 MODULE_DEPEND(intsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); 900 MODULE_VERSION(intsmb, 1); 901 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, intpm, intsmb_products, 902 nitems(intsmb_products)); 903