1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Oleksandr Tymoshenko <gonzo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _DEV_INTEL_SPI_H_ 30 #define _DEV_INTEL_SPI_H_ 31 32 #include <contrib/dev/acpica/include/acpi.h> 33 #include <contrib/dev/acpica/include/accommon.h> 34 35 #include <dev/acpica/acpivar.h> 36 37 enum intelspi_vers { 38 SPI_BAYTRAIL, 39 SPI_BRASWELL, 40 SPI_LYNXPOINT, 41 SPI_SUNRISEPOINT, 42 }; 43 44 /* Same order as intelspi_vers */ 45 static const struct intelspi_info { 46 const char *desc; 47 uint32_t reg_lpss_base; 48 uint32_t reg_cs_ctrl; 49 } intelspi_infos[] = { 50 [SPI_BAYTRAIL] = { 51 .desc = "Intel Bay Trail SPI Controller", 52 .reg_lpss_base = 0x400, 53 .reg_cs_ctrl = 0x18, 54 }, 55 [SPI_BRASWELL] = { 56 .desc = "Intel Braswell SPI Controller", 57 .reg_lpss_base = 0x400, 58 .reg_cs_ctrl = 0x18, 59 }, 60 [SPI_LYNXPOINT] = { 61 .desc = "Intel Lynx Point / Wildcat Point SPI Controller", 62 .reg_lpss_base = 0x800, 63 .reg_cs_ctrl = 0x18, 64 }, 65 [SPI_SUNRISEPOINT] = { 66 .desc = "Intel Sunrise Point SPI Controller", 67 .reg_lpss_base = 0x200, 68 .reg_cs_ctrl = 0x24, 69 }, 70 }; 71 72 struct intelspi_softc { 73 ACPI_HANDLE sc_handle; 74 device_t sc_dev; 75 enum intelspi_vers sc_vers; 76 struct mtx sc_mtx; 77 int sc_mem_rid; 78 struct resource *sc_mem_res; 79 int sc_irq_rid; 80 struct resource *sc_irq_res; 81 void *sc_irq_ih; 82 struct spi_command *sc_cmd; 83 uint32_t sc_len; 84 uint32_t sc_read; 85 uint32_t sc_flags; 86 uint32_t sc_written; 87 uint32_t sc_clock; 88 uint32_t sc_mode; 89 /* LPSS private register storage for suspend-resume */ 90 uint32_t sc_regs[9]; 91 }; 92 93 int intelspi_attach(device_t dev); 94 int intelspi_detach(device_t dev); 95 int intelspi_transfer(device_t dev, device_t child, struct spi_command *cmd); 96 int intelspi_suspend(device_t dev); 97 int intelspi_resume(device_t dev); 98 99 #endif 100