xref: /freebsd/sys/dev/intel/spi.h (revision 1f40866feb2135a4cf764a07b1b90a8a3398ff0a)
1*1f40866fSVal Packett /*-
2*1f40866fSVal Packett  * SPDX-License-Identifier: BSD-2-Clause
3*1f40866fSVal Packett  *
4*1f40866fSVal Packett  * Copyright (c) 2016 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5*1f40866fSVal Packett  * All rights reserved.
6*1f40866fSVal Packett  *
7*1f40866fSVal Packett  * Redistribution and use in source and binary forms, with or without
8*1f40866fSVal Packett  * modification, are permitted provided that the following conditions
9*1f40866fSVal Packett  * are met:
10*1f40866fSVal Packett  * 1. Redistributions of source code must retain the above copyright
11*1f40866fSVal Packett  *    notice, this list of conditions and the following disclaimer.
12*1f40866fSVal Packett  * 2. Redistributions in binary form must reproduce the above copyright
13*1f40866fSVal Packett  *    notice, this list of conditions and the following disclaimer in the
14*1f40866fSVal Packett  *    documentation and/or other materials provided with the distribution.
15*1f40866fSVal Packett  *
16*1f40866fSVal Packett  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17*1f40866fSVal Packett  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18*1f40866fSVal Packett  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19*1f40866fSVal Packett  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20*1f40866fSVal Packett  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21*1f40866fSVal Packett  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22*1f40866fSVal Packett  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23*1f40866fSVal Packett  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24*1f40866fSVal Packett  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25*1f40866fSVal Packett  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26*1f40866fSVal Packett  * SUCH DAMAGE.
27*1f40866fSVal Packett  */
28*1f40866fSVal Packett 
29*1f40866fSVal Packett #ifndef _DEV_INTEL_SPI_H_
30*1f40866fSVal Packett #define _DEV_INTEL_SPI_H_
31*1f40866fSVal Packett 
32*1f40866fSVal Packett #include <contrib/dev/acpica/include/acpi.h>
33*1f40866fSVal Packett #include <contrib/dev/acpica/include/accommon.h>
34*1f40866fSVal Packett 
35*1f40866fSVal Packett #include <dev/acpica/acpivar.h>
36*1f40866fSVal Packett 
37*1f40866fSVal Packett enum intelspi_vers {
38*1f40866fSVal Packett 	SPI_BAYTRAIL,
39*1f40866fSVal Packett 	SPI_BRASWELL,
40*1f40866fSVal Packett 	SPI_LYNXPOINT,
41*1f40866fSVal Packett 	SPI_SUNRISEPOINT,
42*1f40866fSVal Packett };
43*1f40866fSVal Packett 
44*1f40866fSVal Packett /* Same order as intelspi_vers */
45*1f40866fSVal Packett static const struct intelspi_info {
46*1f40866fSVal Packett 	const char *desc;
47*1f40866fSVal Packett 	uint32_t reg_lpss_base;
48*1f40866fSVal Packett 	uint32_t reg_cs_ctrl;
49*1f40866fSVal Packett } intelspi_infos[] = {
50*1f40866fSVal Packett 	[SPI_BAYTRAIL] = {
51*1f40866fSVal Packett 		.desc = "Intel Bay Trail SPI Controller",
52*1f40866fSVal Packett 		.reg_lpss_base = 0x400,
53*1f40866fSVal Packett 		.reg_cs_ctrl = 0x18,
54*1f40866fSVal Packett 	},
55*1f40866fSVal Packett 	[SPI_BRASWELL] = {
56*1f40866fSVal Packett 		.desc = "Intel Braswell SPI Controller",
57*1f40866fSVal Packett 		.reg_lpss_base = 0x400,
58*1f40866fSVal Packett 		.reg_cs_ctrl = 0x18,
59*1f40866fSVal Packett 	},
60*1f40866fSVal Packett 	[SPI_LYNXPOINT] = {
61*1f40866fSVal Packett 		.desc = "Intel Lynx Point / Wildcat Point SPI Controller",
62*1f40866fSVal Packett 		.reg_lpss_base = 0x800,
63*1f40866fSVal Packett 		.reg_cs_ctrl = 0x18,
64*1f40866fSVal Packett 	},
65*1f40866fSVal Packett 	[SPI_SUNRISEPOINT] = {
66*1f40866fSVal Packett 		.desc = "Intel Sunrise Point SPI Controller",
67*1f40866fSVal Packett 		.reg_lpss_base = 0x200,
68*1f40866fSVal Packett 		.reg_cs_ctrl = 0x24,
69*1f40866fSVal Packett 	},
70*1f40866fSVal Packett };
71*1f40866fSVal Packett 
72*1f40866fSVal Packett struct intelspi_softc {
73*1f40866fSVal Packett 	ACPI_HANDLE		sc_handle;
74*1f40866fSVal Packett 	device_t		sc_dev;
75*1f40866fSVal Packett 	enum intelspi_vers sc_vers;
76*1f40866fSVal Packett 	struct mtx		sc_mtx;
77*1f40866fSVal Packett 	int			sc_mem_rid;
78*1f40866fSVal Packett 	struct resource		*sc_mem_res;
79*1f40866fSVal Packett 	int			sc_irq_rid;
80*1f40866fSVal Packett 	struct resource		*sc_irq_res;
81*1f40866fSVal Packett 	void			*sc_irq_ih;
82*1f40866fSVal Packett 	struct spi_command	*sc_cmd;
83*1f40866fSVal Packett 	uint32_t		sc_len;
84*1f40866fSVal Packett 	uint32_t		sc_read;
85*1f40866fSVal Packett 	uint32_t		sc_flags;
86*1f40866fSVal Packett 	uint32_t		sc_written;
87*1f40866fSVal Packett 	uint32_t		sc_clock;
88*1f40866fSVal Packett 	uint32_t		sc_mode;
89*1f40866fSVal Packett 	/* LPSS private register storage for suspend-resume */
90*1f40866fSVal Packett 	uint32_t		sc_regs[9];
91*1f40866fSVal Packett };
92*1f40866fSVal Packett 
93*1f40866fSVal Packett int	intelspi_attach(device_t dev);
94*1f40866fSVal Packett int	intelspi_detach(device_t dev);
95*1f40866fSVal Packett int	intelspi_transfer(device_t dev, device_t child, struct spi_command *cmd);
96*1f40866fSVal Packett int	intelspi_suspend(device_t dev);
97*1f40866fSVal Packett int	intelspi_resume(device_t dev);
98*1f40866fSVal Packett 
99*1f40866fSVal Packett #endif
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