124f93aa0SRavi Pokala /*- 2*4d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 324f93aa0SRavi Pokala * 424f93aa0SRavi Pokala * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org) 524f93aa0SRavi Pokala * 624f93aa0SRavi Pokala * Copyright (c) 2017-2018 Panasas 724f93aa0SRavi Pokala * 824f93aa0SRavi Pokala * Redistribution and use in source and binary forms, with or without 924f93aa0SRavi Pokala * modification, are permitted provided that the following conditions 1024f93aa0SRavi Pokala * are met: 1124f93aa0SRavi Pokala * 1. Redistributions of source code must retain the above copyright 1224f93aa0SRavi Pokala * notice, this list of conditions and the following disclaimer. 1324f93aa0SRavi Pokala * 2. Redistributions in binary form must reproduce the above copyright 1424f93aa0SRavi Pokala * notice, this list of conditions and the following disclaimer in the 1524f93aa0SRavi Pokala * documentation and/or other materials provided with the distribution. 1624f93aa0SRavi Pokala * 1724f93aa0SRavi Pokala * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1824f93aa0SRavi Pokala * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1924f93aa0SRavi Pokala * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2024f93aa0SRavi Pokala * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2124f93aa0SRavi Pokala * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2224f93aa0SRavi Pokala * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2324f93aa0SRavi Pokala * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2424f93aa0SRavi Pokala * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2524f93aa0SRavi Pokala * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2624f93aa0SRavi Pokala * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2724f93aa0SRavi Pokala * SUCH DAMAGE. 2824f93aa0SRavi Pokala */ 2924f93aa0SRavi Pokala 3024f93aa0SRavi Pokala #ifndef _DEV__IMCSMB__IMCSMB_REG_H_ 3124f93aa0SRavi Pokala #define _DEV__IMCSMB__IMCSMB_REG_H_ 3224f93aa0SRavi Pokala 3324f93aa0SRavi Pokala #include <sys/param.h> 3424f93aa0SRavi Pokala #include <sys/systm.h> 3524f93aa0SRavi Pokala #include <sys/kernel.h> 3624f93aa0SRavi Pokala #include <sys/module.h> 3724f93aa0SRavi Pokala #include <sys/endian.h> 3824f93aa0SRavi Pokala #include <sys/errno.h> 3924f93aa0SRavi Pokala #include <sys/lock.h> 4024f93aa0SRavi Pokala #include <sys/mutex.h> 4124f93aa0SRavi Pokala #include <sys/syslog.h> 4224f93aa0SRavi Pokala #include <sys/bus.h> 4324f93aa0SRavi Pokala 4424f93aa0SRavi Pokala #include <machine/bus.h> 4524f93aa0SRavi Pokala #include <machine/atomic.h> 4624f93aa0SRavi Pokala 4724f93aa0SRavi Pokala #include <dev/pci/pcivar.h> 4824f93aa0SRavi Pokala #include <dev/pci/pcireg.h> 4924f93aa0SRavi Pokala 5024f93aa0SRavi Pokala #include <dev/smbus/smbconf.h> 5124f93aa0SRavi Pokala 5224f93aa0SRavi Pokala /* Intel (Sandy,Ivy)bridge and (Has,Broad)well CPUs have integrated memory 5324f93aa0SRavi Pokala * controllers (iMCs), each of which having up to two SMBus controllers. They 5424f93aa0SRavi Pokala * are programmed via sets of registers in the same PCI device, which are 5524f93aa0SRavi Pokala * identical other than the register numbers. 5624f93aa0SRavi Pokala * 5724f93aa0SRavi Pokala * The full documentation for these registers can be found in volume two of the 5824f93aa0SRavi Pokala * datasheets for the CPUs. Refer to the links in imcsmb_pci.c 5924f93aa0SRavi Pokala */ 6024f93aa0SRavi Pokala 6124f93aa0SRavi Pokala #define IMCSMB_REG_STATUS0 0x0180 6224f93aa0SRavi Pokala #define IMCSMB_REG_STATUS1 0x0190 6324f93aa0SRavi Pokala #define IMCSMB_STATUS_BUSY_BIT 0x10000000 6424f93aa0SRavi Pokala #define IMCSMB_STATUS_BUS_ERROR_BIT 0x20000000 6524f93aa0SRavi Pokala #define IMCSMB_STATUS_WRITE_DATA_DONE 0x40000000 6624f93aa0SRavi Pokala #define IMCSMB_STATUS_READ_DATA_VALID 0x80000000 6724f93aa0SRavi Pokala 6824f93aa0SRavi Pokala #define IMCSMB_REG_COMMAND0 0x0184 6924f93aa0SRavi Pokala #define IMCSMB_REG_COMMAND1 0x0194 7024f93aa0SRavi Pokala #define IMCSMB_CMD_WORD_ACCESS 0x20000000 7124f93aa0SRavi Pokala #define IMCSMB_CMD_WRITE_BIT 0x08000000 7224f93aa0SRavi Pokala #define IMCSMB_CMD_TRIGGER_BIT 0x80000000 7324f93aa0SRavi Pokala 7424f93aa0SRavi Pokala #define IMCSMB_REG_CONTROL0 0x0188 7524f93aa0SRavi Pokala #define IMCSMB_REG_CONTROL1 0x0198 7624f93aa0SRavi Pokala #define IMCSMB_CNTL_POLL_EN 0x00000100 7724f93aa0SRavi Pokala #define IMCSMB_CNTL_CLK_OVERRIDE 0x08000000 7824f93aa0SRavi Pokala #define IMCSMB_CNTL_DTI_MASK 0xf0000000 7924f93aa0SRavi Pokala #define IMCSMB_CNTL_WRITE_DISABLE_BIT 0x04000000 8024f93aa0SRavi Pokala 8124f93aa0SRavi Pokala #endif /* _DEV__IMCSMB__IMCSMB_REG_H_ */ 8224f93aa0SRavi Pokala 8324f93aa0SRavi Pokala /* vi: set ts=8 sw=4 sts=8 noet: */ 84