1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org) 5 * 6 * Copyright (c) 2017-2018 Panasas 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/endian.h> 35 #include <sys/errno.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/syslog.h> 39 #include <sys/bus.h> 40 41 #include <machine/bus.h> 42 #include <machine/atomic.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 47 #include <dev/smbus/smbconf.h> 48 49 #include "imcsmb_reg.h" 50 #include "imcsmb_var.h" 51 52 /* (Sandy,Ivy)bridge-Xeon and (Has,Broad)well-Xeon CPUs contain one or two 53 * "Integrated Memory Controllers" (iMCs), and each iMC contains two separate 54 * SMBus controllers. These are used for reading SPD data from the DIMMs, and 55 * for reading the "Thermal Sensor on DIMM" (TSODs). The iMC SMBus controllers 56 * are very simple devices, and have limited functionality compared to 57 * full-fledged SMBus controllers, like the one in Intel ICHs and PCHs. 58 * 59 * The publicly available documentation for the iMC SMBus controllers can be 60 * found in the CPU datasheets for (Sandy,Ivy)bridge-Xeon and 61 * (Has,broad)well-Xeon, respectively: 62 * 63 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/ 64 * Sandybridge xeon-e5-1600-2600-vol-2-datasheet.pdf 65 * Ivybridge xeon-e5-v2-datasheet-vol-2.pdf 66 * Haswell xeon-e5-v3-datasheet-vol-2.pdf 67 * Broadwell xeon-e5-v4-datasheet-vol-2.pdf 68 * 69 * Another useful resource is the Linux driver. It is not in the main tree. 70 * 71 * https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg840043.html 72 * 73 * The iMC SMBus controllers do not support interrupts (thus, they must be 74 * polled for IO completion). All of the iMC registers are in PCI configuration 75 * space; there is no support for PIO or MMIO. As a result, this driver does 76 * not need to perform and newbus resource manipulation. 77 * 78 * Because there are multiple SMBus controllers sharing the same PCI device, 79 * this driver is actually *two* drivers: 80 * 81 * - "imcsmb" is an smbus(4)-compliant SMBus controller driver 82 * 83 * - "imcsmb_pci" recognizes the PCI device and assigns the appropriate set of 84 * PCI config registers to a specific "imcsmb" instance. 85 */ 86 87 /* Depending on the motherboard and firmware, the TSODs might be polled by 88 * firmware. Therefore, when this driver accesses these SMBus controllers, the 89 * firmware polling must be disabled as part of requesting the bus, and 90 * re-enabled when releasing the bus. Unfortunately, the details of how to do 91 * this are vendor-specific. Contact your motherboard vendor to get the 92 * information you need to do proper implementations. 93 * 94 * For NVDIMMs which conform to the ACPI "NFIT" standard, the ACPI firmware 95 * manages the NVDIMM; for those which pre-date the standard, the operating 96 * system interacts with the NVDIMM controller using a vendor-proprietary API 97 * over the SMBus. In that case, the NVDIMM driver would be an SMBus slave 98 * device driver, and would interface with the hardware via an SMBus controller 99 * driver such as this one. 100 */ 101 102 /* PCIe device IDs for (Sandy,Ivy)bridge)-Xeon and (Has,Broad)well-Xeon */ 103 #define PCI_VENDOR_INTEL 0x8086 104 #define IMCSMB_PCI_DEV_ID_IMC0_SBX 0x3ca8 105 #define IMCSMB_PCI_DEV_ID_IMC0_IBX 0x0ea8 106 #define IMCSMB_PCI_DEV_ID_IMC0_HSX 0x2fa8 107 #define IMCSMB_PCI_DEV_ID_IMC0_BDX 0x6fa8 108 /* (Sandy,Ivy)bridge-Xeon only have a single memory controller per socket */ 109 #define IMCSMB_PCI_DEV_ID_IMC1_HSX 0x2f68 110 #define IMCSMB_PCI_DEV_ID_IMC1_BDX 0x6f68 111 112 /* There are two SMBus controllers in each device. These define the registers 113 * for each of these devices. 114 */ 115 static struct imcsmb_reg_set imcsmb_regs[] = { 116 { 117 .smb_stat = IMCSMB_REG_STATUS0, 118 .smb_cmd = IMCSMB_REG_COMMAND0, 119 .smb_cntl = IMCSMB_REG_CONTROL0 120 }, 121 { 122 .smb_stat = IMCSMB_REG_STATUS1, 123 .smb_cmd = IMCSMB_REG_COMMAND1, 124 .smb_cntl = IMCSMB_REG_CONTROL1 125 }, 126 }; 127 128 static struct imcsmb_pci_device { 129 uint16_t id; 130 char *name; 131 } imcsmb_pci_devices[] = { 132 {IMCSMB_PCI_DEV_ID_IMC0_SBX, 133 "Intel Sandybridge Xeon iMC 0 SMBus controllers" }, 134 {IMCSMB_PCI_DEV_ID_IMC0_IBX, 135 "Intel Ivybridge Xeon iMC 0 SMBus controllers" }, 136 {IMCSMB_PCI_DEV_ID_IMC0_HSX, 137 "Intel Haswell Xeon iMC 0 SMBus controllers" }, 138 {IMCSMB_PCI_DEV_ID_IMC1_HSX, 139 "Intel Haswell Xeon iMC 1 SMBus controllers" }, 140 {IMCSMB_PCI_DEV_ID_IMC0_BDX, 141 "Intel Broadwell Xeon iMC 0 SMBus controllers" }, 142 {IMCSMB_PCI_DEV_ID_IMC1_BDX, 143 "Intel Broadwell Xeon iMC 1 SMBus controllers" }, 144 {0, NULL}, 145 }; 146 147 /* Device methods. */ 148 static int imcsmb_pci_attach(device_t dev); 149 static int imcsmb_pci_probe(device_t dev); 150 151 /** 152 * device_attach() method. Set up the PCI device's softc, then explicitly create 153 * children for the actual imcsmbX controllers. Set up the child's ivars to 154 * point to the proper set of the PCI device's config registers. 155 * 156 * @author Joe Kloss, rpokala 157 * 158 * @param[in,out] dev 159 * Device being attached. 160 */ 161 static int 162 imcsmb_pci_attach(device_t dev) 163 { 164 struct imcsmb_pci_softc *sc; 165 device_t child; 166 int rc; 167 int unit; 168 169 /* Initialize private state */ 170 sc = device_get_softc(dev); 171 sc->dev = dev; 172 sc->semaphore = 0; 173 174 /* Create the imcsmbX children */ 175 for (unit = 0; unit < 2; unit++) { 176 child = device_add_child(dev, "imcsmb", DEVICE_UNIT_ANY); 177 if (child == NULL) { 178 /* Nothing has been allocated, so there's no cleanup. */ 179 device_printf(dev, "Child imcsmb not added\n"); 180 rc = ENXIO; 181 goto out; 182 } 183 /* Set the child's ivars to point to the appropriate set of 184 * the PCI device's registers. 185 */ 186 device_set_ivars(child, &imcsmb_regs[unit]); 187 } 188 189 /* Attach the imcsmbX children. */ 190 bus_attach_children(dev); 191 rc = 0; 192 193 out: 194 return (rc); 195 } 196 197 /** 198 * device_probe() method. Look for the right PCI vendor/device IDs. 199 * 200 * @author Joe Kloss, rpokala 201 * 202 * @param[in,out] dev 203 * Device being probed. 204 */ 205 static int 206 imcsmb_pci_probe(device_t dev) 207 { 208 struct imcsmb_pci_device *pci_device; 209 int rc; 210 uint16_t pci_dev_id; 211 212 rc = ENXIO; 213 214 if (pci_get_vendor(dev) != PCI_VENDOR_INTEL) { 215 goto out; 216 } 217 218 pci_dev_id = pci_get_device(dev); 219 for (pci_device = imcsmb_pci_devices; 220 pci_device->name != NULL; 221 pci_device++) { 222 if (pci_dev_id == pci_device->id) { 223 device_set_desc(dev, pci_device->name); 224 rc = BUS_PROBE_DEFAULT; 225 goto out; 226 } 227 } 228 229 out: 230 return (rc); 231 } 232 233 /** 234 * Invoked via smbus_callback() -> imcsmb_callback(); clear the semaphore, and 235 * re-enable motherboard-specific DIMM temperature monitoring if needed. This 236 * gets called after the transaction completes. 237 * 238 * @author Joe Kloss 239 * 240 * @param[in,out] dev 241 * The device whose busses to release. 242 */ 243 void 244 imcsmb_pci_release_bus(device_t dev) 245 { 246 struct imcsmb_pci_softc *sc; 247 248 sc = device_get_softc(dev); 249 250 /* 251 * IF NEEDED, INSERT MOTHERBOARD-SPECIFIC CODE TO RE-ENABLE DIMM 252 * TEMPERATURE MONITORING HERE. 253 */ 254 255 atomic_store_rel_int(&sc->semaphore, 0); 256 } 257 258 /** 259 * Invoked via smbus_callback() -> imcsmb_callback(); set the semaphore, and 260 * disable motherboard-specific DIMM temperature monitoring if needed. This gets 261 * called before the transaction starts. 262 * 263 * @author Joe Kloss 264 * 265 * @param[in,out] dev 266 * The device whose busses to request. 267 */ 268 int 269 imcsmb_pci_request_bus(device_t dev) 270 { 271 struct imcsmb_pci_softc *sc; 272 int rc; 273 274 sc = device_get_softc(dev); 275 rc = 0; 276 277 /* We don't want to block. Use a simple test-and-set semaphore to 278 * protect the bus. 279 */ 280 if (atomic_cmpset_acq_int(&sc->semaphore, 0, 1) == 0) { 281 rc = EWOULDBLOCK; 282 } 283 284 /* 285 * IF NEEDED, INSERT MOTHERBOARD-SPECIFIC CODE TO DISABLE DIMM 286 * TEMPERATURE MONITORING HERE. 287 */ 288 289 return (rc); 290 } 291 292 /* Device methods */ 293 static device_method_t imcsmb_pci_methods[] = { 294 /* Device interface */ 295 DEVMETHOD(device_attach, imcsmb_pci_attach), 296 DEVMETHOD(device_detach, bus_generic_detach), 297 DEVMETHOD(device_probe, imcsmb_pci_probe), 298 299 DEVMETHOD_END 300 }; 301 302 static driver_t imcsmb_pci_driver = { 303 .name = "imcsmb_pci", 304 .methods = imcsmb_pci_methods, 305 .size = sizeof(struct imcsmb_pci_softc), 306 }; 307 308 DRIVER_MODULE(imcsmb_pci, pci, imcsmb_pci_driver, 0, 0); 309 MODULE_DEPEND(imcsmb_pci, pci, 1, 1, 1); 310 MODULE_VERSION(imcsmb_pci, 1); 311 312 /* vi: set ts=8 sw=4 sts=8 noet: */ 313