1*24f93aa0SRavi Pokala /*- 2*24f93aa0SRavi Pokala * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3*24f93aa0SRavi Pokala * 4*24f93aa0SRavi Pokala * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org) 5*24f93aa0SRavi Pokala * 6*24f93aa0SRavi Pokala * Copyright (c) 2017-2018 Panasas 7*24f93aa0SRavi Pokala * All rights reserved. 8*24f93aa0SRavi Pokala * 9*24f93aa0SRavi Pokala * Redistribution and use in source and binary forms, with or without 10*24f93aa0SRavi Pokala * modification, are permitted provided that the following conditions 11*24f93aa0SRavi Pokala * are met: 12*24f93aa0SRavi Pokala * 1. Redistributions of source code must retain the above copyright 13*24f93aa0SRavi Pokala * notice, this list of conditions and the following disclaimer. 14*24f93aa0SRavi Pokala * 2. Redistributions in binary form must reproduce the above copyright 15*24f93aa0SRavi Pokala * notice, this list of conditions and the following disclaimer in the 16*24f93aa0SRavi Pokala * documentation and/or other materials provided with the distribution. 17*24f93aa0SRavi Pokala * 18*24f93aa0SRavi Pokala * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19*24f93aa0SRavi Pokala * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*24f93aa0SRavi Pokala * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*24f93aa0SRavi Pokala * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22*24f93aa0SRavi Pokala * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23*24f93aa0SRavi Pokala * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24*24f93aa0SRavi Pokala * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25*24f93aa0SRavi Pokala * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26*24f93aa0SRavi Pokala * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27*24f93aa0SRavi Pokala * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28*24f93aa0SRavi Pokala * SUCH DAMAGE. 29*24f93aa0SRavi Pokala * 30*24f93aa0SRavi Pokala * $FreeBSD$ 31*24f93aa0SRavi Pokala */ 32*24f93aa0SRavi Pokala 33*24f93aa0SRavi Pokala #include <sys/param.h> 34*24f93aa0SRavi Pokala #include <sys/systm.h> 35*24f93aa0SRavi Pokala #include <sys/kernel.h> 36*24f93aa0SRavi Pokala #include <sys/module.h> 37*24f93aa0SRavi Pokala #include <sys/endian.h> 38*24f93aa0SRavi Pokala #include <sys/errno.h> 39*24f93aa0SRavi Pokala #include <sys/lock.h> 40*24f93aa0SRavi Pokala #include <sys/mutex.h> 41*24f93aa0SRavi Pokala #include <sys/syslog.h> 42*24f93aa0SRavi Pokala #include <sys/bus.h> 43*24f93aa0SRavi Pokala 44*24f93aa0SRavi Pokala #include <machine/bus.h> 45*24f93aa0SRavi Pokala #include <machine/atomic.h> 46*24f93aa0SRavi Pokala 47*24f93aa0SRavi Pokala #include <dev/pci/pcivar.h> 48*24f93aa0SRavi Pokala #include <dev/pci/pcireg.h> 49*24f93aa0SRavi Pokala 50*24f93aa0SRavi Pokala #include <dev/smbus/smbconf.h> 51*24f93aa0SRavi Pokala 52*24f93aa0SRavi Pokala #include "imcsmb_reg.h" 53*24f93aa0SRavi Pokala #include "imcsmb_var.h" 54*24f93aa0SRavi Pokala 55*24f93aa0SRavi Pokala /* (Sandy,Ivy)bridge-Xeon and (Has,Broad)well-Xeon CPUs contain one or two 56*24f93aa0SRavi Pokala * "Integrated Memory Controllers" (iMCs), and each iMC contains two separate 57*24f93aa0SRavi Pokala * SMBus controllers. These are used for reading SPD data from the DIMMs, and 58*24f93aa0SRavi Pokala * for reading the "Thermal Sensor on DIMM" (TSODs). The iMC SMBus controllers 59*24f93aa0SRavi Pokala * are very simple devices, and have limited functionality compared to 60*24f93aa0SRavi Pokala * full-fledged SMBus controllers, like the one in Intel ICHs and PCHs. 61*24f93aa0SRavi Pokala * 62*24f93aa0SRavi Pokala * The publicly available documentation for the iMC SMBus controllers can be 63*24f93aa0SRavi Pokala * found in the CPU datasheets for (Sandy,Ivy)bridge-Xeon and 64*24f93aa0SRavi Pokala * (Has,broad)well-Xeon, respectively: 65*24f93aa0SRavi Pokala * 66*24f93aa0SRavi Pokala * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/ 67*24f93aa0SRavi Pokala * Sandybridge xeon-e5-1600-2600-vol-2-datasheet.pdf 68*24f93aa0SRavi Pokala * Ivybridge xeon-e5-v2-datasheet-vol-2.pdf 69*24f93aa0SRavi Pokala * Haswell xeon-e5-v3-datasheet-vol-2.pdf 70*24f93aa0SRavi Pokala * Broadwell xeon-e5-v4-datasheet-vol-2.pdf 71*24f93aa0SRavi Pokala * 72*24f93aa0SRavi Pokala * Another useful resource is the Linux driver. It is not in the main tree. 73*24f93aa0SRavi Pokala * 74*24f93aa0SRavi Pokala * https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg840043.html 75*24f93aa0SRavi Pokala * 76*24f93aa0SRavi Pokala * The iMC SMBus controllers do not support interrupts (thus, they must be 77*24f93aa0SRavi Pokala * polled for IO completion). All of the iMC registers are in PCI configuration 78*24f93aa0SRavi Pokala * space; there is no support for PIO or MMIO. As a result, this driver does 79*24f93aa0SRavi Pokala * not need to perform and newbus resource manipulation. 80*24f93aa0SRavi Pokala * 81*24f93aa0SRavi Pokala * Because there are multiple SMBus controllers sharing the same PCI device, 82*24f93aa0SRavi Pokala * this driver is actually *two* drivers: 83*24f93aa0SRavi Pokala * 84*24f93aa0SRavi Pokala * - "imcsmb" is an smbus(4)-compliant SMBus controller driver 85*24f93aa0SRavi Pokala * 86*24f93aa0SRavi Pokala * - "imcsmb_pci" recognizes the PCI device and assigns the appropriate set of 87*24f93aa0SRavi Pokala * PCI config registers to a specific "imcsmb" instance. 88*24f93aa0SRavi Pokala */ 89*24f93aa0SRavi Pokala 90*24f93aa0SRavi Pokala /* Depending on the motherboard and firmware, the TSODs might be polled by 91*24f93aa0SRavi Pokala * firmware. Therefore, when this driver accesses these SMBus controllers, the 92*24f93aa0SRavi Pokala * firmware polling must be disabled as part of requesting the bus, and 93*24f93aa0SRavi Pokala * re-enabled when releasing the bus. Unfortunately, the details of how to do 94*24f93aa0SRavi Pokala * this are vendor-specific. Contact your motherboard vendor to get the 95*24f93aa0SRavi Pokala * information you need to do proper implementations. 96*24f93aa0SRavi Pokala * 97*24f93aa0SRavi Pokala * For NVDIMMs which conform to the ACPI "NFIT" standard, the ACPI firmware 98*24f93aa0SRavi Pokala * manages the NVDIMM; for those which pre-date the standard, the operating 99*24f93aa0SRavi Pokala * system interacts with the NVDIMM controller using a vendor-proprietary API 100*24f93aa0SRavi Pokala * over the SMBus. In that case, the NVDIMM driver would be an SMBus slave 101*24f93aa0SRavi Pokala * device driver, and would interface with the hardware via an SMBus controller 102*24f93aa0SRavi Pokala * driver such as this one. 103*24f93aa0SRavi Pokala */ 104*24f93aa0SRavi Pokala 105*24f93aa0SRavi Pokala /* PCIe device IDs for (Sandy,Ivy)bridge)-Xeon and (Has,Broad)well-Xeon */ 106*24f93aa0SRavi Pokala #define PCI_VENDOR_INTEL 0x8086 107*24f93aa0SRavi Pokala #define IMCSMB_PCI_DEV_ID_IMC0_SBX 0x3ca8 108*24f93aa0SRavi Pokala #define IMCSMB_PCI_DEV_ID_IMC0_IBX 0x0ea8 109*24f93aa0SRavi Pokala #define IMCSMB_PCI_DEV_ID_IMC0_HSX 0x2fa8 110*24f93aa0SRavi Pokala #define IMCSMB_PCI_DEV_ID_IMC0_BDX 0x6fa8 111*24f93aa0SRavi Pokala /* (Sandy,Ivy)bridge-Xeon only have a single memory controller per socket */ 112*24f93aa0SRavi Pokala #define IMCSMB_PCI_DEV_ID_IMC1_HSX 0x2f68 113*24f93aa0SRavi Pokala #define IMCSMB_PCI_DEV_ID_IMC1_BDX 0x6f68 114*24f93aa0SRavi Pokala 115*24f93aa0SRavi Pokala /* There are two SMBus controllers in each device. These define the registers 116*24f93aa0SRavi Pokala * for each of these devices. 117*24f93aa0SRavi Pokala */ 118*24f93aa0SRavi Pokala static struct imcsmb_reg_set imcsmb_regs[] = { 119*24f93aa0SRavi Pokala { 120*24f93aa0SRavi Pokala .smb_stat = IMCSMB_REG_STATUS0, 121*24f93aa0SRavi Pokala .smb_cmd = IMCSMB_REG_COMMAND0, 122*24f93aa0SRavi Pokala .smb_cntl = IMCSMB_REG_CONTROL0 123*24f93aa0SRavi Pokala }, 124*24f93aa0SRavi Pokala { 125*24f93aa0SRavi Pokala .smb_stat = IMCSMB_REG_STATUS1, 126*24f93aa0SRavi Pokala .smb_cmd = IMCSMB_REG_COMMAND1, 127*24f93aa0SRavi Pokala .smb_cntl = IMCSMB_REG_CONTROL1 128*24f93aa0SRavi Pokala }, 129*24f93aa0SRavi Pokala }; 130*24f93aa0SRavi Pokala 131*24f93aa0SRavi Pokala static struct imcsmb_pci_device { 132*24f93aa0SRavi Pokala uint16_t id; 133*24f93aa0SRavi Pokala char *name; 134*24f93aa0SRavi Pokala } imcsmb_pci_devices[] = { 135*24f93aa0SRavi Pokala {IMCSMB_PCI_DEV_ID_IMC0_SBX, 136*24f93aa0SRavi Pokala "Intel Sandybridge Xeon iMC 0 SMBus controllers" }, 137*24f93aa0SRavi Pokala {IMCSMB_PCI_DEV_ID_IMC0_IBX, 138*24f93aa0SRavi Pokala "Intel Ivybridge Xeon iMC 0 SMBus controllers" }, 139*24f93aa0SRavi Pokala {IMCSMB_PCI_DEV_ID_IMC0_HSX, 140*24f93aa0SRavi Pokala "Intel Haswell Xeon iMC 0 SMBus controllers" }, 141*24f93aa0SRavi Pokala {IMCSMB_PCI_DEV_ID_IMC1_HSX, 142*24f93aa0SRavi Pokala "Intel Haswell Xeon iMC 1 SMBus controllers" }, 143*24f93aa0SRavi Pokala {IMCSMB_PCI_DEV_ID_IMC0_BDX, 144*24f93aa0SRavi Pokala "Intel Broadwell Xeon iMC 0 SMBus controllers" }, 145*24f93aa0SRavi Pokala {IMCSMB_PCI_DEV_ID_IMC1_BDX, 146*24f93aa0SRavi Pokala "Intel Broadwell Xeon iMC 1 SMBus controllers" }, 147*24f93aa0SRavi Pokala {0, NULL}, 148*24f93aa0SRavi Pokala }; 149*24f93aa0SRavi Pokala 150*24f93aa0SRavi Pokala /* Device methods. */ 151*24f93aa0SRavi Pokala static int imcsmb_pci_attach(device_t dev); 152*24f93aa0SRavi Pokala static int imcsmb_pci_detach(device_t dev); 153*24f93aa0SRavi Pokala static int imcsmb_pci_probe(device_t dev); 154*24f93aa0SRavi Pokala 155*24f93aa0SRavi Pokala /** 156*24f93aa0SRavi Pokala * device_attach() method. Set up the PCI device's softc, then explicitly create 157*24f93aa0SRavi Pokala * children for the actual imcsmbX controllers. Set up the child's ivars to 158*24f93aa0SRavi Pokala * point to the proper set of the PCI device's config registers. 159*24f93aa0SRavi Pokala * 160*24f93aa0SRavi Pokala * @author Joe Kloss, rpokala 161*24f93aa0SRavi Pokala * 162*24f93aa0SRavi Pokala * @param[in,out] dev 163*24f93aa0SRavi Pokala * Device being attached. 164*24f93aa0SRavi Pokala */ 165*24f93aa0SRavi Pokala static int 166*24f93aa0SRavi Pokala imcsmb_pci_attach(device_t dev) 167*24f93aa0SRavi Pokala { 168*24f93aa0SRavi Pokala struct imcsmb_pci_softc *sc; 169*24f93aa0SRavi Pokala device_t child; 170*24f93aa0SRavi Pokala int rc; 171*24f93aa0SRavi Pokala int unit; 172*24f93aa0SRavi Pokala 173*24f93aa0SRavi Pokala /* Initialize private state */ 174*24f93aa0SRavi Pokala sc = device_get_softc(dev); 175*24f93aa0SRavi Pokala sc->dev = dev; 176*24f93aa0SRavi Pokala sc->semaphore = 0; 177*24f93aa0SRavi Pokala 178*24f93aa0SRavi Pokala /* Create the imcsmbX children */ 179*24f93aa0SRavi Pokala for (unit = 0; unit < 2; unit++) { 180*24f93aa0SRavi Pokala child = device_add_child(dev, "imcsmb", -1); 181*24f93aa0SRavi Pokala if (child == NULL) { 182*24f93aa0SRavi Pokala /* Nothing has been allocated, so there's no cleanup. */ 183*24f93aa0SRavi Pokala device_printf(dev, "Child imcsmb not added\n"); 184*24f93aa0SRavi Pokala rc = ENXIO; 185*24f93aa0SRavi Pokala goto out; 186*24f93aa0SRavi Pokala } 187*24f93aa0SRavi Pokala /* Set the child's ivars to point to the appropriate set of 188*24f93aa0SRavi Pokala * the PCI device's registers. 189*24f93aa0SRavi Pokala */ 190*24f93aa0SRavi Pokala device_set_ivars(child, &imcsmb_regs[unit]); 191*24f93aa0SRavi Pokala } 192*24f93aa0SRavi Pokala 193*24f93aa0SRavi Pokala /* Attach the imcsmbX children. */ 194*24f93aa0SRavi Pokala if ((rc = bus_generic_attach(dev)) != 0) { 195*24f93aa0SRavi Pokala device_printf(dev, "failed to attach children: %d\n", rc); 196*24f93aa0SRavi Pokala goto out; 197*24f93aa0SRavi Pokala } 198*24f93aa0SRavi Pokala 199*24f93aa0SRavi Pokala out: 200*24f93aa0SRavi Pokala return (rc); 201*24f93aa0SRavi Pokala } 202*24f93aa0SRavi Pokala 203*24f93aa0SRavi Pokala /** 204*24f93aa0SRavi Pokala * device_detach() method. attach() didn't do any allocations, so all that's 205*24f93aa0SRavi Pokala * needed here is to free up any downstream drivers and children. 206*24f93aa0SRavi Pokala * 207*24f93aa0SRavi Pokala * @author Joe Kloss 208*24f93aa0SRavi Pokala * 209*24f93aa0SRavi Pokala * @param[in] dev 210*24f93aa0SRavi Pokala * Device being detached. 211*24f93aa0SRavi Pokala */ 212*24f93aa0SRavi Pokala static int 213*24f93aa0SRavi Pokala imcsmb_pci_detach(device_t dev) 214*24f93aa0SRavi Pokala { 215*24f93aa0SRavi Pokala int rc; 216*24f93aa0SRavi Pokala 217*24f93aa0SRavi Pokala /* Detach any attached drivers */ 218*24f93aa0SRavi Pokala rc = bus_generic_detach(dev); 219*24f93aa0SRavi Pokala if (rc == 0) { 220*24f93aa0SRavi Pokala /* Remove all children */ 221*24f93aa0SRavi Pokala rc = device_delete_children(dev); 222*24f93aa0SRavi Pokala } 223*24f93aa0SRavi Pokala 224*24f93aa0SRavi Pokala return (rc); 225*24f93aa0SRavi Pokala } 226*24f93aa0SRavi Pokala 227*24f93aa0SRavi Pokala /** 228*24f93aa0SRavi Pokala * device_probe() method. Look for the right PCI vendor/device IDs. 229*24f93aa0SRavi Pokala * 230*24f93aa0SRavi Pokala * @author Joe Kloss, rpokala 231*24f93aa0SRavi Pokala * 232*24f93aa0SRavi Pokala * @param[in,out] dev 233*24f93aa0SRavi Pokala * Device being probed. 234*24f93aa0SRavi Pokala */ 235*24f93aa0SRavi Pokala static int 236*24f93aa0SRavi Pokala imcsmb_pci_probe(device_t dev) 237*24f93aa0SRavi Pokala { 238*24f93aa0SRavi Pokala struct imcsmb_pci_device *pci_device; 239*24f93aa0SRavi Pokala int rc; 240*24f93aa0SRavi Pokala uint16_t pci_dev_id; 241*24f93aa0SRavi Pokala 242*24f93aa0SRavi Pokala rc = ENXIO; 243*24f93aa0SRavi Pokala 244*24f93aa0SRavi Pokala if (pci_get_vendor(dev) != PCI_VENDOR_INTEL) { 245*24f93aa0SRavi Pokala goto out; 246*24f93aa0SRavi Pokala } 247*24f93aa0SRavi Pokala 248*24f93aa0SRavi Pokala pci_dev_id = pci_get_device(dev); 249*24f93aa0SRavi Pokala for (pci_device = imcsmb_pci_devices; 250*24f93aa0SRavi Pokala pci_device->name != NULL; 251*24f93aa0SRavi Pokala pci_device++) { 252*24f93aa0SRavi Pokala if (pci_dev_id == pci_device->id) { 253*24f93aa0SRavi Pokala device_set_desc(dev, pci_device->name); 254*24f93aa0SRavi Pokala rc = BUS_PROBE_DEFAULT; 255*24f93aa0SRavi Pokala goto out; 256*24f93aa0SRavi Pokala } 257*24f93aa0SRavi Pokala } 258*24f93aa0SRavi Pokala 259*24f93aa0SRavi Pokala out: 260*24f93aa0SRavi Pokala return (rc); 261*24f93aa0SRavi Pokala } 262*24f93aa0SRavi Pokala 263*24f93aa0SRavi Pokala /** 264*24f93aa0SRavi Pokala * Invoked via smbus_callback() -> imcsmb_callback(); clear the semaphore, and 265*24f93aa0SRavi Pokala * re-enable motherboard-specific DIMM temperature monitoring if needed. This 266*24f93aa0SRavi Pokala * gets called after the transaction completes. 267*24f93aa0SRavi Pokala * 268*24f93aa0SRavi Pokala * @author Joe Kloss 269*24f93aa0SRavi Pokala * 270*24f93aa0SRavi Pokala * @param[in,out] dev 271*24f93aa0SRavi Pokala * The device whose busses to release. 272*24f93aa0SRavi Pokala */ 273*24f93aa0SRavi Pokala void 274*24f93aa0SRavi Pokala imcsmb_pci_release_bus(device_t dev) 275*24f93aa0SRavi Pokala { 276*24f93aa0SRavi Pokala struct imcsmb_pci_softc *sc; 277*24f93aa0SRavi Pokala 278*24f93aa0SRavi Pokala sc = device_get_softc(dev); 279*24f93aa0SRavi Pokala 280*24f93aa0SRavi Pokala /* 281*24f93aa0SRavi Pokala * IF NEEDED, INSERT MOTHERBOARD-SPECIFIC CODE TO RE-ENABLE DIMM 282*24f93aa0SRavi Pokala * TEMPERATURE MONITORING HERE. 283*24f93aa0SRavi Pokala */ 284*24f93aa0SRavi Pokala 285*24f93aa0SRavi Pokala atomic_store_rel_int(&sc->semaphore, 0); 286*24f93aa0SRavi Pokala } 287*24f93aa0SRavi Pokala 288*24f93aa0SRavi Pokala /** 289*24f93aa0SRavi Pokala * Invoked via smbus_callback() -> imcsmb_callback(); set the semaphore, and 290*24f93aa0SRavi Pokala * disable motherboard-specific DIMM temperature monitoring if needed. This gets 291*24f93aa0SRavi Pokala * called before the transaction starts. 292*24f93aa0SRavi Pokala * 293*24f93aa0SRavi Pokala * @author Joe Kloss 294*24f93aa0SRavi Pokala * 295*24f93aa0SRavi Pokala * @param[in,out] dev 296*24f93aa0SRavi Pokala * The device whose busses to request. 297*24f93aa0SRavi Pokala */ 298*24f93aa0SRavi Pokala int 299*24f93aa0SRavi Pokala imcsmb_pci_request_bus(device_t dev) 300*24f93aa0SRavi Pokala { 301*24f93aa0SRavi Pokala struct imcsmb_pci_softc *sc; 302*24f93aa0SRavi Pokala int rc; 303*24f93aa0SRavi Pokala 304*24f93aa0SRavi Pokala sc = device_get_softc(dev); 305*24f93aa0SRavi Pokala rc = 0; 306*24f93aa0SRavi Pokala 307*24f93aa0SRavi Pokala /* We don't want to block. Use a simple test-and-set semaphore to 308*24f93aa0SRavi Pokala * protect the bus. 309*24f93aa0SRavi Pokala */ 310*24f93aa0SRavi Pokala if (atomic_cmpset_acq_int(&sc->semaphore, 0, 1) == 0) { 311*24f93aa0SRavi Pokala rc = EWOULDBLOCK; 312*24f93aa0SRavi Pokala } 313*24f93aa0SRavi Pokala 314*24f93aa0SRavi Pokala /* 315*24f93aa0SRavi Pokala * IF NEEDED, INSERT MOTHERBOARD-SPECIFIC CODE TO DISABLE DIMM 316*24f93aa0SRavi Pokala * TEMPERATURE MONITORING HERE. 317*24f93aa0SRavi Pokala */ 318*24f93aa0SRavi Pokala 319*24f93aa0SRavi Pokala return (rc); 320*24f93aa0SRavi Pokala } 321*24f93aa0SRavi Pokala 322*24f93aa0SRavi Pokala /* Our device class */ 323*24f93aa0SRavi Pokala static devclass_t imcsmb_pci_devclass; 324*24f93aa0SRavi Pokala 325*24f93aa0SRavi Pokala /* Device methods */ 326*24f93aa0SRavi Pokala static device_method_t imcsmb_pci_methods[] = { 327*24f93aa0SRavi Pokala /* Device interface */ 328*24f93aa0SRavi Pokala DEVMETHOD(device_attach, imcsmb_pci_attach), 329*24f93aa0SRavi Pokala DEVMETHOD(device_detach, imcsmb_pci_detach), 330*24f93aa0SRavi Pokala DEVMETHOD(device_probe, imcsmb_pci_probe), 331*24f93aa0SRavi Pokala 332*24f93aa0SRavi Pokala DEVMETHOD_END 333*24f93aa0SRavi Pokala }; 334*24f93aa0SRavi Pokala 335*24f93aa0SRavi Pokala static driver_t imcsmb_pci_driver = { 336*24f93aa0SRavi Pokala .name = "imcsmb_pci", 337*24f93aa0SRavi Pokala .methods = imcsmb_pci_methods, 338*24f93aa0SRavi Pokala .size = sizeof(struct imcsmb_pci_softc), 339*24f93aa0SRavi Pokala }; 340*24f93aa0SRavi Pokala 341*24f93aa0SRavi Pokala DRIVER_MODULE(imcsmb_pci, pci, imcsmb_pci_driver, imcsmb_pci_devclass, 0, 0); 342*24f93aa0SRavi Pokala MODULE_DEPEND(imcsmb_pci, pci, 1, 1, 1); 343*24f93aa0SRavi Pokala MODULE_VERSION(imcsmb_pci, 1); 344*24f93aa0SRavi Pokala 345*24f93aa0SRavi Pokala /* vi: set ts=8 sw=4 sts=8 noet: */ 346