1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org> 5 * 6 * Development sponsored by Microsemi, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Helper code to recover a hung i2c bus by bit-banging a recovery sequence. 35 * 36 * An i2c bus can be hung by a slave driving the clock (rare) or data lines low. 37 * The most common cause is a partially-completed transaction such as rebooting 38 * while a slave is sending a byte of data. Because i2c allows the clock to 39 * freeze for any amount of time, the slave device will continue driving the 40 * data line until power is removed, or the clock cycles enough times to 41 * complete the current byte. After completing any partial byte, a START/STOP 42 * sequence resets the slave and the bus is recovered. 43 * 44 * Any i2c driver which is able to manually set the level of the clock and data 45 * lines can use this common code for bus recovery. On many SOCs that have 46 * embedded i2c controllers, the i2c pins can be temporarily reassigned as gpio 47 * pins to do the bus recovery, then can be assigned back to the i2c hardware. 48 */ 49 50 #include "opt_platform.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/bus.h> 55 56 #include <dev/iicbus/iic_recover_bus.h> 57 #include <dev/iicbus/iiconf.h> 58 59 int 60 iic_recover_bus(struct iicrb_pin_access *pins) 61 { 62 const u_int timeout_us = 40000; 63 const u_int delay_us = 500; 64 int i; 65 66 /* 67 * Start with clock and data high. 68 */ 69 pins->setsda(pins->ctx, 1); 70 pins->setscl(pins->ctx, 1); 71 72 /* 73 * At this point, SCL should be high. If it's not, some slave on the 74 * bus is doing clock-stretching and we should wait a while. If that 75 * slave is completely locked up there may be no way to recover at all. 76 * We wait up to 40 milliseconds, a seriously pessimistic time (even a 77 * cheap eeprom has a max post-write delay of only 10ms), and also long 78 * enough to allow SMB slaves to timeout normally after 35ms. 79 */ 80 for (i = 0; i < timeout_us; i += delay_us) { 81 if (pins->getscl(pins->ctx)) 82 break; 83 DELAY(delay_us); 84 } 85 if (i >= timeout_us) 86 return (IIC_EBUSERR); 87 88 /* 89 * At this point we should be able to control the clock line. Some 90 * slave may be part way through a byte transfer, and could be holding 91 * the data line low waiting for more clock pulses to finish the byte. 92 * Cycle the clock until we see the data line go high, but only up to 9 93 * times because if it's not free after 9 clocks we're never going to 94 * win this battle. We do 9 max because that's a byte plus an ack/nack 95 * bit, after which the slave must not be driving the data line anymore. 96 */ 97 for (i = 0; ; ++i) { 98 if (pins->getsda(pins->ctx)) 99 break; 100 if (i == 9) 101 return (IIC_EBUSERR); 102 pins->setscl(pins->ctx, 0); 103 DELAY(5); 104 pins->setscl(pins->ctx, 1); 105 DELAY(5); 106 } 107 108 /* 109 * At this point we should be in control of both the clock and data 110 * lines, and both lines should be high. To complete the reset of a 111 * slave that was part way through a transaction, we need to do a 112 * START/STOP sequence, which leaves both lines high at the end. 113 * - START: SDA transitions high->low while SCL remains high. 114 * - STOP: SDA transitions low->high while SCL remains high. 115 * Note that even though the clock line remains high, we transition the 116 * data line no faster than it would change state with a 100khz clock. 117 */ 118 pins->setsda(pins->ctx, 0); 119 DELAY(5); 120 pins->setsda(pins->ctx, 1); 121 DELAY(5); 122 123 return (0); 124 } 125 126