1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org> 5 * 6 * Development sponsored by Microsemi, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 /* 32 * Helper code to recover a hung i2c bus by bit-banging a recovery sequence. 33 * 34 * An i2c bus can be hung by a slave driving the clock (rare) or data lines low. 35 * The most common cause is a partially-completed transaction such as rebooting 36 * while a slave is sending a byte of data. Because i2c allows the clock to 37 * freeze for any amount of time, the slave device will continue driving the 38 * data line until power is removed, or the clock cycles enough times to 39 * complete the current byte. After completing any partial byte, a START/STOP 40 * sequence resets the slave and the bus is recovered. 41 * 42 * Any i2c driver which is able to manually set the level of the clock and data 43 * lines can use this common code for bus recovery. On many SOCs that have 44 * embedded i2c controllers, the i2c pins can be temporarily reassigned as gpio 45 * pins to do the bus recovery, then can be assigned back to the i2c hardware. 46 */ 47 48 #include "opt_platform.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/bus.h> 53 54 #include <dev/iicbus/iic_recover_bus.h> 55 #include <dev/iicbus/iiconf.h> 56 57 int 58 iic_recover_bus(struct iicrb_pin_access *pins) 59 { 60 const u_int timeout_us = 40000; 61 const u_int delay_us = 500; 62 int i; 63 64 /* 65 * Start with clock and data high. 66 */ 67 pins->setsda(pins->ctx, 1); 68 pins->setscl(pins->ctx, 1); 69 70 /* 71 * At this point, SCL should be high. If it's not, some slave on the 72 * bus is doing clock-stretching and we should wait a while. If that 73 * slave is completely locked up there may be no way to recover at all. 74 * We wait up to 40 milliseconds, a seriously pessimistic time (even a 75 * cheap eeprom has a max post-write delay of only 10ms), and also long 76 * enough to allow SMB slaves to timeout normally after 35ms. 77 */ 78 for (i = 0; i < timeout_us; i += delay_us) { 79 if (pins->getscl(pins->ctx)) 80 break; 81 DELAY(delay_us); 82 } 83 if (i >= timeout_us) 84 return (IIC_EBUSERR); 85 86 /* 87 * At this point we should be able to control the clock line. Some 88 * slave may be part way through a byte transfer, and could be holding 89 * the data line low waiting for more clock pulses to finish the byte. 90 * Cycle the clock until we see the data line go high, but only up to 9 91 * times because if it's not free after 9 clocks we're never going to 92 * win this battle. We do 9 max because that's a byte plus an ack/nack 93 * bit, after which the slave must not be driving the data line anymore. 94 */ 95 for (i = 0; ; ++i) { 96 if (pins->getsda(pins->ctx)) 97 break; 98 if (i == 9) 99 return (IIC_EBUSERR); 100 pins->setscl(pins->ctx, 0); 101 DELAY(5); 102 pins->setscl(pins->ctx, 1); 103 DELAY(5); 104 } 105 106 /* 107 * At this point we should be in control of both the clock and data 108 * lines, and both lines should be high. To complete the reset of a 109 * slave that was part way through a transaction, we need to do a 110 * START/STOP sequence, which leaves both lines high at the end. 111 * - START: SDA transitions high->low while SCL remains high. 112 * - STOP: SDA transitions low->high while SCL remains high. 113 * Note that even though the clock line remains high, we transition the 114 * data line no faster than it would change state with a 100khz clock. 115 */ 116 pins->setsda(pins->ctx, 0); 117 DELAY(5); 118 pins->setsda(pins->ctx, 1); 119 DELAY(5); 120 121 return (0); 122 } 123 124