1 /*- 2 * Copyright (c) 2006 Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25 #include <sys/cdefs.h> 26 __FBSDID("$FreeBSD$"); 27 /* 28 * Generic IIC eeprom support, modeled after the AT24C family of products. 29 */ 30 31 #include "opt_platform.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/resource.h> 40 #include <sys/sx.h> 41 #include <sys/uio.h> 42 #include <machine/bus.h> 43 44 #ifdef FDT 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 #endif 48 49 #include <dev/iicbus/iiconf.h> 50 #include <dev/iicbus/iicbus.h> 51 52 #include "iicbus_if.h" 53 54 /* 55 * AT24 parts have a "write page size" that differs per-device, and a "read page 56 * size" that is always equal to the full device size. We define maximum values 57 * here to limit how long we occupy the bus with a single transfer, and because 58 * there are temporary buffers of these sizes allocated on the stack. 59 */ 60 #define MAX_RD_SZ 256 /* Largest read size we support */ 61 #define MAX_WR_SZ 256 /* Largest write size we support */ 62 63 struct icee_softc { 64 device_t dev; /* Myself */ 65 struct cdev *cdev; /* user interface */ 66 int addr; /* Slave address on the bus */ 67 int size; /* How big am I? */ 68 int type; /* What address type 8 or 16 bit? */ 69 int wr_sz; /* What's the write page size */ 70 }; 71 72 #ifdef FDT 73 struct eeprom_desc { 74 int type; 75 int size; 76 int wr_sz; 77 const char *name; 78 }; 79 80 static struct eeprom_desc type_desc[] = { 81 { 8, 128, 8, "AT24C01"}, 82 { 8, 256, 8, "AT24C02"}, 83 { 8, 512, 16, "AT24C04"}, 84 { 8, 1024, 16, "AT24C08"}, 85 { 8, 2 * 1024, 16, "AT24C16"}, 86 {16, 4 * 1024, 32, "AT24C32"}, 87 {16, 8 * 1024, 32, "AT24C64"}, 88 {16, 16 * 1024, 64, "AT24C128"}, 89 {16, 32 * 1024, 64, "AT24C256"}, 90 {16, 64 * 1024, 128, "AT24C512"}, 91 {16, 128 * 1024, 256, "AT24CM01"}, 92 }; 93 94 static struct ofw_compat_data compat_data[] = { 95 {"atmel,24c01", (uintptr_t)(&type_desc[0])}, 96 {"atmel,24c02", (uintptr_t)(&type_desc[1])}, 97 {"atmel,24c04", (uintptr_t)(&type_desc[2])}, 98 {"atmel,24c08", (uintptr_t)(&type_desc[3])}, 99 {"atmel,24c16", (uintptr_t)(&type_desc[4])}, 100 {"atmel,24c32", (uintptr_t)(&type_desc[5])}, 101 {"atmel,24c64", (uintptr_t)(&type_desc[6])}, 102 {"atmel,24c128", (uintptr_t)(&type_desc[7])}, 103 {"atmel,24c256", (uintptr_t)(&type_desc[8])}, 104 {"atmel,24c512", (uintptr_t)(&type_desc[9])}, 105 {"atmel,24c1024", (uintptr_t)(&type_desc[10])}, 106 {NULL, (uintptr_t)NULL}, 107 }; 108 #endif 109 110 #define CDEV2SOFTC(dev) ((dev)->si_drv1) 111 112 /* cdev routines */ 113 static d_open_t icee_open; 114 static d_close_t icee_close; 115 static d_read_t icee_read; 116 static d_write_t icee_write; 117 118 static struct cdevsw icee_cdevsw = 119 { 120 .d_version = D_VERSION, 121 .d_flags = D_TRACKCLOSE, 122 .d_open = icee_open, 123 .d_close = icee_close, 124 .d_read = icee_read, 125 .d_write = icee_write 126 }; 127 128 #ifdef FDT 129 static int 130 icee_probe(device_t dev) 131 { 132 struct eeprom_desc *d; 133 134 if (!ofw_bus_status_okay(dev)) 135 return (ENXIO); 136 137 d = (struct eeprom_desc *) 138 ofw_bus_search_compatible(dev, compat_data)->ocd_data; 139 if (d == NULL) 140 return (ENXIO); 141 142 device_set_desc(dev, d->name); 143 return (BUS_PROBE_DEFAULT); 144 } 145 146 static void 147 icee_init(struct icee_softc *sc) 148 { 149 struct eeprom_desc *d; 150 151 d = (struct eeprom_desc *) 152 ofw_bus_search_compatible(sc->dev, compat_data)->ocd_data; 153 if (d == NULL) 154 return; /* attach will see sc->size == 0 and return error */ 155 156 sc->size = d->size; 157 sc->type = d->type; 158 sc->wr_sz = d->wr_sz; 159 } 160 #else /* !FDT */ 161 static int 162 icee_probe(device_t dev) 163 { 164 165 device_set_desc(dev, "I2C EEPROM"); 166 return (BUS_PROBE_NOWILDCARD); 167 } 168 169 static void 170 icee_init(struct icee_softc *sc) 171 { 172 const char *dname; 173 int dunit; 174 175 dname = device_get_name(sc->dev); 176 dunit = device_get_unit(sc->dev); 177 resource_int_value(dname, dunit, "size", &sc->size); 178 resource_int_value(dname, dunit, "type", &sc->type); 179 resource_int_value(dname, dunit, "wr_sz", &sc->wr_sz); 180 } 181 #endif /* FDT */ 182 183 static int 184 icee_attach(device_t dev) 185 { 186 struct icee_softc *sc = device_get_softc(dev); 187 188 sc->dev = dev; 189 sc->addr = iicbus_get_addr(dev); 190 icee_init(sc); 191 if (sc->size == 0 || sc->type == 0 || sc->wr_sz == 0) { 192 device_printf(sc->dev, "Missing config data, " 193 "these cannot be zero: size %d type %d wr_sz %d\n", 194 sc->size, sc->type, sc->wr_sz); 195 return (EINVAL); 196 } 197 if (bootverbose) 198 device_printf(dev, "size: %d bytes, addressing: %d-bits\n", 199 sc->size, sc->type); 200 sc->cdev = make_dev(&icee_cdevsw, device_get_unit(dev), UID_ROOT, 201 GID_WHEEL, 0600, "icee%d", device_get_unit(dev)); 202 if (sc->cdev == NULL) { 203 return (ENOMEM); 204 } 205 sc->cdev->si_drv1 = sc; 206 return (0); 207 } 208 209 static int 210 icee_open(struct cdev *dev, int oflags, int devtype, struct thread *td) 211 { 212 213 return (0); 214 } 215 216 static int 217 icee_close(struct cdev *dev, int fflag, int devtype, struct thread *td) 218 { 219 220 return (0); 221 } 222 223 static int 224 icee_read(struct cdev *dev, struct uio *uio, int ioflag) 225 { 226 struct icee_softc *sc; 227 uint8_t addr[2]; 228 uint8_t data[MAX_RD_SZ]; 229 int error, i, len, slave; 230 struct iic_msg msgs[2] = { 231 { 0, IIC_M_WR, 1, addr }, 232 { 0, IIC_M_RD, 0, data }, 233 }; 234 235 sc = CDEV2SOFTC(dev); 236 if (uio->uio_offset == sc->size) 237 return (0); 238 if (uio->uio_offset > sc->size) 239 return (EIO); 240 if (sc->type != 8 && sc->type != 16) 241 return (EINVAL); 242 slave = error = 0; 243 while (uio->uio_resid > 0) { 244 if (uio->uio_offset >= sc->size) 245 break; 246 len = MIN(MAX_RD_SZ - (uio->uio_offset & (MAX_RD_SZ - 1)), 247 uio->uio_resid); 248 switch (sc->type) { 249 case 8: 250 slave = (uio->uio_offset >> 7) | sc->addr; 251 msgs[0].len = 1; 252 msgs[1].len = len; 253 addr[0] = uio->uio_offset & 0xff; 254 break; 255 case 16: 256 slave = sc->addr | (uio->uio_offset >> 15); 257 msgs[0].len = 2; 258 msgs[1].len = len; 259 addr[0] = (uio->uio_offset >> 8) & 0xff; 260 addr[1] = uio->uio_offset & 0xff; 261 break; 262 } 263 for (i = 0; i < 2; i++) 264 msgs[i].slave = slave; 265 error = iicbus_transfer_excl(sc->dev, msgs, 2, IIC_INTRWAIT); 266 if (error) { 267 error = iic2errno(error); 268 break; 269 } 270 error = uiomove(data, len, uio); 271 if (error) 272 break; 273 } 274 return (error); 275 } 276 277 /* 278 * Write to the part. We use three transfers here since we're actually 279 * doing a write followed by a read to make sure that the write finished. 280 * It is easier to encode the dummy read here than to break things up 281 * into smaller chunks... 282 */ 283 static int 284 icee_write(struct cdev *dev, struct uio *uio, int ioflag) 285 { 286 struct icee_softc *sc; 287 int error, len, slave, waitlimit; 288 uint8_t data[MAX_WR_SZ + 2]; 289 struct iic_msg wr[1] = { 290 { 0, IIC_M_WR, 0, data }, 291 }; 292 struct iic_msg rd[1] = { 293 { 0, IIC_M_RD, 1, data }, 294 }; 295 296 sc = CDEV2SOFTC(dev); 297 if (uio->uio_offset >= sc->size) 298 return (EIO); 299 if (sc->type != 8 && sc->type != 16) 300 return (EINVAL); 301 302 slave = error = 0; 303 while (uio->uio_resid > 0) { 304 if (uio->uio_offset >= sc->size) 305 break; 306 len = MIN(sc->wr_sz - (uio->uio_offset & (sc->wr_sz - 1)), 307 uio->uio_resid); 308 switch (sc->type) { 309 case 8: 310 slave = (uio->uio_offset >> 7) | sc->addr; 311 wr[0].len = 1 + len; 312 data[0] = uio->uio_offset & 0xff; 313 break; 314 case 16: 315 slave = sc->addr | (uio->uio_offset >> 15); 316 wr[0].len = 2 + len; 317 data[0] = (uio->uio_offset >> 8) & 0xff; 318 data[1] = uio->uio_offset & 0xff; 319 break; 320 } 321 wr[0].slave = slave; 322 error = uiomove(data + sc->type / 8, len, uio); 323 if (error) 324 break; 325 error = iicbus_transfer_excl(sc->dev, wr, 1, IIC_INTRWAIT); 326 if (error) { 327 error = iic2errno(error); 328 break; 329 } 330 /* Read after write to wait for write-done. */ 331 waitlimit = 10000; 332 rd[0].slave = slave; 333 do { 334 error = iicbus_transfer_excl(sc->dev, rd, 1, 335 IIC_INTRWAIT); 336 } while (waitlimit-- > 0 && error != 0); 337 if (error) { 338 error = iic2errno(error); 339 break; 340 } 341 } 342 return error; 343 } 344 345 static device_method_t icee_methods[] = { 346 DEVMETHOD(device_probe, icee_probe), 347 DEVMETHOD(device_attach, icee_attach), 348 349 DEVMETHOD_END 350 }; 351 352 static driver_t icee_driver = { 353 "icee", 354 icee_methods, 355 sizeof(struct icee_softc), 356 }; 357 static devclass_t icee_devclass; 358 359 DRIVER_MODULE(icee, iicbus, icee_driver, icee_devclass, 0, 0); 360 MODULE_VERSION(icee, 1); 361 MODULE_DEPEND(icee, iicbus, 1, 1, 1); 362