1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2024 Pierre-Luc Drouin <pldrouin@pldrouin.net> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Vybrid Family Inter-Integrated Circuit (I2C) 31 * Originally based on Chapter 48, Vybrid Reference Manual, Rev. 5, 07/2013 32 * Currently based on Chapter 21, LX2160A Reference Manual, Rev. 1, 10/2021 33 * 34 * The current implementation is based on the original driver by Ruslan Bukin, 35 * later modified by Dawid Górecki, and split into FDT and ACPI drivers by Val 36 * Packett. 37 */ 38 39 #include <sys/types.h> 40 #include <sys/mutex.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/malloc.h> 47 #include <sys/rman.h> 48 #include <sys/timeet.h> 49 #include <sys/timetc.h> 50 51 #include <dev/iicbus/iiconf.h> 52 #include <dev/iicbus/iicbus.h> 53 54 #include "iicbus_if.h" 55 56 #include <machine/bus.h> 57 #include <machine/cpu.h> 58 #include <machine/intr.h> 59 60 #include <dev/iicbus/controller/vybrid/vf_i2c.h> 61 62 #define I2C_IBAD 0x0 /* I2C Bus Address Register */ 63 #define I2C_IBFD 0x1 /* I2C Bus Frequency Divider Register */ 64 #define I2C_IBCR 0x2 /* I2C Bus Control Register */ 65 #define IBCR_MDIS (1 << 7) /* Module disable. */ 66 #define IBCR_IBIE (1 << 6) /* I-Bus Interrupt Enable. */ 67 #define IBCR_MSSL (1 << 5) /* Master/Slave mode select. */ 68 #define IBCR_TXRX (1 << 4) /* Transmit/Receive mode select. */ 69 #define IBCR_NOACK (1 << 3) /* Data Acknowledge disable. */ 70 #define IBCR_RSTA (1 << 2) /* Repeat Start. */ 71 #define IBCR_DMAEN (1 << 1) /* DMA Enable. */ 72 #define I2C_IBSR 0x3 /* I2C Bus Status Register */ 73 #define IBSR_TCF (1 << 7) /* Transfer complete. */ 74 #define IBSR_IAAS (1 << 6) /* Addressed as a slave. */ 75 #define IBSR_IBB (1 << 5) /* Bus busy. */ 76 #define IBSR_IBAL (1 << 4) /* Arbitration Lost. */ 77 #define IBSR_SRW (1 << 2) /* Slave Read/Write. */ 78 #define IBSR_IBIF (1 << 1) /* I-Bus Interrupt Flag. */ 79 #define IBSR_RXAK (1 << 0) /* Received Acknowledge. */ 80 #define I2C_IBDR 0x4 /* I2C Bus Data I/O Register */ 81 #define I2C_IBIC 0x5 /* I2C Bus Interrupt Config Register */ 82 #define IBIC_BIIE (1 << 7) /* Bus Idle Interrupt Enable bit. */ 83 #define I2C_IBDBG 0x6 /* I2C Bus Debug Register */ 84 85 #define DIV_REG_UNSET 0xFF 86 87 #define READ1(_sc, _reg) bus_space_read_1(_sc->bst, _sc->bsh, _reg) 88 #define WRITE1(_sc, _reg, _val) bus_space_write_1(_sc->bst,\ 89 _sc->bsh, _reg, _val) 90 91 #ifdef DEBUG 92 #define vf_i2c_dbg(_sc, fmt, args...) \ 93 device_printf((_sc)->dev, fmt, ##args) 94 #ifdef DEBUG2 95 #undef WRITE1 96 #define WRITE1(_sc, _reg, _val) ({\ 97 vf_i2c_dbg(_sc, "WRITE1 REG 0x%02X VAL 0x%02X\n",_reg,_val);\ 98 bus_space_write_1(_sc->bst, _sc->bsh, _reg, _val);\ 99 }) 100 #undef READ1 101 #define READ1(_sc, _reg) ({\ 102 uint32_t ret=bus_space_read_1(_sc->bst, _sc->bsh, _reg);\ 103 vf_i2c_dbg(_sc, "READ1 REG 0x%02X RETURNS 0x%02X\n",_reg,ret);\ 104 ret;\ 105 }) 106 #endif 107 #else 108 #define vf_i2c_dbg(_sc, fmt, args...) 109 #endif 110 111 static int i2c_repeated_start(device_t, u_char, int); 112 static int i2c_start(device_t, u_char, int); 113 static int i2c_stop(device_t); 114 static int i2c_reset(device_t, u_char, u_char, u_char *); 115 static int i2c_read(device_t, char *, int, int *, int, int); 116 static int i2c_write(device_t, const char *, int, int *, int); 117 118 struct i2c_div_type { 119 uint32_t reg_val; 120 uint32_t div; 121 }; 122 123 static struct resource_spec i2c_spec[] = { 124 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 125 { SYS_RES_IRQ, 0, RF_ACTIVE }, 126 { -1, 0 } 127 }; 128 129 static struct i2c_div_type vf610_div_table[] = { 130 { 0x00, 20 }, { 0x01, 22 }, { 0x02, 24 }, { 0x03, 26 }, 131 { 0x04, 28 }, { 0x05, 30 }, { 0x09, 32 }, { 0x06, 34 }, 132 { 0x0A, 36 }, { 0x0B, 40 }, { 0x0C, 44 }, { 0x0D, 48 }, 133 { 0x0E, 56 }, { 0x12, 64 }, { 0x13, 72 }, { 0x14, 80 }, 134 { 0x15, 88 }, { 0x19, 96 }, { 0x16, 104 }, { 0x1A, 112 }, 135 { 0x17, 128 }, { 0x1D, 160 }, { 0x1E, 192 }, { 0x22, 224 }, 136 { 0x1F, 240 }, { 0x23, 256 }, { 0x24, 288 }, { 0x25, 320 }, 137 { 0x26, 384 }, { 0x2A, 448 }, { 0x27, 480 }, { 0x2B, 512 }, 138 { 0x2C, 576 }, { 0x2D, 640 }, { 0x2E, 768 }, { 0x32, 896 }, 139 { 0x2F, 960 }, { 0x33, 1024 }, { 0x34, 1152 }, { 0x35, 1280 }, 140 { 0x36, 1536 }, { 0x3A, 1792 }, { 0x37, 1920 }, { 0x3B, 2048 }, 141 { 0x3C, 2304 }, { 0x3D, 2560 }, { 0x3E, 3072 }, { 0x3F, 3840 }, 142 { 0x3F, 3840 }, { 0x7B, 4096 }, { 0x7D, 5120 }, { 0x7E, 6144 }, 143 }; 144 145 int 146 vf_i2c_attach_common(device_t dev) 147 { 148 struct vf_i2c_softc *sc; 149 int error; 150 151 sc = device_get_softc(dev); 152 153 vf_i2c_dbg(sc, "i2c attach common\n"); 154 155 mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF); 156 157 error = bus_alloc_resources(dev, i2c_spec, sc->res); 158 if (error != 0) { 159 mtx_destroy(&sc->mutex); 160 device_printf(dev, "could not allocate resources\n"); 161 return (ENXIO); 162 } 163 164 /* Memory interface */ 165 sc->bst = rman_get_bustag(sc->res[0]); 166 sc->bsh = rman_get_bushandle(sc->res[0]); 167 168 mtx_lock(&sc->mutex); 169 170 WRITE1(sc, I2C_IBIC, IBIC_BIIE); 171 172 if (sc->freq == 0) { 173 uint8_t div_reg; 174 175 div_reg = READ1(sc, I2C_IBFD); 176 177 if (div_reg != 0x00) { 178 sc->freq = UINT32_MAX; 179 device_printf(dev, "Using existing bus frequency divider register value (0x%02X).\n", div_reg); 180 } else { 181 device_printf(dev, "Bus frequency divider value appears unset, defaulting to low I2C bus speed.\n"); 182 } 183 } 184 185 mtx_unlock(&sc->mutex); 186 187 sc->iicbus = device_add_child(dev, "iicbus", DEVICE_UNIT_ANY); 188 189 if (sc->iicbus == NULL) { 190 device_printf(dev, "could not add iicbus child"); 191 mtx_destroy(&sc->mutex); 192 bus_release_resources(dev, i2c_spec, sc->res); 193 return (ENXIO); 194 } 195 196 bus_attach_children(dev); 197 198 return (0); 199 } 200 201 static int 202 i2c_detach(device_t dev) 203 { 204 struct vf_i2c_softc *sc; 205 int error = 0; 206 207 sc = device_get_softc(dev); 208 vf_i2c_dbg(sc, "i2c detach\n"); 209 210 error = bus_generic_detach(dev); 211 if (error != 0) { 212 device_printf(dev, "cannot detach child devices.\n"); 213 return (error); 214 } 215 216 mtx_lock(&sc->mutex); 217 218 if (sc->freq == 0) { 219 vf_i2c_dbg(sc, "Writing 0x00 to clock divider register\n"); 220 WRITE1(sc, I2C_IBFD, 0x00); 221 } 222 223 bus_release_resources(dev, i2c_spec, sc->res); 224 225 mtx_unlock(&sc->mutex); 226 227 mtx_destroy(&sc->mutex); 228 229 return (0); 230 } 231 232 /* Wait for free bus */ 233 static int 234 wait_for_nibb(struct vf_i2c_softc *sc) 235 { 236 int retry; 237 238 retry = 1000; 239 while (retry --) { 240 if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) 241 return (IIC_NOERR); 242 DELAY(10); 243 } 244 245 return (IIC_ETIMEOUT); 246 } 247 248 /* Wait for transfer complete+interrupt flag */ 249 static int 250 wait_for_icf(struct vf_i2c_softc *sc) 251 { 252 int retry; 253 uint8_t ibsr; 254 255 vf_i2c_dbg(sc, "i2c wait for transfer complete + interrupt flag\n"); 256 257 retry = 1000; 258 while (retry --) { 259 ibsr = READ1(sc, I2C_IBSR); 260 261 if (ibsr & IBSR_IBIF) { 262 WRITE1(sc, I2C_IBSR, IBSR_IBIF); 263 264 if (ibsr & IBSR_IBAL) { 265 WRITE1(sc, I2C_IBSR, IBSR_IBAL); 266 return (IIC_EBUSBSY); 267 } 268 269 if (ibsr & IBSR_TCF) 270 return (IIC_NOERR); 271 } 272 DELAY(10); 273 } 274 275 return (IIC_ETIMEOUT); 276 } 277 /* Get ACK bit from last write */ 278 static bool 279 tx_acked(struct vf_i2c_softc *sc) 280 { 281 vf_i2c_dbg(sc, "i2c get ACK bit from last write\n"); 282 283 return (READ1(sc, I2C_IBSR) & IBSR_RXAK) ? false : true; 284 285 } 286 287 static int 288 i2c_repeated_start(device_t dev, u_char slave, int timeout) 289 { 290 struct vf_i2c_softc *sc; 291 int error; 292 int reg; 293 294 sc = device_get_softc(dev); 295 296 vf_i2c_dbg(sc, "i2c repeated start\n"); 297 298 mtx_lock(&sc->mutex); 299 300 if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) { 301 vf_i2c_dbg(sc, "cant i2c repeat start: bus is no longer busy\n"); 302 mtx_unlock(&sc->mutex); 303 return (IIC_EBUSERR); 304 } 305 306 reg = READ1(sc, I2C_IBCR); 307 reg |= (IBCR_RSTA | IBCR_IBIE); 308 WRITE1(sc, I2C_IBCR, reg); 309 310 /* Write target address - LSB is R/W bit */ 311 WRITE1(sc, I2C_IBDR, slave); 312 313 error = wait_for_icf(sc); 314 315 if (!tx_acked(sc)) { 316 mtx_unlock(&sc->mutex); 317 vf_i2c_dbg(sc, "cant i2c repeat start: missing ACK after slave address\n"); 318 return (IIC_ENOACK); 319 } 320 321 mtx_unlock(&sc->mutex); 322 323 if (error != 0) 324 return (error); 325 326 return (IIC_NOERR); 327 } 328 329 static int 330 i2c_start(device_t dev, u_char slave, int timeout) 331 { 332 struct vf_i2c_softc *sc; 333 int error; 334 int reg; 335 336 sc = device_get_softc(dev); 337 338 vf_i2c_dbg(sc, "i2c start\n"); 339 340 mtx_lock(&sc->mutex); 341 342 error = wait_for_nibb(sc); 343 344 /* Reset controller if bus is still busy. */ 345 if (error == IIC_ETIMEOUT) { 346 WRITE1(sc, I2C_IBCR, IBCR_MDIS); 347 DELAY(1000); 348 WRITE1(sc, I2C_IBCR, IBCR_NOACK); 349 error = wait_for_nibb(sc); 350 } 351 352 if (error != 0) { 353 mtx_unlock(&sc->mutex); 354 vf_i2c_dbg(sc, "cant i2c start: %i\n", error); 355 return (error); 356 } 357 358 /* Set start condition */ 359 reg = (IBCR_MSSL | IBCR_NOACK | IBCR_IBIE | IBCR_TXRX); 360 WRITE1(sc, I2C_IBCR, reg); 361 362 WRITE1(sc, I2C_IBSR, IBSR_IBIF); 363 364 /* Write target address - LSB is R/W bit */ 365 WRITE1(sc, I2C_IBDR, slave); 366 367 error = wait_for_icf(sc); 368 if (error != 0) { 369 mtx_unlock(&sc->mutex); 370 vf_i2c_dbg(sc, "cant i2c start: iif error\n"); 371 return (error); 372 } 373 mtx_unlock(&sc->mutex); 374 375 if (!tx_acked(sc)) { 376 vf_i2c_dbg(sc, "cant i2c start: missing ACK after slave address\n"); 377 return (IIC_ENOACK); 378 } 379 380 return (IIC_NOERR); 381 } 382 383 static int 384 i2c_stop(device_t dev) 385 { 386 struct vf_i2c_softc *sc; 387 388 sc = device_get_softc(dev); 389 390 vf_i2c_dbg(sc, "i2c stop\n"); 391 392 mtx_lock(&sc->mutex); 393 394 if ((READ1(sc, I2C_IBCR) & IBCR_MSSL) != 0) 395 WRITE1(sc, I2C_IBCR, IBCR_NOACK | IBCR_IBIE); 396 397 mtx_unlock(&sc->mutex); 398 399 return (IIC_NOERR); 400 } 401 402 static uint8_t 403 i2c_get_div_val(device_t dev) 404 { 405 struct vf_i2c_softc *sc; 406 uint8_t div_reg = DIV_REG_UNSET; 407 408 sc = device_get_softc(dev); 409 410 if (sc->freq == UINT32_MAX) 411 return div_reg; 412 #ifndef FDT 413 div_reg = vf610_div_table[nitems(vf610_div_table) - 1].reg_val; 414 #else 415 if (sc->hwtype == HW_MVF600) 416 div_reg = MVF600_DIV_REG; 417 else if (sc->freq == 0) 418 div_reg = vf610_div_table[nitems(vf610_div_table) - 1].reg_val; 419 else { 420 uint64_t clk_freq; 421 int error, i; 422 423 error = clk_get_freq(sc->clock, &clk_freq); 424 if (error != 0) { 425 device_printf(dev, "Could not get parent clock frequency. " 426 "Using default divider.\n"); 427 div_reg = vf610_div_table[nitems(vf610_div_table) - 1].reg_val; 428 } else { 429 430 for (i = 0; i < nitems(vf610_div_table) - 1; i++) 431 if ((clk_freq / vf610_div_table[i].div) <= sc->freq) 432 break; 433 div_reg = vf610_div_table[i].reg_val; 434 } 435 } 436 #endif 437 vf_i2c_dbg(sc, "Writing 0x%02X to clock divider register\n", div_reg); 438 return div_reg; 439 } 440 441 static int 442 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 443 { 444 struct vf_i2c_softc *sc; 445 uint8_t div_reg; 446 447 sc = device_get_softc(dev); 448 div_reg = i2c_get_div_val(dev); 449 vf_i2c_dbg(sc, "i2c reset\n"); 450 451 mtx_lock(&sc->mutex); 452 WRITE1(sc, I2C_IBCR, IBCR_MDIS); 453 454 if(div_reg != DIV_REG_UNSET) 455 WRITE1(sc, I2C_IBFD, div_reg); 456 457 WRITE1(sc, I2C_IBCR, 0x0); /* Enable i2c */ 458 459 mtx_unlock(&sc->mutex); 460 461 return (IIC_NOERR); 462 } 463 464 static int 465 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 466 { 467 struct vf_i2c_softc *sc; 468 int error; 469 470 sc = device_get_softc(dev); 471 472 vf_i2c_dbg(sc, "i2c read\n"); 473 474 *read = 0; 475 476 mtx_lock(&sc->mutex); 477 478 if (len) { 479 if (len == 1) 480 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | IBCR_NOACK); 481 else 482 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL); 483 484 /* dummy read */ 485 READ1(sc, I2C_IBDR); 486 487 while (*read < len) { 488 error = wait_for_icf(sc); 489 if (error != 0) { 490 mtx_unlock(&sc->mutex); 491 return (error); 492 } 493 494 if (last) { 495 if (*read == len - 2) { 496 /* NO ACK on last byte */ 497 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | IBCR_NOACK); 498 499 } else if (*read == len - 1) { 500 /* Transfer done, remove master bit */ 501 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_NOACK); 502 } 503 } 504 505 *buf++ = READ1(sc, I2C_IBDR); 506 (*read)++; 507 } 508 } 509 mtx_unlock(&sc->mutex); 510 511 return (IIC_NOERR); 512 } 513 514 static int 515 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 516 { 517 struct vf_i2c_softc *sc; 518 int error; 519 520 sc = device_get_softc(dev); 521 522 vf_i2c_dbg(sc, "i2c write\n"); 523 524 *sent = 0; 525 526 mtx_lock(&sc->mutex); 527 while (*sent < len) { 528 WRITE1(sc, I2C_IBDR, *buf++); 529 530 error = wait_for_icf(sc); 531 if (error != 0) { 532 mtx_unlock(&sc->mutex); 533 return (error); 534 } 535 536 if (!tx_acked(sc) && (*sent = (len - 2)) ){ 537 mtx_unlock(&sc->mutex); 538 vf_i2c_dbg(sc, "no ACK on %d write\n", *sent); 539 return (IIC_ENOACK); 540 } 541 542 (*sent)++; 543 } 544 mtx_unlock(&sc->mutex); 545 return (IIC_NOERR); 546 } 547 548 static device_method_t i2c_methods[] = { 549 /* Device interface */ 550 DEVMETHOD(device_detach, i2c_detach), 551 552 /* Device interface */ 553 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 554 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 555 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 556 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 557 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 558 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 559 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 560 561 /* iicbus interface */ 562 DEVMETHOD(iicbus_callback, iicbus_null_callback), 563 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 564 DEVMETHOD(iicbus_start, i2c_start), 565 DEVMETHOD(iicbus_stop, i2c_stop), 566 DEVMETHOD(iicbus_reset, i2c_reset), 567 DEVMETHOD(iicbus_read, i2c_read), 568 DEVMETHOD(iicbus_write, i2c_write), 569 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 570 DEVMETHOD_END 571 }; 572 573 driver_t vf_i2c_driver = { 574 "i2c", 575 i2c_methods, 576 sizeof(struct vf_i2c_softc), 577 }; 578