1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 5 * Copyright (c) 2024 Pierre-Luc Drouin <pldrouin@pldrouin.net> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Vybrid Family Inter-Integrated Circuit (I2C) 31 * Chapter 48, Vybrid Reference Manual, Rev. 5, 07/2013 32 * 33 * The current implementation is based on the original driver by Ruslan Bukin, 34 * later modified by Dawid Górecki, and split into FDT and ACPI drivers by Val 35 * Packett. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/mutex.h> 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/malloc.h> 46 #include <sys/rman.h> 47 #include <sys/timeet.h> 48 #include <sys/timetc.h> 49 50 #include <dev/iicbus/iiconf.h> 51 #include <dev/iicbus/iicbus.h> 52 53 #include "iicbus_if.h" 54 55 #include <machine/bus.h> 56 #include <machine/cpu.h> 57 #include <machine/intr.h> 58 59 #include <dev/iicbus/controller/vybrid/vf_i2c.h> 60 61 #define I2C_IBAD 0x0 /* I2C Bus Address Register */ 62 #define I2C_IBFD 0x1 /* I2C Bus Frequency Divider Register */ 63 #define I2C_IBCR 0x2 /* I2C Bus Control Register */ 64 #define IBCR_MDIS (1 << 7) /* Module disable. */ 65 #define IBCR_IBIE (1 << 6) /* I-Bus Interrupt Enable. */ 66 #define IBCR_MSSL (1 << 5) /* Master/Slave mode select. */ 67 #define IBCR_TXRX (1 << 4) /* Transmit/Receive mode select. */ 68 #define IBCR_NOACK (1 << 3) /* Data Acknowledge disable. */ 69 #define IBCR_RSTA (1 << 2) /* Repeat Start. */ 70 #define IBCR_DMAEN (1 << 1) /* DMA Enable. */ 71 #define I2C_IBSR 0x3 /* I2C Bus Status Register */ 72 #define IBSR_TCF (1 << 7) /* Transfer complete. */ 73 #define IBSR_IAAS (1 << 6) /* Addressed as a slave. */ 74 #define IBSR_IBB (1 << 5) /* Bus busy. */ 75 #define IBSR_IBAL (1 << 4) /* Arbitration Lost. */ 76 #define IBSR_SRW (1 << 2) /* Slave Read/Write. */ 77 #define IBSR_IBIF (1 << 1) /* I-Bus Interrupt Flag. */ 78 #define IBSR_RXAK (1 << 0) /* Received Acknowledge. */ 79 #define I2C_IBDR 0x4 /* I2C Bus Data I/O Register */ 80 #define I2C_IBIC 0x5 /* I2C Bus Interrupt Config Register */ 81 #define IBIC_BIIE (1 << 7) /* Bus Idle Interrupt Enable bit. */ 82 #define I2C_IBDBG 0x6 /* I2C Bus Debug Register */ 83 84 #define DIV_REG_UNSET 0xFF 85 86 #define READ1(_sc, _reg) bus_space_read_1(_sc->bst, _sc->bsh, _reg) 87 #define WRITE1(_sc, _reg, _val) bus_space_write_1(_sc->bst,\ 88 _sc->bsh, _reg, _val) 89 90 #ifdef DEBUG 91 #define vf_i2c_dbg(_sc, fmt, args...) \ 92 device_printf((_sc)->dev, fmt, ##args) 93 #ifdef DEBUG2 94 #undef WRITE1 95 #define WRITE1(_sc, _reg, _val) ({\ 96 vf_i2c_dbg(_sc, "WRITE1 REG 0x%02X VAL 0x%02X\n",_reg,_val);\ 97 bus_space_write_1(_sc->bst, _sc->bsh, _reg, _val);\ 98 }) 99 #undef READ1 100 #define READ1(_sc, _reg) ({\ 101 uint32_t ret=bus_space_read_1(_sc->bst, _sc->bsh, _reg);\ 102 vf_i2c_dbg(_sc, "READ1 REG 0x%02X RETURNS 0x%02X\n",_reg,ret);\ 103 ret;\ 104 }) 105 #endif 106 #else 107 #define vf_i2c_dbg(_sc, fmt, args...) 108 #endif 109 110 static int i2c_repeated_start(device_t, u_char, int); 111 static int i2c_start(device_t, u_char, int); 112 static int i2c_stop(device_t); 113 static int i2c_reset(device_t, u_char, u_char, u_char *); 114 static int i2c_read(device_t, char *, int, int *, int, int); 115 static int i2c_write(device_t, const char *, int, int *, int); 116 117 struct i2c_div_type { 118 uint32_t reg_val; 119 uint32_t div; 120 }; 121 122 static struct resource_spec i2c_spec[] = { 123 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 124 { SYS_RES_IRQ, 0, RF_ACTIVE }, 125 { -1, 0 } 126 }; 127 128 static struct i2c_div_type vf610_div_table[] = { 129 { 0x00, 20 }, { 0x01, 22 }, { 0x02, 24 }, { 0x03, 26 }, 130 { 0x04, 28 }, { 0x05, 30 }, { 0x09, 32 }, { 0x06, 34 }, 131 { 0x0A, 36 }, { 0x0B, 40 }, { 0x0C, 44 }, { 0x0D, 48 }, 132 { 0x0E, 56 }, { 0x12, 64 }, { 0x13, 72 }, { 0x14, 80 }, 133 { 0x15, 88 }, { 0x19, 96 }, { 0x16, 104 }, { 0x1A, 112 }, 134 { 0x17, 128 }, { 0x1D, 160 }, { 0x1E, 192 }, { 0x22, 224 }, 135 { 0x1F, 240 }, { 0x23, 256 }, { 0x24, 288 }, { 0x25, 320 }, 136 { 0x26, 384 }, { 0x2A, 448 }, { 0x27, 480 }, { 0x2B, 512 }, 137 { 0x2C, 576 }, { 0x2D, 640 }, { 0x2E, 768 }, { 0x32, 896 }, 138 { 0x2F, 960 }, { 0x33, 1024 }, { 0x34, 1152 }, { 0x35, 1280 }, 139 { 0x36, 1536 }, { 0x3A, 1792 }, { 0x37, 1920 }, { 0x3B, 2048 }, 140 { 0x3C, 2304 }, { 0x3D, 2560 }, { 0x3E, 3072 }, { 0x3F, 3840 }, 141 { 0x3F, 3840 }, { 0x7B, 4096 }, { 0x7D, 5120 }, { 0x7E, 6144 }, 142 }; 143 144 int 145 vf_i2c_attach_common(device_t dev) 146 { 147 struct vf_i2c_softc *sc; 148 int error; 149 150 sc = device_get_softc(dev); 151 152 vf_i2c_dbg(sc, "i2c attach common\n"); 153 154 mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF); 155 156 error = bus_alloc_resources(dev, i2c_spec, sc->res); 157 if (error != 0) { 158 mtx_destroy(&sc->mutex); 159 device_printf(dev, "could not allocate resources\n"); 160 return (ENXIO); 161 } 162 163 /* Memory interface */ 164 sc->bst = rman_get_bustag(sc->res[0]); 165 sc->bsh = rman_get_bushandle(sc->res[0]); 166 167 mtx_lock(&sc->mutex); 168 169 WRITE1(sc, I2C_IBIC, IBIC_BIIE); 170 171 if (sc->freq == 0) { 172 uint8_t div_reg; 173 174 div_reg = READ1(sc, I2C_IBFD); 175 176 if (div_reg != 0x00) { 177 sc->freq = UINT32_MAX; 178 device_printf(dev, "Using existing bus frequency divider register value (0x%02X).\n", div_reg); 179 } else { 180 device_printf(dev, "Bus frequency divider value appears unset, defaulting to low I2C bus speed.\n"); 181 } 182 } 183 184 mtx_unlock(&sc->mutex); 185 186 sc->iicbus = device_add_child(dev, "iicbus", -1); 187 if (sc->iicbus == NULL) { 188 device_printf(dev, "could not add iicbus child"); 189 mtx_destroy(&sc->mutex); 190 bus_release_resources(dev, i2c_spec, sc->res); 191 return (ENXIO); 192 } 193 194 bus_generic_attach(dev); 195 196 return (0); 197 } 198 199 static int 200 i2c_detach(device_t dev) 201 { 202 struct vf_i2c_softc *sc; 203 int error = 0; 204 205 sc = device_get_softc(dev); 206 vf_i2c_dbg(sc, "i2c detach\n"); 207 208 mtx_lock(&sc->mutex); 209 210 if (sc->freq == 0) { 211 vf_i2c_dbg(sc, "Writing 0x00 to clock divider register\n"); 212 WRITE1(sc, I2C_IBFD, 0x00); 213 } 214 215 error = bus_generic_detach(dev); 216 if (error != 0) { 217 device_printf(dev, "cannot detach child devices.\n"); 218 return (error); 219 } 220 221 error = device_delete_child(dev, sc->iicbus); 222 if (error != 0) { 223 device_printf(dev, "could not delete iicbus child.\n"); 224 return (error); 225 } 226 227 bus_release_resources(dev, i2c_spec, sc->res); 228 229 mtx_unlock(&sc->mutex); 230 231 mtx_destroy(&sc->mutex); 232 233 return (0); 234 } 235 236 /* Wait for transfer interrupt flag */ 237 static int 238 wait_for_iif(struct vf_i2c_softc *sc) 239 { 240 int retry; 241 242 retry = 1000; 243 while (retry --) { 244 if (READ1(sc, I2C_IBSR) & IBSR_IBIF) { 245 WRITE1(sc, I2C_IBSR, IBSR_IBIF); 246 return (IIC_NOERR); 247 } 248 DELAY(10); 249 } 250 251 return (IIC_ETIMEOUT); 252 } 253 254 /* Wait for free bus */ 255 static int 256 wait_for_nibb(struct vf_i2c_softc *sc) 257 { 258 int retry; 259 260 retry = 1000; 261 while (retry --) { 262 if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) 263 return (IIC_NOERR); 264 DELAY(10); 265 } 266 267 return (IIC_ETIMEOUT); 268 } 269 270 /* Wait for transfer complete+interrupt flag */ 271 static int 272 wait_for_icf(struct vf_i2c_softc *sc) 273 { 274 int retry; 275 276 retry = 1000; 277 while (retry --) { 278 if (READ1(sc, I2C_IBSR) & IBSR_TCF) { 279 if (READ1(sc, I2C_IBSR) & IBSR_IBIF) { 280 WRITE1(sc, I2C_IBSR, IBSR_IBIF); 281 return (IIC_NOERR); 282 } 283 } 284 DELAY(10); 285 } 286 287 return (IIC_ETIMEOUT); 288 } 289 /* Get ACK bit from last write */ 290 static bool 291 tx_acked(struct vf_i2c_softc *sc) 292 { 293 vf_i2c_dbg(sc, "i2c get ACK bit from last write\n"); 294 295 return (READ1(sc, I2C_IBSR) & IBSR_RXAK) ? false : true; 296 297 } 298 299 static int 300 i2c_repeated_start(device_t dev, u_char slave, int timeout) 301 { 302 struct vf_i2c_softc *sc; 303 int error; 304 int reg; 305 306 sc = device_get_softc(dev); 307 308 vf_i2c_dbg(sc, "i2c repeated start\n"); 309 310 mtx_lock(&sc->mutex); 311 312 WRITE1(sc, I2C_IBAD, slave); 313 314 if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) { 315 mtx_unlock(&sc->mutex); 316 return (IIC_EBUSERR); 317 } 318 319 /* Set repeated start condition */ 320 DELAY(10); 321 322 reg = READ1(sc, I2C_IBCR); 323 reg |= (IBCR_RSTA | IBCR_IBIE); 324 WRITE1(sc, I2C_IBCR, reg); 325 326 DELAY(10); 327 328 /* Write target address - LSB is R/W bit */ 329 WRITE1(sc, I2C_IBDR, slave); 330 331 error = wait_for_iif(sc); 332 333 if (!tx_acked(sc)) { 334 vf_i2c_dbg(sc, 335 "cant i2c start: missing ACK after slave addres\n"); 336 return (IIC_ENOACK); 337 } 338 339 mtx_unlock(&sc->mutex); 340 341 if (error != 0) 342 return (error); 343 344 return (IIC_NOERR); 345 } 346 347 static int 348 i2c_start(device_t dev, u_char slave, int timeout) 349 { 350 struct vf_i2c_softc *sc; 351 int error; 352 int reg; 353 354 sc = device_get_softc(dev); 355 356 vf_i2c_dbg(sc, "i2c start\n"); 357 358 mtx_lock(&sc->mutex); 359 360 WRITE1(sc, I2C_IBAD, slave); 361 362 if (READ1(sc, I2C_IBSR) & IBSR_IBB) { 363 mtx_unlock(&sc->mutex); 364 vf_i2c_dbg(sc, "cant i2c start: IIC_EBUSBSY\n"); 365 return (IIC_EBUSERR); 366 } 367 368 /* Set start condition */ 369 reg = (IBCR_MSSL | IBCR_NOACK | IBCR_IBIE); 370 WRITE1(sc, I2C_IBCR, reg); 371 372 DELAY(100); 373 374 reg |= (IBCR_TXRX); 375 WRITE1(sc, I2C_IBCR, reg); 376 377 /* Write target address - LSB is R/W bit */ 378 WRITE1(sc, I2C_IBDR, slave); 379 380 error = wait_for_iif(sc); 381 if (error != 0) { 382 mtx_unlock(&sc->mutex); 383 vf_i2c_dbg(sc, "cant i2c start: iif error\n"); 384 return (error); 385 } 386 mtx_unlock(&sc->mutex); 387 388 if (!tx_acked(sc)) { 389 vf_i2c_dbg(sc, 390 "cant i2c start: missing QACK after slave addres\n"); 391 return (IIC_ENOACK); 392 } 393 394 return (IIC_NOERR); 395 } 396 397 static int 398 i2c_stop(device_t dev) 399 { 400 struct vf_i2c_softc *sc; 401 402 sc = device_get_softc(dev); 403 404 vf_i2c_dbg(sc, "i2c stop\n"); 405 406 mtx_lock(&sc->mutex); 407 408 WRITE1(sc, I2C_IBCR, IBCR_NOACK | IBCR_IBIE); 409 410 DELAY(100); 411 412 /* Reset controller if bus still busy after STOP */ 413 if (wait_for_nibb(sc) == IIC_ETIMEOUT) { 414 WRITE1(sc, I2C_IBCR, IBCR_MDIS); 415 DELAY(1000); 416 WRITE1(sc, I2C_IBCR, IBCR_NOACK); 417 } 418 mtx_unlock(&sc->mutex); 419 420 return (IIC_NOERR); 421 } 422 423 static uint8_t 424 i2c_get_div_val(device_t dev) 425 { 426 struct vf_i2c_softc *sc; 427 uint8_t div_reg = DIV_REG_UNSET; 428 429 sc = device_get_softc(dev); 430 431 if (sc->freq == UINT32_MAX) 432 return div_reg; 433 #ifndef FDT 434 div_reg = vf610_div_table[nitems(vf610_div_table) - 1].reg_val; 435 #else 436 if (sc->hwtype == HW_MVF600) 437 div_reg = MVF600_DIV_REG; 438 else if (sc->freq == 0) 439 div_reg = vf610_div_table[nitems(vf610_div_table) - 1].reg_val; 440 else { 441 uint64_t clk_freq; 442 int error, i; 443 444 error = clk_get_freq(sc->clock, &clk_freq); 445 if (error != 0) { 446 device_printf(dev, "Could not get parent clock frequency. " 447 "Using default divider.\n"); 448 div_reg = vf610_div_table[nitems(vf610_div_table) - 1].reg_val; 449 } else { 450 451 for (i = 0; i < nitems(vf610_div_table) - 1; i++) 452 if ((clk_freq / vf610_div_table[i].div) <= sc->freq) 453 break; 454 div_reg = vf610_div_table[i].reg_val; 455 } 456 } 457 #endif 458 vf_i2c_dbg(sc, "Writing 0x%02X to clock divider register\n", div_reg); 459 return div_reg; 460 } 461 462 static int 463 i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 464 { 465 struct vf_i2c_softc *sc; 466 uint8_t div_reg; 467 468 sc = device_get_softc(dev); 469 div_reg = i2c_get_div_val(dev); 470 vf_i2c_dbg(sc, "i2c reset\n"); 471 472 switch (speed) { 473 case IIC_FAST: 474 case IIC_SLOW: 475 case IIC_UNKNOWN: 476 case IIC_FASTEST: 477 default: 478 break; 479 } 480 481 mtx_lock(&sc->mutex); 482 WRITE1(sc, I2C_IBCR, IBCR_MDIS); 483 484 DELAY(1000); 485 486 if(div_reg != DIV_REG_UNSET) 487 WRITE1(sc, I2C_IBFD, div_reg); 488 489 WRITE1(sc, I2C_IBCR, 0x0); /* Enable i2c */ 490 491 DELAY(1000); 492 493 mtx_unlock(&sc->mutex); 494 495 return (IIC_NOERR); 496 } 497 498 static int 499 i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 500 { 501 struct vf_i2c_softc *sc; 502 int error; 503 504 sc = device_get_softc(dev); 505 506 vf_i2c_dbg(sc, "i2c read\n"); 507 508 *read = 0; 509 510 mtx_lock(&sc->mutex); 511 512 if (len) { 513 if (len == 1) 514 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | \ 515 IBCR_NOACK); 516 else 517 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL); 518 519 /* dummy read */ 520 READ1(sc, I2C_IBDR); 521 DELAY(1000); 522 } 523 524 while (*read < len) { 525 error = wait_for_icf(sc); 526 if (error != 0) { 527 mtx_unlock(&sc->mutex); 528 return (error); 529 } 530 531 if ((*read == len - 2) && last) { 532 /* NO ACK on last byte */ 533 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL | \ 534 IBCR_NOACK); 535 } 536 537 if ((*read == len - 1) && last) { 538 /* Transfer done, remove master bit */ 539 WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_NOACK); 540 } 541 542 *buf++ = READ1(sc, I2C_IBDR); 543 (*read)++; 544 } 545 mtx_unlock(&sc->mutex); 546 547 return (IIC_NOERR); 548 } 549 550 static int 551 i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 552 { 553 struct vf_i2c_softc *sc; 554 int error; 555 556 sc = device_get_softc(dev); 557 558 vf_i2c_dbg(sc, "i2c write\n"); 559 560 *sent = 0; 561 562 mtx_lock(&sc->mutex); 563 while (*sent < len) { 564 WRITE1(sc, I2C_IBDR, *buf++); 565 566 error = wait_for_iif(sc); 567 if (error != 0) { 568 mtx_unlock(&sc->mutex); 569 return (error); 570 } 571 572 if (!tx_acked(sc) && (*sent = (len - 2)) ){ 573 mtx_unlock(&sc->mutex); 574 vf_i2c_dbg(sc, "no ACK on %d write\n", *sent); 575 return (IIC_ENOACK); 576 } 577 578 (*sent)++; 579 } 580 mtx_unlock(&sc->mutex); 581 return (IIC_NOERR); 582 } 583 584 static device_method_t i2c_methods[] = { 585 /* Device interface */ 586 DEVMETHOD(device_detach, i2c_detach), 587 588 /* Device interface */ 589 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 590 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 591 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 592 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 593 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 594 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 595 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 596 597 /* iicbus interface */ 598 DEVMETHOD(iicbus_callback, iicbus_null_callback), 599 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 600 DEVMETHOD(iicbus_start, i2c_start), 601 DEVMETHOD(iicbus_stop, i2c_stop), 602 DEVMETHOD(iicbus_reset, i2c_reset), 603 DEVMETHOD(iicbus_read, i2c_read), 604 DEVMETHOD(iicbus_write, i2c_write), 605 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 606 DEVMETHOD_END 607 }; 608 609 driver_t vf_i2c_driver = { 610 "i2c", 611 i2c_methods, 612 sizeof(struct vf_i2c_softc), 613 }; 614