1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019-2020 Thomas Skibo <thomasskibo@yahoo.com> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Cadence / Zynq i2c driver. 29 * 30 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 31 * (v1.12.2) July 1, 2018. Xilinx doc UG585. I2C Controller is documented 32 * in Chapter 20. 33 */ 34 35 #include <sys/cdefs.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/conf.h> 39 #include <sys/kernel.h> 40 #include <sys/module.h> 41 #include <sys/sysctl.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/resource.h> 45 #include <sys/rman.h> 46 #include <sys/uio.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #include <machine/stdarg.h> 51 52 #include <dev/fdt/fdt_common.h> 53 #include <dev/ofw/ofw_bus.h> 54 #include <dev/ofw/ofw_bus_subr.h> 55 56 #include <dev/extres/clk/clk.h> 57 58 #include <dev/iicbus/iiconf.h> 59 #include <dev/iicbus/iicbus.h> 60 61 #include "iicbus_if.h" 62 63 #ifdef I2CDEBUG 64 #define DPRINTF(...) do { printf(__VA_ARGS__); } while (0) 65 #else 66 #define DPRINTF(...) do { } while (0) 67 #endif 68 69 #if 0 70 #define HWTYPE_CDNS_R1P10 1 71 #endif 72 #define HWTYPE_CDNS_R1P14 2 73 74 static struct ofw_compat_data compat_data[] = { 75 #if 0 76 {"cdns,i2c-r1p10", HWTYPE_CDNS_R1P10}, 77 #endif 78 {"cdns,i2c-r1p14", HWTYPE_CDNS_R1P14}, 79 {NULL, 0} 80 }; 81 82 struct cdnc_i2c_softc { 83 device_t dev; 84 device_t iicbus; 85 struct mtx sc_mtx; 86 struct resource *mem_res; 87 struct resource *irq_res; 88 void *intrhandle; 89 90 uint16_t cfg_reg_shadow; 91 uint16_t istat; 92 clk_t ref_clk; 93 uint32_t ref_clock_freq; 94 uint32_t i2c_clock_freq; 95 96 int hwtype; 97 int hold; 98 99 /* sysctls */ 100 unsigned int i2c_clk_real_freq; 101 unsigned int interrupts; 102 unsigned int timeout_ints; 103 }; 104 105 #define I2C_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 106 #define I2C_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 107 #define I2C_SC_LOCK_INIT(sc) \ 108 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF) 109 #define I2C_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) 110 #define I2C_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 111 112 #define RD2(sc, off) (bus_read_2((sc)->mem_res, (off))) 113 #define WR2(sc, off, val) (bus_write_2((sc)->mem_res, (off), (val))) 114 #define RD1(sc, off) (bus_read_1((sc)->mem_res, (off))) 115 #define WR1(sc, off, val) (bus_write_1((sc)->mem_res, (off), (val))) 116 117 /* Cadence I2C controller device registers. */ 118 #define CDNC_I2C_CR 0x0000 /* Config register. */ 119 #define CDNC_I2C_CR_DIV_A_MASK (3 << 14) 120 #define CDNC_I2C_CR_DIV_A_SHIFT 14 121 #define CDNC_I2C_CR_DIV_A(a) ((a) << 14) 122 #define CDNC_I2C_CR_DIV_A_MAX 3 123 #define CDNC_I2C_CR_DIV_B_MASK (0x3f << 8) 124 #define CDNC_I2C_CR_DIV_B_SHIFT 8 125 #define CDNC_I2C_CR_DIV_B(b) ((b) << 8) 126 #define CDNC_I2C_CR_DIV_B_MAX 63 127 #define CDNC_I2C_CR_CLR_FIFO (1 << 6) 128 #define CDNC_I2C_CR_SLVMON_MODE (1 << 5) 129 #define CDNC_I2C_CR_HOLD (1 << 4) 130 #define CDNC_I2C_CR_ACKEN (1 << 3) 131 #define CDNC_I2C_CR_NEA (1 << 2) 132 #define CDNC_I2C_CR_MAST (1 << 1) 133 #define CDNC_I2C_CR_RNW (1 << 0) 134 135 #define CDNC_I2C_SR 0x0004 /* Status register. */ 136 #define CDNC_I2C_SR_BUS_ACTIVE (1 << 8) 137 #define CDNC_I2C_SR_RX_OVF (1 << 7) 138 #define CDNC_I2C_SR_TX_VALID (1 << 6) 139 #define CDNC_I2C_SR_RX_VALID (1 << 5) 140 #define CDNC_I2C_SR_RXRW (1 << 3) 141 142 #define CDNC_I2C_ADDR 0x0008 /* i2c address register. */ 143 #define CDNC_I2C_DATA 0x000C /* i2c data register. */ 144 145 #define CDNC_I2C_ISR 0x0010 /* Int status register. */ 146 #define CDNC_I2C_ISR_ARB_LOST (1 << 9) 147 #define CDNC_I2C_ISR_RX_UNDF (1 << 7) 148 #define CDNC_I2C_ISR_TX_OVF (1 << 6) 149 #define CDNC_I2C_ISR_RX_OVF (1 << 5) 150 #define CDNC_I2C_ISR_SLV_RDY (1 << 4) 151 #define CDNC_I2C_ISR_XFER_TMOUT (1 << 3) 152 #define CDNC_I2C_ISR_XFER_NACK (1 << 2) 153 #define CDNC_I2C_ISR_XFER_DATA (1 << 1) 154 #define CDNC_I2C_ISR_XFER_DONE (1 << 0) 155 #define CDNC_I2C_ISR_ALL 0x2ff 156 #define CDNC_I2C_TRANS_SIZE 0x0014 /* Transfer size. */ 157 #define CDNC_I2C_PAUSE 0x0018 /* Slv Monitor Pause reg. */ 158 #define CDNC_I2C_TIME_OUT 0x001C /* Time-out register. */ 159 #define CDNC_I2C_TIME_OUT_MIN 31 160 #define CDNC_I2C_TIME_OUT_MAX 255 161 #define CDNC_I2C_IMR 0x0020 /* Int mask register. */ 162 #define CDNC_I2C_IER 0x0024 /* Int enable register. */ 163 #define CDNC_I2C_IDR 0x0028 /* Int disable register. */ 164 165 #define CDNC_I2C_FIFO_SIZE 16 166 #define CDNC_I2C_DEFAULT_I2C_CLOCK 400000 /* 400Khz default */ 167 168 #define CDNC_I2C_ISR_ERRS (CDNC_I2C_ISR_ARB_LOST | CDNC_I2C_ISR_RX_UNDF | \ 169 CDNC_I2C_ISR_TX_OVF | CDNC_I2C_ISR_RX_OVF | CDNC_I2C_ISR_XFER_TMOUT | \ 170 CDNC_I2C_ISR_XFER_NACK) 171 172 /* Configure clock dividers. */ 173 static int 174 cdnc_i2c_set_freq(struct cdnc_i2c_softc *sc) 175 { 176 uint32_t div_a, div_b, err, clk_out; 177 uint32_t best_div_a, best_div_b, best_err; 178 179 best_div_a = 0; 180 best_div_b = 0; 181 best_err = ~0U; 182 183 /* 184 * The i2c controller has a two-stage clock divider to create 185 * the "clock enable" signal used to sample the incoming SCL and 186 * SDA signals. The Clock Enable signal is divided by 22 to create 187 * the outgoing SCL signal. 188 * 189 * Try all div_a values and pick best match. 190 */ 191 for (div_a = 0; div_a <= CDNC_I2C_CR_DIV_A_MAX; div_a++) { 192 div_b = sc->ref_clock_freq / (22 * sc->i2c_clock_freq * 193 (div_a + 1)); 194 if (div_b > CDNC_I2C_CR_DIV_B_MAX) 195 continue; 196 clk_out = sc->ref_clock_freq / (22 * (div_a + 1) * 197 (div_b + 1)); 198 err = clk_out > sc->i2c_clock_freq ? 199 clk_out - sc->i2c_clock_freq : 200 sc->i2c_clock_freq - clk_out; 201 if (err < best_err) { 202 best_err = err; 203 best_div_a = div_a; 204 best_div_b = div_b; 205 } 206 } 207 208 if (best_err == ~0U) { 209 device_printf(sc->dev, "cannot configure clock divider.\n"); 210 return (EINVAL); /* out of range */ 211 } 212 213 clk_out = sc->ref_clock_freq / (22 * (best_div_a + 1) * 214 (best_div_b + 1)); 215 216 DPRINTF("%s: ref_clock_freq=%d i2c_clock_freq=%d\n", __func__, 217 sc->ref_clock_freq, sc->i2c_clock_freq); 218 DPRINTF("%s: div_a=%d div_b=%d real-freq=%d\n", __func__, best_div_a, 219 best_div_b, clk_out); 220 221 sc->cfg_reg_shadow &= ~(CDNC_I2C_CR_DIV_A_MASK | 222 CDNC_I2C_CR_DIV_B_MASK); 223 sc->cfg_reg_shadow |= CDNC_I2C_CR_DIV_A(best_div_a) | 224 CDNC_I2C_CR_DIV_B(best_div_b); 225 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow); 226 227 sc->i2c_clk_real_freq = clk_out; 228 229 return (0); 230 } 231 232 /* Initialize hardware. */ 233 static int 234 cdnc_i2c_init_hw(struct cdnc_i2c_softc *sc) 235 { 236 237 /* Reset config register and clear FIFO. */ 238 sc->cfg_reg_shadow = 0; 239 WR2(sc, CDNC_I2C_CR, CDNC_I2C_CR_CLR_FIFO); 240 sc->hold = 0; 241 242 /* Clear and disable all interrupts. */ 243 WR2(sc, CDNC_I2C_ISR, CDNC_I2C_ISR_ALL); 244 WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_ALL); 245 246 /* Max out bogus time-out register. */ 247 WR1(sc, CDNC_I2C_TIME_OUT, CDNC_I2C_TIME_OUT_MAX); 248 249 /* Set up clock dividers. */ 250 return (cdnc_i2c_set_freq(sc)); 251 } 252 253 static int 254 cdnc_i2c_errs(struct cdnc_i2c_softc *sc, uint16_t istat) 255 { 256 257 DPRINTF("%s: istat=0x%x\n", __func__, istat); 258 259 /* XXX: clean up after errors. */ 260 261 /* Reset config register and clear FIFO. */ 262 sc->cfg_reg_shadow &= CDNC_I2C_CR_DIV_A_MASK | CDNC_I2C_CR_DIV_B_MASK; 263 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow | CDNC_I2C_CR_CLR_FIFO); 264 sc->hold = 0; 265 266 if (istat & CDNC_I2C_ISR_XFER_TMOUT) 267 return (IIC_ETIMEOUT); 268 else if (istat & CDNC_I2C_ISR_RX_UNDF) 269 return (IIC_EUNDERFLOW); 270 else if (istat & (CDNC_I2C_ISR_RX_OVF | CDNC_I2C_ISR_TX_OVF)) 271 return (IIC_EOVERFLOW); 272 else if (istat & CDNC_I2C_ISR_XFER_NACK) 273 return (IIC_ENOACK); 274 else if (istat & CDNC_I2C_ISR_ARB_LOST) 275 return (IIC_EBUSERR); /* XXX: ???? */ 276 else 277 /* Should not happen */ 278 return (IIC_NOERR); 279 } 280 281 static int 282 cdnc_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 283 { 284 struct cdnc_i2c_softc *sc = device_get_softc(dev); 285 int error; 286 287 DPRINTF("%s: speed=%d addr=0x%x\n", __func__, speed, addr); 288 289 I2C_SC_LOCK(sc); 290 291 sc->i2c_clock_freq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 292 293 error = cdnc_i2c_init_hw(sc); 294 295 I2C_SC_UNLOCK(sc); 296 297 return (error ? IIC_ENOTSUPP : IIC_NOERR); 298 } 299 300 static void 301 cdnc_i2c_intr(void *arg) 302 { 303 struct cdnc_i2c_softc *sc = (struct cdnc_i2c_softc *)arg; 304 uint16_t status; 305 306 I2C_SC_LOCK(sc); 307 308 sc->interrupts++; 309 310 /* Read active interrupts. */ 311 status = RD2(sc, CDNC_I2C_ISR) & ~RD2(sc, CDNC_I2C_IMR); 312 313 /* Clear interrupts. */ 314 WR2(sc, CDNC_I2C_ISR, status); 315 316 if (status & CDNC_I2C_ISR_XFER_TMOUT) 317 sc->timeout_ints++; 318 319 sc->istat |= status; 320 321 if (status) 322 wakeup(sc); 323 324 I2C_SC_UNLOCK(sc); 325 } 326 327 static int 328 cdnc_i2c_xfer_rd(struct cdnc_i2c_softc *sc, struct iic_msg *msg) 329 { 330 int error = IIC_NOERR; 331 uint16_t flags = msg->flags; 332 uint16_t len = msg->len; 333 int idx = 0, nbytes, last, first = 1; 334 uint16_t statr; 335 336 DPRINTF("%s: flags=0x%x len=%d\n", __func__, flags, len); 337 338 #if 0 339 if (sc->hwtype == HWTYPE_CDNS_R1P10 && (flags & IIC_M_NOSTOP)) 340 return (IIC_ENOTSUPP); 341 #endif 342 343 I2C_SC_ASSERT_LOCKED(sc); 344 345 /* Program config register. */ 346 sc->cfg_reg_shadow &= CDNC_I2C_CR_DIV_A_MASK | CDNC_I2C_CR_DIV_B_MASK; 347 sc->cfg_reg_shadow |= CDNC_I2C_CR_HOLD | CDNC_I2C_CR_ACKEN | 348 CDNC_I2C_CR_NEA | CDNC_I2C_CR_MAST | CDNC_I2C_CR_RNW; 349 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow | CDNC_I2C_CR_CLR_FIFO); 350 sc->hold = 1; 351 352 while (len > 0) { 353 nbytes = MIN(CDNC_I2C_FIFO_SIZE - 2, len); 354 WR1(sc, CDNC_I2C_TRANS_SIZE, nbytes); 355 356 last = nbytes == len && !(flags & IIC_M_NOSTOP); 357 if (last) { 358 /* Clear HOLD bit on last transfer. */ 359 sc->cfg_reg_shadow &= ~CDNC_I2C_CR_HOLD; 360 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow); 361 sc->hold = 0; 362 } 363 364 /* Writing slv address for a start or repeated start. */ 365 if (first && !(flags & IIC_M_NOSTART)) 366 WR2(sc, CDNC_I2C_ADDR, msg->slave >> 1); 367 first = 0; 368 369 /* Enable FIFO interrupts and wait. */ 370 if (last) 371 WR2(sc, CDNC_I2C_IER, CDNC_I2C_ISR_XFER_DONE | 372 CDNC_I2C_ISR_ERRS); 373 else 374 WR2(sc, CDNC_I2C_IER, CDNC_I2C_ISR_XFER_DATA | 375 CDNC_I2C_ISR_ERRS); 376 377 error = mtx_sleep(sc, &sc->sc_mtx, 0, "cdi2c", hz); 378 379 /* Disable FIFO interrupts. */ 380 WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_XFER_DATA | 381 CDNC_I2C_ISR_XFER_DONE | CDNC_I2C_ISR_ERRS); 382 383 if (error == EWOULDBLOCK) 384 error = cdnc_i2c_errs(sc, CDNC_I2C_ISR_XFER_TMOUT); 385 else if (sc->istat & CDNC_I2C_ISR_ERRS) 386 error = cdnc_i2c_errs(sc, sc->istat); 387 sc->istat = 0; 388 389 if (error != IIC_NOERR) 390 break; 391 392 /* Read nbytes from FIFO. */ 393 while (nbytes-- > 0) { 394 statr = RD2(sc, CDNC_I2C_SR); 395 if (!(statr & CDNC_I2C_SR_RX_VALID)) { 396 printf("%s: RX FIFO underflow?\n", __func__); 397 break; 398 } 399 msg->buf[idx++] = RD2(sc, CDNC_I2C_DATA); 400 len--; 401 } 402 } 403 404 return (error); 405 } 406 407 static int 408 cdnc_i2c_xfer_wr(struct cdnc_i2c_softc *sc, struct iic_msg *msg) 409 { 410 int error = IIC_NOERR; 411 uint16_t flags = msg->flags; 412 uint16_t len = msg->len; 413 int idx = 0, nbytes, last, first = 1; 414 415 DPRINTF("%s: flags=0x%x len=%d\n", __func__, flags, len); 416 417 I2C_SC_ASSERT_LOCKED(sc); 418 419 /* Program config register. */ 420 sc->cfg_reg_shadow &= CDNC_I2C_CR_DIV_A_MASK | CDNC_I2C_CR_DIV_B_MASK; 421 sc->cfg_reg_shadow |= CDNC_I2C_CR_HOLD | CDNC_I2C_CR_ACKEN | 422 CDNC_I2C_CR_NEA | CDNC_I2C_CR_MAST; 423 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow | CDNC_I2C_CR_CLR_FIFO); 424 sc->hold = 1; 425 426 while (len > 0) { 427 /* Put as much data into fifo as you can. */ 428 nbytes = MIN(len, CDNC_I2C_FIFO_SIZE - 429 RD1(sc, CDNC_I2C_TRANS_SIZE) - 1); 430 len -= nbytes; 431 while (nbytes-- > 0) 432 WR2(sc, CDNC_I2C_DATA, msg->buf[idx++]); 433 434 last = len == 0 && !(flags & IIC_M_NOSTOP); 435 if (last) { 436 /* Clear HOLD bit on last transfer. */ 437 sc->cfg_reg_shadow &= ~CDNC_I2C_CR_HOLD; 438 WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow); 439 sc->hold = 0; 440 } 441 442 /* Perform START if this is start or repeated start. */ 443 if (first && !(flags & IIC_M_NOSTART)) 444 WR2(sc, CDNC_I2C_ADDR, msg->slave >> 1); 445 first = 0; 446 447 /* Enable FIFO interrupts. */ 448 WR2(sc, CDNC_I2C_IER, CDNC_I2C_ISR_XFER_DONE | 449 CDNC_I2C_ISR_ERRS); 450 451 /* Wait for end of data transfer. */ 452 error = mtx_sleep(sc, &sc->sc_mtx, 0, "cdi2c", hz); 453 454 /* Disable FIFO interrupts. */ 455 WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_XFER_DONE | 456 CDNC_I2C_ISR_ERRS); 457 458 if (error == EWOULDBLOCK) 459 error = cdnc_i2c_errs(sc, CDNC_I2C_ISR_XFER_TMOUT); 460 else if (sc->istat & CDNC_I2C_ISR_ERRS) 461 error = cdnc_i2c_errs(sc, sc->istat); 462 sc->istat = 0; 463 if (error) 464 break; 465 } 466 467 return (error); 468 } 469 470 static int 471 cdnc_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 472 { 473 struct cdnc_i2c_softc *sc = device_get_softc(dev); 474 int i, error = IIC_NOERR; 475 476 DPRINTF("%s: nmsgs=%d\n", __func__, nmsgs); 477 478 I2C_SC_LOCK(sc); 479 480 for (i = 0; i < nmsgs; i++) { 481 DPRINTF("%s: msg[%d]: hold=%d slv=0x%x flags=0x%x len=%d\n", 482 __func__, i, sc->hold, msgs[i].slave, msgs[i].flags, 483 msgs[i].len); 484 485 if (!sc->hold && (msgs[i].flags & IIC_M_NOSTART)) 486 return (IIC_ENOTSUPP); 487 488 if (msgs[i].flags & IIC_M_RD) { 489 error = cdnc_i2c_xfer_rd(sc, &msgs[i]); 490 if (error != IIC_NOERR) 491 break; 492 } else { 493 error = cdnc_i2c_xfer_wr(sc, &msgs[i]); 494 if (error != IIC_NOERR) 495 break; 496 } 497 } 498 499 I2C_SC_UNLOCK(sc); 500 501 return (error); 502 } 503 504 static void 505 cdnc_i2c_add_sysctls(device_t dev) 506 { 507 struct cdnc_i2c_softc *sc = device_get_softc(dev); 508 struct sysctl_ctx_list *ctx; 509 struct sysctl_oid_list *child; 510 511 ctx = device_get_sysctl_ctx(dev); 512 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 513 514 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "i2c_clk_real_freq", CTLFLAG_RD, 515 &sc->i2c_clk_real_freq, 0, "i2c clock real frequency"); 516 517 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_interrupts", CTLFLAG_RD, 518 &sc->interrupts, 0, "interrupt calls"); 519 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_timeouts", CTLFLAG_RD, 520 &sc->timeout_ints, 0, "hardware timeout interrupts"); 521 } 522 523 524 static int 525 cdnc_i2c_probe(device_t dev) 526 { 527 528 if (!ofw_bus_status_okay(dev)) 529 return (ENXIO); 530 531 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 532 return (ENXIO); 533 534 device_set_desc(dev, "Cadence I2C Controller"); 535 536 return (BUS_PROBE_DEFAULT); 537 } 538 539 540 static int cdnc_i2c_detach(device_t); 541 542 static int 543 cdnc_i2c_attach(device_t dev) 544 { 545 struct cdnc_i2c_softc *sc; 546 int rid, err; 547 phandle_t node; 548 pcell_t cell; 549 uint64_t freq; 550 551 sc = device_get_softc(dev); 552 sc->dev = dev; 553 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 554 555 I2C_SC_LOCK_INIT(sc); 556 557 /* Get ref-clock and i2c-clock properties. */ 558 node = ofw_bus_get_node(dev); 559 if (OF_getprop(node, "ref-clock", &cell, sizeof(cell)) > 0) 560 sc->ref_clock_freq = fdt32_to_cpu(cell); 561 else if (clk_get_by_ofw_index(dev, node, 0, &sc->ref_clk) == 0) { 562 if ((err = clk_enable(sc->ref_clk)) != 0) 563 device_printf(dev, "Cannot enable clock. err=%d\n", 564 err); 565 else if ((err = clk_get_freq(sc->ref_clk, &freq)) != 0) 566 device_printf(dev, 567 "Cannot get clock frequency. err=%d\n", err); 568 else 569 sc->ref_clock_freq = freq; 570 } 571 else { 572 device_printf(dev, "must have ref-clock property\n"); 573 return (ENXIO); 574 } 575 if (OF_getprop(node, "clock-frequency", &cell, sizeof(cell)) > 0) 576 sc->i2c_clock_freq = fdt32_to_cpu(cell); 577 else 578 sc->i2c_clock_freq = CDNC_I2C_DEFAULT_I2C_CLOCK; 579 580 /* Get memory resource. */ 581 rid = 0; 582 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 583 RF_ACTIVE); 584 if (sc->mem_res == NULL) { 585 device_printf(dev, "could not allocate memory resources.\n"); 586 cdnc_i2c_detach(dev); 587 return (ENOMEM); 588 } 589 590 /* Allocate IRQ. */ 591 rid = 0; 592 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 593 RF_ACTIVE); 594 if (sc->irq_res == NULL) { 595 device_printf(dev, "could not allocate IRQ resource.\n"); 596 cdnc_i2c_detach(dev); 597 return (ENOMEM); 598 } 599 600 /* Activate the interrupt. */ 601 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 602 NULL, cdnc_i2c_intr, sc, &sc->intrhandle); 603 if (err) { 604 device_printf(dev, "could not setup IRQ.\n"); 605 cdnc_i2c_detach(dev); 606 return (err); 607 } 608 609 /* Configure the device. */ 610 err = cdnc_i2c_init_hw(sc); 611 if (err) { 612 cdnc_i2c_detach(dev); 613 return (err); 614 } 615 616 sc->iicbus = device_add_child(dev, "iicbus", -1); 617 618 cdnc_i2c_add_sysctls(dev); 619 620 /* Probe and attach iicbus when interrupts work. */ 621 return (bus_delayed_attach_children(dev)); 622 } 623 624 static int 625 cdnc_i2c_detach(device_t dev) 626 { 627 struct cdnc_i2c_softc *sc = device_get_softc(dev); 628 629 if (device_is_attached(dev)) 630 bus_generic_detach(dev); 631 632 if (sc->ref_clk != NULL) { 633 clk_release(sc->ref_clk); 634 sc->ref_clk = NULL; 635 } 636 637 /* Delete iic bus. */ 638 if (sc->iicbus) 639 device_delete_child(dev, sc->iicbus); 640 641 /* Disable hardware. */ 642 if (sc->mem_res != NULL) { 643 sc->cfg_reg_shadow = 0; 644 WR2(sc, CDNC_I2C_CR, CDNC_I2C_CR_CLR_FIFO); 645 646 /* Clear and disable all interrupts. */ 647 WR2(sc, CDNC_I2C_ISR, CDNC_I2C_ISR_ALL); 648 WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_ALL); 649 } 650 651 /* Teardown and release interrupt. */ 652 if (sc->irq_res != NULL) { 653 if (sc->intrhandle) 654 bus_teardown_intr(dev, sc->irq_res, sc->intrhandle); 655 bus_release_resource(dev, SYS_RES_IRQ, 656 rman_get_rid(sc->irq_res), sc->irq_res); 657 sc->irq_res = NULL; 658 } 659 660 /* Release memory resource. */ 661 if (sc->mem_res != NULL) { 662 bus_release_resource(dev, SYS_RES_MEMORY, 663 rman_get_rid(sc->mem_res), sc->mem_res); 664 sc->mem_res = NULL; 665 } 666 667 I2C_SC_LOCK_DESTROY(sc); 668 669 return (0); 670 } 671 672 673 static phandle_t 674 cdnc_i2c_get_node(device_t bus, device_t dev) 675 { 676 677 return (ofw_bus_get_node(bus)); 678 } 679 680 static device_method_t cdnc_i2c_methods[] = { 681 /* Device interface */ 682 DEVMETHOD(device_probe, cdnc_i2c_probe), 683 DEVMETHOD(device_attach, cdnc_i2c_attach), 684 DEVMETHOD(device_detach, cdnc_i2c_detach), 685 686 /* ofw_bus interface */ 687 DEVMETHOD(ofw_bus_get_node, cdnc_i2c_get_node), 688 689 /* iicbus methods */ 690 DEVMETHOD(iicbus_callback, iicbus_null_callback), 691 DEVMETHOD(iicbus_reset, cdnc_i2c_reset), 692 DEVMETHOD(iicbus_transfer, cdnc_i2c_transfer), 693 694 DEVMETHOD_END 695 }; 696 697 static driver_t cdnc_i2c_driver = { 698 "cdnc_i2c", 699 cdnc_i2c_methods, 700 sizeof(struct cdnc_i2c_softc), 701 }; 702 703 DRIVER_MODULE(cdnc_i2c, simplebus, cdnc_i2c_driver, NULL, NULL); 704 DRIVER_MODULE(ofw_iicbus, cdnc_i2c, ofw_iicbus_driver, NULL, NULL); 705 MODULE_DEPEND(cdnc_i2c, iicbus, 1, 1, 1); 706 MODULE_DEPEND(cdnc_i2c, ofw_iicbus, 1, 1, 1); 707 SIMPLEBUS_PNP_INFO(compat_data); 708