1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Matthew Macy <mmacy@mattmacy.io> 5 * All rights reserved. 6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include "if_igc.h" 32 33 #ifdef RSS 34 #include <net/rss_config.h> 35 #include <netinet/in_rss.h> 36 #endif 37 38 #ifdef VERBOSE_DEBUG 39 #define DPRINTF device_printf 40 #else 41 #define DPRINTF(...) 42 #endif 43 44 /********************************************************************* 45 * Local Function prototypes 46 *********************************************************************/ 47 static int igc_isc_txd_encap(void *arg, if_pkt_info_t pi); 48 static void igc_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx); 49 static int igc_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear); 50 51 static void igc_isc_rxd_refill(void *arg, if_rxd_update_t iru); 52 53 static void igc_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, 54 qidx_t pidx); 55 static int igc_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, 56 qidx_t budget); 57 58 static int igc_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri); 59 60 static int igc_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, 61 uint32_t *cmd_type_len, uint32_t *olinfo_status); 62 static int igc_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, 63 uint32_t *cmd_type_len, uint32_t *olinfo_status); 64 65 static void igc_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype); 66 static int igc_determine_rsstype(uint16_t pkt_info); 67 68 extern void igc_if_enable_intr(if_ctx_t ctx); 69 extern int igc_intr(void *arg); 70 71 struct if_txrx igc_txrx = { 72 .ift_txd_encap = igc_isc_txd_encap, 73 .ift_txd_flush = igc_isc_txd_flush, 74 .ift_txd_credits_update = igc_isc_txd_credits_update, 75 .ift_rxd_available = igc_isc_rxd_available, 76 .ift_rxd_pkt_get = igc_isc_rxd_pkt_get, 77 .ift_rxd_refill = igc_isc_rxd_refill, 78 .ift_rxd_flush = igc_isc_rxd_flush, 79 .ift_legacy_intr = igc_intr 80 }; 81 82 void 83 igc_dump_rs(struct igc_adapter *adapter) 84 { 85 if_softc_ctx_t scctx = adapter->shared; 86 struct igc_tx_queue *que; 87 struct tx_ring *txr; 88 qidx_t i, ntxd, qid, cur; 89 int16_t rs_cidx; 90 uint8_t status; 91 92 printf("\n"); 93 ntxd = scctx->isc_ntxd[0]; 94 for (qid = 0; qid < adapter->tx_num_queues; qid++) { 95 que = &adapter->tx_queues[qid]; 96 txr = &que->txr; 97 rs_cidx = txr->tx_rs_cidx; 98 if (rs_cidx != txr->tx_rs_pidx) { 99 cur = txr->tx_rsq[rs_cidx]; 100 status = txr->tx_base[cur].upper.fields.status; 101 if (!(status & IGC_TXD_STAT_DD)) 102 printf("qid[%d]->tx_rsq[%d]: %d clear ", qid, rs_cidx, cur); 103 } else { 104 rs_cidx = (rs_cidx-1)&(ntxd-1); 105 cur = txr->tx_rsq[rs_cidx]; 106 printf("qid[%d]->tx_rsq[rs_cidx-1=%d]: %d ", qid, rs_cidx, cur); 107 } 108 printf("cidx_prev=%d rs_pidx=%d ",txr->tx_cidx_processed, txr->tx_rs_pidx); 109 for (i = 0; i < ntxd; i++) { 110 if (txr->tx_base[i].upper.fields.status & IGC_TXD_STAT_DD) 111 printf("%d set ", i); 112 } 113 printf("\n"); 114 } 115 } 116 117 /********************************************************************** 118 * 119 * Setup work for hardware segmentation offload (TSO) on 120 * adapters using advanced tx descriptors 121 * 122 **********************************************************************/ 123 static int 124 igc_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len, 125 uint32_t *olinfo_status) 126 { 127 struct igc_adv_tx_context_desc *TXD; 128 uint32_t type_tucmd_mlhl = 0, vlan_macip_lens = 0; 129 uint32_t mss_l4len_idx = 0; 130 uint32_t paylen; 131 132 switch(pi->ipi_etype) { 133 case ETHERTYPE_IPV6: 134 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6; 135 break; 136 case ETHERTYPE_IP: 137 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4; 138 /* Tell transmit desc to also do IPv4 checksum. */ 139 *olinfo_status |= IGC_TXD_POPTS_IXSM << 8; 140 break; 141 default: 142 panic("%s: CSUM_TSO but no supported IP version (0x%04x)", 143 __func__, ntohs(pi->ipi_etype)); 144 break; 145 } 146 147 TXD = (struct igc_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 148 149 /* This is used in the transmit desc in encap */ 150 paylen = pi->ipi_len - pi->ipi_ehdrlen - pi->ipi_ip_hlen - pi->ipi_tcp_hlen; 151 152 /* VLAN MACLEN IPLEN */ 153 if (pi->ipi_mflags & M_VLANTAG) { 154 vlan_macip_lens |= (pi->ipi_vtag << IGC_ADVTXD_VLAN_SHIFT); 155 } 156 157 vlan_macip_lens |= pi->ipi_ehdrlen << IGC_ADVTXD_MACLEN_SHIFT; 158 vlan_macip_lens |= pi->ipi_ip_hlen; 159 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 160 161 /* ADV DTYPE TUCMD */ 162 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT; 163 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP; 164 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 165 166 /* MSS L4LEN IDX */ 167 mss_l4len_idx |= (pi->ipi_tso_segsz << IGC_ADVTXD_MSS_SHIFT); 168 mss_l4len_idx |= (pi->ipi_tcp_hlen << IGC_ADVTXD_L4LEN_SHIFT); 169 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 170 171 TXD->seqnum_seed = htole32(0); 172 *cmd_type_len |= IGC_ADVTXD_DCMD_TSE; 173 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 174 *olinfo_status |= paylen << IGC_ADVTXD_PAYLEN_SHIFT; 175 176 return (1); 177 } 178 179 /********************************************************************* 180 * 181 * Advanced Context Descriptor setup for VLAN, CSUM or TSO 182 * 183 **********************************************************************/ 184 static int 185 igc_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len, 186 uint32_t *olinfo_status) 187 { 188 struct igc_adv_tx_context_desc *TXD; 189 uint32_t vlan_macip_lens, type_tucmd_mlhl; 190 uint32_t mss_l4len_idx; 191 mss_l4len_idx = vlan_macip_lens = type_tucmd_mlhl = 0; 192 193 /* First check if TSO is to be used */ 194 if (pi->ipi_csum_flags & CSUM_TSO) 195 return (igc_tso_setup(txr, pi, cmd_type_len, olinfo_status)); 196 197 /* Indicate the whole packet as payload when not doing TSO */ 198 *olinfo_status |= pi->ipi_len << IGC_ADVTXD_PAYLEN_SHIFT; 199 200 /* Now ready a context descriptor */ 201 TXD = (struct igc_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 202 203 /* 204 ** In advanced descriptors the vlan tag must 205 ** be placed into the context descriptor. Hence 206 ** we need to make one even if not doing offloads. 207 */ 208 if (pi->ipi_mflags & M_VLANTAG) { 209 vlan_macip_lens |= (pi->ipi_vtag << IGC_ADVTXD_VLAN_SHIFT); 210 } else if ((pi->ipi_csum_flags & IGC_CSUM_OFFLOAD) == 0) { 211 return (0); 212 } 213 214 /* Set the ether header length */ 215 vlan_macip_lens |= pi->ipi_ehdrlen << IGC_ADVTXD_MACLEN_SHIFT; 216 217 switch(pi->ipi_etype) { 218 case ETHERTYPE_IP: 219 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4; 220 break; 221 case ETHERTYPE_IPV6: 222 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6; 223 break; 224 default: 225 break; 226 } 227 228 vlan_macip_lens |= pi->ipi_ip_hlen; 229 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT; 230 231 switch (pi->ipi_ipproto) { 232 case IPPROTO_TCP: 233 if (pi->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP)) { 234 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP; 235 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 236 } 237 break; 238 case IPPROTO_UDP: 239 if (pi->ipi_csum_flags & (CSUM_IP_UDP | CSUM_IP6_UDP)) { 240 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_UDP; 241 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 242 } 243 break; 244 case IPPROTO_SCTP: 245 if (pi->ipi_csum_flags & (CSUM_IP_SCTP | CSUM_IP6_SCTP)) { 246 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_SCTP; 247 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 248 } 249 break; 250 default: 251 break; 252 } 253 254 /* Now copy bits into descriptor */ 255 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 256 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 257 TXD->seqnum_seed = htole32(0); 258 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 259 260 return (1); 261 } 262 263 static int 264 igc_isc_txd_encap(void *arg, if_pkt_info_t pi) 265 { 266 struct igc_adapter *sc = arg; 267 if_softc_ctx_t scctx = sc->shared; 268 struct igc_tx_queue *que = &sc->tx_queues[pi->ipi_qsidx]; 269 struct tx_ring *txr = &que->txr; 270 int nsegs = pi->ipi_nsegs; 271 bus_dma_segment_t *segs = pi->ipi_segs; 272 union igc_adv_tx_desc *txd = NULL; 273 int i, j, pidx_last; 274 uint32_t olinfo_status, cmd_type_len, txd_flags; 275 qidx_t ntxd; 276 277 pidx_last = olinfo_status = 0; 278 /* Basic descriptor defines */ 279 cmd_type_len = (IGC_ADVTXD_DTYP_DATA | 280 IGC_ADVTXD_DCMD_IFCS | IGC_ADVTXD_DCMD_DEXT); 281 282 if (pi->ipi_mflags & M_VLANTAG) 283 cmd_type_len |= IGC_ADVTXD_DCMD_VLE; 284 285 i = pi->ipi_pidx; 286 ntxd = scctx->isc_ntxd[0]; 287 txd_flags = pi->ipi_flags & IPI_TX_INTR ? IGC_ADVTXD_DCMD_RS : 0; 288 /* Consume the first descriptor */ 289 i += igc_tx_ctx_setup(txr, pi, &cmd_type_len, &olinfo_status); 290 if (i == scctx->isc_ntxd[0]) 291 i = 0; 292 293 for (j = 0; j < nsegs; j++) { 294 bus_size_t seglen; 295 bus_addr_t segaddr; 296 297 txd = (union igc_adv_tx_desc *)&txr->tx_base[i]; 298 seglen = segs[j].ds_len; 299 segaddr = htole64(segs[j].ds_addr); 300 301 txd->read.buffer_addr = segaddr; 302 txd->read.cmd_type_len = htole32(IGC_ADVTXD_DCMD_IFCS | 303 cmd_type_len | seglen); 304 txd->read.olinfo_status = htole32(olinfo_status); 305 pidx_last = i; 306 if (++i == scctx->isc_ntxd[0]) { 307 i = 0; 308 } 309 } 310 if (txd_flags) { 311 txr->tx_rsq[txr->tx_rs_pidx] = pidx_last; 312 txr->tx_rs_pidx = (txr->tx_rs_pidx+1) & (ntxd-1); 313 MPASS(txr->tx_rs_pidx != txr->tx_rs_cidx); 314 } 315 316 txd->read.cmd_type_len |= htole32(IGC_ADVTXD_DCMD_EOP | txd_flags); 317 pi->ipi_new_pidx = i; 318 319 /* Sent data accounting for AIM */ 320 txr->tx_bytes += pi->ipi_len; 321 ++txr->tx_packets; 322 323 return (0); 324 } 325 326 static void 327 igc_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx) 328 { 329 struct igc_adapter *adapter = arg; 330 struct igc_tx_queue *que = &adapter->tx_queues[txqid]; 331 struct tx_ring *txr = &que->txr; 332 333 IGC_WRITE_REG(&adapter->hw, IGC_TDT(txr->me), pidx); 334 } 335 336 static int 337 igc_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear) 338 { 339 struct igc_adapter *adapter = arg; 340 if_softc_ctx_t scctx = adapter->shared; 341 struct igc_tx_queue *que = &adapter->tx_queues[txqid]; 342 struct tx_ring *txr = &que->txr; 343 344 qidx_t processed = 0; 345 int updated; 346 qidx_t cur, prev, ntxd, rs_cidx; 347 int32_t delta; 348 uint8_t status; 349 350 rs_cidx = txr->tx_rs_cidx; 351 if (rs_cidx == txr->tx_rs_pidx) 352 return (0); 353 cur = txr->tx_rsq[rs_cidx]; 354 status = ((union igc_adv_tx_desc *)&txr->tx_base[cur])->wb.status; 355 updated = !!(status & IGC_TXD_STAT_DD); 356 357 if (!updated) 358 return (0); 359 360 /* If clear is false just let caller know that there 361 * are descriptors to reclaim */ 362 if (!clear) 363 return (1); 364 365 prev = txr->tx_cidx_processed; 366 ntxd = scctx->isc_ntxd[0]; 367 do { 368 MPASS(prev != cur); 369 delta = (int32_t)cur - (int32_t)prev; 370 if (delta < 0) 371 delta += ntxd; 372 MPASS(delta > 0); 373 374 processed += delta; 375 prev = cur; 376 rs_cidx = (rs_cidx + 1) & (ntxd-1); 377 if (rs_cidx == txr->tx_rs_pidx) 378 break; 379 cur = txr->tx_rsq[rs_cidx]; 380 status = ((union igc_adv_tx_desc *)&txr->tx_base[cur])->wb.status; 381 } while ((status & IGC_TXD_STAT_DD)); 382 383 txr->tx_rs_cidx = rs_cidx; 384 txr->tx_cidx_processed = prev; 385 return (processed); 386 } 387 388 static void 389 igc_isc_rxd_refill(void *arg, if_rxd_update_t iru) 390 { 391 struct igc_adapter *sc = arg; 392 if_softc_ctx_t scctx = sc->shared; 393 uint16_t rxqid = iru->iru_qsidx; 394 struct igc_rx_queue *que = &sc->rx_queues[rxqid]; 395 union igc_adv_rx_desc *rxd; 396 struct rx_ring *rxr = &que->rxr; 397 uint64_t *paddrs; 398 uint32_t next_pidx, pidx; 399 uint16_t count; 400 int i; 401 402 paddrs = iru->iru_paddrs; 403 pidx = iru->iru_pidx; 404 count = iru->iru_count; 405 406 for (i = 0, next_pidx = pidx; i < count; i++) { 407 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[next_pidx]; 408 409 rxd->read.pkt_addr = htole64(paddrs[i]); 410 if (++next_pidx == scctx->isc_nrxd[0]) 411 next_pidx = 0; 412 } 413 } 414 415 static void 416 igc_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, qidx_t pidx) 417 { 418 struct igc_adapter *sc = arg; 419 struct igc_rx_queue *que = &sc->rx_queues[rxqid]; 420 struct rx_ring *rxr = &que->rxr; 421 422 IGC_WRITE_REG(&sc->hw, IGC_RDT(rxr->me), pidx); 423 } 424 425 static int 426 igc_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget) 427 { 428 struct igc_adapter *sc = arg; 429 if_softc_ctx_t scctx = sc->shared; 430 struct igc_rx_queue *que = &sc->rx_queues[rxqid]; 431 struct rx_ring *rxr = &que->rxr; 432 union igc_adv_rx_desc *rxd; 433 uint32_t staterr = 0; 434 int cnt, i; 435 436 for (cnt = 0, i = idx; cnt < scctx->isc_nrxd[0] && cnt <= budget;) { 437 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[i]; 438 staterr = le32toh(rxd->wb.upper.status_error); 439 440 if ((staterr & IGC_RXD_STAT_DD) == 0) 441 break; 442 if (++i == scctx->isc_nrxd[0]) 443 i = 0; 444 if (staterr & IGC_RXD_STAT_EOP) 445 cnt++; 446 } 447 return (cnt); 448 } 449 450 /**************************************************************** 451 * Routine sends data which has been dma'ed into host memory 452 * to upper layer. Initialize ri structure. 453 * 454 * Returns 0 upon success, errno on failure 455 ***************************************************************/ 456 457 static int 458 igc_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri) 459 { 460 struct igc_adapter *adapter = arg; 461 if_softc_ctx_t scctx = adapter->shared; 462 struct igc_rx_queue *que = &adapter->rx_queues[ri->iri_qsidx]; 463 struct rx_ring *rxr = &que->rxr; 464 union igc_adv_rx_desc *rxd; 465 466 uint16_t pkt_info, len; 467 uint32_t ptype, staterr; 468 int i, cidx; 469 bool eop; 470 471 staterr = i = 0; 472 cidx = ri->iri_cidx; 473 474 do { 475 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[cidx]; 476 staterr = le32toh(rxd->wb.upper.status_error); 477 pkt_info = le16toh(rxd->wb.lower.lo_dword.hs_rss.pkt_info); 478 479 MPASS ((staterr & IGC_RXD_STAT_DD) != 0); 480 481 len = le16toh(rxd->wb.upper.length); 482 ptype = le32toh(rxd->wb.lower.lo_dword.data) & IGC_PKTTYPE_MASK; 483 484 ri->iri_len += len; 485 rxr->rx_bytes += ri->iri_len; 486 487 rxd->wb.upper.status_error = 0; 488 eop = ((staterr & IGC_RXD_STAT_EOP) == IGC_RXD_STAT_EOP); 489 490 /* Make sure bad packets are discarded */ 491 if (eop && ((staterr & IGC_RXDEXT_STATERR_RXE) != 0)) { 492 adapter->dropped_pkts++; 493 ++rxr->rx_discarded; 494 return (EBADMSG); 495 } 496 ri->iri_frags[i].irf_flid = 0; 497 ri->iri_frags[i].irf_idx = cidx; 498 ri->iri_frags[i].irf_len = len; 499 500 if (++cidx == scctx->isc_nrxd[0]) 501 cidx = 0; 502 #ifdef notyet 503 if (rxr->hdr_split == true) { 504 ri->iri_frags[i].irf_flid = 1; 505 ri->iri_frags[i].irf_idx = cidx; 506 if (++cidx == scctx->isc_nrxd[0]) 507 cidx = 0; 508 } 509 #endif 510 i++; 511 } while (!eop); 512 513 rxr->rx_packets++; 514 515 if ((scctx->isc_capenable & IFCAP_RXCSUM) != 0) 516 igc_rx_checksum(staterr, ri, ptype); 517 518 if (staterr & IGC_RXD_STAT_VP) { 519 ri->iri_vtag = le16toh(rxd->wb.upper.vlan); 520 ri->iri_flags |= M_VLANTAG; 521 } 522 523 ri->iri_flowid = 524 le32toh(rxd->wb.lower.hi_dword.rss); 525 ri->iri_rsstype = igc_determine_rsstype(pkt_info); 526 ri->iri_nfrags = i; 527 528 return (0); 529 } 530 531 /********************************************************************* 532 * 533 * Verify that the hardware indicated that the checksum is valid. 534 * Inform the stack about the status of checksum so that stack 535 * doesn't spend time verifying the checksum. 536 * 537 *********************************************************************/ 538 static void 539 igc_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype) 540 { 541 uint16_t status = (uint16_t)staterr; 542 uint8_t errors = (uint8_t)(staterr >> 24); 543 544 if (__predict_false(status & IGC_RXD_STAT_IXSM)) 545 return; 546 547 /* If there is a layer 3 or 4 error we are done */ 548 if (__predict_false(errors & (IGC_RXD_ERR_IPE | IGC_RXD_ERR_TCPE))) 549 return; 550 551 /* IP Checksum Good */ 552 if (status & IGC_RXD_STAT_IPCS) 553 ri->iri_csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID); 554 555 /* Valid L4E checksum */ 556 if (__predict_true(status & 557 (IGC_RXD_STAT_TCPCS | IGC_RXD_STAT_UDPCS))) { 558 /* SCTP header present */ 559 if (__predict_false((ptype & IGC_RXDADV_PKTTYPE_ETQF) == 0 && 560 (ptype & IGC_RXDADV_PKTTYPE_SCTP) != 0)) { 561 ri->iri_csum_flags |= CSUM_SCTP_VALID; 562 } else { 563 ri->iri_csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 564 ri->iri_csum_data = htons(0xffff); 565 } 566 } 567 } 568 569 /******************************************************************** 570 * 571 * Parse the packet type to determine the appropriate hash 572 * 573 ******************************************************************/ 574 static int 575 igc_determine_rsstype(uint16_t pkt_info) 576 { 577 switch (pkt_info & IGC_RXDADV_RSSTYPE_MASK) { 578 case IGC_RXDADV_RSSTYPE_IPV4_TCP: 579 return M_HASHTYPE_RSS_TCP_IPV4; 580 case IGC_RXDADV_RSSTYPE_IPV4: 581 return M_HASHTYPE_RSS_IPV4; 582 case IGC_RXDADV_RSSTYPE_IPV6_TCP: 583 return M_HASHTYPE_RSS_TCP_IPV6; 584 case IGC_RXDADV_RSSTYPE_IPV6_EX: 585 return M_HASHTYPE_RSS_IPV6_EX; 586 case IGC_RXDADV_RSSTYPE_IPV6: 587 return M_HASHTYPE_RSS_IPV6; 588 case IGC_RXDADV_RSSTYPE_IPV6_TCP_EX: 589 return M_HASHTYPE_RSS_TCP_IPV6_EX; 590 default: 591 return M_HASHTYPE_OPAQUE; 592 } 593 } 594