1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Matthew Macy <mmacy@mattmacy.io> 5 * All rights reserved. 6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "if_igc.h" 34 35 #ifdef RSS 36 #include <net/rss_config.h> 37 #include <netinet/in_rss.h> 38 #endif 39 40 #ifdef VERBOSE_DEBUG 41 #define DPRINTF device_printf 42 #else 43 #define DPRINTF(...) 44 #endif 45 46 /********************************************************************* 47 * Local Function prototypes 48 *********************************************************************/ 49 static int igc_isc_txd_encap(void *arg, if_pkt_info_t pi); 50 static void igc_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx); 51 static int igc_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear); 52 53 static void igc_isc_rxd_refill(void *arg, if_rxd_update_t iru); 54 55 static void igc_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, qidx_t pidx); 56 static int igc_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget); 57 58 static int igc_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri); 59 60 static int igc_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, u32 *cmd_type_len, u32 *olinfo_status); 61 static int igc_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, u32 *cmd_type_len, u32 *olinfo_status); 62 63 static void igc_rx_checksum(u32 staterr, if_rxd_info_t ri, u32 ptype); 64 static int igc_determine_rsstype(u16 pkt_info); 65 66 extern void igc_if_enable_intr(if_ctx_t ctx); 67 extern int igc_intr(void *arg); 68 69 struct if_txrx igc_txrx = { 70 .ift_txd_encap = igc_isc_txd_encap, 71 .ift_txd_flush = igc_isc_txd_flush, 72 .ift_txd_credits_update = igc_isc_txd_credits_update, 73 .ift_rxd_available = igc_isc_rxd_available, 74 .ift_rxd_pkt_get = igc_isc_rxd_pkt_get, 75 .ift_rxd_refill = igc_isc_rxd_refill, 76 .ift_rxd_flush = igc_isc_rxd_flush, 77 .ift_legacy_intr = igc_intr 78 }; 79 80 void 81 igc_dump_rs(struct igc_adapter *adapter) 82 { 83 if_softc_ctx_t scctx = adapter->shared; 84 struct igc_tx_queue *que; 85 struct tx_ring *txr; 86 qidx_t i, ntxd, qid, cur; 87 int16_t rs_cidx; 88 uint8_t status; 89 90 printf("\n"); 91 ntxd = scctx->isc_ntxd[0]; 92 for (qid = 0; qid < adapter->tx_num_queues; qid++) { 93 que = &adapter->tx_queues[qid]; 94 txr = &que->txr; 95 rs_cidx = txr->tx_rs_cidx; 96 if (rs_cidx != txr->tx_rs_pidx) { 97 cur = txr->tx_rsq[rs_cidx]; 98 status = txr->tx_base[cur].upper.fields.status; 99 if (!(status & IGC_TXD_STAT_DD)) 100 printf("qid[%d]->tx_rsq[%d]: %d clear ", qid, rs_cidx, cur); 101 } else { 102 rs_cidx = (rs_cidx-1)&(ntxd-1); 103 cur = txr->tx_rsq[rs_cidx]; 104 printf("qid[%d]->tx_rsq[rs_cidx-1=%d]: %d ", qid, rs_cidx, cur); 105 } 106 printf("cidx_prev=%d rs_pidx=%d ",txr->tx_cidx_processed, txr->tx_rs_pidx); 107 for (i = 0; i < ntxd; i++) { 108 if (txr->tx_base[i].upper.fields.status & IGC_TXD_STAT_DD) 109 printf("%d set ", i); 110 } 111 printf("\n"); 112 } 113 } 114 115 /********************************************************************** 116 * 117 * Setup work for hardware segmentation offload (TSO) on 118 * adapters using advanced tx descriptors 119 * 120 **********************************************************************/ 121 static int 122 igc_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, u32 *cmd_type_len, u32 *olinfo_status) 123 { 124 struct igc_adv_tx_context_desc *TXD; 125 u32 type_tucmd_mlhl = 0, vlan_macip_lens = 0; 126 u32 mss_l4len_idx = 0; 127 u32 paylen; 128 129 switch(pi->ipi_etype) { 130 case ETHERTYPE_IPV6: 131 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6; 132 break; 133 case ETHERTYPE_IP: 134 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4; 135 /* Tell transmit desc to also do IPv4 checksum. */ 136 *olinfo_status |= IGC_TXD_POPTS_IXSM << 8; 137 break; 138 default: 139 panic("%s: CSUM_TSO but no supported IP version (0x%04x)", 140 __func__, ntohs(pi->ipi_etype)); 141 break; 142 } 143 144 TXD = (struct igc_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 145 146 /* This is used in the transmit desc in encap */ 147 paylen = pi->ipi_len - pi->ipi_ehdrlen - pi->ipi_ip_hlen - pi->ipi_tcp_hlen; 148 149 /* VLAN MACLEN IPLEN */ 150 if (pi->ipi_mflags & M_VLANTAG) { 151 vlan_macip_lens |= (pi->ipi_vtag << IGC_ADVTXD_VLAN_SHIFT); 152 } 153 154 vlan_macip_lens |= pi->ipi_ehdrlen << IGC_ADVTXD_MACLEN_SHIFT; 155 vlan_macip_lens |= pi->ipi_ip_hlen; 156 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 157 158 /* ADV DTYPE TUCMD */ 159 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT; 160 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP; 161 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 162 163 /* MSS L4LEN IDX */ 164 mss_l4len_idx |= (pi->ipi_tso_segsz << IGC_ADVTXD_MSS_SHIFT); 165 mss_l4len_idx |= (pi->ipi_tcp_hlen << IGC_ADVTXD_L4LEN_SHIFT); 166 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 167 168 TXD->seqnum_seed = htole32(0); 169 *cmd_type_len |= IGC_ADVTXD_DCMD_TSE; 170 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 171 *olinfo_status |= paylen << IGC_ADVTXD_PAYLEN_SHIFT; 172 173 return (1); 174 } 175 176 /********************************************************************* 177 * 178 * Advanced Context Descriptor setup for VLAN, CSUM or TSO 179 * 180 **********************************************************************/ 181 static int 182 igc_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, u32 *cmd_type_len, u32 *olinfo_status) 183 { 184 struct igc_adv_tx_context_desc *TXD; 185 u32 vlan_macip_lens, type_tucmd_mlhl; 186 u32 mss_l4len_idx; 187 mss_l4len_idx = vlan_macip_lens = type_tucmd_mlhl = 0; 188 189 /* First check if TSO is to be used */ 190 if (pi->ipi_csum_flags & CSUM_TSO) 191 return (igc_tso_setup(txr, pi, cmd_type_len, olinfo_status)); 192 193 /* Indicate the whole packet as payload when not doing TSO */ 194 *olinfo_status |= pi->ipi_len << IGC_ADVTXD_PAYLEN_SHIFT; 195 196 /* Now ready a context descriptor */ 197 TXD = (struct igc_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx]; 198 199 /* 200 ** In advanced descriptors the vlan tag must 201 ** be placed into the context descriptor. Hence 202 ** we need to make one even if not doing offloads. 203 */ 204 if (pi->ipi_mflags & M_VLANTAG) { 205 vlan_macip_lens |= (pi->ipi_vtag << IGC_ADVTXD_VLAN_SHIFT); 206 } else if ((pi->ipi_csum_flags & IGC_CSUM_OFFLOAD) == 0) { 207 return (0); 208 } 209 210 /* Set the ether header length */ 211 vlan_macip_lens |= pi->ipi_ehdrlen << IGC_ADVTXD_MACLEN_SHIFT; 212 213 switch(pi->ipi_etype) { 214 case ETHERTYPE_IP: 215 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV4; 216 break; 217 case ETHERTYPE_IPV6: 218 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_IPV6; 219 break; 220 default: 221 break; 222 } 223 224 vlan_macip_lens |= pi->ipi_ip_hlen; 225 type_tucmd_mlhl |= IGC_ADVTXD_DCMD_DEXT | IGC_ADVTXD_DTYP_CTXT; 226 227 switch (pi->ipi_ipproto) { 228 case IPPROTO_TCP: 229 if (pi->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP)) { 230 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_TCP; 231 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 232 } 233 break; 234 case IPPROTO_UDP: 235 if (pi->ipi_csum_flags & (CSUM_IP_UDP | CSUM_IP6_UDP)) { 236 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_UDP; 237 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 238 } 239 break; 240 case IPPROTO_SCTP: 241 if (pi->ipi_csum_flags & (CSUM_IP_SCTP | CSUM_IP6_SCTP)) { 242 type_tucmd_mlhl |= IGC_ADVTXD_TUCMD_L4T_SCTP; 243 *olinfo_status |= IGC_TXD_POPTS_TXSM << 8; 244 } 245 break; 246 default: 247 break; 248 } 249 250 /* Now copy bits into descriptor */ 251 TXD->vlan_macip_lens = htole32(vlan_macip_lens); 252 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl); 253 TXD->seqnum_seed = htole32(0); 254 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 255 256 return (1); 257 } 258 259 static int 260 igc_isc_txd_encap(void *arg, if_pkt_info_t pi) 261 { 262 struct igc_adapter *sc = arg; 263 if_softc_ctx_t scctx = sc->shared; 264 struct igc_tx_queue *que = &sc->tx_queues[pi->ipi_qsidx]; 265 struct tx_ring *txr = &que->txr; 266 int nsegs = pi->ipi_nsegs; 267 bus_dma_segment_t *segs = pi->ipi_segs; 268 union igc_adv_tx_desc *txd = NULL; 269 int i, j, pidx_last; 270 u32 olinfo_status, cmd_type_len, txd_flags; 271 qidx_t ntxd; 272 273 pidx_last = olinfo_status = 0; 274 /* Basic descriptor defines */ 275 cmd_type_len = (IGC_ADVTXD_DTYP_DATA | 276 IGC_ADVTXD_DCMD_IFCS | IGC_ADVTXD_DCMD_DEXT); 277 278 if (pi->ipi_mflags & M_VLANTAG) 279 cmd_type_len |= IGC_ADVTXD_DCMD_VLE; 280 281 i = pi->ipi_pidx; 282 ntxd = scctx->isc_ntxd[0]; 283 txd_flags = pi->ipi_flags & IPI_TX_INTR ? IGC_ADVTXD_DCMD_RS : 0; 284 /* Consume the first descriptor */ 285 i += igc_tx_ctx_setup(txr, pi, &cmd_type_len, &olinfo_status); 286 if (i == scctx->isc_ntxd[0]) 287 i = 0; 288 289 for (j = 0; j < nsegs; j++) { 290 bus_size_t seglen; 291 bus_addr_t segaddr; 292 293 txd = (union igc_adv_tx_desc *)&txr->tx_base[i]; 294 seglen = segs[j].ds_len; 295 segaddr = htole64(segs[j].ds_addr); 296 297 txd->read.buffer_addr = segaddr; 298 txd->read.cmd_type_len = htole32(IGC_ADVTXD_DCMD_IFCS | 299 cmd_type_len | seglen); 300 txd->read.olinfo_status = htole32(olinfo_status); 301 pidx_last = i; 302 if (++i == scctx->isc_ntxd[0]) { 303 i = 0; 304 } 305 } 306 if (txd_flags) { 307 txr->tx_rsq[txr->tx_rs_pidx] = pidx_last; 308 txr->tx_rs_pidx = (txr->tx_rs_pidx+1) & (ntxd-1); 309 MPASS(txr->tx_rs_pidx != txr->tx_rs_cidx); 310 } 311 312 txd->read.cmd_type_len |= htole32(IGC_ADVTXD_DCMD_EOP | txd_flags); 313 pi->ipi_new_pidx = i; 314 315 return (0); 316 } 317 318 static void 319 igc_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx) 320 { 321 struct igc_adapter *adapter = arg; 322 struct igc_tx_queue *que = &adapter->tx_queues[txqid]; 323 struct tx_ring *txr = &que->txr; 324 325 IGC_WRITE_REG(&adapter->hw, IGC_TDT(txr->me), pidx); 326 } 327 328 static int 329 igc_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear) 330 { 331 struct igc_adapter *adapter = arg; 332 if_softc_ctx_t scctx = adapter->shared; 333 struct igc_tx_queue *que = &adapter->tx_queues[txqid]; 334 struct tx_ring *txr = &que->txr; 335 336 qidx_t processed = 0; 337 int updated; 338 qidx_t cur, prev, ntxd, rs_cidx; 339 int32_t delta; 340 uint8_t status; 341 342 rs_cidx = txr->tx_rs_cidx; 343 if (rs_cidx == txr->tx_rs_pidx) 344 return (0); 345 cur = txr->tx_rsq[rs_cidx]; 346 status = ((union igc_adv_tx_desc *)&txr->tx_base[cur])->wb.status; 347 updated = !!(status & IGC_TXD_STAT_DD); 348 349 if (!updated) 350 return (0); 351 352 /* If clear is false just let caller know that there 353 * are descriptors to reclaim */ 354 if (!clear) 355 return (1); 356 357 prev = txr->tx_cidx_processed; 358 ntxd = scctx->isc_ntxd[0]; 359 do { 360 MPASS(prev != cur); 361 delta = (int32_t)cur - (int32_t)prev; 362 if (delta < 0) 363 delta += ntxd; 364 MPASS(delta > 0); 365 366 processed += delta; 367 prev = cur; 368 rs_cidx = (rs_cidx + 1) & (ntxd-1); 369 if (rs_cidx == txr->tx_rs_pidx) 370 break; 371 cur = txr->tx_rsq[rs_cidx]; 372 status = ((union igc_adv_tx_desc *)&txr->tx_base[cur])->wb.status; 373 } while ((status & IGC_TXD_STAT_DD)); 374 375 txr->tx_rs_cidx = rs_cidx; 376 txr->tx_cidx_processed = prev; 377 return (processed); 378 } 379 380 static void 381 igc_isc_rxd_refill(void *arg, if_rxd_update_t iru) 382 { 383 struct igc_adapter *sc = arg; 384 if_softc_ctx_t scctx = sc->shared; 385 uint16_t rxqid = iru->iru_qsidx; 386 struct igc_rx_queue *que = &sc->rx_queues[rxqid]; 387 union igc_adv_rx_desc *rxd; 388 struct rx_ring *rxr = &que->rxr; 389 uint64_t *paddrs; 390 uint32_t next_pidx, pidx; 391 uint16_t count; 392 int i; 393 394 paddrs = iru->iru_paddrs; 395 pidx = iru->iru_pidx; 396 count = iru->iru_count; 397 398 for (i = 0, next_pidx = pidx; i < count; i++) { 399 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[next_pidx]; 400 401 rxd->read.pkt_addr = htole64(paddrs[i]); 402 if (++next_pidx == scctx->isc_nrxd[0]) 403 next_pidx = 0; 404 } 405 } 406 407 static void 408 igc_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, qidx_t pidx) 409 { 410 struct igc_adapter *sc = arg; 411 struct igc_rx_queue *que = &sc->rx_queues[rxqid]; 412 struct rx_ring *rxr = &que->rxr; 413 414 IGC_WRITE_REG(&sc->hw, IGC_RDT(rxr->me), pidx); 415 } 416 417 static int 418 igc_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx, qidx_t budget) 419 { 420 struct igc_adapter *sc = arg; 421 if_softc_ctx_t scctx = sc->shared; 422 struct igc_rx_queue *que = &sc->rx_queues[rxqid]; 423 struct rx_ring *rxr = &que->rxr; 424 union igc_adv_rx_desc *rxd; 425 u32 staterr = 0; 426 int cnt, i; 427 428 for (cnt = 0, i = idx; cnt < scctx->isc_nrxd[0] && cnt <= budget;) { 429 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[i]; 430 staterr = le32toh(rxd->wb.upper.status_error); 431 432 if ((staterr & IGC_RXD_STAT_DD) == 0) 433 break; 434 if (++i == scctx->isc_nrxd[0]) 435 i = 0; 436 if (staterr & IGC_RXD_STAT_EOP) 437 cnt++; 438 } 439 return (cnt); 440 } 441 442 /**************************************************************** 443 * Routine sends data which has been dma'ed into host memory 444 * to upper layer. Initialize ri structure. 445 * 446 * Returns 0 upon success, errno on failure 447 ***************************************************************/ 448 449 static int 450 igc_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri) 451 { 452 struct igc_adapter *adapter = arg; 453 if_softc_ctx_t scctx = adapter->shared; 454 struct igc_rx_queue *que = &adapter->rx_queues[ri->iri_qsidx]; 455 struct rx_ring *rxr = &que->rxr; 456 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 457 union igc_adv_rx_desc *rxd; 458 459 u16 pkt_info, len; 460 u16 vtag = 0; 461 u32 ptype; 462 u32 staterr = 0; 463 bool eop; 464 int i = 0; 465 int cidx = ri->iri_cidx; 466 467 do { 468 rxd = (union igc_adv_rx_desc *)&rxr->rx_base[cidx]; 469 staterr = le32toh(rxd->wb.upper.status_error); 470 pkt_info = le16toh(rxd->wb.lower.lo_dword.hs_rss.pkt_info); 471 472 MPASS ((staterr & IGC_RXD_STAT_DD) != 0); 473 474 len = le16toh(rxd->wb.upper.length); 475 ptype = le32toh(rxd->wb.lower.lo_dword.data) & IGC_PKTTYPE_MASK; 476 477 ri->iri_len += len; 478 rxr->rx_bytes += ri->iri_len; 479 480 rxd->wb.upper.status_error = 0; 481 eop = ((staterr & IGC_RXD_STAT_EOP) == IGC_RXD_STAT_EOP); 482 483 vtag = le16toh(rxd->wb.upper.vlan); 484 485 /* Make sure bad packets are discarded */ 486 if (eop && ((staterr & IGC_RXDEXT_STATERR_RXE) != 0)) { 487 adapter->dropped_pkts++; 488 ++rxr->rx_discarded; 489 return (EBADMSG); 490 } 491 ri->iri_frags[i].irf_flid = 0; 492 ri->iri_frags[i].irf_idx = cidx; 493 ri->iri_frags[i].irf_len = len; 494 495 if (++cidx == scctx->isc_nrxd[0]) 496 cidx = 0; 497 #ifdef notyet 498 if (rxr->hdr_split == true) { 499 ri->iri_frags[i].irf_flid = 1; 500 ri->iri_frags[i].irf_idx = cidx; 501 if (++cidx == scctx->isc_nrxd[0]) 502 cidx = 0; 503 } 504 #endif 505 i++; 506 } while (!eop); 507 508 rxr->rx_packets++; 509 510 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 511 igc_rx_checksum(staterr, ri, ptype); 512 513 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 514 (staterr & IGC_RXD_STAT_VP) != 0) { 515 ri->iri_vtag = vtag; 516 ri->iri_flags |= M_VLANTAG; 517 } 518 ri->iri_flowid = 519 le32toh(rxd->wb.lower.hi_dword.rss); 520 ri->iri_rsstype = igc_determine_rsstype(pkt_info); 521 ri->iri_nfrags = i; 522 523 return (0); 524 } 525 526 /********************************************************************* 527 * 528 * Verify that the hardware indicated that the checksum is valid. 529 * Inform the stack about the status of checksum so that stack 530 * doesn't spend time verifying the checksum. 531 * 532 *********************************************************************/ 533 static void 534 igc_rx_checksum(u32 staterr, if_rxd_info_t ri, u32 ptype) 535 { 536 u16 status = (u16)staterr; 537 u8 errors = (u8) (staterr >> 24); 538 539 /* Ignore Checksum bit is set */ 540 if (status & IGC_RXD_STAT_IXSM) { 541 ri->iri_csum_flags = 0; 542 return; 543 } 544 545 if (status & (IGC_RXD_STAT_TCPCS | IGC_RXD_STAT_UDPCS)) { 546 u64 type = (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 547 /* Did it pass? */ 548 if (!(errors & IGC_RXD_ERR_TCPE)) { 549 ri->iri_csum_flags |= type; 550 ri->iri_csum_data = htons(0xffff); 551 } 552 } 553 return; 554 } 555 556 /******************************************************************** 557 * 558 * Parse the packet type to determine the appropriate hash 559 * 560 ******************************************************************/ 561 static int 562 igc_determine_rsstype(u16 pkt_info) 563 { 564 switch (pkt_info & IGC_RXDADV_RSSTYPE_MASK) { 565 case IGC_RXDADV_RSSTYPE_IPV4_TCP: 566 return M_HASHTYPE_RSS_TCP_IPV4; 567 case IGC_RXDADV_RSSTYPE_IPV4: 568 return M_HASHTYPE_RSS_IPV4; 569 case IGC_RXDADV_RSSTYPE_IPV6_TCP: 570 return M_HASHTYPE_RSS_TCP_IPV6; 571 case IGC_RXDADV_RSSTYPE_IPV6_EX: 572 return M_HASHTYPE_RSS_IPV6_EX; 573 case IGC_RXDADV_RSSTYPE_IPV6: 574 return M_HASHTYPE_RSS_IPV6; 575 case IGC_RXDADV_RSSTYPE_IPV6_TCP_EX: 576 return M_HASHTYPE_RSS_TCP_IPV6_EX; 577 default: 578 return M_HASHTYPE_OPAQUE; 579 } 580 } 581