1 /*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <sys/cdefs.h> 8 __FBSDID("$FreeBSD$"); 9 10 #include "igc_api.h" 11 12 static s32 igc_wait_autoneg(struct igc_hw *hw); 13 14 /** 15 * igc_init_phy_ops_generic - Initialize PHY function pointers 16 * @hw: pointer to the HW structure 17 * 18 * Setups up the function pointers to no-op functions 19 **/ 20 void igc_init_phy_ops_generic(struct igc_hw *hw) 21 { 22 struct igc_phy_info *phy = &hw->phy; 23 DEBUGFUNC("igc_init_phy_ops_generic"); 24 25 /* Initialize function pointers */ 26 phy->ops.init_params = igc_null_ops_generic; 27 phy->ops.acquire = igc_null_ops_generic; 28 phy->ops.check_reset_block = igc_null_ops_generic; 29 phy->ops.force_speed_duplex = igc_null_ops_generic; 30 phy->ops.get_info = igc_null_ops_generic; 31 phy->ops.set_page = igc_null_set_page; 32 phy->ops.read_reg = igc_null_read_reg; 33 phy->ops.read_reg_locked = igc_null_read_reg; 34 phy->ops.read_reg_page = igc_null_read_reg; 35 phy->ops.release = igc_null_phy_generic; 36 phy->ops.reset = igc_null_ops_generic; 37 phy->ops.set_d0_lplu_state = igc_null_lplu_state; 38 phy->ops.set_d3_lplu_state = igc_null_lplu_state; 39 phy->ops.write_reg = igc_null_write_reg; 40 phy->ops.write_reg_locked = igc_null_write_reg; 41 phy->ops.write_reg_page = igc_null_write_reg; 42 phy->ops.power_up = igc_null_phy_generic; 43 phy->ops.power_down = igc_null_phy_generic; 44 } 45 46 /** 47 * igc_null_set_page - No-op function, return 0 48 * @hw: pointer to the HW structure 49 * @data: dummy variable 50 **/ 51 s32 igc_null_set_page(struct igc_hw IGC_UNUSEDARG *hw, 52 u16 IGC_UNUSEDARG data) 53 { 54 DEBUGFUNC("igc_null_set_page"); 55 return IGC_SUCCESS; 56 } 57 58 /** 59 * igc_null_read_reg - No-op function, return 0 60 * @hw: pointer to the HW structure 61 * @offset: dummy variable 62 * @data: dummy variable 63 **/ 64 s32 igc_null_read_reg(struct igc_hw IGC_UNUSEDARG *hw, 65 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG *data) 66 { 67 DEBUGFUNC("igc_null_read_reg"); 68 return IGC_SUCCESS; 69 } 70 71 /** 72 * igc_null_phy_generic - No-op function, return void 73 * @hw: pointer to the HW structure 74 **/ 75 void igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG *hw) 76 { 77 DEBUGFUNC("igc_null_phy_generic"); 78 return; 79 } 80 81 /** 82 * igc_null_lplu_state - No-op function, return 0 83 * @hw: pointer to the HW structure 84 * @active: dummy variable 85 **/ 86 s32 igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG *hw, 87 bool IGC_UNUSEDARG active) 88 { 89 DEBUGFUNC("igc_null_lplu_state"); 90 return IGC_SUCCESS; 91 } 92 93 /** 94 * igc_null_write_reg - No-op function, return 0 95 * @hw: pointer to the HW structure 96 * @offset: dummy variable 97 * @data: dummy variable 98 **/ 99 s32 igc_null_write_reg(struct igc_hw IGC_UNUSEDARG *hw, 100 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG data) 101 { 102 DEBUGFUNC("igc_null_write_reg"); 103 return IGC_SUCCESS; 104 } 105 106 /** 107 * igc_check_reset_block_generic - Check if PHY reset is blocked 108 * @hw: pointer to the HW structure 109 * 110 * Read the PHY management control register and check whether a PHY reset 111 * is blocked. If a reset is not blocked return IGC_SUCCESS, otherwise 112 * return IGC_BLK_PHY_RESET (12). 113 **/ 114 s32 igc_check_reset_block_generic(struct igc_hw *hw) 115 { 116 u32 manc; 117 118 DEBUGFUNC("igc_check_reset_block"); 119 120 manc = IGC_READ_REG(hw, IGC_MANC); 121 122 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ? 123 IGC_BLK_PHY_RESET : IGC_SUCCESS; 124 } 125 126 /** 127 * igc_get_phy_id - Retrieve the PHY ID and revision 128 * @hw: pointer to the HW structure 129 * 130 * Reads the PHY registers and stores the PHY ID and possibly the PHY 131 * revision in the hardware structure. 132 **/ 133 s32 igc_get_phy_id(struct igc_hw *hw) 134 { 135 struct igc_phy_info *phy = &hw->phy; 136 s32 ret_val = IGC_SUCCESS; 137 u16 phy_id; 138 139 DEBUGFUNC("igc_get_phy_id"); 140 141 if (!phy->ops.read_reg) 142 return IGC_SUCCESS; 143 144 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 145 if (ret_val) 146 return ret_val; 147 148 phy->id = (u32)(phy_id << 16); 149 usec_delay(200); 150 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 151 if (ret_val) 152 return ret_val; 153 154 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 155 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 156 157 return IGC_SUCCESS; 158 } 159 160 /** 161 * igc_read_phy_reg_mdic - Read MDI control register 162 * @hw: pointer to the HW structure 163 * @offset: register offset to be read 164 * @data: pointer to the read data 165 * 166 * Reads the MDI control register in the PHY at offset and stores the 167 * information read to data. 168 **/ 169 s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data) 170 { 171 struct igc_phy_info *phy = &hw->phy; 172 u32 i, mdic = 0; 173 174 DEBUGFUNC("igc_read_phy_reg_mdic"); 175 176 if (offset > MAX_PHY_REG_ADDRESS) { 177 DEBUGOUT1("PHY Address %d is out of range\n", offset); 178 return -IGC_ERR_PARAM; 179 } 180 181 /* Set up Op-code, Phy Address, and register offset in the MDI 182 * Control register. The MAC will take care of interfacing with the 183 * PHY to retrieve the desired data. 184 */ 185 mdic = ((offset << IGC_MDIC_REG_SHIFT) | 186 (phy->addr << IGC_MDIC_PHY_SHIFT) | 187 (IGC_MDIC_OP_READ)); 188 189 IGC_WRITE_REG(hw, IGC_MDIC, mdic); 190 191 /* Poll the ready bit to see if the MDI read completed 192 * Increasing the time out as testing showed failures with 193 * the lower time out 194 */ 195 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) { 196 usec_delay_irq(50); 197 mdic = IGC_READ_REG(hw, IGC_MDIC); 198 if (mdic & IGC_MDIC_READY) 199 break; 200 } 201 if (!(mdic & IGC_MDIC_READY)) { 202 DEBUGOUT("MDI Read did not complete\n"); 203 return -IGC_ERR_PHY; 204 } 205 if (mdic & IGC_MDIC_ERROR) { 206 DEBUGOUT("MDI Error\n"); 207 return -IGC_ERR_PHY; 208 } 209 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) { 210 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", 211 offset, 212 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT); 213 return -IGC_ERR_PHY; 214 } 215 *data = (u16) mdic; 216 217 return IGC_SUCCESS; 218 } 219 220 /** 221 * igc_write_phy_reg_mdic - Write MDI control register 222 * @hw: pointer to the HW structure 223 * @offset: register offset to write to 224 * @data: data to write to register at offset 225 * 226 * Writes data to MDI control register in the PHY at offset. 227 **/ 228 s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data) 229 { 230 struct igc_phy_info *phy = &hw->phy; 231 u32 i, mdic = 0; 232 233 DEBUGFUNC("igc_write_phy_reg_mdic"); 234 235 if (offset > MAX_PHY_REG_ADDRESS) { 236 DEBUGOUT1("PHY Address %d is out of range\n", offset); 237 return -IGC_ERR_PARAM; 238 } 239 240 /* Set up Op-code, Phy Address, and register offset in the MDI 241 * Control register. The MAC will take care of interfacing with the 242 * PHY to retrieve the desired data. 243 */ 244 mdic = (((u32)data) | 245 (offset << IGC_MDIC_REG_SHIFT) | 246 (phy->addr << IGC_MDIC_PHY_SHIFT) | 247 (IGC_MDIC_OP_WRITE)); 248 249 IGC_WRITE_REG(hw, IGC_MDIC, mdic); 250 251 /* Poll the ready bit to see if the MDI read completed 252 * Increasing the time out as testing showed failures with 253 * the lower time out 254 */ 255 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) { 256 usec_delay_irq(50); 257 mdic = IGC_READ_REG(hw, IGC_MDIC); 258 if (mdic & IGC_MDIC_READY) 259 break; 260 } 261 if (!(mdic & IGC_MDIC_READY)) { 262 DEBUGOUT("MDI Write did not complete\n"); 263 return -IGC_ERR_PHY; 264 } 265 if (mdic & IGC_MDIC_ERROR) { 266 DEBUGOUT("MDI Error\n"); 267 return -IGC_ERR_PHY; 268 } 269 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) { 270 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n", 271 offset, 272 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT); 273 return -IGC_ERR_PHY; 274 } 275 276 return IGC_SUCCESS; 277 } 278 279 /** 280 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation 281 * @hw: pointer to the HW structure 282 * 283 * Reads the MII auto-neg advertisement register and/or the 1000T control 284 * register and if the PHY is already setup for auto-negotiation, then 285 * return successful. Otherwise, setup advertisement and flow control to 286 * the appropriate values for the wanted auto-negotiation. 287 **/ 288 static s32 igc_phy_setup_autoneg(struct igc_hw *hw) 289 { 290 struct igc_phy_info *phy = &hw->phy; 291 s32 ret_val; 292 u16 mii_autoneg_adv_reg; 293 u16 mii_1000t_ctrl_reg = 0; 294 u16 aneg_multigbt_an_ctrl = 0; 295 296 DEBUGFUNC("igc_phy_setup_autoneg"); 297 298 phy->autoneg_advertised &= phy->autoneg_mask; 299 300 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 301 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 302 if (ret_val) 303 return ret_val; 304 305 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 306 /* Read the MII 1000Base-T Control Register (Address 9). */ 307 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 308 &mii_1000t_ctrl_reg); 309 if (ret_val) 310 return ret_val; 311 } 312 313 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) && 314 hw->phy.id == I225_I_PHY_ID) { 315 /* Read the MULTI GBT AN Control Register - reg 7.32 */ 316 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << 317 MMD_DEVADDR_SHIFT) | 318 ANEG_MULTIGBT_AN_CTRL, 319 &aneg_multigbt_an_ctrl); 320 321 if (ret_val) 322 return ret_val; 323 } 324 325 /* Need to parse both autoneg_advertised and fc and set up 326 * the appropriate PHY registers. First we will parse for 327 * autoneg_advertised software override. Since we can advertise 328 * a plethora of combinations, we need to check each bit 329 * individually. 330 */ 331 332 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 333 * Advertisement Register (Address 4) and the 1000 mb speed bits in 334 * the 1000Base-T Control Register (Address 9). 335 */ 336 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 337 NWAY_AR_100TX_HD_CAPS | 338 NWAY_AR_10T_FD_CAPS | 339 NWAY_AR_10T_HD_CAPS); 340 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 341 342 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 343 344 /* Do we want to advertise 10 Mb Half Duplex? */ 345 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 346 DEBUGOUT("Advertise 10mb Half duplex\n"); 347 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 348 } 349 350 /* Do we want to advertise 10 Mb Full Duplex? */ 351 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 352 DEBUGOUT("Advertise 10mb Full duplex\n"); 353 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 354 } 355 356 /* Do we want to advertise 100 Mb Half Duplex? */ 357 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 358 DEBUGOUT("Advertise 100mb Half duplex\n"); 359 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 360 } 361 362 /* Do we want to advertise 100 Mb Full Duplex? */ 363 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 364 DEBUGOUT("Advertise 100mb Full duplex\n"); 365 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 366 } 367 368 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 369 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 370 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 371 372 /* Do we want to advertise 1000 Mb Full Duplex? */ 373 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 374 DEBUGOUT("Advertise 1000mb Full duplex\n"); 375 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 376 } 377 378 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */ 379 if (phy->autoneg_advertised & ADVERTISE_2500_HALF) 380 DEBUGOUT("Advertise 2500mb Half duplex request denied!\n"); 381 382 /* Do we want to advertise 2500 Mb Full Duplex? */ 383 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) { 384 DEBUGOUT("Advertise 2500mb Full duplex\n"); 385 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS; 386 } else { 387 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS; 388 } 389 390 /* Check for a software override of the flow control settings, and 391 * setup the PHY advertisement registers accordingly. If 392 * auto-negotiation is enabled, then software will have to set the 393 * "PAUSE" bits to the correct value in the Auto-Negotiation 394 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 395 * negotiation. 396 * 397 * The possible values of the "fc" parameter are: 398 * 0: Flow control is completely disabled 399 * 1: Rx flow control is enabled (we can receive pause frames 400 * but not send pause frames). 401 * 2: Tx flow control is enabled (we can send pause frames 402 * but we do not support receiving pause frames). 403 * 3: Both Rx and Tx flow control (symmetric) are enabled. 404 * other: No software override. The flow control configuration 405 * in the EEPROM is used. 406 */ 407 switch (hw->fc.current_mode) { 408 case igc_fc_none: 409 /* Flow control (Rx & Tx) is completely disabled by a 410 * software over-ride. 411 */ 412 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 413 break; 414 case igc_fc_rx_pause: 415 /* Rx Flow control is enabled, and Tx Flow control is 416 * disabled, by a software over-ride. 417 * 418 * Since there really isn't a way to advertise that we are 419 * capable of Rx Pause ONLY, we will advertise that we 420 * support both symmetric and asymmetric Rx PAUSE. Later 421 * (in igc_config_fc_after_link_up) we will disable the 422 * hw's ability to send PAUSE frames. 423 */ 424 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 425 break; 426 case igc_fc_tx_pause: 427 /* Tx Flow control is enabled, and Rx Flow control is 428 * disabled, by a software over-ride. 429 */ 430 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 431 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 432 break; 433 case igc_fc_full: 434 /* Flow control (both Rx and Tx) is enabled by a software 435 * over-ride. 436 */ 437 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 438 break; 439 default: 440 DEBUGOUT("Flow control param set incorrectly\n"); 441 return -IGC_ERR_CONFIG; 442 } 443 444 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 445 if (ret_val) 446 return ret_val; 447 448 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 449 450 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 451 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 452 mii_1000t_ctrl_reg); 453 454 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) && 455 hw->phy.id == I225_I_PHY_ID) 456 ret_val = phy->ops.write_reg(hw, 457 (STANDARD_AN_REG_MASK << 458 MMD_DEVADDR_SHIFT) | 459 ANEG_MULTIGBT_AN_CTRL, 460 aneg_multigbt_an_ctrl); 461 462 return ret_val; 463 } 464 465 /** 466 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link 467 * @hw: pointer to the HW structure 468 * 469 * Performs initial bounds checking on autoneg advertisement parameter, then 470 * configure to advertise the full capability. Setup the PHY to autoneg 471 * and restart the negotiation process between the link partner. If 472 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 473 **/ 474 static s32 igc_copper_link_autoneg(struct igc_hw *hw) 475 { 476 struct igc_phy_info *phy = &hw->phy; 477 s32 ret_val; 478 u16 phy_ctrl; 479 480 DEBUGFUNC("igc_copper_link_autoneg"); 481 482 /* Perform some bounds checking on the autoneg advertisement 483 * parameter. 484 */ 485 phy->autoneg_advertised &= phy->autoneg_mask; 486 487 /* If autoneg_advertised is zero, we assume it was not defaulted 488 * by the calling code so we set to advertise full capability. 489 */ 490 if (!phy->autoneg_advertised) 491 phy->autoneg_advertised = phy->autoneg_mask; 492 493 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 494 ret_val = igc_phy_setup_autoneg(hw); 495 if (ret_val) { 496 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 497 return ret_val; 498 } 499 DEBUGOUT("Restarting Auto-Neg\n"); 500 501 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 502 * the Auto Neg Restart bit in the PHY control register. 503 */ 504 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 505 if (ret_val) 506 return ret_val; 507 508 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 509 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 510 if (ret_val) 511 return ret_val; 512 513 /* Does the user want to wait for Auto-Neg to complete here, or 514 * check at a later time (for example, callback routine). 515 */ 516 if (phy->autoneg_wait_to_complete) { 517 ret_val = igc_wait_autoneg(hw); 518 if (ret_val) { 519 DEBUGOUT("Error while waiting for autoneg to complete\n"); 520 return ret_val; 521 } 522 } 523 524 hw->mac.get_link_status = true; 525 526 return ret_val; 527 } 528 529 /** 530 * igc_setup_copper_link_generic - Configure copper link settings 531 * @hw: pointer to the HW structure 532 * 533 * Calls the appropriate function to configure the link for auto-neg or forced 534 * speed and duplex. Then we check for link, once link is established calls 535 * to configure collision distance and flow control are called. If link is 536 * not established, we return -IGC_ERR_PHY (-2). 537 **/ 538 s32 igc_setup_copper_link_generic(struct igc_hw *hw) 539 { 540 s32 ret_val; 541 bool link; 542 543 DEBUGFUNC("igc_setup_copper_link_generic"); 544 545 if (hw->mac.autoneg) { 546 /* Setup autoneg and flow control advertisement and perform 547 * autonegotiation. 548 */ 549 ret_val = igc_copper_link_autoneg(hw); 550 if (ret_val) 551 return ret_val; 552 } else { 553 /* PHY will be set to 10H, 10F, 100H or 100F 554 * depending on user settings. 555 */ 556 DEBUGOUT("Forcing Speed and Duplex\n"); 557 ret_val = hw->phy.ops.force_speed_duplex(hw); 558 if (ret_val) { 559 DEBUGOUT("Error Forcing Speed and Duplex\n"); 560 return ret_val; 561 } 562 } 563 564 /* Check link status. Wait up to 100 microseconds for link to become 565 * valid. 566 */ 567 ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 568 &link); 569 if (ret_val) 570 return ret_val; 571 572 if (link) { 573 DEBUGOUT("Valid link established!!!\n"); 574 hw->mac.ops.config_collision_dist(hw); 575 ret_val = igc_config_fc_after_link_up_generic(hw); 576 } else { 577 DEBUGOUT("Unable to establish link!!!\n"); 578 } 579 580 return ret_val; 581 } 582 583 /** 584 * igc_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 585 * @hw: pointer to the HW structure 586 * @phy_ctrl: pointer to current value of PHY_CONTROL 587 * 588 * Forces speed and duplex on the PHY by doing the following: disable flow 589 * control, force speed/duplex on the MAC, disable auto speed detection, 590 * disable auto-negotiation, configure duplex, configure speed, configure 591 * the collision distance, write configuration to CTRL register. The 592 * caller must write to the PHY_CONTROL register for these settings to 593 * take effect. 594 **/ 595 void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl) 596 { 597 struct igc_mac_info *mac = &hw->mac; 598 u32 ctrl; 599 600 DEBUGFUNC("igc_phy_force_speed_duplex_setup"); 601 602 /* Turn off flow control when forcing speed/duplex */ 603 hw->fc.current_mode = igc_fc_none; 604 605 /* Force speed/duplex on the mac */ 606 ctrl = IGC_READ_REG(hw, IGC_CTRL); 607 ctrl |= (IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX); 608 ctrl &= ~IGC_CTRL_SPD_SEL; 609 610 /* Disable Auto Speed Detection */ 611 ctrl &= ~IGC_CTRL_ASDE; 612 613 /* Disable autoneg on the phy */ 614 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 615 616 /* Forcing Full or Half Duplex? */ 617 if (mac->forced_speed_duplex & IGC_ALL_HALF_DUPLEX) { 618 ctrl &= ~IGC_CTRL_FD; 619 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 620 DEBUGOUT("Half Duplex\n"); 621 } else { 622 ctrl |= IGC_CTRL_FD; 623 *phy_ctrl |= MII_CR_FULL_DUPLEX; 624 DEBUGOUT("Full Duplex\n"); 625 } 626 627 /* Forcing 10mb or 100mb? */ 628 if (mac->forced_speed_duplex & IGC_ALL_100_SPEED) { 629 ctrl |= IGC_CTRL_SPD_100; 630 *phy_ctrl |= MII_CR_SPEED_100; 631 *phy_ctrl &= ~MII_CR_SPEED_1000; 632 DEBUGOUT("Forcing 100mb\n"); 633 } else { 634 ctrl &= ~(IGC_CTRL_SPD_1000 | IGC_CTRL_SPD_100); 635 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 636 DEBUGOUT("Forcing 10mb\n"); 637 } 638 639 hw->mac.ops.config_collision_dist(hw); 640 641 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 642 } 643 644 /** 645 * igc_set_d3_lplu_state_generic - Sets low power link up state for D3 646 * @hw: pointer to the HW structure 647 * @active: boolean used to enable/disable lplu 648 * 649 * Success returns 0, Failure returns 1 650 * 651 * The low power link up (lplu) state is set to the power management level D3 652 * and SmartSpeed is disabled when active is true, else clear lplu for D3 653 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 654 * is used during Dx states where the power conservation is most important. 655 * During driver activity, SmartSpeed should be enabled so performance is 656 * maintained. 657 **/ 658 s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active) 659 { 660 struct igc_phy_info *phy = &hw->phy; 661 s32 ret_val; 662 u16 data; 663 664 DEBUGFUNC("igc_set_d3_lplu_state_generic"); 665 666 if (!hw->phy.ops.read_reg) 667 return IGC_SUCCESS; 668 669 ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data); 670 if (ret_val) 671 return ret_val; 672 673 if (!active) { 674 data &= ~IGP02IGC_PM_D3_LPLU; 675 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT, 676 data); 677 if (ret_val) 678 return ret_val; 679 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 680 * during Dx states where the power conservation is most 681 * important. During driver activity we should enable 682 * SmartSpeed, so performance is maintained. 683 */ 684 if (phy->smart_speed == igc_smart_speed_on) { 685 ret_val = phy->ops.read_reg(hw, 686 IGP01IGC_PHY_PORT_CONFIG, 687 &data); 688 if (ret_val) 689 return ret_val; 690 691 data |= IGP01IGC_PSCFR_SMART_SPEED; 692 ret_val = phy->ops.write_reg(hw, 693 IGP01IGC_PHY_PORT_CONFIG, 694 data); 695 if (ret_val) 696 return ret_val; 697 } else if (phy->smart_speed == igc_smart_speed_off) { 698 ret_val = phy->ops.read_reg(hw, 699 IGP01IGC_PHY_PORT_CONFIG, 700 &data); 701 if (ret_val) 702 return ret_val; 703 704 data &= ~IGP01IGC_PSCFR_SMART_SPEED; 705 ret_val = phy->ops.write_reg(hw, 706 IGP01IGC_PHY_PORT_CONFIG, 707 data); 708 if (ret_val) 709 return ret_val; 710 } 711 } else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) || 712 (phy->autoneg_advertised == IGC_ALL_NOT_GIG) || 713 (phy->autoneg_advertised == IGC_ALL_10_SPEED)) { 714 data |= IGP02IGC_PM_D3_LPLU; 715 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT, 716 data); 717 if (ret_val) 718 return ret_val; 719 720 /* When LPLU is enabled, we should disable SmartSpeed */ 721 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG, 722 &data); 723 if (ret_val) 724 return ret_val; 725 726 data &= ~IGP01IGC_PSCFR_SMART_SPEED; 727 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG, 728 data); 729 } 730 731 return ret_val; 732 } 733 734 /** 735 * igc_check_downshift_generic - Checks whether a downshift in speed occurred 736 * @hw: pointer to the HW structure 737 * 738 * Success returns 0, Failure returns 1 739 * 740 * A downshift is detected by querying the PHY link health. 741 **/ 742 s32 igc_check_downshift_generic(struct igc_hw *hw) 743 { 744 struct igc_phy_info *phy = &hw->phy; 745 s32 ret_val; 746 747 DEBUGFUNC("igc_check_downshift_generic"); 748 749 switch (phy->type) { 750 case igc_phy_i225: 751 default: 752 /* speed downshift not supported */ 753 phy->speed_downgraded = false; 754 return IGC_SUCCESS; 755 } 756 757 return ret_val; 758 } 759 760 /** 761 * igc_wait_autoneg - Wait for auto-neg completion 762 * @hw: pointer to the HW structure 763 * 764 * Waits for auto-negotiation to complete or for the auto-negotiation time 765 * limit to expire, which ever happens first. 766 **/ 767 static s32 igc_wait_autoneg(struct igc_hw *hw) 768 { 769 s32 ret_val = IGC_SUCCESS; 770 u16 i, phy_status; 771 772 DEBUGFUNC("igc_wait_autoneg"); 773 774 if (!hw->phy.ops.read_reg) 775 return IGC_SUCCESS; 776 777 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 778 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 779 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 780 if (ret_val) 781 break; 782 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 783 if (ret_val) 784 break; 785 if (phy_status & MII_SR_AUTONEG_COMPLETE) 786 break; 787 msec_delay(100); 788 } 789 790 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 791 * has completed. 792 */ 793 return ret_val; 794 } 795 796 /** 797 * igc_phy_has_link_generic - Polls PHY for link 798 * @hw: pointer to the HW structure 799 * @iterations: number of times to poll for link 800 * @usec_interval: delay between polling attempts 801 * @success: pointer to whether polling was successful or not 802 * 803 * Polls the PHY status register for link, 'iterations' number of times. 804 **/ 805 s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations, 806 u32 usec_interval, bool *success) 807 { 808 s32 ret_val = IGC_SUCCESS; 809 u16 i, phy_status; 810 811 DEBUGFUNC("igc_phy_has_link_generic"); 812 813 if (!hw->phy.ops.read_reg) 814 return IGC_SUCCESS; 815 816 for (i = 0; i < iterations; i++) { 817 /* Some PHYs require the PHY_STATUS register to be read 818 * twice due to the link bit being sticky. No harm doing 819 * it across the board. 820 */ 821 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 822 if (ret_val) { 823 /* If the first read fails, another entity may have 824 * ownership of the resources, wait and try again to 825 * see if they have relinquished the resources yet. 826 */ 827 if (usec_interval >= 1000) 828 msec_delay(usec_interval/1000); 829 else 830 usec_delay(usec_interval); 831 } 832 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 833 if (ret_val) 834 break; 835 if (phy_status & MII_SR_LINK_STATUS) 836 break; 837 if (usec_interval >= 1000) 838 msec_delay(usec_interval/1000); 839 else 840 usec_delay(usec_interval); 841 } 842 843 *success = (i < iterations); 844 845 return ret_val; 846 } 847 848 /** 849 * igc_phy_hw_reset_generic - PHY hardware reset 850 * @hw: pointer to the HW structure 851 * 852 * Verify the reset block is not blocking us from resetting. Acquire 853 * semaphore (if necessary) and read/set/write the device control reset 854 * bit in the PHY. Wait the appropriate delay time for the device to 855 * reset and release the semaphore (if necessary). 856 **/ 857 s32 igc_phy_hw_reset_generic(struct igc_hw *hw) 858 { 859 struct igc_phy_info *phy = &hw->phy; 860 s32 ret_val; 861 u32 ctrl, timeout = 10000, phpm = 0; 862 863 DEBUGFUNC("igc_phy_hw_reset_generic"); 864 865 if (phy->ops.check_reset_block) { 866 ret_val = phy->ops.check_reset_block(hw); 867 if (ret_val) 868 return IGC_SUCCESS; 869 } 870 871 ret_val = phy->ops.acquire(hw); 872 if (ret_val) 873 return ret_val; 874 875 phpm = IGC_READ_REG(hw, IGC_I225_PHPM); 876 877 ctrl = IGC_READ_REG(hw, IGC_CTRL); 878 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST); 879 IGC_WRITE_FLUSH(hw); 880 881 usec_delay(phy->reset_delay_us); 882 883 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 884 IGC_WRITE_FLUSH(hw); 885 886 usec_delay(150); 887 888 do { 889 phpm = IGC_READ_REG(hw, IGC_I225_PHPM); 890 timeout--; 891 usec_delay(1); 892 } while (!(phpm & IGC_I225_PHPM_RST_COMPL) && timeout); 893 894 if (!timeout) 895 DEBUGOUT("Timeout expired after a phy reset\n"); 896 897 phy->ops.release(hw); 898 899 return ret_val; 900 } 901 902 /** 903 * igc_power_up_phy_copper - Restore copper link in case of PHY power down 904 * @hw: pointer to the HW structure 905 * 906 * In the case of a PHY power down to save power, or to turn off link during a 907 * driver unload, or wake on lan is not enabled, restore the link to previous 908 * settings. 909 **/ 910 void igc_power_up_phy_copper(struct igc_hw *hw) 911 { 912 u16 mii_reg = 0; 913 914 /* The PHY will retain its settings across a power down/up cycle */ 915 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 916 mii_reg &= ~MII_CR_POWER_DOWN; 917 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 918 usec_delay(300); 919 } 920 921 /** 922 * igc_power_down_phy_copper - Restore copper link in case of PHY power down 923 * @hw: pointer to the HW structure 924 * 925 * In the case of a PHY power down to save power, or to turn off link during a 926 * driver unload, or wake on lan is not enabled, restore the link to previous 927 * settings. 928 **/ 929 void igc_power_down_phy_copper(struct igc_hw *hw) 930 { 931 u16 mii_reg = 0; 932 933 /* The PHY will retain its settings across a power down/up cycle */ 934 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 935 mii_reg |= MII_CR_POWER_DOWN; 936 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 937 msec_delay(1); 938 } 939 /** 940 * igc_write_phy_reg_gpy - Write GPY PHY register 941 * @hw: pointer to the HW structure 942 * @offset: register offset to write to 943 * @data: data to write at register offset 944 * 945 * Acquires semaphore, if necessary, then writes the data to PHY register 946 * at the offset. Release any acquired semaphores before exiting. 947 **/ 948 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data) 949 { 950 s32 ret_val; 951 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 952 953 DEBUGFUNC("igc_write_phy_reg_gpy"); 954 955 offset = offset & GPY_REG_MASK; 956 957 if (!dev_addr) { 958 ret_val = hw->phy.ops.acquire(hw); 959 if (ret_val) 960 return ret_val; 961 ret_val = igc_write_phy_reg_mdic(hw, offset, data); 962 if (ret_val) 963 return ret_val; 964 hw->phy.ops.release(hw); 965 } else { 966 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr, 967 data); 968 } 969 return ret_val; 970 } 971 972 /** 973 * igc_read_phy_reg_gpy - Read GPY PHY register 974 * @hw: pointer to the HW structure 975 * @offset: lower half is register offset to read to 976 * upper half is MMD to use. 977 * @data: data to read at register offset 978 * 979 * Acquires semaphore, if necessary, then reads the data in the PHY register 980 * at the offset. Release any acquired semaphores before exiting. 981 **/ 982 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data) 983 { 984 s32 ret_val; 985 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 986 987 DEBUGFUNC("igc_read_phy_reg_gpy"); 988 989 offset = offset & GPY_REG_MASK; 990 991 if (!dev_addr) { 992 ret_val = hw->phy.ops.acquire(hw); 993 if (ret_val) 994 return ret_val; 995 ret_val = igc_read_phy_reg_mdic(hw, offset, data); 996 if (ret_val) 997 return ret_val; 998 hw->phy.ops.release(hw); 999 } else { 1000 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr, 1001 data); 1002 } 1003 return ret_val; 1004 } 1005 1006 1007 /** 1008 * __igc_access_xmdio_reg - Read/write XMDIO register 1009 * @hw: pointer to the HW structure 1010 * @address: XMDIO address to program 1011 * @dev_addr: device address to program 1012 * @data: pointer to value to read/write from/to the XMDIO address 1013 * @read: boolean flag to indicate read or write 1014 **/ 1015 static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address, 1016 u8 dev_addr, u16 *data, bool read) 1017 { 1018 s32 ret_val; 1019 1020 DEBUGFUNC("__igc_access_xmdio_reg"); 1021 1022 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr); 1023 if (ret_val) 1024 return ret_val; 1025 1026 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address); 1027 if (ret_val) 1028 return ret_val; 1029 1030 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA | 1031 dev_addr); 1032 if (ret_val) 1033 return ret_val; 1034 1035 if (read) 1036 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data); 1037 else 1038 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data); 1039 if (ret_val) 1040 return ret_val; 1041 1042 /* Recalibrate the device back to 0 */ 1043 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0); 1044 if (ret_val) 1045 return ret_val; 1046 1047 return ret_val; 1048 } 1049 1050 /** 1051 * igc_read_xmdio_reg - Read XMDIO register 1052 * @hw: pointer to the HW structure 1053 * @addr: XMDIO address to program 1054 * @dev_addr: device address to program 1055 * @data: value to be read from the EMI address 1056 **/ 1057 s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 *data) 1058 { 1059 DEBUGFUNC("igc_read_xmdio_reg"); 1060 1061 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true); 1062 } 1063 1064 /** 1065 * igc_write_xmdio_reg - Write XMDIO register 1066 * @hw: pointer to the HW structure 1067 * @addr: XMDIO address to program 1068 * @dev_addr: device address to program 1069 * @data: value to be written to the XMDIO address 1070 **/ 1071 s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 data) 1072 { 1073 DEBUGFUNC("igc_write_xmdio_reg"); 1074 1075 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false); 1076 } 1077